src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30 #include "midgard_ops.h"
  31
  32 #include "util/hash_table.h"
  33 #include "util/u_dynarray.h"
  34 #include "util/set.h"
  35 #include "util/list.h"
  36
  37 #include "main/mtypes.h"
  38 #include "compiler/nir_types.h"
  39 #include "compiler/nir/nir.h"
  40 #include "panfrost/util/pan_ir.h"
  41 #include "panfrost/util/lcra.h"
  42
  43 /* Forward declare */
  44 struct midgard_block;
  45
  46 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  47  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  48  * instruction is actually a discard op. */
  49
  50 #define TARGET_GOTO 0
  51 #define TARGET_BREAK 1
  52 #define TARGET_CONTINUE 2
  53 #define TARGET_DISCARD 3
  54 #define TARGET_TILEBUF_WAIT 4
  55
  56 typedef struct midgard_branch {
  57         /* If conditional, the condition is specified in r31.w */
  58         bool conditional;
  59
  60         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  61         bool invert_conditional;
  62
  63         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  64         unsigned target_type;
  65
  66         /* The actual target */
  67         union {
  68                 int target_block;
  69                 int target_break;
  70                 int target_continue;
  71         };
  72 } midgard_branch;
  73
  74 #define PAN_WRITEOUT_C 1
  75 #define PAN_WRITEOUT_Z 2
  76 #define PAN_WRITEOUT_S 4
  77
  78 /* Generic in-memory data type repesenting a single logical instruction, rather
  79  * than a single instruction group. This is the preferred form for code gen.
  80  * Multiple midgard_insturctions will later be combined during scheduling,
  81  * though this is not represented in this structure.  Its format bridges
  82  * the low-level binary representation with the higher level semantic meaning.
  83  *
  84  * Notably, it allows registers to be specified as block local SSA, for code
  85  * emitted before the register allocation pass.
  86  */
  87
  88 #define MIR_SRC_COUNT 4
  89 #define MIR_VEC_COMPONENTS 16
  90
  91 typedef struct midgard_instruction {
  92         /* Must be first for casting */
  93         struct list_head link;
  94
  95         unsigned type; /* ALU, load/store, texture */
  96
  97         /* Instruction arguments represented as block-local SSA
  98          * indices, rather than registers. ~0 means unused. */
  99         unsigned src[MIR_SRC_COUNT];
 100         unsigned dest;
 101
 102         /* vec16 swizzle, unpacked, per source */
 103         unsigned swizzle[MIR_SRC_COUNT][MIR_VEC_COMPONENTS];
 104
 105         /* Types! */
 106         nir_alu_type src_types[MIR_SRC_COUNT];
 107         nir_alu_type dest_type;
 108
 109         /* Packing ops have non-32-bit dest types even though they functionally
 110          * work at the 32-bit level, use this as a signal to disable copyprop.
 111          * We maybe need synthetic pack ops instead. */
 112         bool is_pack;
 113
 114         /* Modifiers, depending on type */
 115         union {
 116                 struct {
 117                         bool src_abs[MIR_SRC_COUNT];
 118                         bool src_neg[MIR_SRC_COUNT];
 119                 };
 120
 121                 struct {
 122                         bool src_shift[MIR_SRC_COUNT];
 123                 };
 124         };
 125
 126         /* Out of the union for csel (could maybe be fixed..) */
 127         bool src_invert[MIR_SRC_COUNT];
 128
 129         /* If the op supports it */
 130         enum midgard_roundmode roundmode;
 131
 132         /* Special fields for an ALU instruction */
 133         midgard_reg_info registers;
 134
 135         /* For textures: should helpers execute this instruction (instead of
 136          * just helping with derivatives)? Should helpers terminate after? */
 137         bool helper_terminate;
 138         bool helper_execute;
 139
 140         /* I.e. (1 << alu_bit) */
 141         int unit;
 142
 143         bool has_constants;
 144         midgard_constants constants;
 145         uint16_t inline_constant;
 146         bool has_blend_constant;
 147         bool has_inline_constant;
 148
 149         bool compact_branch;
 150         uint8_t writeout;
 151         bool last_writeout;
 152
 153         /* Masks in a saneish format. One bit per channel, not packed fancy.
 154          * Use this instead of the op specific ones, and switch over at emit
 155          * time */
 156
 157         uint16_t mask;
 158
 159         /* Hint for the register allocator not to spill the destination written
 160          * from this instruction (because it is a spill/unspill node itself).
 161          * Bitmask of spilled classes */
 162
 163         unsigned no_spill;
 164
 165         /* Generic hint for intra-pass use */
 166         bool hint;
 167
 168         /* During scheduling, the backwards dependency graph
 169          * (DAG). nr_dependencies is the number of unscheduled
 170          * instructions that must still be scheduled after
 171          * (before) this instruction. dependents are which
 172          * instructions need to be scheduled before (after) this
 173          * instruction. */
 174
 175         unsigned nr_dependencies;
 176         BITSET_WORD *dependents;
 177
 178         /* Use this in conjunction with `type` */
 179         unsigned op;
 180
 181         union {
 182                 midgard_load_store_word load_store;
 183                 midgard_vector_alu alu;
 184                 midgard_texture_word texture;
 185                 midgard_branch_extended branch_extended;
 186                 uint16_t br_compact;
 187
 188                 /* General branch, rather than packed br_compact. Higher level
 189                  * than the other components */
 190                 midgard_branch branch;
 191         };
 192 } midgard_instruction;
 193
 194 typedef struct midgard_block {
 195         pan_block base;
 196
 197         bool scheduled;
 198
 199         /* List of midgard_bundles emitted (after the scheduler has run) */
 200         struct util_dynarray bundles;
 201
 202         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 203         unsigned quadword_count;
 204
 205         /* Indicates this is a fixed-function fragment epilogue block */
 206         bool epilogue;
 207
 208         /* Are helper invocations required by this block? */
 209         bool helpers_in;
 210 } midgard_block;
 211
 212 typedef struct midgard_bundle {
 213         /* Tag for the overall bundle */
 214         int tag;
 215
 216         /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
 217          * sadd, vadd, smul, vlut, branch) */
 218         int instruction_count;
 219         midgard_instruction *instructions[6];
 220
 221         /* Bundle-wide ALU configuration */
 222         int padding;
 223         int control;
 224         bool has_embedded_constants;
 225         midgard_constants constants;
 226         bool has_blend_constant;
 227         bool last_writeout;
 228 } midgard_bundle;
 229
 230 enum midgard_rt_id {
 231         MIDGARD_COLOR_RT0 = 0,
 232         MIDGARD_COLOR_RT1,
 233         MIDGARD_COLOR_RT2,
 234         MIDGARD_COLOR_RT3,
 235         MIDGARD_COLOR_RT4,
 236         MIDGARD_COLOR_RT5,
 237         MIDGARD_COLOR_RT6,
 238         MIDGARD_COLOR_RT7,
 239         MIDGARD_ZS_RT,
 240         MIDGARD_NUM_RTS,
 241 };
 242
 243 typedef struct compiler_context {
 244         nir_shader *nir;
 245         gl_shader_stage stage;
 246
 247         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 248         bool is_blend;
 249
 250         /* Render target number for a keyed blend shader. Depends on is_blend */
 251         unsigned blend_rt;
 252
 253         /* Index to precolour to r0 for an input blend colour */
 254         unsigned blend_input;
 255
 256         /* Index to precolour to r2 for a dual-source blend colour */
 257         unsigned blend_src1;
 258
 259         /* Tracking for blend constant patching */
 260         int blend_constant_offset;
 261
 262         /* Number of bytes used for Thread Local Storage */
 263         unsigned tls_size;
 264
 265         /* Count of spills and fills for shaderdb */
 266         unsigned spills;
 267         unsigned fills;
 268
 269         /* Current NIR function */
 270         nir_function *func;
 271
 272         /* Allocated compiler temporary counter */
 273         unsigned temp_alloc;
 274
 275         /* Unordered list of midgard_blocks */
 276         int block_count;
 277         struct list_head blocks;
 278
 279         /* TODO merge with block_count? */
 280         unsigned block_source_count;
 281
 282         /* List of midgard_instructions emitted for the current block */
 283         midgard_block *current_block;
 284
 285         /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
 286         midgard_block *after_block;
 287
 288         /* The current "depth" of the loop, for disambiguating breaks/continues
 289          * when using nested loops */
 290         int current_loop_depth;
 291
 292         /* Total number of loops for shader-db */
 293         unsigned loop_count;
 294
 295         /* Constants which have been loaded, for later inlining */
 296         struct hash_table_u64 *ssa_constants;
 297
 298         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 299         struct hash_table_u64 *hash_to_temp;
 300         int temp_count;
 301         int max_hash;
 302
 303         /* Set of NIR indices that were already emitted as outmods */
 304         BITSET_WORD *already_emitted;
 305
 306         /* Just the count of the max register used. Higher count => higher
 307          * register pressure */
 308         int work_registers;
 309
 310         /* The number of uniforms allowable for the fast path */
 311         int uniform_cutoff;
 312
 313         /* Count of instructions emitted from NIR overall, across all blocks */
 314         int instruction_count;
 315
 316         /* Alpha ref value passed in */
 317         float alpha_ref;
 318
 319         unsigned quadword_count;
 320
 321         /* Bitmask of valid metadata */
 322         unsigned metadata;
 323
 324         /* Model-specific quirk set */
 325         uint32_t quirks;
 326
 327         /* Writeout instructions for each render target */
 328         midgard_instruction *writeout_branch[MIDGARD_NUM_RTS];
 329
 330         struct panfrost_sysvals sysvals;
 331 } compiler_context;
 332
 333 /* Per-block live_in/live_out */
 334 #define MIDGARD_METADATA_LIVENESS (1 << 0)
 335
 336 /* Helpers for manipulating the above structures (forming the driver IR) */
 337
 338 /* Append instruction to end of current block */
 339
 340 static inline midgard_instruction *
 341 mir_upload_ins(struct compiler_context *ctx, struct midgard_instruction ins)
 342 {
 343         midgard_instruction *heap = ralloc(ctx, struct midgard_instruction);
 344         memcpy(heap, &ins, sizeof(ins));
 345         return heap;
 346 }
 347
 348 static inline midgard_instruction *
 349 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 350 {
 351         midgard_instruction *u = mir_upload_ins(ctx, ins);
 352         list_addtail(&u->link, &ctx->current_block->base.instructions);
 353         return u;
 354 }
 355
 356 static inline struct midgard_instruction *
 357 mir_insert_instruction_before(struct compiler_context *ctx,
 358                               struct midgard_instruction *tag,
 359                               struct midgard_instruction ins)
 360 {
 361         struct midgard_instruction *u = mir_upload_ins(ctx, ins);
 362         list_addtail(&u->link, &tag->link);
 363         return u;
 364 }
 365
 366 static inline void
 367 mir_remove_instruction(struct midgard_instruction *ins)
 368 {
 369         list_del(&ins->link);
 370 }
 371
 372 static inline midgard_instruction*
 373 mir_prev_op(struct midgard_instruction *ins)
 374 {
 375         return list_last_entry(&(ins->link), midgard_instruction, link);
 376 }
 377
 378 static inline midgard_instruction*
 379 mir_next_op(struct midgard_instruction *ins)
 380 {
 381         return list_first_entry(&(ins->link), midgard_instruction, link);
 382 }
 383
 384 #define mir_foreach_block(ctx, v) \
 385         list_for_each_entry(pan_block, v, &ctx->blocks, link)
 386
 387 #define mir_foreach_block_from(ctx, from, v) \
 388         list_for_each_entry_from(pan_block, v, &from->base, &ctx->blocks, link)
 389
 390 #define mir_foreach_instr_in_block(block, v) \
 391         list_for_each_entry(struct midgard_instruction, v, &block->base.instructions, link)
 392 #define mir_foreach_instr_in_block_rev(block, v) \
 393         list_for_each_entry_rev(struct midgard_instruction, v, &block->base.instructions, link)
 394
 395 #define mir_foreach_instr_in_block_safe(block, v) \
 396         list_for_each_entry_safe(struct midgard_instruction, v, &block->base.instructions, link)
 397
 398 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 399         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->base.instructions, link)
 400
 401 #define mir_foreach_instr_in_block_from(block, v, from) \
 402         list_for_each_entry_from(struct midgard_instruction, v, from, &block->base.instructions, link)
 403
 404 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 405         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->base.instructions, link)
 406
 407 #define mir_foreach_bundle_in_block(block, v) \
 408         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 409
 410 #define mir_foreach_bundle_in_block_rev(block, v) \
 411         util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
 412
 413 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
 414         midgard_instruction* v; \
 415         signed i = 0; \
 416         mir_foreach_bundle_in_block_rev(block, _bundle) \
 417                 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
 418                                 i >= 0; \
 419                                 --i, v = (i >= 0) ? _bundle->instructions[i] : NULL) \
 420
 421 #define mir_foreach_instr_global(ctx, v) \
 422         mir_foreach_block(ctx, v_block) \
 423                 mir_foreach_instr_in_block(((midgard_block *) v_block), v)
 424
 425 #define mir_foreach_instr_global_safe(ctx, v) \
 426         mir_foreach_block(ctx, v_block) \
 427                 mir_foreach_instr_in_block_safe(((midgard_block *) v_block), v)
 428
 429 /* Based on set_foreach, expanded with automatic type casts */
 430
 431 #define mir_foreach_predecessor(blk, v) \
 432         struct set_entry *_entry_##v; \
 433         struct midgard_block *v; \
 434         for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
 435                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 436                 _entry_##v != NULL; \
 437                 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
 438                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
 439
 440 #define mir_foreach_src(ins, v) \
 441         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 442
 443 static inline midgard_instruction *
 444 mir_last_in_block(struct midgard_block *block)
 445 {
 446         return list_last_entry(&block->base.instructions, struct midgard_instruction, link);
 447 }
 448
 449 static inline midgard_block *
 450 mir_get_block(compiler_context *ctx, int idx)
 451 {
 452         struct list_head *lst = &ctx->blocks;
 453
 454         while ((idx--) + 1)
 455                 lst = lst->next;
 456
 457         return (struct midgard_block *) lst;
 458 }
 459
 460 static inline bool
 461 mir_is_alu_bundle(midgard_bundle *bundle)
 462 {
 463         return IS_ALU(bundle->tag);
 464 }
 465
 466 static inline unsigned
 467 make_compiler_temp(compiler_context *ctx)
 468 {
 469         return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
 470 }
 471
 472 static inline unsigned
 473 make_compiler_temp_reg(compiler_context *ctx)
 474 {
 475         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | PAN_IS_REG;
 476 }
 477
 478 static inline unsigned
 479 nir_ssa_index(nir_ssa_def *ssa)
 480 {
 481         return (ssa->index << 1) | 0;
 482 }
 483
 484 static inline unsigned
 485 nir_src_index(compiler_context *ctx, nir_src *src)
 486 {
 487         if (src->is_ssa)
 488                 return nir_ssa_index(src->ssa);
 489         else {
 490                 assert(!src->reg.indirect);
 491                 return (src->reg.reg->index << 1) | PAN_IS_REG;
 492         }
 493 }
 494
 495 static inline unsigned
 496 nir_dest_index(nir_dest *dst)
 497 {
 498         if (dst->is_ssa)
 499                 return (dst->ssa.index << 1) | 0;
 500         else {
 501                 assert(!dst->reg.indirect);
 502                 return (dst->reg.reg->index << 1) | PAN_IS_REG;
 503         }
 504 }
 505
 506
 507
 508 /* MIR manipulation */
 509
 510 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 511 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 512 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 513 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new);
 514 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 515 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned *swizzle);
 516 bool mir_single_use(compiler_context *ctx, unsigned value);
 517 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 518 uint16_t mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node);
 519 uint16_t mir_bytemask_of_read_components_index(midgard_instruction *ins, unsigned i);
 520 uint16_t mir_from_bytemask(uint16_t bytemask, unsigned bits);
 521 uint16_t mir_bytemask(midgard_instruction *ins);
 522 uint16_t mir_round_bytemask_up(uint16_t mask, unsigned bits);
 523 void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
 524 signed mir_upper_override(midgard_instruction *ins, unsigned inst_size);
 525 unsigned mir_components_for_type(nir_alu_type T);
 526 unsigned max_bitsize_for_alu(midgard_instruction *ins);
 527 midgard_reg_mode reg_mode_for_bitsize(unsigned bitsize);
 528
 529 /* MIR printing */
 530
 531 void mir_print_instruction(midgard_instruction *ins);
 532 void mir_print_bundle(midgard_bundle *ctx);
 533 void mir_print_block(midgard_block *block);
 534 void mir_print_shader(compiler_context *ctx);
 535 bool mir_nontrivial_mod(midgard_instruction *ins, unsigned i, bool check_swizzle);
 536 bool mir_nontrivial_outmod(midgard_instruction *ins);
 537
 538 void mir_insert_instruction_before_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 539 void mir_insert_instruction_after_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 540 void mir_flip(midgard_instruction *ins);
 541 void mir_compute_temp_count(compiler_context *ctx);
 542
 543 void mir_set_offset(compiler_context *ctx, midgard_instruction *ins, nir_src *offset, bool is_shared);
 544
 545 /* 'Intrinsic' move for aliasing */
 546
 547 static inline midgard_instruction
 548 v_mov(unsigned src, unsigned dest)
 549 {
 550         midgard_instruction ins = {
 551                 .type = TAG_ALU_4,
 552                 .mask = 0xF,
 553                 .src = { ~0, src, ~0, ~0 },
 554                 .src_types = { 0, nir_type_uint32 },
 555                 .swizzle = SWIZZLE_IDENTITY,
 556                 .dest = dest,
 557                 .dest_type = nir_type_uint32,
 558                 .op = midgard_alu_op_imov,
 559                 .alu = {
 560                         .outmod = midgard_outmod_int_wrap
 561                 },
 562         };
 563
 564         return ins;
 565 }
 566
 567 /* Broad types of register classes so we can handle special
 568  * registers */
 569
 570 #define REG_CLASS_WORK          0
 571 #define REG_CLASS_LDST          1
 572 #define REG_CLASS_TEXR          3
 573 #define REG_CLASS_TEXW          4
 574
 575 /* Like a move, but to thread local storage! */
 576
 577 static inline midgard_instruction
 578 v_load_store_scratch(
 579                 unsigned srcdest,
 580                 unsigned index,
 581                 bool is_store,
 582                 unsigned mask)
 583 {
 584         /* We index by 32-bit vec4s */
 585         unsigned byte = (index * 4 * 4);
 586
 587         midgard_instruction ins = {
 588                 .type = TAG_LOAD_STORE_4,
 589                 .mask = mask,
 590                 .dest_type = nir_type_uint32,
 591                 .dest = ~0,
 592                 .src = { ~0, ~0, ~0, ~0 },
 593                 .swizzle = SWIZZLE_IDENTITY_4,
 594                 .load_store = {
 595                         .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
 596
 597                         /* For register spilling - to thread local storage */
 598                         .arg_1 = 0xEA,
 599                         .arg_2 = 0x1E,
 600                 },
 601
 602                 /* If we spill an unspill, RA goes into an infinite loop */
 603                 .no_spill = (1 << REG_CLASS_WORK)
 604         };
 605
 606         ins.constants.u32[0] = byte;
 607
 608         if (is_store) {
 609                 ins.src[0] = srcdest;
 610                 ins.src_types[0] = nir_type_uint32;
 611
 612                 /* Ensure we are tightly swizzled so liveness analysis is
 613                  * correct */
 614
 615                 for (unsigned i = 0; i < 4; ++i) {
 616                         if (!(mask & (1 << i)))
 617                                 ins.swizzle[0][i] = COMPONENT_X;
 618                 }
 619         } else
 620                 ins.dest = srcdest;
 621
 622         return ins;
 623 }
 624
 625 static inline bool
 626 mir_has_arg(midgard_instruction *ins, unsigned arg)
 627 {
 628         if (!ins)
 629                 return false;
 630
 631         mir_foreach_src(ins, i) {
 632                 if (ins->src[i] == arg)
 633                         return true;
 634         }
 635
 636         return false;
 637 }
 638
 639 /* Scheduling */
 640
 641 void midgard_schedule_program(compiler_context *ctx);
 642
 643 void mir_ra(compiler_context *ctx);
 644 void mir_squeeze_index(compiler_context *ctx);
 645 void mir_lower_special_reads(compiler_context *ctx);
 646 void mir_liveness_ins_update(uint16_t *live, midgard_instruction *ins, unsigned max);
 647 void mir_compute_liveness(compiler_context *ctx);
 648 void mir_invalidate_liveness(compiler_context *ctx);
 649 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 650
 651 void mir_create_pipeline_registers(compiler_context *ctx);
 652 void midgard_promote_uniforms(compiler_context *ctx);
 653
 654 void
 655 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
 656
 657 void
 658 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
 659
 660 bool mir_op_computes_derivatives(gl_shader_stage stage, unsigned op);
 661
 662 void mir_analyze_helper_terminate(compiler_context *ctx);
 663 void mir_analyze_helper_requirements(compiler_context *ctx);
 664
 665 /* Final emission */
 666
 667 void emit_binary_bundle(
 668         compiler_context *ctx,
 669         midgard_block *block,
 670         midgard_bundle *bundle,
 671         struct util_dynarray *emission,
 672         int next_tag);
 673
 674 bool
 675 nir_undef_to_zero(nir_shader *shader);
 676 bool nir_fuse_io_16(nir_shader *shader);
 677
 678 void midgard_nir_lod_errata(nir_shader *shader);
 679
 680 /* Optimizations */
 681
 682 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 683 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 684 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 685 bool midgard_opt_dead_code_eliminate(compiler_context *ctx);
 686 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 687
 688 #endif