src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30 #include "midgard_ops.h"
  31
  32 #include "util/hash_table.h"
  33 #include "util/u_dynarray.h"
  34 #include "util/set.h"
  35 #include "util/list.h"
  36
  37 #include "main/mtypes.h"
  38 #include "compiler/nir_types.h"
  39 #include "compiler/nir/nir.h"
  40 #include "panfrost/util/pan_ir.h"
  41 #include "panfrost/util/lcra.h"
  42
  43 /* Forward declare */
  44 struct midgard_block;
  45
  46 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  47  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  48  * instruction is actually a discard op. */
  49
  50 #define TARGET_GOTO 0
  51 #define TARGET_BREAK 1
  52 #define TARGET_CONTINUE 2
  53 #define TARGET_DISCARD 3
  54
  55 typedef struct midgard_branch {
  56         /* If conditional, the condition is specified in r31.w */
  57         bool conditional;
  58
  59         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  60         bool invert_conditional;
  61
  62         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  63         unsigned target_type;
  64
  65         /* The actual target */
  66         union {
  67                 int target_block;
  68                 int target_break;
  69                 int target_continue;
  70         };
  71 } midgard_branch;
  72
  73 /* Generic in-memory data type repesenting a single logical instruction, rather
  74  * than a single instruction group. This is the preferred form for code gen.
  75  * Multiple midgard_insturctions will later be combined during scheduling,
  76  * though this is not represented in this structure.  Its format bridges
  77  * the low-level binary representation with the higher level semantic meaning.
  78  *
  79  * Notably, it allows registers to be specified as block local SSA, for code
  80  * emitted before the register allocation pass.
  81  */
  82
  83 #define MIR_SRC_COUNT 4
  84 #define MIR_VEC_COMPONENTS 16
  85
  86 typedef struct midgard_instruction {
  87         /* Must be first for casting */
  88         struct list_head link;
  89
  90         unsigned type; /* ALU, load/store, texture */
  91
  92         /* Instruction arguments represented as block-local SSA
  93          * indices, rather than registers. ~0 means unused. */
  94         unsigned src[MIR_SRC_COUNT];
  95         unsigned dest;
  96
  97         /* vec16 swizzle, unpacked, per source */
  98         unsigned swizzle[MIR_SRC_COUNT][MIR_VEC_COMPONENTS];
  99
 100         /* Special fields for an ALU instruction */
 101         midgard_reg_info registers;
 102
 103         /* I.e. (1 << alu_bit) */
 104         int unit;
 105
 106         bool has_constants;
 107         midgard_constants constants;
 108         uint16_t inline_constant;
 109         bool has_blend_constant;
 110         bool has_inline_constant;
 111
 112         bool compact_branch;
 113         bool writeout;
 114         bool writeout_depth;
 115         bool writeout_stencil;
 116         bool last_writeout;
 117
 118         /* Kind of a hack, but hint against aggressive DCE */
 119         bool dont_eliminate;
 120
 121         /* Masks in a saneish format. One bit per channel, not packed fancy.
 122          * Use this instead of the op specific ones, and switch over at emit
 123          * time */
 124
 125         uint16_t mask;
 126
 127         /* For ALU ops only: set to true to invert (bitwise NOT) the
 128          * destination of an integer-out op. Not implemented in hardware but
 129          * allows more optimizations */
 130
 131         bool invert;
 132
 133         /* Hint for the register allocator not to spill the destination written
 134          * from this instruction (because it is a spill/unspill node itself).
 135          * Bitmask of spilled classes */
 136
 137         unsigned no_spill;
 138
 139         /* Generic hint for intra-pass use */
 140         bool hint;
 141
 142         /* During scheduling, the backwards dependency graph
 143          * (DAG). nr_dependencies is the number of unscheduled
 144          * instructions that must still be scheduled after
 145          * (before) this instruction. dependents are which
 146          * instructions need to be scheduled before (after) this
 147          * instruction. */
 148
 149         unsigned nr_dependencies;
 150         BITSET_WORD *dependents;
 151
 152         /* For load/store ops.. force 64-bit destination */
 153         bool load_64;
 154
 155         union {
 156                 midgard_load_store_word load_store;
 157                 midgard_vector_alu alu;
 158                 midgard_texture_word texture;
 159                 midgard_branch_extended branch_extended;
 160                 uint16_t br_compact;
 161
 162                 /* General branch, rather than packed br_compact. Higher level
 163                  * than the other components */
 164                 midgard_branch branch;
 165         };
 166 } midgard_instruction;
 167
 168 typedef struct midgard_block {
 169         pan_block base;
 170
 171         bool scheduled;
 172
 173         /* List of midgard_bundles emitted (after the scheduler has run) */
 174         struct util_dynarray bundles;
 175
 176         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 177         unsigned quadword_count;
 178
 179         /* Indicates this is a fixed-function fragment epilogue block */
 180         bool epilogue;
 181 } midgard_block;
 182
 183 typedef struct midgard_bundle {
 184         /* Tag for the overall bundle */
 185         int tag;
 186
 187         /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
 188          * sadd, vadd, smul, vlut, branch) */
 189         int instruction_count;
 190         midgard_instruction *instructions[6];
 191
 192         /* Bundle-wide ALU configuration */
 193         int padding;
 194         int control;
 195         bool has_embedded_constants;
 196         midgard_constants constants;
 197         bool has_blend_constant;
 198         bool last_writeout;
 199 } midgard_bundle;
 200
 201 enum midgard_rt_id {
 202         MIDGARD_COLOR_RT0,
 203         MIDGARD_COLOR_RT1,
 204         MIDGARD_COLOR_RT2,
 205         MIDGARD_COLOR_RT3,
 206         MIDGARD_ZS_RT,
 207         MIDGARD_NUM_RTS,
 208 };
 209
 210 typedef struct compiler_context {
 211         nir_shader *nir;
 212         gl_shader_stage stage;
 213
 214         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 215         bool is_blend;
 216
 217         /* Render target number for a keyed blend shader. Depends on is_blend */
 218         unsigned blend_rt;
 219
 220         /* Tracking for blend constant patching */
 221         int blend_constant_offset;
 222
 223         /* Number of bytes used for Thread Local Storage */
 224         unsigned tls_size;
 225
 226         /* Count of spills and fills for shaderdb */
 227         unsigned spills;
 228         unsigned fills;
 229
 230         /* Current NIR function */
 231         nir_function *func;
 232
 233         /* Allocated compiler temporary counter */
 234         unsigned temp_alloc;
 235
 236         /* Unordered list of midgard_blocks */
 237         int block_count;
 238         struct list_head blocks;
 239
 240         /* TODO merge with block_count? */
 241         unsigned block_source_count;
 242
 243         /* List of midgard_instructions emitted for the current block */
 244         midgard_block *current_block;
 245
 246         /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
 247         midgard_block *after_block;
 248
 249         /* The current "depth" of the loop, for disambiguating breaks/continues
 250          * when using nested loops */
 251         int current_loop_depth;
 252
 253         /* Total number of loops for shader-db */
 254         unsigned loop_count;
 255
 256         /* Constants which have been loaded, for later inlining */
 257         struct hash_table_u64 *ssa_constants;
 258
 259         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 260         struct hash_table_u64 *hash_to_temp;
 261         int temp_count;
 262         int max_hash;
 263
 264         /* Just the count of the max register used. Higher count => higher
 265          * register pressure */
 266         int work_registers;
 267
 268         /* Used for cont/last hinting. Increase when a tex op is added.
 269          * Decrease when a tex op is removed. */
 270         int texture_op_count;
 271
 272         /* The number of uniforms allowable for the fast path */
 273         int uniform_cutoff;
 274
 275         /* Count of instructions emitted from NIR overall, across all blocks */
 276         int instruction_count;
 277
 278         /* Alpha ref value passed in */
 279         float alpha_ref;
 280
 281         unsigned quadword_count;
 282
 283         /* Bitmask of valid metadata */
 284         unsigned metadata;
 285
 286         /* Model-specific quirk set */
 287         uint32_t quirks;
 288
 289         /* Writeout instructions for each render target */
 290         midgard_instruction *writeout_branch[MIDGARD_NUM_RTS];
 291
 292         struct panfrost_sysvals sysvals;
 293 } compiler_context;
 294
 295 /* Per-block live_in/live_out */
 296 #define MIDGARD_METADATA_LIVENESS (1 << 0)
 297
 298 /* Helpers for manipulating the above structures (forming the driver IR) */
 299
 300 /* Append instruction to end of current block */
 301
 302 static inline midgard_instruction *
 303 mir_upload_ins(struct compiler_context *ctx, struct midgard_instruction ins)
 304 {
 305         midgard_instruction *heap = ralloc(ctx, struct midgard_instruction);
 306         memcpy(heap, &ins, sizeof(ins));
 307         return heap;
 308 }
 309
 310 static inline midgard_instruction *
 311 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 312 {
 313         midgard_instruction *u = mir_upload_ins(ctx, ins);
 314         list_addtail(&u->link, &ctx->current_block->base.instructions);
 315         return u;
 316 }
 317
 318 static inline struct midgard_instruction *
 319 mir_insert_instruction_before(struct compiler_context *ctx,
 320                               struct midgard_instruction *tag,
 321                               struct midgard_instruction ins)
 322 {
 323         struct midgard_instruction *u = mir_upload_ins(ctx, ins);
 324         list_addtail(&u->link, &tag->link);
 325         return u;
 326 }
 327
 328 static inline void
 329 mir_remove_instruction(struct midgard_instruction *ins)
 330 {
 331         list_del(&ins->link);
 332 }
 333
 334 static inline midgard_instruction*
 335 mir_prev_op(struct midgard_instruction *ins)
 336 {
 337         return list_last_entry(&(ins->link), midgard_instruction, link);
 338 }
 339
 340 static inline midgard_instruction*
 341 mir_next_op(struct midgard_instruction *ins)
 342 {
 343         return list_first_entry(&(ins->link), midgard_instruction, link);
 344 }
 345
 346 #define mir_foreach_block(ctx, v) \
 347         list_for_each_entry(pan_block, v, &ctx->blocks, link)
 348
 349 #define mir_foreach_block_from(ctx, from, v) \
 350         list_for_each_entry_from(pan_block, v, &from->base, &ctx->blocks, link)
 351
 352 #define mir_foreach_instr_in_block(block, v) \
 353         list_for_each_entry(struct midgard_instruction, v, &block->base.instructions, link)
 354 #define mir_foreach_instr_in_block_rev(block, v) \
 355         list_for_each_entry_rev(struct midgard_instruction, v, &block->base.instructions, link)
 356
 357 #define mir_foreach_instr_in_block_safe(block, v) \
 358         list_for_each_entry_safe(struct midgard_instruction, v, &block->base.instructions, link)
 359
 360 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 361         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->base.instructions, link)
 362
 363 #define mir_foreach_instr_in_block_from(block, v, from) \
 364         list_for_each_entry_from(struct midgard_instruction, v, from, &block->base.instructions, link)
 365
 366 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 367         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->base.instructions, link)
 368
 369 #define mir_foreach_bundle_in_block(block, v) \
 370         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 371
 372 #define mir_foreach_bundle_in_block_rev(block, v) \
 373         util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
 374
 375 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
 376         midgard_instruction* v; \
 377         signed i = 0; \
 378         mir_foreach_bundle_in_block_rev(block, _bundle) \
 379                 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
 380                                 i >= 0; \
 381                                 --i, v = (i >= 0) ? _bundle->instructions[i] : NULL) \
 382
 383 #define mir_foreach_instr_global(ctx, v) \
 384         mir_foreach_block(ctx, v_block) \
 385                 mir_foreach_instr_in_block(((midgard_block *) v_block), v)
 386
 387 #define mir_foreach_instr_global_safe(ctx, v) \
 388         mir_foreach_block(ctx, v_block) \
 389                 mir_foreach_instr_in_block_safe(((midgard_block *) v_block), v)
 390
 391 /* Based on set_foreach, expanded with automatic type casts */
 392
 393 #define mir_foreach_predecessor(blk, v) \
 394         struct set_entry *_entry_##v; \
 395         struct midgard_block *v; \
 396         for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
 397                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 398                 _entry_##v != NULL; \
 399                 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
 400                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
 401
 402 #define mir_foreach_src(ins, v) \
 403         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 404
 405 static inline midgard_instruction *
 406 mir_last_in_block(struct midgard_block *block)
 407 {
 408         return list_last_entry(&block->base.instructions, struct midgard_instruction, link);
 409 }
 410
 411 static inline midgard_block *
 412 mir_get_block(compiler_context *ctx, int idx)
 413 {
 414         struct list_head *lst = &ctx->blocks;
 415
 416         while ((idx--) + 1)
 417                 lst = lst->next;
 418
 419         return (struct midgard_block *) lst;
 420 }
 421
 422 static inline bool
 423 mir_is_alu_bundle(midgard_bundle *bundle)
 424 {
 425         return IS_ALU(bundle->tag);
 426 }
 427
 428 /* Registers/SSA are distinguish in the backend by the bottom-most bit */
 429
 430 #define IS_REG (1)
 431
 432 static inline unsigned
 433 make_compiler_temp(compiler_context *ctx)
 434 {
 435         return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
 436 }
 437
 438 static inline unsigned
 439 make_compiler_temp_reg(compiler_context *ctx)
 440 {
 441         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | IS_REG;
 442 }
 443
 444 static inline unsigned
 445 nir_ssa_index(nir_ssa_def *ssa)
 446 {
 447         return (ssa->index << 1) | 0;
 448 }
 449
 450 static inline unsigned
 451 nir_src_index(compiler_context *ctx, nir_src *src)
 452 {
 453         if (src->is_ssa)
 454                 return nir_ssa_index(src->ssa);
 455         else {
 456                 assert(!src->reg.indirect);
 457                 return (src->reg.reg->index << 1) | IS_REG;
 458         }
 459 }
 460
 461 static inline unsigned
 462 nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
 463 {
 464         return nir_src_index(ctx, &src->src);
 465 }
 466
 467 static inline unsigned
 468 nir_dest_index(nir_dest *dst)
 469 {
 470         if (dst->is_ssa)
 471                 return (dst->ssa.index << 1) | 0;
 472         else {
 473                 assert(!dst->reg.indirect);
 474                 return (dst->reg.reg->index << 1) | IS_REG;
 475         }
 476 }
 477
 478
 479
 480 /* MIR manipulation */
 481
 482 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 483 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 484 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 485 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new);
 486 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 487 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned *swizzle);
 488 bool mir_single_use(compiler_context *ctx, unsigned value);
 489 bool mir_special_index(compiler_context *ctx, unsigned idx);
 490 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 491 bool mir_is_written_before(compiler_context *ctx, midgard_instruction *ins, unsigned node);
 492 uint16_t mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node);
 493 uint16_t mir_bytemask_of_read_components_index(midgard_instruction *ins, unsigned i);
 494 midgard_reg_mode mir_typesize(midgard_instruction *ins);
 495 midgard_reg_mode mir_srcsize(midgard_instruction *ins, unsigned i);
 496 unsigned mir_bytes_for_mode(midgard_reg_mode mode);
 497 midgard_reg_mode mir_mode_for_destsize(unsigned size);
 498 uint16_t mir_from_bytemask(uint16_t bytemask, midgard_reg_mode mode);
 499 uint16_t mir_bytemask(midgard_instruction *ins);
 500 uint16_t mir_round_bytemask_up(uint16_t mask, midgard_reg_mode mode);
 501 void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
 502 unsigned mir_upper_override(midgard_instruction *ins);
 503
 504 /* MIR printing */
 505
 506 void mir_print_instruction(midgard_instruction *ins);
 507 void mir_print_bundle(midgard_bundle *ctx);
 508 void mir_print_block(midgard_block *block);
 509 void mir_print_shader(compiler_context *ctx);
 510 bool mir_nontrivial_source2_mod(midgard_instruction *ins);
 511 bool mir_nontrivial_source2_mod_simple(midgard_instruction *ins);
 512 bool mir_nontrivial_outmod(midgard_instruction *ins);
 513
 514 void mir_insert_instruction_before_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 515 void mir_insert_instruction_after_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 516 void mir_flip(midgard_instruction *ins);
 517 void mir_compute_temp_count(compiler_context *ctx);
 518
 519 void mir_set_offset(compiler_context *ctx, midgard_instruction *ins, nir_src *offset, bool is_shared);
 520
 521 /* 'Intrinsic' move for aliasing */
 522
 523 static inline midgard_instruction
 524 v_mov(unsigned src, unsigned dest)
 525 {
 526         midgard_instruction ins = {
 527                 .type = TAG_ALU_4,
 528                 .mask = 0xF,
 529                 .src = { ~0, src, ~0, ~0 },
 530                 .swizzle = SWIZZLE_IDENTITY,
 531                 .dest = dest,
 532                 .alu = {
 533                         .op = midgard_alu_op_imov,
 534                         .reg_mode = midgard_reg_mode_32,
 535                         .dest_override = midgard_dest_override_none,
 536                         .outmod = midgard_outmod_int_wrap
 537                 },
 538         };
 539
 540         return ins;
 541 }
 542
 543 /* Broad types of register classes so we can handle special
 544  * registers */
 545
 546 #define REG_CLASS_WORK          0
 547 #define REG_CLASS_LDST          1
 548 #define REG_CLASS_TEXR          3
 549 #define REG_CLASS_TEXW          4
 550
 551 /* Like a move, but to thread local storage! */
 552
 553 static inline midgard_instruction
 554 v_load_store_scratch(
 555                 unsigned srcdest,
 556                 unsigned index,
 557                 bool is_store,
 558                 unsigned mask)
 559 {
 560         /* We index by 32-bit vec4s */
 561         unsigned byte = (index * 4 * 4);
 562
 563         midgard_instruction ins = {
 564                 .type = TAG_LOAD_STORE_4,
 565                 .mask = mask,
 566                 .dest = ~0,
 567                 .src = { ~0, ~0, ~0, ~0 },
 568                 .swizzle = SWIZZLE_IDENTITY_4,
 569                 .load_store = {
 570                         .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
 571
 572                         /* For register spilling - to thread local storage */
 573                         .arg_1 = 0xEA,
 574                         .arg_2 = 0x1E,
 575                 },
 576
 577                 /* If we spill an unspill, RA goes into an infinite loop */
 578                 .no_spill = (1 << REG_CLASS_WORK)
 579         };
 580
 581         ins.constants.u32[0] = byte;
 582
 583         if (is_store) {
 584                 ins.src[0] = srcdest;
 585
 586                 /* Ensure we are tightly swizzled so liveness analysis is
 587                  * correct */
 588
 589                 for (unsigned i = 0; i < 4; ++i) {
 590                         if (!(mask & (1 << i)))
 591                                 ins.swizzle[0][i] = COMPONENT_X;
 592                 }
 593         } else
 594                 ins.dest = srcdest;
 595
 596         return ins;
 597 }
 598
 599 static inline bool
 600 mir_has_arg(midgard_instruction *ins, unsigned arg)
 601 {
 602         if (!ins)
 603                 return false;
 604
 605         mir_foreach_src(ins, i) {
 606                 if (ins->src[i] == arg)
 607                         return true;
 608         }
 609
 610         return false;
 611 }
 612
 613 /* Scheduling */
 614
 615 void midgard_schedule_program(compiler_context *ctx);
 616
 617 void mir_ra(compiler_context *ctx);
 618 void mir_squeeze_index(compiler_context *ctx);
 619 void mir_lower_special_reads(compiler_context *ctx);
 620 void mir_liveness_ins_update(uint16_t *live, midgard_instruction *ins, unsigned max);
 621 void mir_compute_liveness(compiler_context *ctx);
 622 void mir_invalidate_liveness(compiler_context *ctx);
 623 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 624
 625 void mir_create_pipeline_registers(compiler_context *ctx);
 626 void midgard_promote_uniforms(compiler_context *ctx);
 627
 628 void
 629 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
 630
 631 void
 632 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
 633
 634 bool mir_op_computes_derivatives(gl_shader_stage stage, unsigned op);
 635
 636 /* Final emission */
 637
 638 void emit_binary_bundle(
 639         compiler_context *ctx,
 640         midgard_bundle *bundle,
 641         struct util_dynarray *emission,
 642         int next_tag);
 643
 644 bool
 645 nir_undef_to_zero(nir_shader *shader);
 646
 647 void midgard_nir_lod_errata(nir_shader *shader);
 648
 649 /* Optimizations */
 650
 651 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 652 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 653 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 654 bool midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block);
 655 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 656
 657 void midgard_lower_invert(compiler_context *ctx, midgard_block *block);
 658 bool midgard_opt_not_propagate(compiler_context *ctx, midgard_block *block);
 659 bool midgard_opt_fuse_src_invert(compiler_context *ctx, midgard_block *block);
 660 bool midgard_opt_fuse_dest_invert(compiler_context *ctx, midgard_block *block);
 661 bool midgard_opt_csel_invert(compiler_context *ctx, midgard_block *block);
 662 bool midgard_opt_promote_fmov(compiler_context *ctx, midgard_block *block);
 663 bool midgard_opt_drop_cmp_invert(compiler_context *ctx, midgard_block *block);
 664 bool midgard_opt_invert_branch(compiler_context *ctx, midgard_block *block);
 665
 666 #endif