src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30 #include "midgard_ops.h"
  31
  32 #include "util/hash_table.h"
  33 #include "util/u_dynarray.h"
  34 #include "util/set.h"
  35 #include "util/list.h"
  36
  37 #include "main/mtypes.h"
  38 #include "compiler/nir_types.h"
  39 #include "compiler/nir/nir.h"
  40 #include "panfrost/util/pan_ir.h"
  41 #include "panfrost/util/lcra.h"
  42
  43 /* Forward declare */
  44 struct midgard_block;
  45
  46 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  47  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  48  * instruction is actually a discard op. */
  49
  50 #define TARGET_GOTO 0
  51 #define TARGET_BREAK 1
  52 #define TARGET_CONTINUE 2
  53 #define TARGET_DISCARD 3
  54 #define TARGET_TILEBUF_WAIT 4
  55
  56 typedef struct midgard_branch {
  57         /* If conditional, the condition is specified in r31.w */
  58         bool conditional;
  59
  60         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  61         bool invert_conditional;
  62
  63         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  64         unsigned target_type;
  65
  66         /* The actual target */
  67         union {
  68                 int target_block;
  69                 int target_break;
  70                 int target_continue;
  71         };
  72 } midgard_branch;
  73
  74 #define PAN_WRITEOUT_C 1
  75 #define PAN_WRITEOUT_Z 2
  76 #define PAN_WRITEOUT_S 4
  77
  78 /* Generic in-memory data type repesenting a single logical instruction, rather
  79  * than a single instruction group. This is the preferred form for code gen.
  80  * Multiple midgard_insturctions will later be combined during scheduling,
  81  * though this is not represented in this structure.  Its format bridges
  82  * the low-level binary representation with the higher level semantic meaning.
  83  *
  84  * Notably, it allows registers to be specified as block local SSA, for code
  85  * emitted before the register allocation pass.
  86  */
  87
  88 #define MIR_SRC_COUNT 4
  89 #define MIR_VEC_COMPONENTS 16
  90
  91 typedef struct midgard_instruction {
  92         /* Must be first for casting */
  93         struct list_head link;
  94
  95         unsigned type; /* ALU, load/store, texture */
  96
  97         /* Instruction arguments represented as block-local SSA
  98          * indices, rather than registers. ~0 means unused. */
  99         unsigned src[MIR_SRC_COUNT];
 100         unsigned dest;
 101
 102         /* vec16 swizzle, unpacked, per source */
 103         unsigned swizzle[MIR_SRC_COUNT][MIR_VEC_COMPONENTS];
 104
 105         /* Types! */
 106         nir_alu_type src_types[MIR_SRC_COUNT];
 107         nir_alu_type dest_type;
 108
 109         /* Packing ops have non-32-bit dest types even though they functionally
 110          * work at the 32-bit level, use this as a signal to disable copyprop.
 111          * We maybe need synthetic pack ops instead. */
 112         bool is_pack;
 113
 114         /* Modifiers, depending on type */
 115         union {
 116                 struct {
 117                         bool src_abs[MIR_SRC_COUNT];
 118                         bool src_neg[MIR_SRC_COUNT];
 119                 };
 120
 121                 struct {
 122                         bool src_shift[MIR_SRC_COUNT];
 123                 };
 124         };
 125
 126         /* Out of the union for csel (could maybe be fixed..) */
 127         bool src_invert[MIR_SRC_COUNT];
 128
 129         /* If the op supports it */
 130         enum midgard_roundmode roundmode;
 131
 132         /* For textures: should helpers execute this instruction (instead of
 133          * just helping with derivatives)? Should helpers terminate after? */
 134         bool helper_terminate;
 135         bool helper_execute;
 136
 137         /* I.e. (1 << alu_bit) */
 138         int unit;
 139
 140         bool has_constants;
 141         midgard_constants constants;
 142         uint16_t inline_constant;
 143         bool has_blend_constant;
 144         bool has_inline_constant;
 145
 146         bool compact_branch;
 147         uint8_t writeout;
 148         bool last_writeout;
 149
 150         /* Masks in a saneish format. One bit per channel, not packed fancy.
 151          * Use this instead of the op specific ones, and switch over at emit
 152          * time */
 153
 154         uint16_t mask;
 155
 156         /* Hint for the register allocator not to spill the destination written
 157          * from this instruction (because it is a spill/unspill node itself).
 158          * Bitmask of spilled classes */
 159
 160         unsigned no_spill;
 161
 162         /* Generic hint for intra-pass use */
 163         bool hint;
 164
 165         /* During scheduling, the backwards dependency graph
 166          * (DAG). nr_dependencies is the number of unscheduled
 167          * instructions that must still be scheduled after
 168          * (before) this instruction. dependents are which
 169          * instructions need to be scheduled before (after) this
 170          * instruction. */
 171
 172         unsigned nr_dependencies;
 173         BITSET_WORD *dependents;
 174
 175         /* Use this in conjunction with `type` */
 176         unsigned op;
 177
 178         /* This refers to midgard_outmod_float or midgard_outmod_int.
 179          * In case of a ALU op, use midgard_is_integer_out_op() to know which
 180          * one is used.
 181          * If it's a texture op, it's always midgard_outmod_float. */
 182         unsigned outmod;
 183
 184         union {
 185                 midgard_load_store_word load_store;
 186                 midgard_texture_word texture;
 187
 188                 midgard_branch branch;
 189         };
 190 } midgard_instruction;
 191
 192 typedef struct midgard_block {
 193         pan_block base;
 194
 195         bool scheduled;
 196
 197         /* List of midgard_bundles emitted (after the scheduler has run) */
 198         struct util_dynarray bundles;
 199
 200         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 201         unsigned quadword_count;
 202
 203         /* Indicates this is a fixed-function fragment epilogue block */
 204         bool epilogue;
 205
 206         /* Are helper invocations required by this block? */
 207         bool helpers_in;
 208 } midgard_block;
 209
 210 typedef struct midgard_bundle {
 211         /* Tag for the overall bundle */
 212         int tag;
 213
 214         /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
 215          * sadd, vadd, smul, vlut, branch) */
 216         int instruction_count;
 217         midgard_instruction *instructions[6];
 218
 219         /* Bundle-wide ALU configuration */
 220         int padding;
 221         int control;
 222         bool has_embedded_constants;
 223         midgard_constants constants;
 224         bool has_blend_constant;
 225         bool last_writeout;
 226 } midgard_bundle;
 227
 228 enum midgard_rt_id {
 229         MIDGARD_COLOR_RT0 = 0,
 230         MIDGARD_COLOR_RT1,
 231         MIDGARD_COLOR_RT2,
 232         MIDGARD_COLOR_RT3,
 233         MIDGARD_COLOR_RT4,
 234         MIDGARD_COLOR_RT5,
 235         MIDGARD_COLOR_RT6,
 236         MIDGARD_COLOR_RT7,
 237         MIDGARD_ZS_RT,
 238         MIDGARD_NUM_RTS,
 239 };
 240
 241 typedef struct compiler_context {
 242         nir_shader *nir;
 243         gl_shader_stage stage;
 244
 245         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 246         bool is_blend;
 247
 248         /* Render target number for a keyed blend shader. Depends on is_blend */
 249         unsigned blend_rt;
 250
 251         /* Index to precolour to r0 for an input blend colour */
 252         unsigned blend_input;
 253
 254         /* Index to precolour to r2 for a dual-source blend colour */
 255         unsigned blend_src1;
 256
 257         /* Tracking for blend constant patching */
 258         int blend_constant_offset;
 259
 260         /* Number of bytes used for Thread Local Storage */
 261         unsigned tls_size;
 262
 263         /* Count of spills and fills for shaderdb */
 264         unsigned spills;
 265         unsigned fills;
 266
 267         /* Current NIR function */
 268         nir_function *func;
 269
 270         /* Allocated compiler temporary counter */
 271         unsigned temp_alloc;
 272
 273         /* Unordered list of midgard_blocks */
 274         int block_count;
 275         struct list_head blocks;
 276
 277         /* TODO merge with block_count? */
 278         unsigned block_source_count;
 279
 280         /* List of midgard_instructions emitted for the current block */
 281         midgard_block *current_block;
 282
 283         /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
 284         midgard_block *after_block;
 285
 286         /* The current "depth" of the loop, for disambiguating breaks/continues
 287          * when using nested loops */
 288         int current_loop_depth;
 289
 290         /* Total number of loops for shader-db */
 291         unsigned loop_count;
 292
 293         /* Constants which have been loaded, for later inlining */
 294         struct hash_table_u64 *ssa_constants;
 295
 296         int temp_count;
 297         int max_hash;
 298
 299         /* Set of NIR indices that were already emitted as outmods */
 300         BITSET_WORD *already_emitted;
 301
 302         /* Just the count of the max register used. Higher count => higher
 303          * register pressure */
 304         int work_registers;
 305
 306         /* The number of uniforms allowable for the fast path */
 307         int uniform_cutoff;
 308
 309         /* Count of instructions emitted from NIR overall, across all blocks */
 310         int instruction_count;
 311
 312         unsigned quadword_count;
 313
 314         /* Bitmask of valid metadata */
 315         unsigned metadata;
 316
 317         /* Model-specific quirk set */
 318         uint32_t quirks;
 319
 320         /* Writeout instructions for each render target */
 321         midgard_instruction *writeout_branch[MIDGARD_NUM_RTS];
 322
 323         struct panfrost_sysvals sysvals;
 324 } compiler_context;
 325
 326 /* Per-block live_in/live_out */
 327 #define MIDGARD_METADATA_LIVENESS (1 << 0)
 328
 329 /* Helpers for manipulating the above structures (forming the driver IR) */
 330
 331 /* Append instruction to end of current block */
 332
 333 static inline midgard_instruction *
 334 mir_upload_ins(struct compiler_context *ctx, struct midgard_instruction ins)
 335 {
 336         midgard_instruction *heap = ralloc(ctx, struct midgard_instruction);
 337         memcpy(heap, &ins, sizeof(ins));
 338         return heap;
 339 }
 340
 341 static inline midgard_instruction *
 342 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 343 {
 344         midgard_instruction *u = mir_upload_ins(ctx, ins);
 345         list_addtail(&u->link, &ctx->current_block->base.instructions);
 346         return u;
 347 }
 348
 349 static inline struct midgard_instruction *
 350 mir_insert_instruction_before(struct compiler_context *ctx,
 351                               struct midgard_instruction *tag,
 352                               struct midgard_instruction ins)
 353 {
 354         struct midgard_instruction *u = mir_upload_ins(ctx, ins);
 355         list_addtail(&u->link, &tag->link);
 356         return u;
 357 }
 358
 359 static inline void
 360 mir_remove_instruction(struct midgard_instruction *ins)
 361 {
 362         list_del(&ins->link);
 363 }
 364
 365 static inline midgard_instruction*
 366 mir_prev_op(struct midgard_instruction *ins)
 367 {
 368         return list_last_entry(&(ins->link), midgard_instruction, link);
 369 }
 370
 371 static inline midgard_instruction*
 372 mir_next_op(struct midgard_instruction *ins)
 373 {
 374         return list_first_entry(&(ins->link), midgard_instruction, link);
 375 }
 376
 377 #define mir_foreach_block(ctx, v) \
 378         list_for_each_entry(pan_block, v, &ctx->blocks, link)
 379
 380 #define mir_foreach_block_from(ctx, from, v) \
 381         list_for_each_entry_from(pan_block, v, &from->base, &ctx->blocks, link)
 382
 383 #define mir_foreach_instr_in_block(block, v) \
 384         list_for_each_entry(struct midgard_instruction, v, &block->base.instructions, link)
 385 #define mir_foreach_instr_in_block_rev(block, v) \
 386         list_for_each_entry_rev(struct midgard_instruction, v, &block->base.instructions, link)
 387
 388 #define mir_foreach_instr_in_block_safe(block, v) \
 389         list_for_each_entry_safe(struct midgard_instruction, v, &block->base.instructions, link)
 390
 391 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 392         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->base.instructions, link)
 393
 394 #define mir_foreach_instr_in_block_from(block, v, from) \
 395         list_for_each_entry_from(struct midgard_instruction, v, from, &block->base.instructions, link)
 396
 397 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 398         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->base.instructions, link)
 399
 400 #define mir_foreach_bundle_in_block(block, v) \
 401         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 402
 403 #define mir_foreach_bundle_in_block_rev(block, v) \
 404         util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
 405
 406 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
 407         midgard_instruction* v; \
 408         signed i = 0; \
 409         mir_foreach_bundle_in_block_rev(block, _bundle) \
 410                 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
 411                                 i >= 0; \
 412                                 --i, v = (i >= 0) ? _bundle->instructions[i] : NULL) \
 413
 414 #define mir_foreach_instr_global(ctx, v) \
 415         mir_foreach_block(ctx, v_block) \
 416                 mir_foreach_instr_in_block(((midgard_block *) v_block), v)
 417
 418 #define mir_foreach_instr_global_safe(ctx, v) \
 419         mir_foreach_block(ctx, v_block) \
 420                 mir_foreach_instr_in_block_safe(((midgard_block *) v_block), v)
 421
 422 /* Based on set_foreach, expanded with automatic type casts */
 423
 424 #define mir_foreach_predecessor(blk, v) \
 425         struct set_entry *_entry_##v; \
 426         struct midgard_block *v; \
 427         for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
 428                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 429                 _entry_##v != NULL; \
 430                 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
 431                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
 432
 433 #define mir_foreach_src(ins, v) \
 434         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 435
 436 static inline midgard_instruction *
 437 mir_last_in_block(struct midgard_block *block)
 438 {
 439         return list_last_entry(&block->base.instructions, struct midgard_instruction, link);
 440 }
 441
 442 static inline midgard_block *
 443 mir_get_block(compiler_context *ctx, int idx)
 444 {
 445         struct list_head *lst = &ctx->blocks;
 446
 447         while ((idx--) + 1)
 448                 lst = lst->next;
 449
 450         return (struct midgard_block *) lst;
 451 }
 452
 453 static inline bool
 454 mir_is_alu_bundle(midgard_bundle *bundle)
 455 {
 456         return IS_ALU(bundle->tag);
 457 }
 458
 459 static inline unsigned
 460 make_compiler_temp(compiler_context *ctx)
 461 {
 462         return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
 463 }
 464
 465 static inline unsigned
 466 make_compiler_temp_reg(compiler_context *ctx)
 467 {
 468         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | PAN_IS_REG;
 469 }
 470
 471 static inline unsigned
 472 nir_ssa_index(nir_ssa_def *ssa)
 473 {
 474         return (ssa->index << 1) | 0;
 475 }
 476
 477 static inline unsigned
 478 nir_src_index(compiler_context *ctx, nir_src *src)
 479 {
 480         if (src->is_ssa)
 481                 return nir_ssa_index(src->ssa);
 482         else {
 483                 assert(!src->reg.indirect);
 484                 return (src->reg.reg->index << 1) | PAN_IS_REG;
 485         }
 486 }
 487
 488 static inline unsigned
 489 nir_dest_index(nir_dest *dst)
 490 {
 491         if (dst->is_ssa)
 492                 return (dst->ssa.index << 1) | 0;
 493         else {
 494                 assert(!dst->reg.indirect);
 495                 return (dst->reg.reg->index << 1) | PAN_IS_REG;
 496         }
 497 }
 498
 499
 500
 501 /* MIR manipulation */
 502
 503 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 504 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 505 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 506 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new);
 507 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 508 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned *swizzle);
 509 bool mir_single_use(compiler_context *ctx, unsigned value);
 510 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 511 uint16_t mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node);
 512 uint16_t mir_bytemask_of_read_components_index(midgard_instruction *ins, unsigned i);
 513 uint16_t mir_from_bytemask(uint16_t bytemask, unsigned bits);
 514 uint16_t mir_bytemask(midgard_instruction *ins);
 515 uint16_t mir_round_bytemask_up(uint16_t mask, unsigned bits);
 516 void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
 517 signed mir_upper_override(midgard_instruction *ins, unsigned inst_size);
 518 unsigned mir_components_for_type(nir_alu_type T);
 519 unsigned max_bitsize_for_alu(midgard_instruction *ins);
 520 midgard_reg_mode reg_mode_for_bitsize(unsigned bitsize);
 521
 522 /* MIR printing */
 523
 524 void mir_print_instruction(midgard_instruction *ins);
 525 void mir_print_bundle(midgard_bundle *ctx);
 526 void mir_print_block(midgard_block *block);
 527 void mir_print_shader(compiler_context *ctx);
 528 bool mir_nontrivial_mod(midgard_instruction *ins, unsigned i, bool check_swizzle);
 529 bool mir_nontrivial_outmod(midgard_instruction *ins);
 530
 531 void mir_insert_instruction_before_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 532 void mir_insert_instruction_after_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 533 void mir_flip(midgard_instruction *ins);
 534 void mir_compute_temp_count(compiler_context *ctx);
 535
 536 void mir_set_offset(compiler_context *ctx, midgard_instruction *ins, nir_src *offset, bool is_shared);
 537
 538 /* 'Intrinsic' move for aliasing */
 539
 540 static inline midgard_instruction
 541 v_mov(unsigned src, unsigned dest)
 542 {
 543         midgard_instruction ins = {
 544                 .type = TAG_ALU_4,
 545                 .mask = 0xF,
 546                 .src = { ~0, src, ~0, ~0 },
 547                 .src_types = { 0, nir_type_uint32 },
 548                 .swizzle = SWIZZLE_IDENTITY,
 549                 .dest = dest,
 550                 .dest_type = nir_type_uint32,
 551                 .op = midgard_alu_op_imov,
 552                 .outmod = midgard_outmod_int_wrap
 553         };
 554
 555         return ins;
 556 }
 557
 558 /* Broad types of register classes so we can handle special
 559  * registers */
 560
 561 #define REG_CLASS_WORK          0
 562 #define REG_CLASS_LDST          1
 563 #define REG_CLASS_TEXR          3
 564 #define REG_CLASS_TEXW          4
 565
 566 /* Like a move, but to thread local storage! */
 567
 568 static inline midgard_instruction
 569 v_load_store_scratch(
 570                 unsigned srcdest,
 571                 unsigned index,
 572                 bool is_store,
 573                 unsigned mask)
 574 {
 575         /* We index by 32-bit vec4s */
 576         unsigned byte = (index * 4 * 4);
 577
 578         midgard_instruction ins = {
 579                 .type = TAG_LOAD_STORE_4,
 580                 .mask = mask,
 581                 .dest_type = nir_type_uint32,
 582                 .dest = ~0,
 583                 .src = { ~0, ~0, ~0, ~0 },
 584                 .swizzle = SWIZZLE_IDENTITY_4,
 585                 .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
 586                 .load_store = {
 587                         /* For register spilling - to thread local storage */
 588                         .arg_1 = 0xEA,
 589                         .arg_2 = 0x1E,
 590                 },
 591
 592                 /* If we spill an unspill, RA goes into an infinite loop */
 593                 .no_spill = (1 << REG_CLASS_WORK)
 594         };
 595
 596         ins.constants.u32[0] = byte;
 597
 598         if (is_store) {
 599                 ins.src[0] = srcdest;
 600                 ins.src_types[0] = nir_type_uint32;
 601
 602                 /* Ensure we are tightly swizzled so liveness analysis is
 603                  * correct */
 604
 605                 for (unsigned i = 0; i < 4; ++i) {
 606                         if (!(mask & (1 << i)))
 607                                 ins.swizzle[0][i] = COMPONENT_X;
 608                 }
 609         } else
 610                 ins.dest = srcdest;
 611
 612         return ins;
 613 }
 614
 615 static inline bool
 616 mir_has_arg(midgard_instruction *ins, unsigned arg)
 617 {
 618         if (!ins)
 619                 return false;
 620
 621         mir_foreach_src(ins, i) {
 622                 if (ins->src[i] == arg)
 623                         return true;
 624         }
 625
 626         return false;
 627 }
 628
 629 /* Scheduling */
 630
 631 void midgard_schedule_program(compiler_context *ctx);
 632
 633 void mir_ra(compiler_context *ctx);
 634 void mir_squeeze_index(compiler_context *ctx);
 635 void mir_lower_special_reads(compiler_context *ctx);
 636 void mir_liveness_ins_update(uint16_t *live, midgard_instruction *ins, unsigned max);
 637 void mir_compute_liveness(compiler_context *ctx);
 638 void mir_invalidate_liveness(compiler_context *ctx);
 639 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 640
 641 void mir_create_pipeline_registers(compiler_context *ctx);
 642 void midgard_promote_uniforms(compiler_context *ctx);
 643
 644 void
 645 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
 646
 647 void
 648 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
 649
 650 bool mir_op_computes_derivatives(gl_shader_stage stage, unsigned op);
 651
 652 void mir_analyze_helper_terminate(compiler_context *ctx);
 653 void mir_analyze_helper_requirements(compiler_context *ctx);
 654
 655 /* Final emission */
 656
 657 void emit_binary_bundle(
 658         compiler_context *ctx,
 659         midgard_block *block,
 660         midgard_bundle *bundle,
 661         struct util_dynarray *emission,
 662         int next_tag);
 663
 664 bool
 665 nir_undef_to_zero(nir_shader *shader);
 666 bool nir_fuse_io_16(nir_shader *shader);
 667
 668 void midgard_nir_lod_errata(nir_shader *shader);
 669
 670 unsigned midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx);
 671
 672 /* Optimizations */
 673
 674 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 675 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 676 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 677 bool midgard_opt_dead_code_eliminate(compiler_context *ctx);
 678 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 679
 680 #endif