panfrost: Pipe the GPU ID into compiler and disassembler
[mesa.git] / src / panfrost / midgard / disassemble.c
1 /* Author(s):
2 * Connor Abbott
3 * Alyssa Rosenzweig
4 *
5 * Copyright (c) 2013 Connor Abbott (connor@abbott.cx)
6 * Copyright (c) 2018 Alyssa Rosenzweig (alyssa@rosenzweig.io)
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #include <stdio.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <assert.h>
31 #include <inttypes.h>
32 #include <ctype.h>
33 #include <string.h>
34 #include "midgard.h"
35 #include "midgard-parse.h"
36 #include "midgard_ops.h"
37 #include "disassemble.h"
38 #include "helpers.h"
39 #include "util/half_float.h"
40 #include "util/u_math.h"
41
42 #define DEFINE_CASE(define, str) case define: { printf(str); break; }
43
44 static unsigned *midg_tags;
45 static bool is_instruction_int = false;
46
47 /* Stats */
48
49 static struct midgard_disasm_stats midg_stats;
50
51 /* Prints a short form of the tag for branching, the minimum needed to be
52 * legible and unambiguous */
53
54 static void
55 print_tag_short(unsigned tag)
56 {
57 switch (midgard_word_types[tag]) {
58 case midgard_word_type_texture:
59 printf("tex/%X", tag);
60 break;
61
62 case midgard_word_type_load_store:
63 printf("ldst");
64 break;
65
66 case midgard_word_type_alu:
67 printf("alu%u/%X", midgard_word_size[tag], tag);
68 break;
69
70 default:
71 printf("%s%X", (tag > 0) ? "" : "unk", tag);
72 break;
73 }
74 }
75
76 static void
77 print_alu_opcode(midgard_alu_op op)
78 {
79 bool int_op = false;
80
81 if (alu_opcode_props[op].name) {
82 printf("%s", alu_opcode_props[op].name);
83
84 int_op = midgard_is_integer_op(op);
85 } else
86 printf("alu_op_%02X", op);
87
88 /* For constant analysis */
89 is_instruction_int = int_op;
90 }
91
92 static void
93 print_ld_st_opcode(midgard_load_store_op op)
94 {
95 if (load_store_opcode_props[op].name)
96 printf("%s", load_store_opcode_props[op].name);
97 else
98 printf("ldst_op_%02X", op);
99 }
100
101 static bool is_embedded_constant_half = false;
102 static bool is_embedded_constant_int = false;
103
104 static char
105 prefix_for_bits(unsigned bits)
106 {
107 switch (bits) {
108 case 8:
109 return 'q';
110 case 16:
111 return 'h';
112 case 64:
113 return 'd';
114 default:
115 return 0;
116 }
117 }
118
119 /* For static analysis to ensure all registers are written at least once before
120 * use along the source code path (TODO: does this break done for complex CF?)
121 */
122
123 uint16_t midg_ever_written = 0;
124
125 static void
126 print_reg(unsigned reg, unsigned bits)
127 {
128 /* Perform basic static analysis for expanding constants correctly */
129
130 if (reg == 26) {
131 is_embedded_constant_int = is_instruction_int;
132 is_embedded_constant_half = (bits < 32);
133 }
134
135 unsigned uniform_reg = 23 - reg;
136 bool is_uniform = false;
137
138 /* For r8-r15, it could be a work or uniform. We distinguish based on
139 * the fact work registers are ALWAYS written before use, but uniform
140 * registers are NEVER written before use. */
141
142 if ((reg >= 8 && reg < 16) && !(midg_ever_written & (1 << reg)))
143 is_uniform = true;
144
145 /* r16-r23 are always uniform */
146
147 if (reg >= 16 && reg <= 23)
148 is_uniform = true;
149
150 /* Update the uniform count appropriately */
151
152 if (is_uniform)
153 midg_stats.uniform_count =
154 MAX2(uniform_reg + 1, midg_stats.uniform_count);
155
156 char prefix = prefix_for_bits(bits);
157
158 if (prefix)
159 putchar(prefix);
160
161 printf("r%u", reg);
162 }
163
164 static char *outmod_names_float[4] = {
165 "",
166 ".pos",
167 ".unk2",
168 ".sat"
169 };
170
171 static char *outmod_names_int[4] = {
172 ".isat",
173 ".usat",
174 "",
175 ".hi"
176 };
177
178 static char *srcmod_names_int[4] = {
179 "sext(",
180 "zext(",
181 "",
182 "("
183 };
184
185 static void
186 print_outmod(unsigned outmod, bool is_int)
187 {
188 printf("%s", is_int ? outmod_names_int[outmod] :
189 outmod_names_float[outmod]);
190 }
191
192 static void
193 print_quad_word(uint32_t *words, unsigned tabs)
194 {
195 unsigned i;
196
197 for (i = 0; i < 4; i++)
198 printf("0x%08X%s ", words[i], i == 3 ? "" : ",");
199
200 printf("\n");
201 }
202
203 static const char components[16] = "xyzwefghijklmnop";
204
205 /* Helper to print 4 chars of a swizzle */
206 static void
207 print_swizzle_helper(unsigned swizzle, bool upper)
208 {
209 for (unsigned i = 0; i < 4; ++i) {
210 unsigned c = (swizzle >> (i * 2)) & 3;
211 c += upper*4;
212 printf("%c", components[c]);
213 }
214 }
215
216 /* Helper to print 8 chars of a swizzle, duplicating over */
217 static void
218 print_swizzle_helper_8(unsigned swizzle, bool upper)
219 {
220 for (unsigned i = 0; i < 4; ++i) {
221 unsigned c = (swizzle >> (i * 2)) & 3;
222 c *= 2;
223 c += upper*8;
224 printf("%c%c", components[c], components[c+1]);
225 }
226 }
227
228 static void
229 print_swizzle_vec16(unsigned swizzle, bool rep_high, bool rep_low,
230 midgard_dest_override override)
231 {
232 printf(".");
233
234 if (override == midgard_dest_override_upper) {
235 if (rep_high)
236 printf(" /* rep_high */ ");
237 if (rep_low)
238 printf(" /* rep_low */ ");
239
240 if (!rep_high && rep_low)
241 print_swizzle_helper_8(swizzle, true);
242 else
243 print_swizzle_helper_8(swizzle, false);
244 } else {
245 print_swizzle_helper_8(swizzle, rep_high & 1);
246 print_swizzle_helper_8(swizzle, !(rep_low & 1));
247 }
248 }
249
250 static void
251 print_swizzle_vec8(unsigned swizzle, bool rep_high, bool rep_low)
252 {
253 printf(".");
254
255 print_swizzle_helper(swizzle, rep_high & 1);
256 print_swizzle_helper(swizzle, !(rep_low & 1));
257 }
258
259 static void
260 print_swizzle_vec4(unsigned swizzle, bool rep_high, bool rep_low)
261 {
262 if (rep_high)
263 printf(" /* rep_high */ ");
264 if (rep_low)
265 printf(" /* rep_low */ ");
266
267 if (swizzle == 0xE4) return; /* xyzw */
268
269 printf(".");
270 print_swizzle_helper(swizzle, 0);
271 }
272 static void
273 print_swizzle_vec2(unsigned swizzle, bool rep_high, bool rep_low)
274 {
275 if (rep_high)
276 printf(" /* rep_high */ ");
277 if (rep_low)
278 printf(" /* rep_low */ ");
279
280 if (swizzle == 0xE4) return; /* XY */
281
282 printf(".");
283
284 for (unsigned i = 0; i < 4; i += 2) {
285 unsigned a = (swizzle >> (i * 2)) & 3;
286 unsigned b = (swizzle >> ((i+1) * 2)) & 3;
287
288 /* Normally we're adjacent, but if there's an issue, don't make
289 * it ambiguous */
290
291 if (a & 0x1)
292 printf("[%c%c]", components[a], components[b]);
293 else if (a == b)
294 printf("%c", components[a >> 1]);
295 else if (b == (a + 1))
296 printf("%c", "XY"[a >> 1]);
297 else
298 printf("[%c%c]", components[a], components[b]);
299 }
300 }
301
302 static int
303 bits_for_mode(midgard_reg_mode mode)
304 {
305 switch (mode) {
306 case midgard_reg_mode_8:
307 return 8;
308 case midgard_reg_mode_16:
309 return 16;
310 case midgard_reg_mode_32:
311 return 32;
312 case midgard_reg_mode_64:
313 return 64;
314 default:
315 unreachable("Invalid reg mode");
316 return 0;
317 }
318 }
319
320 static int
321 bits_for_mode_halved(midgard_reg_mode mode, bool half)
322 {
323 unsigned bits = bits_for_mode(mode);
324
325 if (half)
326 bits >>= 1;
327
328 return bits;
329 }
330
331 static void
332 print_vector_src(unsigned src_binary,
333 midgard_reg_mode mode, unsigned reg,
334 midgard_dest_override override, bool is_int)
335 {
336 midgard_vector_alu_src *src = (midgard_vector_alu_src *)&src_binary;
337
338 /* Modifiers change meaning depending on the op's context */
339
340 midgard_int_mod int_mod = src->mod;
341
342 if (is_int) {
343 printf("%s", srcmod_names_int[int_mod]);
344 } else {
345 if (src->mod & MIDGARD_FLOAT_MOD_NEG)
346 printf("-");
347
348 if (src->mod & MIDGARD_FLOAT_MOD_ABS)
349 printf("abs(");
350 }
351
352 //register
353 unsigned bits = bits_for_mode_halved(mode, src->half);
354 print_reg(reg, bits);
355
356 //swizzle
357 if (bits == 16)
358 print_swizzle_vec8(src->swizzle, src->rep_high, src->rep_low);
359 else if (bits == 8)
360 print_swizzle_vec16(src->swizzle, src->rep_high, src->rep_low, override);
361 else if (bits == 32)
362 print_swizzle_vec4(src->swizzle, src->rep_high, src->rep_low);
363 else if (bits == 64)
364 print_swizzle_vec2(src->swizzle, src->rep_high, src->rep_low);
365
366 /* Since we wrapped with a function-looking thing */
367
368 if (is_int && int_mod == midgard_int_shift)
369 printf(") << %u", bits);
370 else if ((is_int && (int_mod != midgard_int_normal))
371 || (!is_int && src->mod & MIDGARD_FLOAT_MOD_ABS))
372 printf(")");
373 }
374
375 static uint16_t
376 decode_vector_imm(unsigned src2_reg, unsigned imm)
377 {
378 uint16_t ret;
379 ret = src2_reg << 11;
380 ret |= (imm & 0x7) << 8;
381 ret |= (imm >> 3) & 0xFF;
382 return ret;
383 }
384
385 static void
386 print_immediate(uint16_t imm)
387 {
388 if (is_instruction_int)
389 printf("#%u", imm);
390 else
391 printf("#%g", _mesa_half_to_float(imm));
392 }
393
394 static void
395 update_dest(unsigned reg)
396 {
397 /* We should record writes as marking this as a work register. Store
398 * the max register in work_count; we'll add one at the end */
399
400 if (reg < 16) {
401 midg_stats.work_count = MAX2(reg, midg_stats.work_count);
402 midg_ever_written |= (1 << reg);
403 }
404 }
405
406 static void
407 print_dest(unsigned reg, midgard_reg_mode mode, midgard_dest_override override)
408 {
409 /* Depending on the mode and override, we determine the type of
410 * destination addressed. Absent an override, we address just the
411 * type of the operation itself */
412
413 unsigned bits = bits_for_mode(mode);
414
415 if (override != midgard_dest_override_none)
416 bits /= 2;
417
418 update_dest(reg);
419 print_reg(reg, bits);
420 }
421
422 static void
423 print_mask_vec16(uint8_t mask, midgard_dest_override override)
424 {
425 printf(".");
426
427 for (unsigned i = 0; i < 8; i++) {
428 if (mask & (1 << i))
429 printf("%c%c",
430 components[i*2 + 0],
431 components[i*2 + 1]);
432 }
433 }
434
435 /* For 16-bit+ masks, we read off from the 8-bit mask field. For 16-bit (vec8),
436 * it's just one bit per channel, easy peasy. For 32-bit (vec4), it's one bit
437 * per channel with one duplicate bit in the middle. For 64-bit (vec2), it's
438 * one-bit per channel with _3_ duplicate bits in the middle. Basically, just
439 * subdividing the 128-bit word in 16-bit increments. For 64-bit, we uppercase
440 * the mask to make it obvious what happened */
441
442 static void
443 print_mask(uint8_t mask, unsigned bits, midgard_dest_override override)
444 {
445 if (bits == 8) {
446 print_mask_vec16(mask, override);
447 return;
448 }
449
450 /* Skip 'complete' masks */
451
452 if (override == midgard_dest_override_none) {
453 if (bits >= 32 && mask == 0xFF) return;
454
455 if (bits == 16) {
456 if (mask == 0x0F)
457 return;
458 else if (mask == 0xF0) {
459 printf("'");
460 return;
461 }
462 }
463 }
464
465 printf(".");
466
467 unsigned skip = (bits / 16);
468 bool uppercase = bits > 32;
469 bool tripped = false;
470
471 /* To apply an upper destination override, we "shift" the alphabet.
472 * E.g. with an upper override on 32-bit, instead of xyzw, print efgh.
473 * For upper 16-bit, instead of xyzwefgh, print ijklmnop */
474
475 const char *alphabet = components;
476
477 if (override == midgard_dest_override_upper) {
478 unsigned components = 128 / bits;
479 alphabet += components;
480 }
481
482 for (unsigned i = 0; i < 8; i += skip) {
483 bool a = (mask & (1 << i)) != 0;
484
485 for (unsigned j = 1; j < skip; ++j) {
486 bool dupe = (mask & (1 << (i + j))) != 0;
487 tripped |= (dupe != a);
488 }
489
490 if (a) {
491 char c = alphabet[i / skip];
492
493 if (uppercase)
494 c = toupper(c);
495
496 printf("%c", c);
497 }
498 }
499
500 if (tripped)
501 printf(" /* %X */", mask);
502 }
503
504 /* Prints the 4-bit masks found in texture and load/store ops, as opposed to
505 * the 8-bit masks found in (vector) ALU ops */
506
507 static void
508 print_mask_4(unsigned mask)
509 {
510 if (mask == 0xF) return;
511
512 printf(".");
513
514 for (unsigned i = 0; i < 4; ++i) {
515 bool a = (mask & (1 << i)) != 0;
516 if (a)
517 printf("%c", components[i]);
518 }
519 }
520
521 static void
522 print_vector_field(const char *name, uint16_t *words, uint16_t reg_word,
523 unsigned tabs)
524 {
525 midgard_reg_info *reg_info = (midgard_reg_info *)&reg_word;
526 midgard_vector_alu *alu_field = (midgard_vector_alu *) words;
527 midgard_reg_mode mode = alu_field->reg_mode;
528 unsigned override = alu_field->dest_override;
529
530 /* For now, prefix instruction names with their unit, until we
531 * understand how this works on a deeper level */
532 printf("%s.", name);
533
534 print_alu_opcode(alu_field->op);
535
536 /* Postfix with the size to disambiguate if necessary */
537 char postfix = prefix_for_bits(bits_for_mode(mode));
538 bool size_ambiguous = override != midgard_dest_override_none;
539
540 if (size_ambiguous)
541 printf("%c", postfix ? postfix : 'r');
542
543 /* Print the outmod, if there is one */
544 print_outmod(alu_field->outmod,
545 midgard_is_integer_out_op(alu_field->op));
546
547 printf(" ");
548
549 /* Mask denoting status of 8-lanes */
550 uint8_t mask = alu_field->mask;
551
552 /* First, print the destination */
553 print_dest(reg_info->out_reg, mode, alu_field->dest_override);
554
555 if (override != midgard_dest_override_none) {
556 bool modeable = (mode != midgard_reg_mode_8);
557 bool known = override != 0x3; /* Unused value */
558
559 if (!(modeable && known))
560 printf("/* do%u */ ", override);
561 }
562
563 print_mask(mask, bits_for_mode(mode), override);
564
565 printf(", ");
566
567 bool is_int = midgard_is_integer_op(alu_field->op);
568 print_vector_src(alu_field->src1, mode, reg_info->src1_reg, override, is_int);
569
570 printf(", ");
571
572 if (reg_info->src2_imm) {
573 uint16_t imm = decode_vector_imm(reg_info->src2_reg, alu_field->src2 >> 2);
574 print_immediate(imm);
575 } else {
576 print_vector_src(alu_field->src2, mode,
577 reg_info->src2_reg, override, is_int);
578 }
579
580 midg_stats.instruction_count++;
581 printf("\n");
582 }
583
584 static void
585 print_scalar_src(unsigned src_binary, unsigned reg)
586 {
587 midgard_scalar_alu_src *src = (midgard_scalar_alu_src *)&src_binary;
588
589 if (src->negate)
590 printf("-");
591
592 if (src->abs)
593 printf("abs(");
594
595 print_reg(reg, src->full ? 32 : 16);
596
597 unsigned c = src->component;
598
599 if (src->full) {
600 assert((c & 1) == 0);
601 c >>= 1;
602 }
603
604 printf(".%c", components[c]);
605
606 if (src->abs)
607 printf(")");
608
609 }
610
611 static uint16_t
612 decode_scalar_imm(unsigned src2_reg, unsigned imm)
613 {
614 uint16_t ret;
615 ret = src2_reg << 11;
616 ret |= (imm & 3) << 9;
617 ret |= (imm & 4) << 6;
618 ret |= (imm & 0x38) << 2;
619 ret |= imm >> 6;
620 return ret;
621 }
622
623 static void
624 print_scalar_field(const char *name, uint16_t *words, uint16_t reg_word,
625 unsigned tabs)
626 {
627 midgard_reg_info *reg_info = (midgard_reg_info *)&reg_word;
628 midgard_scalar_alu *alu_field = (midgard_scalar_alu *) words;
629
630 if (alu_field->unknown)
631 printf("scalar ALU unknown bit set\n");
632
633 printf("%s.", name);
634 print_alu_opcode(alu_field->op);
635 print_outmod(alu_field->outmod,
636 midgard_is_integer_out_op(alu_field->op));
637 printf(" ");
638
639 bool full = alu_field->output_full;
640 update_dest(reg_info->out_reg);
641 print_reg(reg_info->out_reg, full ? 32 : 16);
642 unsigned c = alu_field->output_component;
643
644 if (full) {
645 assert((c & 1) == 0);
646 c >>= 1;
647 }
648
649 printf(".%c, ", components[c]);
650
651 print_scalar_src(alu_field->src1, reg_info->src1_reg);
652
653 printf(", ");
654
655 if (reg_info->src2_imm) {
656 uint16_t imm = decode_scalar_imm(reg_info->src2_reg,
657 alu_field->src2);
658 print_immediate(imm);
659 } else
660 print_scalar_src(alu_field->src2, reg_info->src2_reg);
661
662 midg_stats.instruction_count++;
663 printf("\n");
664 }
665
666 static void
667 print_branch_op(unsigned op)
668 {
669 switch (op) {
670 case midgard_jmp_writeout_op_branch_uncond:
671 printf("uncond.");
672 break;
673
674 case midgard_jmp_writeout_op_branch_cond:
675 printf("cond.");
676 break;
677
678 case midgard_jmp_writeout_op_writeout:
679 printf("write.");
680 break;
681
682 case midgard_jmp_writeout_op_tilebuffer_pending:
683 printf("tilebuffer.");
684 break;
685
686 case midgard_jmp_writeout_op_discard:
687 printf("discard.");
688 break;
689
690 default:
691 printf("unk%u.", op);
692 break;
693 }
694 }
695
696 static void
697 print_branch_cond(int cond)
698 {
699 switch (cond) {
700 case midgard_condition_write0:
701 printf("write0");
702 break;
703
704 case midgard_condition_false:
705 printf("false");
706 break;
707
708 case midgard_condition_true:
709 printf("true");
710 break;
711
712 case midgard_condition_always:
713 printf("always");
714 break;
715
716 default:
717 printf("unk%X", cond);
718 break;
719 }
720 }
721
722 static void
723 print_compact_branch_writeout_field(uint16_t word)
724 {
725 midgard_jmp_writeout_op op = word & 0x7;
726
727 switch (op) {
728 case midgard_jmp_writeout_op_branch_uncond: {
729 midgard_branch_uncond br_uncond;
730 memcpy((char *) &br_uncond, (char *) &word, sizeof(br_uncond));
731 printf("br.uncond ");
732
733 if (br_uncond.unknown != 1)
734 printf("unknown:%u, ", br_uncond.unknown);
735
736 if (br_uncond.offset >= 0)
737 printf("+");
738
739 printf("%d -> ", br_uncond.offset);
740 print_tag_short(br_uncond.dest_tag);
741 printf("\n");
742
743 break;
744 }
745
746 case midgard_jmp_writeout_op_branch_cond:
747 case midgard_jmp_writeout_op_writeout:
748 case midgard_jmp_writeout_op_discard:
749 default: {
750 midgard_branch_cond br_cond;
751 memcpy((char *) &br_cond, (char *) &word, sizeof(br_cond));
752
753 printf("br.");
754
755 print_branch_op(br_cond.op);
756 print_branch_cond(br_cond.cond);
757
758 printf(" ");
759
760 if (br_cond.offset >= 0)
761 printf("+");
762
763 printf("%d -> ", br_cond.offset);
764 print_tag_short(br_cond.dest_tag);
765 printf("\n");
766
767 break;
768 }
769 }
770
771 midg_stats.instruction_count++;
772 }
773
774 static void
775 print_extended_branch_writeout_field(uint8_t *words, unsigned next)
776 {
777 midgard_branch_extended br;
778 memcpy((char *) &br, (char *) words, sizeof(br));
779
780 printf("brx.");
781
782 print_branch_op(br.op);
783
784 /* Condition codes are a LUT in the general case, but simply repeated 8 times for single-channel conditions.. Check this. */
785
786 bool single_channel = true;
787
788 for (unsigned i = 0; i < 16; i += 2) {
789 single_channel &= (((br.cond >> i) & 0x3) == (br.cond & 0x3));
790 }
791
792 if (single_channel)
793 print_branch_cond(br.cond & 0x3);
794 else
795 printf("lut%X", br.cond);
796
797 if (br.unknown)
798 printf(".unknown%u", br.unknown);
799
800 printf(" ");
801
802 if (br.offset >= 0)
803 printf("+");
804
805 printf("%d -> ", br.offset);
806 print_tag_short(br.dest_tag);
807 printf("\n");
808
809 unsigned I = next + br.offset * 4;
810
811 if (midg_tags[I] && midg_tags[I] != br.dest_tag) {
812 printf("\t/* XXX TAG ERROR: jumping to ");
813 print_tag_short(br.dest_tag);
814 printf(" but tagged ");
815 print_tag_short(midg_tags[I]);
816 printf(" */\n");
817 }
818
819 midg_tags[I] = br.dest_tag;
820
821 midg_stats.instruction_count++;
822 }
823
824 static unsigned
825 num_alu_fields_enabled(uint32_t control_word)
826 {
827 unsigned ret = 0;
828
829 if ((control_word >> 17) & 1)
830 ret++;
831
832 if ((control_word >> 19) & 1)
833 ret++;
834
835 if ((control_word >> 21) & 1)
836 ret++;
837
838 if ((control_word >> 23) & 1)
839 ret++;
840
841 if ((control_word >> 25) & 1)
842 ret++;
843
844 return ret;
845 }
846
847 static float
848 float_bitcast(uint32_t integer)
849 {
850 union {
851 uint32_t i;
852 float f;
853 } v;
854
855 v.i = integer;
856 return v.f;
857 }
858
859 static void
860 print_alu_word(uint32_t *words, unsigned num_quad_words,
861 unsigned tabs, unsigned next)
862 {
863 uint32_t control_word = words[0];
864 uint16_t *beginning_ptr = (uint16_t *)(words + 1);
865 unsigned num_fields = num_alu_fields_enabled(control_word);
866 uint16_t *word_ptr = beginning_ptr + num_fields;
867 unsigned num_words = 2 + num_fields;
868
869 if ((control_word >> 16) & 1)
870 printf("unknown bit 16 enabled\n");
871
872 if ((control_word >> 17) & 1) {
873 print_vector_field("vmul", word_ptr, *beginning_ptr, tabs);
874 beginning_ptr += 1;
875 word_ptr += 3;
876 num_words += 3;
877 }
878
879 if ((control_word >> 18) & 1)
880 printf("unknown bit 18 enabled\n");
881
882 if ((control_word >> 19) & 1) {
883 print_scalar_field("sadd", word_ptr, *beginning_ptr, tabs);
884 beginning_ptr += 1;
885 word_ptr += 2;
886 num_words += 2;
887 }
888
889 if ((control_word >> 20) & 1)
890 printf("unknown bit 20 enabled\n");
891
892 if ((control_word >> 21) & 1) {
893 print_vector_field("vadd", word_ptr, *beginning_ptr, tabs);
894 beginning_ptr += 1;
895 word_ptr += 3;
896 num_words += 3;
897 }
898
899 if ((control_word >> 22) & 1)
900 printf("unknown bit 22 enabled\n");
901
902 if ((control_word >> 23) & 1) {
903 print_scalar_field("smul", word_ptr, *beginning_ptr, tabs);
904 beginning_ptr += 1;
905 word_ptr += 2;
906 num_words += 2;
907 }
908
909 if ((control_word >> 24) & 1)
910 printf("unknown bit 24 enabled\n");
911
912 if ((control_word >> 25) & 1) {
913 print_vector_field("lut", word_ptr, *beginning_ptr, tabs);
914 word_ptr += 3;
915 num_words += 3;
916 }
917
918 if ((control_word >> 26) & 1) {
919 print_compact_branch_writeout_field(*word_ptr);
920 word_ptr += 1;
921 num_words += 1;
922 }
923
924 if ((control_word >> 27) & 1) {
925 print_extended_branch_writeout_field((uint8_t *) word_ptr, next);
926 word_ptr += 3;
927 num_words += 3;
928 }
929
930 if (num_quad_words > (num_words + 7) / 8) {
931 assert(num_quad_words == (num_words + 15) / 8);
932 //Assume that the extra quadword is constants
933 void *consts = words + (4 * num_quad_words - 4);
934
935 if (is_embedded_constant_int) {
936 if (is_embedded_constant_half) {
937 int16_t *sconsts = (int16_t *) consts;
938 printf("sconstants %d, %d, %d, %d\n",
939 sconsts[0],
940 sconsts[1],
941 sconsts[2],
942 sconsts[3]);
943 } else {
944 uint32_t *iconsts = (uint32_t *) consts;
945 printf("iconstants 0x%X, 0x%X, 0x%X, 0x%X\n",
946 iconsts[0],
947 iconsts[1],
948 iconsts[2],
949 iconsts[3]);
950 }
951 } else {
952 if (is_embedded_constant_half) {
953 uint16_t *hconsts = (uint16_t *) consts;
954 printf("hconstants %g, %g, %g, %g\n",
955 _mesa_half_to_float(hconsts[0]),
956 _mesa_half_to_float(hconsts[1]),
957 _mesa_half_to_float(hconsts[2]),
958 _mesa_half_to_float(hconsts[3]));
959 } else {
960 uint32_t *fconsts = (uint32_t *) consts;
961 printf("fconstants %g, %g, %g, %g\n",
962 float_bitcast(fconsts[0]),
963 float_bitcast(fconsts[1]),
964 float_bitcast(fconsts[2]),
965 float_bitcast(fconsts[3]));
966 }
967
968 }
969 }
970 }
971
972 static void
973 print_varying_parameters(midgard_load_store_word *word)
974 {
975 midgard_varying_parameter param;
976 unsigned v = word->varying_parameters;
977 memcpy(&param, &v, sizeof(param));
978
979 if (param.is_varying) {
980 /* If a varying, there are qualifiers */
981 if (param.flat)
982 printf(".flat");
983
984 if (param.interpolation != midgard_interp_default) {
985 if (param.interpolation == midgard_interp_centroid)
986 printf(".centroid");
987 else
988 printf(".interp%d", param.interpolation);
989 }
990
991 if (param.modifier != midgard_varying_mod_none) {
992 if (param.modifier == midgard_varying_mod_perspective_w)
993 printf(".perspectivew");
994 else if (param.modifier == midgard_varying_mod_perspective_z)
995 printf(".perspectivez");
996 else
997 printf(".mod%d", param.modifier);
998 }
999 } else if (param.flat || param.interpolation || param.modifier) {
1000 printf(" /* is_varying not set but varying metadata attached */");
1001 }
1002
1003 if (param.zero0 || param.zero1 || param.zero2)
1004 printf(" /* zero tripped, %u %u %u */ ", param.zero0, param.zero1, param.zero2);
1005 }
1006
1007 static bool
1008 is_op_varying(unsigned op)
1009 {
1010 switch (op) {
1011 case midgard_op_st_vary_16:
1012 case midgard_op_st_vary_32:
1013 case midgard_op_st_vary_32i:
1014 case midgard_op_st_vary_32u:
1015 case midgard_op_ld_vary_16:
1016 case midgard_op_ld_vary_32:
1017 case midgard_op_ld_vary_32i:
1018 case midgard_op_ld_vary_32u:
1019 return true;
1020 }
1021
1022 return false;
1023 }
1024
1025 static bool
1026 is_op_attribute(unsigned op)
1027 {
1028 switch (op) {
1029 case midgard_op_ld_attr_16:
1030 case midgard_op_ld_attr_32:
1031 case midgard_op_ld_attr_32i:
1032 case midgard_op_ld_attr_32u:
1033 return true;
1034 }
1035
1036 return false;
1037 }
1038
1039 static void
1040 print_load_store_arg(uint8_t arg, unsigned index)
1041 {
1042 /* Try to interpret as a register */
1043 midgard_ldst_register_select sel;
1044 memcpy(&sel, &arg, sizeof(arg));
1045
1046 /* If unknown is set, we're not sure what this is or how to
1047 * interpret it. But if it's zero, we get it. */
1048
1049 if (sel.unknown) {
1050 printf("0x%02X", arg);
1051 return;
1052 }
1053
1054 unsigned reg = REGISTER_LDST_BASE + sel.select;
1055 char comp = components[sel.component];
1056
1057 printf("r%u.%c", reg, comp);
1058
1059 /* Only print a shift if it's non-zero. Shifts only make sense for the
1060 * second index. For the first, we're not sure what it means yet */
1061
1062 if (index == 1) {
1063 if (sel.shift)
1064 printf(" << %u", sel.shift);
1065 } else {
1066 printf(" /* %X */", sel.shift);
1067 }
1068 }
1069
1070 static void
1071 update_stats(signed *stat, unsigned address)
1072 {
1073 if (*stat >= 0)
1074 *stat = MAX2(*stat, address + 1);
1075 }
1076
1077 static void
1078 print_load_store_instr(uint64_t data,
1079 unsigned tabs)
1080 {
1081 midgard_load_store_word *word = (midgard_load_store_word *) &data;
1082
1083 print_ld_st_opcode(word->op);
1084
1085 unsigned address = word->address;
1086
1087 if (is_op_varying(word->op)) {
1088 print_varying_parameters(word);
1089
1090 /* Do some analysis: check if direct cacess */
1091
1092 if ((word->arg_2 == 0x1E) && midg_stats.varying_count >= 0)
1093 update_stats(&midg_stats.varying_count, address);
1094 else
1095 midg_stats.varying_count = -16;
1096 } else if (is_op_attribute(word->op)) {
1097 if ((word->arg_2 == 0x1E) && midg_stats.attribute_count >= 0)
1098 update_stats(&midg_stats.attribute_count, address);
1099 else
1100 midg_stats.attribute_count = -16;
1101 }
1102
1103 printf(" r%u", word->reg);
1104 print_mask_4(word->mask);
1105
1106 if (!OP_IS_STORE(word->op))
1107 update_dest(word->reg);
1108
1109 bool is_ubo = OP_IS_UBO_READ(word->op);
1110
1111 if (is_ubo) {
1112 /* UBOs use their own addressing scheme */
1113
1114 int lo = word->varying_parameters >> 7;
1115 int hi = word->address;
1116
1117 /* TODO: Combine fields logically */
1118 address = (hi << 3) | lo;
1119 }
1120
1121 printf(", %u", address);
1122
1123 print_swizzle_vec4(word->swizzle, false, false);
1124
1125 printf(", ");
1126
1127 if (is_ubo) {
1128 printf("ubo%u", word->arg_1);
1129 update_stats(&midg_stats.uniform_buffer_count, word->arg_1);
1130 } else
1131 print_load_store_arg(word->arg_1, 0);
1132
1133 printf(", ");
1134 print_load_store_arg(word->arg_2, 1);
1135 printf(" /* %X */\n", word->varying_parameters);
1136
1137 midg_stats.instruction_count++;
1138 }
1139
1140 static void
1141 print_load_store_word(uint32_t *word, unsigned tabs)
1142 {
1143 midgard_load_store *load_store = (midgard_load_store *) word;
1144
1145 if (load_store->word1 != 3) {
1146 print_load_store_instr(load_store->word1, tabs);
1147 }
1148
1149 if (load_store->word2 != 3) {
1150 print_load_store_instr(load_store->word2, tabs);
1151 }
1152 }
1153
1154 static void
1155 print_texture_reg(bool full, bool select, bool upper)
1156 {
1157 if (full)
1158 printf("r%d", REG_TEX_BASE + select);
1159 else
1160 printf("hr%d", (REG_TEX_BASE + select) * 2 + upper);
1161
1162 if (full && upper)
1163 printf("// error: out full / upper mutually exclusive\n");
1164
1165 }
1166
1167 static void
1168 print_texture_reg_triple(unsigned triple)
1169 {
1170 bool full = triple & 1;
1171 bool select = triple & 2;
1172 bool upper = triple & 4;
1173
1174 print_texture_reg(full, select, upper);
1175 }
1176
1177 static void
1178 print_texture_reg_select(uint8_t u)
1179 {
1180 midgard_tex_register_select sel;
1181 memcpy(&sel, &u, sizeof(u));
1182
1183 if (!sel.full)
1184 printf("h");
1185
1186 printf("r%u", REG_TEX_BASE + sel.select);
1187
1188 unsigned component = sel.component;
1189
1190 /* Use the upper half in half-reg mode */
1191 if (sel.upper) {
1192 assert(!sel.full);
1193 component += 4;
1194 }
1195
1196 printf(".%c", components[component]);
1197
1198 assert(sel.zero == 0);
1199 }
1200
1201 static void
1202 print_texture_format(int format)
1203 {
1204 /* Act like a modifier */
1205 printf(".");
1206
1207 switch (format) {
1208 DEFINE_CASE(MALI_TEX_1D, "1d");
1209 DEFINE_CASE(MALI_TEX_2D, "2d");
1210 DEFINE_CASE(MALI_TEX_3D, "3d");
1211 DEFINE_CASE(MALI_TEX_CUBE, "cube");
1212
1213 default:
1214 unreachable("Bad format");
1215 }
1216 }
1217
1218 static bool
1219 midgard_op_has_helpers(unsigned op, bool gather)
1220 {
1221 if (gather)
1222 return true;
1223
1224 switch (op) {
1225 case TEXTURE_OP_NORMAL:
1226 case TEXTURE_OP_DFDX:
1227 case TEXTURE_OP_DFDY:
1228 return true;
1229 default:
1230 return false;
1231 }
1232 }
1233
1234 static void
1235 print_texture_op(unsigned op, bool gather)
1236 {
1237 /* Act like a bare name, like ESSL functions */
1238
1239 if (gather) {
1240 printf("textureGather");
1241
1242 unsigned component = op >> 4;
1243 unsigned bottom = op & 0xF;
1244
1245 if (bottom != 0x2)
1246 printf("_unk%u", bottom);
1247
1248 printf(".%c", components[component]);
1249 return;
1250 }
1251
1252 switch (op) {
1253 DEFINE_CASE(TEXTURE_OP_NORMAL, "texture");
1254 DEFINE_CASE(TEXTURE_OP_LOD, "textureLod");
1255 DEFINE_CASE(TEXTURE_OP_TEXEL_FETCH, "texelFetch");
1256 DEFINE_CASE(TEXTURE_OP_DFDX, "dFdx");
1257 DEFINE_CASE(TEXTURE_OP_DFDY, "dFdy");
1258
1259 default:
1260 printf("tex_%X", op);
1261 break;
1262 }
1263 }
1264
1265 static bool
1266 texture_op_takes_bias(unsigned op)
1267 {
1268 return op == TEXTURE_OP_NORMAL;
1269 }
1270
1271 static char
1272 sampler_type_name(enum mali_sampler_type t)
1273 {
1274 switch (t) {
1275 case MALI_SAMPLER_FLOAT:
1276 return 'f';
1277 case MALI_SAMPLER_UNSIGNED:
1278 return 'u';
1279 case MALI_SAMPLER_SIGNED:
1280 return 'i';
1281 default:
1282 return '?';
1283 }
1284
1285 }
1286
1287 #undef DEFINE_CASE
1288
1289 static void
1290 print_texture_word(uint32_t *word, unsigned tabs)
1291 {
1292 midgard_texture_word *texture = (midgard_texture_word *) word;
1293
1294 midg_stats.helper_invocations |=
1295 midgard_op_has_helpers(texture->op, texture->is_gather);
1296
1297 /* Broad category of texture operation in question */
1298 print_texture_op(texture->op, texture->is_gather);
1299
1300 /* Specific format in question */
1301 print_texture_format(texture->format);
1302
1303 /* Instruction "modifiers" parallel the ALU instructions. */
1304
1305 if (texture->shadow)
1306 printf(".shadow");
1307
1308 if (texture->cont)
1309 printf(".cont");
1310
1311 if (texture->last)
1312 printf(".last");
1313
1314 /* Output modifiers are always interpreted floatly */
1315 print_outmod(texture->outmod, false);
1316
1317 printf(" ");
1318
1319 print_texture_reg(texture->out_full, texture->out_reg_select, texture->out_upper);
1320 print_mask_4(texture->mask);
1321 printf(", ");
1322
1323 /* Depending on whether we read from textures directly or indirectly,
1324 * we may be able to update our analysis */
1325
1326 if (texture->texture_register) {
1327 printf("texture[");
1328 print_texture_reg_select(texture->texture_handle);
1329 printf("], ");
1330
1331 /* Indirect, tut tut */
1332 midg_stats.texture_count = -16;
1333 } else {
1334 printf("texture%u, ", texture->texture_handle);
1335 update_stats(&midg_stats.texture_count, texture->texture_handle);
1336 }
1337
1338 /* Print the type, GL style */
1339 printf("%csampler", sampler_type_name(texture->sampler_type));
1340
1341 if (texture->sampler_register) {
1342 printf("[");
1343 print_texture_reg_select(texture->sampler_handle);
1344 printf("]");
1345
1346 midg_stats.sampler_count = -16;
1347 } else {
1348 printf("%u", texture->sampler_handle);
1349 update_stats(&midg_stats.sampler_count, texture->sampler_handle);
1350 }
1351
1352 print_swizzle_vec4(texture->swizzle, false, false);
1353 printf(", ");
1354
1355 print_texture_reg(texture->in_reg_full, texture->in_reg_select, texture->in_reg_upper);
1356 print_swizzle_vec4(texture->in_reg_swizzle, false, false);
1357
1358 /* There is *always* an offset attached. Of
1359 * course, that offset is just immediate #0 for a
1360 * GLES call that doesn't take an offset. If there
1361 * is a non-negative non-zero offset, this is
1362 * specified in immediate offset mode, with the
1363 * values in the offset_* fields as immediates. If
1364 * this is a negative offset, we instead switch to
1365 * a register offset mode, where the offset_*
1366 * fields become register triplets */
1367
1368 if (texture->offset_register) {
1369 printf(" + ");
1370 print_texture_reg_triple(texture->offset_x);
1371
1372 /* The less questions you ask, the better. */
1373
1374 unsigned swizzle_lo, swizzle_hi;
1375 unsigned orig_y = texture->offset_y;
1376 unsigned orig_z = texture->offset_z;
1377
1378 memcpy(&swizzle_lo, &orig_y, sizeof(unsigned));
1379 memcpy(&swizzle_hi, &orig_z, sizeof(unsigned));
1380
1381 /* Duplicate hi swizzle over */
1382 assert(swizzle_hi < 4);
1383 swizzle_hi = (swizzle_hi << 2) | swizzle_hi;
1384
1385 unsigned swiz = (swizzle_lo << 4) | swizzle_hi;
1386 unsigned reversed = util_bitreverse(swiz) >> 24;
1387 print_swizzle_vec4(reversed, false, false);
1388
1389 printf(", ");
1390 } else if (texture->offset_x || texture->offset_y || texture->offset_z) {
1391 /* Only select ops allow negative immediate offsets, verify */
1392
1393 bool neg_x = texture->offset_x < 0;
1394 bool neg_y = texture->offset_y < 0;
1395 bool neg_z = texture->offset_z < 0;
1396 bool any_neg = neg_x || neg_y || neg_z;
1397
1398 if (any_neg && texture->op != TEXTURE_OP_TEXEL_FETCH)
1399 printf("/* invalid negative */ ");
1400
1401 /* Regardless, just print the immediate offset */
1402
1403 printf(" + <%d, %d, %d>, ",
1404 texture->offset_x,
1405 texture->offset_y,
1406 texture->offset_z);
1407 } else {
1408 printf(", ");
1409 }
1410
1411 char lod_operand = texture_op_takes_bias(texture->op) ? '+' : '=';
1412
1413 if (texture->lod_register) {
1414 printf("lod %c ", lod_operand);
1415 print_texture_reg_select(texture->bias);
1416 printf(", ");
1417
1418 if (texture->bias_int)
1419 printf(" /* bias_int = 0x%X */", texture->bias_int);
1420 } else if (texture->op == TEXTURE_OP_TEXEL_FETCH) {
1421 /* For texel fetch, the int LOD is in the fractional place and
1422 * there is no fraction / possibility of bias. We *always* have
1423 * an explicit LOD, even if it's zero. */
1424
1425 if (texture->bias_int)
1426 printf(" /* bias_int = 0x%X */ ", texture->bias_int);
1427
1428 printf("lod = %u, ", texture->bias);
1429 } else if (texture->bias || texture->bias_int) {
1430 signed bias_int = texture->bias_int;
1431 float bias_frac = texture->bias / 256.0f;
1432 float bias = bias_int + bias_frac;
1433
1434 bool is_bias = texture_op_takes_bias(texture->op);
1435 char sign = (bias >= 0.0) ? '+' : '-';
1436 char operand = is_bias ? sign : '=';
1437
1438 printf("lod %c %f, ", operand, fabsf(bias));
1439 }
1440
1441 printf("\n");
1442
1443 /* While not zero in general, for these simple instructions the
1444 * following unknowns are zero, so we don't include them */
1445
1446 if (texture->unknown4 ||
1447 texture->unknownA ||
1448 texture->unknown8) {
1449 printf("// unknown4 = 0x%x\n", texture->unknown4);
1450 printf("// unknownA = 0x%x\n", texture->unknownA);
1451 printf("// unknown8 = 0x%x\n", texture->unknown8);
1452 }
1453
1454 midg_stats.instruction_count++;
1455 }
1456
1457 struct midgard_disasm_stats
1458 disassemble_midgard(uint8_t *code, size_t size, unsigned gpu_id)
1459 {
1460 uint32_t *words = (uint32_t *) code;
1461 unsigned num_words = size / 4;
1462 int tabs = 0;
1463
1464 bool prefetch_flag = false;
1465
1466 int last_next_tag = -1;
1467
1468 unsigned i = 0;
1469
1470 midg_tags = calloc(sizeof(midg_tags[0]), num_words);
1471
1472 /* Stats for shader-db */
1473 memset(&midg_stats, 0, sizeof(midg_stats));
1474 midg_ever_written = 0;
1475
1476 while (i < num_words) {
1477 unsigned tag = words[i] & 0xF;
1478 unsigned next_tag = (words[i] >> 4) & 0xF;
1479 unsigned num_quad_words = midgard_word_size[tag];
1480
1481 if (midg_tags[i] && midg_tags[i] != tag) {
1482 printf("\t/* XXX: TAG ERROR branch, got ");
1483 print_tag_short(tag);
1484 printf(" expected ");
1485 print_tag_short(midg_tags[i]);
1486 printf(" */\n");
1487 }
1488
1489 midg_tags[i] = tag;
1490
1491 /* Check the tag */
1492 if (last_next_tag > 1) {
1493 if (last_next_tag != tag) {
1494 printf("\t/* XXX: TAG ERROR sequence, got ");
1495 print_tag_short(tag);
1496 printf(" expected ");
1497 print_tag_short(last_next_tag);
1498 printf(" */\n");
1499 }
1500 } else {
1501 /* TODO: Check ALU case */
1502 }
1503
1504 last_next_tag = next_tag;
1505
1506 switch (midgard_word_types[tag]) {
1507 case midgard_word_type_texture:
1508 print_texture_word(&words[i], tabs);
1509 break;
1510
1511 case midgard_word_type_load_store:
1512 print_load_store_word(&words[i], tabs);
1513 break;
1514
1515 case midgard_word_type_alu:
1516 print_alu_word(&words[i], num_quad_words, tabs, i + 4*num_quad_words);
1517
1518 /* Reset word static analysis state */
1519 is_embedded_constant_half = false;
1520 is_embedded_constant_int = false;
1521
1522 break;
1523
1524 default:
1525 printf("Unknown word type %u:\n", words[i] & 0xF);
1526 num_quad_words = 1;
1527 print_quad_word(&words[i], tabs);
1528 printf("\n");
1529 break;
1530 }
1531
1532 if (prefetch_flag && midgard_word_types[tag] == midgard_word_type_alu)
1533 break;
1534
1535 printf("\n");
1536
1537 unsigned next = (words[i] & 0xF0) >> 4;
1538
1539 /* We are parsing per bundle anyway */
1540 midg_stats.bundle_count++;
1541 midg_stats.quadword_count += num_quad_words;
1542
1543 /* Break based on instruction prefetch flag */
1544
1545 if (i < num_words && next == 1) {
1546 prefetch_flag = true;
1547
1548 if (midgard_word_types[words[i] & 0xF] != midgard_word_type_alu)
1549 break;
1550 }
1551
1552 i += 4 * num_quad_words;
1553 }
1554
1555 /* We computed work_count as max_work_registers, so add one to get the
1556 * count. If no work registers are written, you still have one work
1557 * reported, which is exactly what the hardware expects */
1558
1559 midg_stats.work_count++;
1560
1561 return midg_stats;
1562 }