5 * Copyright (c) 2013 Connor Abbott (connor@abbott.cx)
6 * Copyright (c) 2018 Alyssa Rosenzweig (alyssa@rosenzweig.io)
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
34 #include "midgard-parse.h"
35 #include "midgard_ops.h"
36 #include "disassemble.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
41 #define DEFINE_CASE(define, str) case define: { printf(str); break; }
43 static bool is_instruction_int
= false;
47 static struct midgard_disasm_stats midg_stats
;
49 /* Prints a short form of the tag for branching, the minimum needed to be
50 * legible and unambiguous */
53 print_tag_short(unsigned tag
)
55 switch (midgard_word_types
[tag
]) {
56 case midgard_word_type_texture
:
57 printf("tex/%X", tag
);
60 case midgard_word_type_load_store
:
64 case midgard_word_type_alu
:
65 printf("alu%d/%X", midgard_word_size
[tag
], tag
);
69 printf("%s%X", (tag
> 0) ? "" : "unk", tag
);
75 print_alu_opcode(midgard_alu_op op
)
79 if (alu_opcode_props
[op
].name
) {
80 printf("%s", alu_opcode_props
[op
].name
);
82 int_op
= midgard_is_integer_op(op
);
84 printf("alu_op_%02X", op
);
86 /* For constant analysis */
87 is_instruction_int
= int_op
;
91 print_ld_st_opcode(midgard_load_store_op op
)
93 if (load_store_opcode_names
[op
])
94 printf("%s", load_store_opcode_names
[op
]);
96 printf("ldst_op_%02X", op
);
99 static bool is_embedded_constant_half
= false;
100 static bool is_embedded_constant_int
= false;
103 prefix_for_bits(unsigned bits
)
117 /* For static analysis to ensure all registers are written at least once before
118 * use along the source code path (TODO: does this break done for complex CF?)
121 uint16_t midg_ever_written
= 0;
124 print_reg(unsigned reg
, unsigned bits
)
126 /* Perform basic static analysis for expanding constants correctly */
129 is_embedded_constant_int
= is_instruction_int
;
130 is_embedded_constant_half
= (bits
< 32);
133 unsigned uniform_reg
= 23 - reg
;
134 bool is_uniform
= false;
136 /* For r8-r15, it could be a work or uniform. We distinguish based on
137 * the fact work registers are ALWAYS written before use, but uniform
138 * registers are NEVER written before use. */
140 if ((reg
>= 8 && reg
< 16) && !(midg_ever_written
& (1 << reg
)))
143 /* r16-r23 are always uniform */
145 if (reg
>= 16 && reg
<= 23)
148 /* Update the uniform count appropriately */
151 midg_stats
.uniform_count
=
152 MAX2(uniform_reg
+ 1, midg_stats
.uniform_count
);
154 char prefix
= prefix_for_bits(bits
);
162 static char *outmod_names_float
[4] = {
169 static char *outmod_names_int
[4] = {
176 static char *srcmod_names_int
[4] = {
184 print_outmod(unsigned outmod
, bool is_int
)
186 printf("%s", is_int
? outmod_names_int
[outmod
] :
187 outmod_names_float
[outmod
]);
191 print_quad_word(uint32_t *words
, unsigned tabs
)
195 for (i
= 0; i
< 4; i
++)
196 printf("0x%08X%s ", words
[i
], i
== 3 ? "" : ",");
201 static const char components
[16] = "xyzwefghijklmnop";
203 /* Helper to print 4 chars of a swizzle */
205 print_swizzle_helper(unsigned swizzle
, bool upper
)
207 for (unsigned i
= 0; i
< 4; ++i
) {
208 unsigned c
= (swizzle
>> (i
* 2)) & 3;
210 printf("%c", components
[c
]);
214 /* Helper to print 8 chars of a swizzle, duplicating over */
216 print_swizzle_helper_8(unsigned swizzle
, bool upper
)
218 for (unsigned i
= 0; i
< 4; ++i
) {
219 unsigned c
= (swizzle
>> (i
* 2)) & 3;
222 printf("%c%c", components
[c
], components
[c
+1]);
227 print_swizzle_vec16(unsigned swizzle
, bool rep_high
, bool rep_low
,
228 midgard_dest_override override
)
232 if (override
== midgard_dest_override_upper
) {
234 printf(" /* rep_high */ ");
236 printf(" /* rep_low */ ");
238 if (!rep_high
&& rep_low
)
239 print_swizzle_helper_8(swizzle
, true);
241 print_swizzle_helper_8(swizzle
, false);
243 print_swizzle_helper_8(swizzle
, rep_high
& 1);
244 print_swizzle_helper_8(swizzle
, !rep_low
& 1);
249 print_swizzle_vec8(unsigned swizzle
, bool rep_high
, bool rep_low
)
253 print_swizzle_helper(swizzle
, rep_high
& 1);
254 print_swizzle_helper(swizzle
, !rep_low
& 1);
258 print_swizzle_vec4(unsigned swizzle
, bool rep_high
, bool rep_low
)
261 printf(" /* rep_high */ ");
263 printf(" /* rep_low */ ");
265 if (swizzle
== 0xE4) return; /* xyzw */
268 print_swizzle_helper(swizzle
, 0);
271 print_swizzle_vec2(unsigned swizzle
, bool rep_high
, bool rep_low
)
274 printf(" /* rep_high */ ");
276 printf(" /* rep_low */ ");
278 if (swizzle
== 0xE4) return; /* XY */
282 for (unsigned i
= 0; i
< 4; i
+= 2) {
283 unsigned a
= (swizzle
>> (i
* 2)) & 3;
284 unsigned b
= (swizzle
>> ((i
+1) * 2)) & 3;
286 /* Normally we're adjacent, but if there's an issue, don't make
290 printf("[%c%c]", components
[a
], components
[b
]);
292 printf("%c", components
[a
>> 1]);
293 else if (b
== (a
+ 1))
294 printf("%c", "XY"[a
>> 1]);
296 printf("[%c%c]", components
[a
], components
[b
]);
301 bits_for_mode(midgard_reg_mode mode
)
304 case midgard_reg_mode_8
:
306 case midgard_reg_mode_16
:
308 case midgard_reg_mode_32
:
310 case midgard_reg_mode_64
:
313 unreachable("Invalid reg mode");
319 bits_for_mode_halved(midgard_reg_mode mode
, bool half
)
321 unsigned bits
= bits_for_mode(mode
);
330 print_vector_src(unsigned src_binary
,
331 midgard_reg_mode mode
, unsigned reg
,
332 midgard_dest_override override
, bool is_int
)
334 midgard_vector_alu_src
*src
= (midgard_vector_alu_src
*)&src_binary
;
336 /* Modifiers change meaning depending on the op's context */
338 midgard_int_mod int_mod
= src
->mod
;
341 printf("%s", srcmod_names_int
[int_mod
]);
343 if (src
->mod
& MIDGARD_FLOAT_MOD_NEG
)
346 if (src
->mod
& MIDGARD_FLOAT_MOD_ABS
)
351 unsigned bits
= bits_for_mode_halved(mode
, src
->half
);
352 print_reg(reg
, bits
);
356 print_swizzle_vec8(src
->swizzle
, src
->rep_high
, src
->rep_low
);
358 print_swizzle_vec16(src
->swizzle
, src
->rep_high
, src
->rep_low
, override
);
360 print_swizzle_vec4(src
->swizzle
, src
->rep_high
, src
->rep_low
);
362 print_swizzle_vec2(src
->swizzle
, src
->rep_high
, src
->rep_low
);
364 /* Since we wrapped with a function-looking thing */
366 if (is_int
&& int_mod
== midgard_int_shift
)
367 printf(") << %d", bits
);
368 else if ((is_int
&& (int_mod
!= midgard_int_normal
))
369 || (!is_int
&& src
->mod
& MIDGARD_FLOAT_MOD_ABS
))
374 decode_vector_imm(unsigned src2_reg
, unsigned imm
)
377 ret
= src2_reg
<< 11;
378 ret
|= (imm
& 0x7) << 8;
379 ret
|= (imm
>> 3) & 0xFF;
384 print_immediate(uint16_t imm
)
386 if (is_instruction_int
)
389 printf("#%g", _mesa_half_to_float(imm
));
393 update_dest(unsigned reg
)
395 /* We should record writes as marking this as a work register. Store
396 * the max register in work_count; we'll add one at the end */
399 midg_stats
.work_count
= MAX2(reg
, midg_stats
.work_count
);
400 midg_ever_written
|= (1 << reg
);
405 print_dest(unsigned reg
, midgard_reg_mode mode
, midgard_dest_override override
)
407 /* Depending on the mode and override, we determine the type of
408 * destination addressed. Absent an override, we address just the
409 * type of the operation itself */
411 unsigned bits
= bits_for_mode(mode
);
413 if (override
!= midgard_dest_override_none
)
417 print_reg(reg
, bits
);
423 print_mask_vec16(uint8_t mask
, midgard_dest_override override
)
427 if (override
== midgard_dest_override_none
) {
428 for (unsigned i
= 0; i
< 8; i
++) {
432 components
[i
*2 + 1]);
435 bool upper
= (override
== midgard_dest_override_upper
);
437 for (unsigned i
= 0; i
< 8; i
++) {
439 printf("%c", components
[i
+ (upper
? 8 : 0)]);
444 /* For 16-bit+ masks, we read off from the 8-bit mask field. For 16-bit (vec8),
445 * it's just one bit per channel, easy peasy. For 32-bit (vec4), it's one bit
446 * per channel with one duplicate bit in the middle. For 64-bit (vec2), it's
447 * one-bit per channel with _3_ duplicate bits in the middle. Basically, just
448 * subdividing the 128-bit word in 16-bit increments. For 64-bit, we uppercase
449 * the mask to make it obvious what happened */
452 print_mask(uint8_t mask
, unsigned bits
, midgard_dest_override override
)
455 print_mask_vec16(mask
, override
);
460 /* Shouldn't happen but with junk / out-of-spec shaders it
461 * would cause an infinite loop */
463 printf("/* XXX: bits = %d */", bits
);
467 /* Skip 'complete' masks */
469 if (bits
>= 32 && mask
== 0xFF) return;
474 else if (mask
== 0xF0) {
482 unsigned skip
= (bits
/ 16);
483 bool uppercase
= bits
> 32;
484 bool tripped
= false;
486 for (unsigned i
= 0; i
< 8; i
+= skip
) {
487 bool a
= (mask
& (1 << i
)) != 0;
489 for (unsigned j
= 1; j
< skip
; ++j
) {
490 bool dupe
= (mask
& (1 << (i
+ j
))) != 0;
491 tripped
|= (dupe
!= a
);
495 char c
= components
[i
/ skip
];
505 printf(" /* %X */", mask
);
508 /* Prints the 4-bit masks found in texture and load/store ops, as opposed to
509 * the 8-bit masks found in (vector) ALU ops */
512 print_mask_4(unsigned mask
)
514 if (mask
== 0xF) return;
518 for (unsigned i
= 0; i
< 4; ++i
) {
519 bool a
= (mask
& (1 << i
)) != 0;
521 printf("%c", components
[i
]);
526 print_vector_field(const char *name
, uint16_t *words
, uint16_t reg_word
,
529 midgard_reg_info
*reg_info
= (midgard_reg_info
*)®_word
;
530 midgard_vector_alu
*alu_field
= (midgard_vector_alu
*) words
;
531 midgard_reg_mode mode
= alu_field
->reg_mode
;
532 unsigned override
= alu_field
->dest_override
;
534 /* For now, prefix instruction names with their unit, until we
535 * understand how this works on a deeper level */
538 print_alu_opcode(alu_field
->op
);
540 /* Postfix with the size to disambiguate if necessary */
541 char postfix
= prefix_for_bits(bits_for_mode(mode
));
542 bool size_ambiguous
= override
!= midgard_dest_override_none
;
545 printf("%c", postfix
? postfix
: 'r');
547 /* Print the outmod, if there is one */
548 print_outmod(alu_field
->outmod
,
549 midgard_is_integer_out_op(alu_field
->op
));
553 /* Mask denoting status of 8-lanes */
554 uint8_t mask
= alu_field
->mask
;
556 /* First, print the destination */
558 print_dest(reg_info
->out_reg
, mode
, alu_field
->dest_override
);
560 /* Apply the destination override to the mask */
562 if (mode
== midgard_reg_mode_32
|| mode
== midgard_reg_mode_64
) {
563 if (override
== midgard_dest_override_lower
)
565 else if (override
== midgard_dest_override_upper
)
567 } else if (mode
== midgard_reg_mode_16
568 && override
== midgard_dest_override_lower
) {
572 if (override
!= midgard_dest_override_none
) {
573 bool modeable
= (mode
!= midgard_reg_mode_8
);
574 bool known
= override
!= 0x3; /* Unused value */
576 if (!(modeable
&& known
))
577 printf("/* do%d */ ", override
);
580 print_mask(mask
, dest_size
, override
);
584 bool is_int
= midgard_is_integer_op(alu_field
->op
);
585 print_vector_src(alu_field
->src1
, mode
, reg_info
->src1_reg
, override
, is_int
);
589 if (reg_info
->src2_imm
) {
590 uint16_t imm
= decode_vector_imm(reg_info
->src2_reg
, alu_field
->src2
>> 2);
591 print_immediate(imm
);
593 print_vector_src(alu_field
->src2
, mode
,
594 reg_info
->src2_reg
, override
, is_int
);
597 midg_stats
.instruction_count
++;
602 print_scalar_src(unsigned src_binary
, unsigned reg
)
604 midgard_scalar_alu_src
*src
= (midgard_scalar_alu_src
*)&src_binary
;
612 print_reg(reg
, src
->full
? 32 : 16);
614 unsigned c
= src
->component
;
617 assert((c
& 1) == 0);
621 printf(".%c", components
[c
]);
629 decode_scalar_imm(unsigned src2_reg
, unsigned imm
)
632 ret
= src2_reg
<< 11;
633 ret
|= (imm
& 3) << 9;
634 ret
|= (imm
& 4) << 6;
635 ret
|= (imm
& 0x38) << 2;
641 print_scalar_field(const char *name
, uint16_t *words
, uint16_t reg_word
,
644 midgard_reg_info
*reg_info
= (midgard_reg_info
*)®_word
;
645 midgard_scalar_alu
*alu_field
= (midgard_scalar_alu
*) words
;
647 if (alu_field
->unknown
)
648 printf("scalar ALU unknown bit set\n");
651 print_alu_opcode(alu_field
->op
);
652 print_outmod(alu_field
->outmod
,
653 midgard_is_integer_out_op(alu_field
->op
));
656 bool full
= alu_field
->output_full
;
657 update_dest(reg_info
->out_reg
);
658 print_reg(reg_info
->out_reg
, full
? 32 : 16);
659 unsigned c
= alu_field
->output_component
;
662 assert((c
& 1) == 0);
666 printf(".%c, ", components
[c
]);
668 print_scalar_src(alu_field
->src1
, reg_info
->src1_reg
);
672 if (reg_info
->src2_imm
) {
673 uint16_t imm
= decode_scalar_imm(reg_info
->src2_reg
,
675 print_immediate(imm
);
677 print_scalar_src(alu_field
->src2
, reg_info
->src2_reg
);
679 midg_stats
.instruction_count
++;
684 print_branch_op(int op
)
687 case midgard_jmp_writeout_op_branch_uncond
:
691 case midgard_jmp_writeout_op_branch_cond
:
695 case midgard_jmp_writeout_op_writeout
:
699 case midgard_jmp_writeout_op_tilebuffer_pending
:
700 printf("tilebuffer.");
703 case midgard_jmp_writeout_op_discard
:
708 printf("unk%d.", op
);
714 print_branch_cond(int cond
)
717 case midgard_condition_write0
:
721 case midgard_condition_false
:
725 case midgard_condition_true
:
729 case midgard_condition_always
:
734 printf("unk%X", cond
);
740 print_compact_branch_writeout_field(uint16_t word
)
742 midgard_jmp_writeout_op op
= word
& 0x7;
745 case midgard_jmp_writeout_op_branch_uncond
: {
746 midgard_branch_uncond br_uncond
;
747 memcpy((char *) &br_uncond
, (char *) &word
, sizeof(br_uncond
));
748 printf("br.uncond ");
750 if (br_uncond
.unknown
!= 1)
751 printf("unknown:%d, ", br_uncond
.unknown
);
753 if (br_uncond
.offset
>= 0)
756 printf("%d -> ", br_uncond
.offset
);
757 print_tag_short(br_uncond
.dest_tag
);
763 case midgard_jmp_writeout_op_branch_cond
:
764 case midgard_jmp_writeout_op_writeout
:
765 case midgard_jmp_writeout_op_discard
:
767 midgard_branch_cond br_cond
;
768 memcpy((char *) &br_cond
, (char *) &word
, sizeof(br_cond
));
772 print_branch_op(br_cond
.op
);
773 print_branch_cond(br_cond
.cond
);
777 if (br_cond
.offset
>= 0)
780 printf("%d -> ", br_cond
.offset
);
781 print_tag_short(br_cond
.dest_tag
);
788 midg_stats
.instruction_count
++;
792 print_extended_branch_writeout_field(uint8_t *words
)
794 midgard_branch_extended br
;
795 memcpy((char *) &br
, (char *) words
, sizeof(br
));
799 print_branch_op(br
.op
);
801 /* Condition codes are a LUT in the general case, but simply repeated 8 times for single-channel conditions.. Check this. */
803 bool single_channel
= true;
805 for (unsigned i
= 0; i
< 16; i
+= 2) {
806 single_channel
&= (((br
.cond
>> i
) & 0x3) == (br
.cond
& 0x3));
810 print_branch_cond(br
.cond
& 0x3);
812 printf("lut%X", br
.cond
);
815 printf(".unknown%d", br
.unknown
);
822 printf("%d -> ", br
.offset
);
823 print_tag_short(br
.dest_tag
);
826 midg_stats
.instruction_count
++;
830 num_alu_fields_enabled(uint32_t control_word
)
834 if ((control_word
>> 17) & 1)
837 if ((control_word
>> 19) & 1)
840 if ((control_word
>> 21) & 1)
843 if ((control_word
>> 23) & 1)
846 if ((control_word
>> 25) & 1)
853 float_bitcast(uint32_t integer
)
865 print_alu_word(uint32_t *words
, unsigned num_quad_words
,
868 uint32_t control_word
= words
[0];
869 uint16_t *beginning_ptr
= (uint16_t *)(words
+ 1);
870 unsigned num_fields
= num_alu_fields_enabled(control_word
);
871 uint16_t *word_ptr
= beginning_ptr
+ num_fields
;
872 unsigned num_words
= 2 + num_fields
;
874 if ((control_word
>> 16) & 1)
875 printf("unknown bit 16 enabled\n");
877 if ((control_word
>> 17) & 1) {
878 print_vector_field("vmul", word_ptr
, *beginning_ptr
, tabs
);
884 if ((control_word
>> 18) & 1)
885 printf("unknown bit 18 enabled\n");
887 if ((control_word
>> 19) & 1) {
888 print_scalar_field("sadd", word_ptr
, *beginning_ptr
, tabs
);
894 if ((control_word
>> 20) & 1)
895 printf("unknown bit 20 enabled\n");
897 if ((control_word
>> 21) & 1) {
898 print_vector_field("vadd", word_ptr
, *beginning_ptr
, tabs
);
904 if ((control_word
>> 22) & 1)
905 printf("unknown bit 22 enabled\n");
907 if ((control_word
>> 23) & 1) {
908 print_scalar_field("smul", word_ptr
, *beginning_ptr
, tabs
);
914 if ((control_word
>> 24) & 1)
915 printf("unknown bit 24 enabled\n");
917 if ((control_word
>> 25) & 1) {
918 print_vector_field("lut", word_ptr
, *beginning_ptr
, tabs
);
924 if ((control_word
>> 26) & 1) {
925 print_compact_branch_writeout_field(*word_ptr
);
930 if ((control_word
>> 27) & 1) {
931 print_extended_branch_writeout_field((uint8_t *) word_ptr
);
936 if (num_quad_words
> (num_words
+ 7) / 8) {
937 assert(num_quad_words
== (num_words
+ 15) / 8);
938 //Assume that the extra quadword is constants
939 void *consts
= words
+ (4 * num_quad_words
- 4);
941 if (is_embedded_constant_int
) {
942 if (is_embedded_constant_half
) {
943 int16_t *sconsts
= (int16_t *) consts
;
944 printf("sconstants %d, %d, %d, %d\n",
950 uint32_t *iconsts
= (uint32_t *) consts
;
951 printf("iconstants 0x%X, 0x%X, 0x%X, 0x%X\n",
958 if (is_embedded_constant_half
) {
959 uint16_t *hconsts
= (uint16_t *) consts
;
960 printf("hconstants %g, %g, %g, %g\n",
961 _mesa_half_to_float(hconsts
[0]),
962 _mesa_half_to_float(hconsts
[1]),
963 _mesa_half_to_float(hconsts
[2]),
964 _mesa_half_to_float(hconsts
[3]));
966 uint32_t *fconsts
= (uint32_t *) consts
;
967 printf("fconstants %g, %g, %g, %g\n",
968 float_bitcast(fconsts
[0]),
969 float_bitcast(fconsts
[1]),
970 float_bitcast(fconsts
[2]),
971 float_bitcast(fconsts
[3]));
979 print_varying_parameters(midgard_load_store_word
*word
)
981 midgard_varying_parameter param
;
982 unsigned v
= word
->varying_parameters
;
983 memcpy(¶m
, &v
, sizeof(param
));
985 if (param
.is_varying
) {
986 /* If a varying, there are qualifiers */
990 if (param
.interpolation
!= midgard_interp_default
) {
991 if (param
.interpolation
== midgard_interp_centroid
)
994 printf(".interp%d", param
.interpolation
);
997 if (param
.modifier
!= midgard_varying_mod_none
) {
998 if (param
.modifier
== midgard_varying_mod_perspective_w
)
999 printf(".perspectivew");
1000 else if (param
.modifier
== midgard_varying_mod_perspective_z
)
1001 printf(".perspectivez");
1003 printf(".mod%d", param
.modifier
);
1005 } else if (param
.flat
|| param
.interpolation
|| param
.modifier
) {
1006 printf(" /* is_varying not set but varying metadata attached */");
1009 if (param
.zero0
|| param
.zero1
|| param
.zero2
)
1010 printf(" /* zero tripped, %d %d %d */ ", param
.zero0
, param
.zero1
, param
.zero2
);
1014 is_op_varying(unsigned op
)
1017 case midgard_op_st_vary_16
:
1018 case midgard_op_st_vary_32
:
1019 case midgard_op_st_vary_32i
:
1020 case midgard_op_st_vary_32u
:
1021 case midgard_op_ld_vary_16
:
1022 case midgard_op_ld_vary_32
:
1023 case midgard_op_ld_vary_32i
:
1024 case midgard_op_ld_vary_32u
:
1032 is_op_attribute(unsigned op
)
1035 case midgard_op_ld_attr_16
:
1036 case midgard_op_ld_attr_32
:
1037 case midgard_op_ld_attr_32i
:
1038 case midgard_op_ld_attr_32u
:
1046 print_load_store_arg(uint8_t arg
, unsigned index
)
1048 /* Try to interpret as a register */
1049 midgard_ldst_register_select sel
;
1050 memcpy(&sel
, &arg
, sizeof(arg
));
1052 /* If unknown is set, we're not sure what this is or how to
1053 * interpret it. But if it's zero, we get it. */
1056 printf("0x%02X", arg
);
1060 unsigned reg
= REGISTER_LDST_BASE
+ sel
.select
;
1061 char comp
= components
[sel
.component
];
1063 printf("r%d.%c", reg
, comp
);
1065 /* Only print a shift if it's non-zero. Shifts only make sense for the
1066 * second index. For the first, we're not sure what it means yet */
1070 printf(" << %d", sel
.shift
);
1072 printf(" /* %X */", sel
.shift
);
1077 update_stats(signed *stat
, unsigned address
)
1080 *stat
= MAX2(*stat
, address
+ 1);
1084 print_load_store_instr(uint64_t data
,
1087 midgard_load_store_word
*word
= (midgard_load_store_word
*) &data
;
1089 print_ld_st_opcode(word
->op
);
1091 unsigned address
= word
->address
;
1093 if (is_op_varying(word
->op
)) {
1094 print_varying_parameters(word
);
1096 /* Do some analysis: check if direct cacess */
1098 if ((word
->arg_2
== 0x1E) && midg_stats
.varying_count
>= 0)
1099 update_stats(&midg_stats
.varying_count
, address
);
1101 midg_stats
.varying_count
= -16;
1102 } else if (is_op_attribute(word
->op
)) {
1103 if ((word
->arg_2
== 0x1E) && midg_stats
.attribute_count
>= 0)
1104 update_stats(&midg_stats
.attribute_count
, address
);
1106 midg_stats
.attribute_count
= -16;
1109 printf(" r%d", word
->reg
);
1110 print_mask_4(word
->mask
);
1112 if (!OP_IS_STORE(word
->op
))
1113 update_dest(word
->reg
);
1115 bool is_ubo
= OP_IS_UBO_READ(word
->op
);
1118 /* UBOs use their own addressing scheme */
1120 int lo
= word
->varying_parameters
>> 7;
1121 int hi
= word
->address
;
1123 /* TODO: Combine fields logically */
1124 address
= (hi
<< 3) | lo
;
1127 printf(", %d", address
);
1129 print_swizzle_vec4(word
->swizzle
, false, false);
1134 printf("ubo%d", word
->arg_1
);
1135 update_stats(&midg_stats
.uniform_buffer_count
, word
->arg_1
);
1137 print_load_store_arg(word
->arg_1
, 0);
1140 print_load_store_arg(word
->arg_2
, 1);
1141 printf(" /* %X */\n", word
->varying_parameters
);
1143 midg_stats
.instruction_count
++;
1147 print_load_store_word(uint32_t *word
, unsigned tabs
)
1149 midgard_load_store
*load_store
= (midgard_load_store
*) word
;
1151 if (load_store
->word1
!= 3) {
1152 print_load_store_instr(load_store
->word1
, tabs
);
1155 if (load_store
->word2
!= 3) {
1156 print_load_store_instr(load_store
->word2
, tabs
);
1161 print_texture_reg(bool full
, bool select
, bool upper
)
1164 printf("r%d", REG_TEX_BASE
+ select
);
1166 printf("hr%d", (REG_TEX_BASE
+ select
) * 2 + upper
);
1169 printf("// error: out full / upper mutually exclusive\n");
1174 print_texture_reg_triple(unsigned triple
)
1176 bool full
= triple
& 1;
1177 bool select
= triple
& 2;
1178 bool upper
= triple
& 4;
1180 print_texture_reg(full
, select
, upper
);
1184 print_texture_reg_select(uint8_t u
)
1186 midgard_tex_register_select sel
;
1187 memcpy(&sel
, &u
, sizeof(u
));
1192 printf("r%d", REG_TEX_BASE
+ sel
.select
);
1194 unsigned component
= sel
.component
;
1196 /* Use the upper half in half-reg mode */
1202 printf(".%c", components
[component
]);
1204 assert(sel
.zero
== 0);
1208 print_texture_format(int format
)
1210 /* Act like a modifier */
1214 DEFINE_CASE(MALI_TEX_1D
, "1d");
1215 DEFINE_CASE(MALI_TEX_2D
, "2d");
1216 DEFINE_CASE(MALI_TEX_3D
, "3d");
1217 DEFINE_CASE(MALI_TEX_CUBE
, "cube");
1220 unreachable("Bad format");
1225 midgard_op_has_helpers(unsigned op
, bool gather
)
1231 case TEXTURE_OP_NORMAL
:
1232 case TEXTURE_OP_DFDX
:
1233 case TEXTURE_OP_DFDY
:
1241 print_texture_op(unsigned op
, bool gather
)
1243 /* Act like a bare name, like ESSL functions */
1246 printf("textureGather");
1248 unsigned component
= op
>> 4;
1249 unsigned bottom
= op
& 0xF;
1252 printf("_unk%d", bottom
);
1254 printf(".%c", components
[component
]);
1259 DEFINE_CASE(TEXTURE_OP_NORMAL
, "texture");
1260 DEFINE_CASE(TEXTURE_OP_LOD
, "textureLod");
1261 DEFINE_CASE(TEXTURE_OP_TEXEL_FETCH
, "texelFetch");
1262 DEFINE_CASE(TEXTURE_OP_DFDX
, "dFdx");
1263 DEFINE_CASE(TEXTURE_OP_DFDY
, "dFdy");
1266 printf("tex_%X", op
);
1272 texture_op_takes_bias(unsigned op
)
1274 return op
== TEXTURE_OP_NORMAL
;
1278 sampler_type_name(enum mali_sampler_type t
)
1281 case MALI_SAMPLER_FLOAT
:
1283 case MALI_SAMPLER_UNSIGNED
:
1285 case MALI_SAMPLER_SIGNED
:
1296 print_texture_word(uint32_t *word
, unsigned tabs
)
1298 midgard_texture_word
*texture
= (midgard_texture_word
*) word
;
1300 midg_stats
.helper_invocations
|=
1301 midgard_op_has_helpers(texture
->op
, texture
->is_gather
);
1303 /* Broad category of texture operation in question */
1304 print_texture_op(texture
->op
, texture
->is_gather
);
1306 /* Specific format in question */
1307 print_texture_format(texture
->format
);
1309 /* Instruction "modifiers" parallel the ALU instructions. */
1311 if (texture
->shadow
)
1320 /* Output modifiers are always interpreted floatly */
1321 print_outmod(texture
->outmod
, false);
1325 print_texture_reg(texture
->out_full
, texture
->out_reg_select
, texture
->out_upper
);
1326 print_mask_4(texture
->mask
);
1329 /* Depending on whether we read from textures directly or indirectly,
1330 * we may be able to update our analysis */
1332 if (texture
->texture_register
) {
1334 print_texture_reg_select(texture
->texture_handle
);
1337 /* Indirect, tut tut */
1338 midg_stats
.texture_count
= -16;
1340 printf("texture%d, ", texture
->texture_handle
);
1341 update_stats(&midg_stats
.texture_count
, texture
->texture_handle
);
1344 /* Print the type, GL style */
1345 printf("%csampler", sampler_type_name(texture
->sampler_type
));
1347 if (texture
->sampler_register
) {
1349 print_texture_reg_select(texture
->sampler_handle
);
1352 midg_stats
.sampler_count
= -16;
1354 printf("%d", texture
->sampler_handle
);
1355 update_stats(&midg_stats
.sampler_count
, texture
->sampler_handle
);
1358 print_swizzle_vec4(texture
->swizzle
, false, false);
1361 print_texture_reg(texture
->in_reg_full
, texture
->in_reg_select
, texture
->in_reg_upper
);
1362 print_swizzle_vec4(texture
->in_reg_swizzle
, false, false);
1364 /* There is *always* an offset attached. Of
1365 * course, that offset is just immediate #0 for a
1366 * GLES call that doesn't take an offset. If there
1367 * is a non-negative non-zero offset, this is
1368 * specified in immediate offset mode, with the
1369 * values in the offset_* fields as immediates. If
1370 * this is a negative offset, we instead switch to
1371 * a register offset mode, where the offset_*
1372 * fields become register triplets */
1374 if (texture
->offset_register
) {
1376 print_texture_reg_triple(texture
->offset_x
);
1378 /* The less questions you ask, the better. */
1380 unsigned swizzle_lo
, swizzle_hi
;
1381 unsigned orig_y
= texture
->offset_y
;
1382 unsigned orig_z
= texture
->offset_z
;
1384 memcpy(&swizzle_lo
, &orig_y
, sizeof(unsigned));
1385 memcpy(&swizzle_hi
, &orig_z
, sizeof(unsigned));
1387 /* Duplicate hi swizzle over */
1388 assert(swizzle_hi
< 4);
1389 swizzle_hi
= (swizzle_hi
<< 2) | swizzle_hi
;
1391 unsigned swiz
= (swizzle_lo
<< 4) | swizzle_hi
;
1392 unsigned reversed
= util_bitreverse(swiz
) >> 24;
1393 print_swizzle_vec4(reversed
, false, false);
1396 } else if (texture
->offset_x
|| texture
->offset_y
|| texture
->offset_z
) {
1397 /* Only select ops allow negative immediate offsets, verify */
1399 bool neg_x
= texture
->offset_x
< 0;
1400 bool neg_y
= texture
->offset_y
< 0;
1401 bool neg_z
= texture
->offset_z
< 0;
1402 bool any_neg
= neg_x
|| neg_y
|| neg_z
;
1404 if (any_neg
&& texture
->op
!= TEXTURE_OP_TEXEL_FETCH
)
1405 printf("/* invalid negative */ ");
1407 /* Regardless, just print the immediate offset */
1409 printf(" + <%d, %d, %d>, ",
1417 char lod_operand
= texture_op_takes_bias(texture
->op
) ? '+' : '=';
1419 if (texture
->lod_register
) {
1420 printf("lod %c ", lod_operand
);
1421 print_texture_reg_select(texture
->bias
);
1424 if (texture
->bias_int
)
1425 printf(" /* bias_int = 0x%X */", texture
->bias_int
);
1426 } else if (texture
->op
== TEXTURE_OP_TEXEL_FETCH
) {
1427 /* For texel fetch, the int LOD is in the fractional place and
1428 * there is no fraction / possibility of bias. We *always* have
1429 * an explicit LOD, even if it's zero. */
1431 if (texture
->bias_int
)
1432 printf(" /* bias_int = 0x%X */ ", texture
->bias_int
);
1434 printf("lod = %d, ", texture
->bias
);
1435 } else if (texture
->bias
|| texture
->bias_int
) {
1436 signed bias_int
= texture
->bias_int
;
1437 float bias_frac
= texture
->bias
/ 256.0f
;
1438 float bias
= bias_int
+ bias_frac
;
1440 bool is_bias
= texture_op_takes_bias(texture
->op
);
1441 char sign
= (bias
>= 0.0) ? '+' : '-';
1442 char operand
= is_bias
? sign
: '=';
1444 printf("lod %c %f, ", operand
, fabsf(bias
));
1449 /* While not zero in general, for these simple instructions the
1450 * following unknowns are zero, so we don't include them */
1452 if (texture
->unknown4
||
1453 texture
->unknownA
||
1454 texture
->unknown8
) {
1455 printf("// unknown4 = 0x%x\n", texture
->unknown4
);
1456 printf("// unknownA = 0x%x\n", texture
->unknownA
);
1457 printf("// unknown8 = 0x%x\n", texture
->unknown8
);
1460 midg_stats
.instruction_count
++;
1463 struct midgard_disasm_stats
1464 disassemble_midgard(uint8_t *code
, size_t size
)
1466 uint32_t *words
= (uint32_t *) code
;
1467 unsigned num_words
= size
/ 4;
1470 bool prefetch_flag
= false;
1472 int last_next_tag
= -1;
1476 /* Stats for shader-db */
1477 memset(&midg_stats
, 0, sizeof(midg_stats
));
1478 midg_ever_written
= 0;
1480 while (i
< num_words
) {
1481 unsigned tag
= words
[i
] & 0xF;
1482 unsigned next_tag
= (words
[i
] >> 4) & 0xF;
1483 unsigned num_quad_words
= midgard_word_size
[tag
];
1486 if (last_next_tag
> 1) {
1487 if (last_next_tag
!= tag
) {
1488 printf("/* TAG ERROR got ");
1489 print_tag_short(tag
);
1490 printf(" expected ");
1491 print_tag_short(last_next_tag
);
1495 /* TODO: Check ALU case */
1498 last_next_tag
= next_tag
;
1500 switch (midgard_word_types
[tag
]) {
1501 case midgard_word_type_texture
:
1502 print_texture_word(&words
[i
], tabs
);
1505 case midgard_word_type_load_store
:
1506 print_load_store_word(&words
[i
], tabs
);
1509 case midgard_word_type_alu
:
1510 print_alu_word(&words
[i
], num_quad_words
, tabs
);
1512 /* Reset word static analysis state */
1513 is_embedded_constant_half
= false;
1514 is_embedded_constant_int
= false;
1519 printf("Unknown word type %u:\n", words
[i
] & 0xF);
1521 print_quad_word(&words
[i
], tabs
);
1526 if (prefetch_flag
&& midgard_word_types
[tag
] == midgard_word_type_alu
)
1531 unsigned next
= (words
[i
] & 0xF0) >> 4;
1533 /* We are parsing per bundle anyway */
1534 midg_stats
.bundle_count
++;
1535 midg_stats
.quadword_count
+= num_quad_words
;
1537 /* Break based on instruction prefetch flag */
1539 if (i
< num_words
&& next
== 1) {
1540 prefetch_flag
= true;
1542 if (midgard_word_types
[words
[i
] & 0xF] != midgard_word_type_alu
)
1546 i
+= 4 * num_quad_words
;
1549 /* We computed work_count as max_work_registers, so add one to get the
1550 * count. If no work registers are written, you still have one work
1551 * reported, which is exactly what the hardware expects */
1553 midg_stats
.work_count
++;