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panfrost/midgard: Prettify embedded constant prints
[mesa.git] / src / panfrost / midgard / disassemble.c
1 /* Author(s):
2 * Connor Abbott
3 * Alyssa Rosenzweig
4 *
5 * Copyright (c) 2013 Connor Abbott (connor@abbott.cx)
6 * Copyright (c) 2018 Alyssa Rosenzweig (alyssa@rosenzweig.io)
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #include <stdio.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <assert.h>
31 #include <inttypes.h>
32 #include <ctype.h>
33 #include <string.h>
34 #include "midgard.h"
35 #include "midgard_ops.h"
36 #include "midgard_quirks.h"
37 #include "disassemble.h"
38 #include "helpers.h"
39 #include "util/bitscan.h"
40 #include "util/half_float.h"
41 #include "util/u_math.h"
42
43 #define DEFINE_CASE(define, str) case define: { fprintf(fp, str); break; }
44
45 static unsigned *midg_tags;
46 static bool is_instruction_int = false;
47
48 /* Stats */
49
50 static struct midgard_disasm_stats midg_stats;
51
52 /* Prints a short form of the tag for branching, the minimum needed to be
53 * legible and unambiguous */
54
55 static void
56 print_tag_short(FILE *fp, unsigned tag)
57 {
58 switch (midgard_word_types[tag]) {
59 case midgard_word_type_texture:
60 fprintf(fp, "tex/%X", tag);
61 break;
62
63 case midgard_word_type_load_store:
64 fprintf(fp, "ldst");
65 break;
66
67 case midgard_word_type_alu:
68 fprintf(fp, "alu%u/%X", midgard_word_size[tag], tag);
69 break;
70
71 default:
72 fprintf(fp, "%s%X", (tag > 0) ? "" : "unk", tag);
73 break;
74 }
75 }
76
77 static void
78 print_alu_opcode(FILE *fp, midgard_alu_op op)
79 {
80 bool int_op = false;
81
82 if (alu_opcode_props[op].name) {
83 fprintf(fp, "%s", alu_opcode_props[op].name);
84
85 int_op = midgard_is_integer_op(op);
86 } else
87 fprintf(fp, "alu_op_%02X", op);
88
89 /* For constant analysis */
90 is_instruction_int = int_op;
91 }
92
93 static void
94 print_ld_st_opcode(FILE *fp, midgard_load_store_op op)
95 {
96 if (load_store_opcode_props[op].name)
97 fprintf(fp, "%s", load_store_opcode_props[op].name);
98 else
99 fprintf(fp, "ldst_op_%02X", op);
100 }
101
102 static bool is_embedded_constant_half = false;
103 static bool is_embedded_constant_int = false;
104
105 static char
106 prefix_for_bits(unsigned bits)
107 {
108 switch (bits) {
109 case 8:
110 return 'q';
111 case 16:
112 return 'h';
113 case 64:
114 return 'd';
115 default:
116 return 0;
117 }
118 }
119
120 /* For static analysis to ensure all registers are written at least once before
121 * use along the source code path (TODO: does this break done for complex CF?)
122 */
123
124 uint16_t midg_ever_written = 0;
125
126 static void
127 print_reg(FILE *fp, unsigned reg, unsigned bits)
128 {
129 /* Perform basic static analysis for expanding constants correctly */
130
131 if (reg == 26) {
132 is_embedded_constant_int = is_instruction_int;
133 is_embedded_constant_half = (bits < 32);
134 }
135
136 unsigned uniform_reg = 23 - reg;
137 bool is_uniform = false;
138
139 /* For r8-r15, it could be a work or uniform. We distinguish based on
140 * the fact work registers are ALWAYS written before use, but uniform
141 * registers are NEVER written before use. */
142
143 if ((reg >= 8 && reg < 16) && !(midg_ever_written & (1 << reg)))
144 is_uniform = true;
145
146 /* r16-r23 are always uniform */
147
148 if (reg >= 16 && reg <= 23)
149 is_uniform = true;
150
151 /* Update the uniform count appropriately */
152
153 if (is_uniform)
154 midg_stats.uniform_count =
155 MAX2(uniform_reg + 1, midg_stats.uniform_count);
156
157 char prefix = prefix_for_bits(bits);
158
159 if (prefix)
160 putchar(prefix);
161
162 fprintf(fp, "r%u", reg);
163 }
164
165 static char *outmod_names_float[4] = {
166 "",
167 ".pos",
168 ".unk2",
169 ".sat"
170 };
171
172 static char *outmod_names_int[4] = {
173 ".isat",
174 ".usat",
175 "",
176 ".hi"
177 };
178
179 static char *srcmod_names_int[4] = {
180 "sext(",
181 "zext(",
182 "",
183 "("
184 };
185
186 static void
187 print_outmod(FILE *fp, unsigned outmod, bool is_int)
188 {
189 fprintf(fp, "%s", is_int ? outmod_names_int[outmod] :
190 outmod_names_float[outmod]);
191 }
192
193 static void
194 print_quad_word(FILE *fp, uint32_t *words, unsigned tabs)
195 {
196 unsigned i;
197
198 for (i = 0; i < 4; i++)
199 fprintf(fp, "0x%08X%s ", words[i], i == 3 ? "" : ",");
200
201 fprintf(fp, "\n");
202 }
203
204 static const char components[16] = "xyzwefghijklmnop";
205
206 /* Helper to print 4 chars of a swizzle */
207 static void
208 print_swizzle_helper(FILE *fp, unsigned swizzle, bool upper)
209 {
210 for (unsigned i = 0; i < 4; ++i) {
211 unsigned c = (swizzle >> (i * 2)) & 3;
212 c += upper*4;
213 fprintf(fp, "%c", components[c]);
214 }
215 }
216
217 /* Helper to print 8 chars of a swizzle, duplicating over */
218 static void
219 print_swizzle_helper_8(FILE *fp, unsigned swizzle, bool upper)
220 {
221 for (unsigned i = 0; i < 4; ++i) {
222 unsigned c = (swizzle >> (i * 2)) & 3;
223 c *= 2;
224 c += upper*8;
225 fprintf(fp, "%c%c", components[c], components[c+1]);
226 }
227 }
228
229 static void
230 print_swizzle_vec16(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low,
231 midgard_dest_override override)
232 {
233 fprintf(fp, ".");
234
235 if (override == midgard_dest_override_upper) {
236 if (rep_high)
237 fprintf(fp, " /* rep_high */ ");
238 if (rep_low)
239 fprintf(fp, " /* rep_low */ ");
240
241 if (!rep_high && rep_low)
242 print_swizzle_helper_8(fp, swizzle, true);
243 else
244 print_swizzle_helper_8(fp, swizzle, false);
245 } else {
246 print_swizzle_helper_8(fp, swizzle, rep_high & 1);
247 print_swizzle_helper_8(fp, swizzle, !(rep_low & 1));
248 }
249 }
250
251 static void
252 print_swizzle_vec8(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low)
253 {
254 fprintf(fp, ".");
255
256 print_swizzle_helper(fp, swizzle, rep_high & 1);
257 print_swizzle_helper(fp, swizzle, !(rep_low & 1));
258 }
259
260 static void
261 print_swizzle_vec4(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low)
262 {
263 if (rep_high)
264 fprintf(fp, " /* rep_high */ ");
265 if (rep_low)
266 fprintf(fp, " /* rep_low */ ");
267
268 if (swizzle == 0xE4) return; /* xyzw */
269
270 fprintf(fp, ".");
271 print_swizzle_helper(fp, swizzle, 0);
272 }
273 static void
274 print_swizzle_vec2(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low)
275 {
276 if (rep_high)
277 fprintf(fp, " /* rep_high */ ");
278 if (rep_low)
279 fprintf(fp, " /* rep_low */ ");
280
281 if (swizzle == 0xE4) return; /* XY */
282
283 fprintf(fp, ".");
284
285 for (unsigned i = 0; i < 4; i += 2) {
286 unsigned a = (swizzle >> (i * 2)) & 3;
287 unsigned b = (swizzle >> ((i+1) * 2)) & 3;
288
289 /* Normally we're adjacent, but if there's an issue, don't make
290 * it ambiguous */
291
292 if (a & 0x1)
293 fprintf(fp, "[%c%c]", components[a], components[b]);
294 else if (a == b)
295 fprintf(fp, "%c", components[a >> 1]);
296 else if (b == (a + 1))
297 fprintf(fp, "%c", "XY"[a >> 1]);
298 else
299 fprintf(fp, "[%c%c]", components[a], components[b]);
300 }
301 }
302
303 static int
304 bits_for_mode(midgard_reg_mode mode)
305 {
306 switch (mode) {
307 case midgard_reg_mode_8:
308 return 8;
309 case midgard_reg_mode_16:
310 return 16;
311 case midgard_reg_mode_32:
312 return 32;
313 case midgard_reg_mode_64:
314 return 64;
315 default:
316 unreachable("Invalid reg mode");
317 return 0;
318 }
319 }
320
321 static int
322 bits_for_mode_halved(midgard_reg_mode mode, bool half)
323 {
324 unsigned bits = bits_for_mode(mode);
325
326 if (half)
327 bits >>= 1;
328
329 return bits;
330 }
331
332 static void
333 print_scalar_constant(FILE *fp, unsigned src_binary,
334 const midgard_constants *consts,
335 midgard_scalar_alu *alu)
336 {
337 midgard_scalar_alu_src *src = (midgard_scalar_alu_src *)&src_binary;
338 unsigned mod = 0;
339
340 if (!midgard_is_integer_op(alu->op)) {
341 if (src->abs)
342 mod |= MIDGARD_FLOAT_MOD_ABS;
343 if (src->negate)
344 mod |= MIDGARD_FLOAT_MOD_NEG;
345 } else {
346 mod = midgard_int_normal;
347 }
348
349 fprintf(fp, "#");
350 mir_print_constant_component(fp, consts, src->component,
351 src->full ?
352 midgard_reg_mode_32 : midgard_reg_mode_16,
353 false, mod, alu->op);
354 }
355
356 static void
357 print_vector_constants(FILE *fp, unsigned src_binary,
358 const midgard_constants *consts,
359 midgard_vector_alu *alu)
360 {
361 midgard_vector_alu_src *src = (midgard_vector_alu_src *)&src_binary;
362 unsigned bits = bits_for_mode_halved(alu->reg_mode, src->half);
363 unsigned max_comp = MIN2((sizeof(*consts) * 8) / bits, 8);
364 unsigned comp_mask, num_comp = 0;
365
366 assert(consts);
367
368 comp_mask = effective_writemask(alu, condense_writemask(alu->mask, bits));
369 num_comp = util_bitcount(comp_mask);
370
371 fprintf(fp, "#");
372 if (num_comp > 1)
373 fprintf(fp, "vec%d(", num_comp);
374
375 bool first = true;
376
377 for (unsigned i = 0; i < max_comp; ++i) {
378 if (!(comp_mask & (1 << i))) continue;
379
380 unsigned c = (src->swizzle >> (i * 2)) & 3;
381
382 if (first)
383 first = false;
384 else
385 fprintf(fp, ", ");
386
387 mir_print_constant_component(fp, consts, c, alu->reg_mode,
388 src->half, src->mod, alu->op);
389 }
390
391 if (num_comp > 1)
392 fprintf(fp, ")");
393 }
394
395 static void
396 print_vector_src(FILE *fp, unsigned src_binary,
397 midgard_reg_mode mode, unsigned reg,
398 midgard_dest_override override, bool is_int)
399 {
400 midgard_vector_alu_src *src = (midgard_vector_alu_src *)&src_binary;
401
402 /* Modifiers change meaning depending on the op's context */
403
404 midgard_int_mod int_mod = src->mod;
405
406 if (is_int) {
407 fprintf(fp, "%s", srcmod_names_int[int_mod]);
408 } else {
409 if (src->mod & MIDGARD_FLOAT_MOD_NEG)
410 fprintf(fp, "-");
411
412 if (src->mod & MIDGARD_FLOAT_MOD_ABS)
413 fprintf(fp, "abs(");
414 }
415
416 //register
417 unsigned bits = bits_for_mode_halved(mode, src->half);
418 print_reg(fp, reg, bits);
419
420 //swizzle
421 if (bits == 16) {
422 /* When the mode of the instruction is itself 16-bit,
423 * rep_low/high work more or less as expected. But if the mode
424 * is 32-bit and we're stepping down, you only have vec4 and
425 * the meaning shifts to rep_low as higher-half and rep_high is
426 * never seen. TODO: are other modes similar? */
427
428 if (mode == midgard_reg_mode_32) {
429 fprintf(fp, ".");
430 print_swizzle_helper(fp, src->swizzle, src->rep_low);
431 assert(!src->rep_high);
432 } else {
433 print_swizzle_vec8(fp, src->swizzle, src->rep_high, src->rep_low);
434 }
435 } else if (bits == 8)
436 print_swizzle_vec16(fp, src->swizzle, src->rep_high, src->rep_low, override);
437 else if (bits == 32)
438 print_swizzle_vec4(fp, src->swizzle, src->rep_high, src->rep_low);
439 else if (bits == 64)
440 print_swizzle_vec2(fp, src->swizzle, src->rep_high, src->rep_low);
441
442 /* Since we wrapped with a function-looking thing */
443
444 if (is_int && int_mod == midgard_int_shift)
445 fprintf(fp, ") << %u", bits);
446 else if ((is_int && (int_mod != midgard_int_normal))
447 || (!is_int && src->mod & MIDGARD_FLOAT_MOD_ABS))
448 fprintf(fp, ")");
449 }
450
451 static uint16_t
452 decode_vector_imm(unsigned src2_reg, unsigned imm)
453 {
454 uint16_t ret;
455 ret = src2_reg << 11;
456 ret |= (imm & 0x7) << 8;
457 ret |= (imm >> 3) & 0xFF;
458 return ret;
459 }
460
461 static void
462 print_immediate(FILE *fp, uint16_t imm)
463 {
464 if (is_instruction_int)
465 fprintf(fp, "#%u", imm);
466 else
467 fprintf(fp, "#%g", _mesa_half_to_float(imm));
468 }
469
470 static void
471 update_dest(unsigned reg)
472 {
473 /* We should record writes as marking this as a work register. Store
474 * the max register in work_count; we'll add one at the end */
475
476 if (reg < 16) {
477 midg_stats.work_count = MAX2(reg, midg_stats.work_count);
478 midg_ever_written |= (1 << reg);
479 }
480 }
481
482 static void
483 print_dest(FILE *fp, unsigned reg, midgard_reg_mode mode, midgard_dest_override override)
484 {
485 /* Depending on the mode and override, we determine the type of
486 * destination addressed. Absent an override, we address just the
487 * type of the operation itself */
488
489 unsigned bits = bits_for_mode(mode);
490
491 if (override != midgard_dest_override_none)
492 bits /= 2;
493
494 update_dest(reg);
495 print_reg(fp, reg, bits);
496 }
497
498 static void
499 print_mask_vec16(FILE *fp, uint8_t mask, midgard_dest_override override)
500 {
501 fprintf(fp, ".");
502
503 for (unsigned i = 0; i < 8; i++) {
504 if (mask & (1 << i))
505 fprintf(fp, "%c%c",
506 components[i*2 + 0],
507 components[i*2 + 1]);
508 }
509 }
510
511 /* For 16-bit+ masks, we read off from the 8-bit mask field. For 16-bit (vec8),
512 * it's just one bit per channel, easy peasy. For 32-bit (vec4), it's one bit
513 * per channel with one duplicate bit in the middle. For 64-bit (vec2), it's
514 * one-bit per channel with _3_ duplicate bits in the middle. Basically, just
515 * subdividing the 128-bit word in 16-bit increments. For 64-bit, we uppercase
516 * the mask to make it obvious what happened */
517
518 static void
519 print_mask(FILE *fp, uint8_t mask, unsigned bits, midgard_dest_override override)
520 {
521 if (bits == 8) {
522 print_mask_vec16(fp, mask, override);
523 return;
524 }
525
526 /* Skip 'complete' masks */
527
528 if (override == midgard_dest_override_none) {
529 if (bits >= 32 && mask == 0xFF) return;
530
531 if (bits == 16) {
532 if (mask == 0x0F)
533 return;
534 else if (mask == 0xF0) {
535 fprintf(fp, "'");
536 return;
537 }
538 }
539 }
540
541 fprintf(fp, ".");
542
543 unsigned skip = (bits / 16);
544 bool uppercase = bits > 32;
545 bool tripped = false;
546
547 /* To apply an upper destination override, we "shift" the alphabet.
548 * E.g. with an upper override on 32-bit, instead of xyzw, print efgh.
549 * For upper 16-bit, instead of xyzwefgh, print ijklmnop */
550
551 const char *alphabet = components;
552
553 if (override == midgard_dest_override_upper)
554 alphabet += (128 / bits);
555
556 for (unsigned i = 0; i < 8; i += skip) {
557 bool a = (mask & (1 << i)) != 0;
558
559 for (unsigned j = 1; j < skip; ++j) {
560 bool dupe = (mask & (1 << (i + j))) != 0;
561 tripped |= (dupe != a);
562 }
563
564 if (a) {
565 char c = alphabet[i / skip];
566
567 if (uppercase)
568 c = toupper(c);
569
570 fprintf(fp, "%c", c);
571 }
572 }
573
574 if (tripped)
575 fprintf(fp, " /* %X */", mask);
576 }
577
578 /* Prints the 4-bit masks found in texture and load/store ops, as opposed to
579 * the 8-bit masks found in (vector) ALU ops. Supports texture-style 16-bit
580 * mode as well, but not load/store-style 16-bit mode. */
581
582 static void
583 print_mask_4(FILE *fp, unsigned mask, bool upper)
584 {
585 if (mask == 0xF) {
586 if (upper)
587 fprintf(fp, "'");
588
589 return;
590 }
591
592 fprintf(fp, ".");
593
594 for (unsigned i = 0; i < 4; ++i) {
595 bool a = (mask & (1 << i)) != 0;
596 if (a)
597 fprintf(fp, "%c", components[i + (upper ? 4 : 0)]);
598 }
599 }
600
601 static void
602 print_vector_field(FILE *fp, const char *name, uint16_t *words, uint16_t reg_word,
603 const midgard_constants *consts, unsigned tabs)
604 {
605 midgard_reg_info *reg_info = (midgard_reg_info *)&reg_word;
606 midgard_vector_alu *alu_field = (midgard_vector_alu *) words;
607 midgard_reg_mode mode = alu_field->reg_mode;
608 unsigned override = alu_field->dest_override;
609
610 /* For now, prefix instruction names with their unit, until we
611 * understand how this works on a deeper level */
612 fprintf(fp, "%s.", name);
613
614 print_alu_opcode(fp, alu_field->op);
615
616 /* Postfix with the size to disambiguate if necessary */
617 char postfix = prefix_for_bits(bits_for_mode(mode));
618 bool size_ambiguous = override != midgard_dest_override_none;
619
620 if (size_ambiguous)
621 fprintf(fp, "%c", postfix ? postfix : 'r');
622
623 /* Print the outmod, if there is one */
624 print_outmod(fp, alu_field->outmod,
625 midgard_is_integer_out_op(alu_field->op));
626
627 fprintf(fp, " ");
628
629 /* Mask denoting status of 8-lanes */
630 uint8_t mask = alu_field->mask;
631
632 /* First, print the destination */
633 print_dest(fp, reg_info->out_reg, mode, alu_field->dest_override);
634
635 if (override != midgard_dest_override_none) {
636 bool modeable = (mode != midgard_reg_mode_8);
637 bool known = override != 0x3; /* Unused value */
638
639 if (!(modeable && known))
640 fprintf(fp, "/* do%u */ ", override);
641 }
642
643 print_mask(fp, mask, bits_for_mode(mode), override);
644
645 fprintf(fp, ", ");
646
647 bool is_int = midgard_is_integer_op(alu_field->op);
648
649 if (reg_info->src1_reg == 26)
650 print_vector_constants(fp, alu_field->src1, consts, alu_field);
651 else
652 print_vector_src(fp, alu_field->src1, mode, reg_info->src1_reg, override, is_int);
653
654 fprintf(fp, ", ");
655
656 if (reg_info->src2_imm) {
657 uint16_t imm = decode_vector_imm(reg_info->src2_reg, alu_field->src2 >> 2);
658 print_immediate(fp, imm);
659 } else if (reg_info->src2_reg == 26) {
660 print_vector_constants(fp, alu_field->src2, consts, alu_field);
661 } else {
662 print_vector_src(fp, alu_field->src2, mode,
663 reg_info->src2_reg, override, is_int);
664 }
665
666 midg_stats.instruction_count++;
667 fprintf(fp, "\n");
668 }
669
670 static void
671 print_scalar_src(FILE *fp, unsigned src_binary, unsigned reg)
672 {
673 midgard_scalar_alu_src *src = (midgard_scalar_alu_src *)&src_binary;
674
675 if (src->negate)
676 fprintf(fp, "-");
677
678 if (src->abs)
679 fprintf(fp, "abs(");
680
681 print_reg(fp, reg, src->full ? 32 : 16);
682
683 unsigned c = src->component;
684
685 if (src->full) {
686 assert((c & 1) == 0);
687 c >>= 1;
688 }
689
690 fprintf(fp, ".%c", components[c]);
691
692 if (src->abs)
693 fprintf(fp, ")");
694
695 }
696
697 static uint16_t
698 decode_scalar_imm(unsigned src2_reg, unsigned imm)
699 {
700 uint16_t ret;
701 ret = src2_reg << 11;
702 ret |= (imm & 3) << 9;
703 ret |= (imm & 4) << 6;
704 ret |= (imm & 0x38) << 2;
705 ret |= imm >> 6;
706 return ret;
707 }
708
709 static void
710 print_scalar_field(FILE *fp, const char *name, uint16_t *words, uint16_t reg_word,
711 const midgard_constants *consts, unsigned tabs)
712 {
713 midgard_reg_info *reg_info = (midgard_reg_info *)&reg_word;
714 midgard_scalar_alu *alu_field = (midgard_scalar_alu *) words;
715
716 if (alu_field->unknown)
717 fprintf(fp, "scalar ALU unknown bit set\n");
718
719 fprintf(fp, "%s.", name);
720 print_alu_opcode(fp, alu_field->op);
721 print_outmod(fp, alu_field->outmod,
722 midgard_is_integer_out_op(alu_field->op));
723 fprintf(fp, " ");
724
725 bool full = alu_field->output_full;
726 update_dest(reg_info->out_reg);
727 print_reg(fp, reg_info->out_reg, full ? 32 : 16);
728 unsigned c = alu_field->output_component;
729
730 if (full) {
731 assert((c & 1) == 0);
732 c >>= 1;
733 }
734
735 fprintf(fp, ".%c, ", components[c]);
736
737 if (reg_info->src1_reg == 26)
738 print_scalar_constant(fp, alu_field->src1, consts, alu_field);
739 else
740 print_scalar_src(fp, alu_field->src1, reg_info->src1_reg);
741
742 fprintf(fp, ", ");
743
744 if (reg_info->src2_imm) {
745 uint16_t imm = decode_scalar_imm(reg_info->src2_reg,
746 alu_field->src2);
747 print_immediate(fp, imm);
748 } else if (reg_info->src2_reg == 26) {
749 print_scalar_constant(fp, alu_field->src2, consts, alu_field);
750 } else
751 print_scalar_src(fp, alu_field->src2, reg_info->src2_reg);
752
753 midg_stats.instruction_count++;
754 fprintf(fp, "\n");
755 }
756
757 static void
758 print_branch_op(FILE *fp, unsigned op)
759 {
760 switch (op) {
761 case midgard_jmp_writeout_op_branch_uncond:
762 fprintf(fp, "uncond.");
763 break;
764
765 case midgard_jmp_writeout_op_branch_cond:
766 fprintf(fp, "cond.");
767 break;
768
769 case midgard_jmp_writeout_op_writeout:
770 fprintf(fp, "write.");
771 break;
772
773 case midgard_jmp_writeout_op_tilebuffer_pending:
774 fprintf(fp, "tilebuffer.");
775 break;
776
777 case midgard_jmp_writeout_op_discard:
778 fprintf(fp, "discard.");
779 break;
780
781 default:
782 fprintf(fp, "unk%u.", op);
783 break;
784 }
785 }
786
787 static void
788 print_branch_cond(FILE *fp, int cond)
789 {
790 switch (cond) {
791 case midgard_condition_write0:
792 fprintf(fp, "write0");
793 break;
794
795 case midgard_condition_false:
796 fprintf(fp, "false");
797 break;
798
799 case midgard_condition_true:
800 fprintf(fp, "true");
801 break;
802
803 case midgard_condition_always:
804 fprintf(fp, "always");
805 break;
806
807 default:
808 fprintf(fp, "unk%X", cond);
809 break;
810 }
811 }
812
813 static bool
814 print_compact_branch_writeout_field(FILE *fp, uint16_t word)
815 {
816 midgard_jmp_writeout_op op = word & 0x7;
817 midg_stats.instruction_count++;
818
819 switch (op) {
820 case midgard_jmp_writeout_op_branch_uncond: {
821 midgard_branch_uncond br_uncond;
822 memcpy((char *) &br_uncond, (char *) &word, sizeof(br_uncond));
823 fprintf(fp, "br.uncond ");
824
825 if (br_uncond.unknown != 1)
826 fprintf(fp, "unknown:%u, ", br_uncond.unknown);
827
828 if (br_uncond.offset >= 0)
829 fprintf(fp, "+");
830
831 fprintf(fp, "%d -> ", br_uncond.offset);
832 print_tag_short(fp, br_uncond.dest_tag);
833 fprintf(fp, "\n");
834
835 return br_uncond.offset >= 0;
836 }
837
838 case midgard_jmp_writeout_op_branch_cond:
839 case midgard_jmp_writeout_op_writeout:
840 case midgard_jmp_writeout_op_discard:
841 default: {
842 midgard_branch_cond br_cond;
843 memcpy((char *) &br_cond, (char *) &word, sizeof(br_cond));
844
845 fprintf(fp, "br.");
846
847 print_branch_op(fp, br_cond.op);
848 print_branch_cond(fp, br_cond.cond);
849
850 fprintf(fp, " ");
851
852 if (br_cond.offset >= 0)
853 fprintf(fp, "+");
854
855 fprintf(fp, "%d -> ", br_cond.offset);
856 print_tag_short(fp, br_cond.dest_tag);
857 fprintf(fp, "\n");
858
859 return br_cond.offset >= 0;
860 }
861 }
862
863 return false;
864 }
865
866 static bool
867 print_extended_branch_writeout_field(FILE *fp, uint8_t *words, unsigned next)
868 {
869 midgard_branch_extended br;
870 memcpy((char *) &br, (char *) words, sizeof(br));
871
872 fprintf(fp, "brx.");
873
874 print_branch_op(fp, br.op);
875
876 /* Condition codes are a LUT in the general case, but simply repeated 8 times for single-channel conditions.. Check this. */
877
878 bool single_channel = true;
879
880 for (unsigned i = 0; i < 16; i += 2) {
881 single_channel &= (((br.cond >> i) & 0x3) == (br.cond & 0x3));
882 }
883
884 if (single_channel)
885 print_branch_cond(fp, br.cond & 0x3);
886 else
887 fprintf(fp, "lut%X", br.cond);
888
889 if (br.unknown)
890 fprintf(fp, ".unknown%u", br.unknown);
891
892 fprintf(fp, " ");
893
894 if (br.offset >= 0)
895 fprintf(fp, "+");
896
897 fprintf(fp, "%d -> ", br.offset);
898 print_tag_short(fp, br.dest_tag);
899 fprintf(fp, "\n");
900
901 unsigned I = next + br.offset * 4;
902
903 if (midg_tags[I] && midg_tags[I] != br.dest_tag) {
904 fprintf(fp, "\t/* XXX TAG ERROR: jumping to ");
905 print_tag_short(fp, br.dest_tag);
906 fprintf(fp, " but tagged ");
907 print_tag_short(fp, midg_tags[I]);
908 fprintf(fp, " */\n");
909 }
910
911 midg_tags[I] = br.dest_tag;
912
913 midg_stats.instruction_count++;
914 return br.offset >= 0;
915 }
916
917 static unsigned
918 num_alu_fields_enabled(uint32_t control_word)
919 {
920 unsigned ret = 0;
921
922 if ((control_word >> 17) & 1)
923 ret++;
924
925 if ((control_word >> 19) & 1)
926 ret++;
927
928 if ((control_word >> 21) & 1)
929 ret++;
930
931 if ((control_word >> 23) & 1)
932 ret++;
933
934 if ((control_word >> 25) & 1)
935 ret++;
936
937 return ret;
938 }
939
940 static float
941 float_bitcast(uint32_t integer)
942 {
943 union {
944 uint32_t i;
945 float f;
946 } v;
947
948 v.i = integer;
949 return v.f;
950 }
951
952 static bool
953 print_alu_word(FILE *fp, uint32_t *words, unsigned num_quad_words,
954 unsigned tabs, unsigned next)
955 {
956 uint32_t control_word = words[0];
957 uint16_t *beginning_ptr = (uint16_t *)(words + 1);
958 unsigned num_fields = num_alu_fields_enabled(control_word);
959 uint16_t *word_ptr = beginning_ptr + num_fields;
960 unsigned num_words = 2 + num_fields;
961 const midgard_constants *consts = NULL;
962 bool branch_forward = false;
963
964 if ((control_word >> 17) & 1)
965 num_words += 3;
966
967 if ((control_word >> 19) & 1)
968 num_words += 2;
969
970 if ((control_word >> 21) & 1)
971 num_words += 3;
972
973 if ((control_word >> 23) & 1)
974 num_words += 2;
975
976 if ((control_word >> 25) & 1)
977 num_words += 3;
978
979 if ((control_word >> 26) & 1)
980 num_words += 1;
981
982 if ((control_word >> 27) & 1)
983 num_words += 3;
984
985 if (num_quad_words > (num_words + 7) / 8) {
986 assert(num_quad_words == (num_words + 15) / 8);
987 //Assume that the extra quadword is constants
988 consts = (midgard_constants *)(words + (4 * num_quad_words - 4));
989 }
990
991 if ((control_word >> 16) & 1)
992 fprintf(fp, "unknown bit 16 enabled\n");
993
994 if ((control_word >> 17) & 1) {
995 print_vector_field(fp, "vmul", word_ptr, *beginning_ptr, consts, tabs);
996 beginning_ptr += 1;
997 word_ptr += 3;
998 }
999
1000 if ((control_word >> 18) & 1)
1001 fprintf(fp, "unknown bit 18 enabled\n");
1002
1003 if ((control_word >> 19) & 1) {
1004 print_scalar_field(fp, "sadd", word_ptr, *beginning_ptr, consts, tabs);
1005 beginning_ptr += 1;
1006 word_ptr += 2;
1007 }
1008
1009 if ((control_word >> 20) & 1)
1010 fprintf(fp, "unknown bit 20 enabled\n");
1011
1012 if ((control_word >> 21) & 1) {
1013 print_vector_field(fp, "vadd", word_ptr, *beginning_ptr, consts, tabs);
1014 beginning_ptr += 1;
1015 word_ptr += 3;
1016 }
1017
1018 if ((control_word >> 22) & 1)
1019 fprintf(fp, "unknown bit 22 enabled\n");
1020
1021 if ((control_word >> 23) & 1) {
1022 print_scalar_field(fp, "smul", word_ptr, *beginning_ptr, consts, tabs);
1023 beginning_ptr += 1;
1024 word_ptr += 2;
1025 }
1026
1027 if ((control_word >> 24) & 1)
1028 fprintf(fp, "unknown bit 24 enabled\n");
1029
1030 if ((control_word >> 25) & 1) {
1031 print_vector_field(fp, "lut", word_ptr, *beginning_ptr, consts, tabs);
1032 word_ptr += 3;
1033 }
1034
1035 if ((control_word >> 26) & 1) {
1036 branch_forward |= print_compact_branch_writeout_field(fp, *word_ptr);
1037 word_ptr += 1;
1038 }
1039
1040 if ((control_word >> 27) & 1) {
1041 branch_forward |= print_extended_branch_writeout_field(fp, (uint8_t *) word_ptr, next);
1042 word_ptr += 3;
1043 }
1044
1045 if (consts)
1046 fprintf(fp, "uconstants 0x%X, 0x%X, 0x%X, 0x%X\n",
1047 consts->u32[0], consts->u32[1],
1048 consts->u32[2], consts->u32[3]);
1049
1050 return branch_forward;
1051 }
1052
1053 static void
1054 print_varying_parameters(FILE *fp, midgard_load_store_word *word)
1055 {
1056 midgard_varying_parameter param;
1057 unsigned v = word->varying_parameters;
1058 memcpy(&param, &v, sizeof(param));
1059
1060 if (param.is_varying) {
1061 /* If a varying, there are qualifiers */
1062 if (param.flat)
1063 fprintf(fp, ".flat");
1064
1065 if (param.interpolation != midgard_interp_default) {
1066 if (param.interpolation == midgard_interp_centroid)
1067 fprintf(fp, ".centroid");
1068 else
1069 fprintf(fp, ".interp%d", param.interpolation);
1070 }
1071
1072 if (param.modifier != midgard_varying_mod_none) {
1073 if (param.modifier == midgard_varying_mod_perspective_w)
1074 fprintf(fp, ".perspectivew");
1075 else if (param.modifier == midgard_varying_mod_perspective_z)
1076 fprintf(fp, ".perspectivez");
1077 else
1078 fprintf(fp, ".mod%d", param.modifier);
1079 }
1080 } else if (param.flat || param.interpolation || param.modifier) {
1081 fprintf(fp, " /* is_varying not set but varying metadata attached */");
1082 }
1083
1084 if (param.zero0 || param.zero1 || param.zero2)
1085 fprintf(fp, " /* zero tripped, %u %u %u */ ", param.zero0, param.zero1, param.zero2);
1086 }
1087
1088 static bool
1089 is_op_varying(unsigned op)
1090 {
1091 switch (op) {
1092 case midgard_op_st_vary_16:
1093 case midgard_op_st_vary_32:
1094 case midgard_op_st_vary_32i:
1095 case midgard_op_st_vary_32u:
1096 case midgard_op_ld_vary_16:
1097 case midgard_op_ld_vary_32:
1098 case midgard_op_ld_vary_32i:
1099 case midgard_op_ld_vary_32u:
1100 return true;
1101 }
1102
1103 return false;
1104 }
1105
1106 static bool
1107 is_op_attribute(unsigned op)
1108 {
1109 switch (op) {
1110 case midgard_op_ld_attr_16:
1111 case midgard_op_ld_attr_32:
1112 case midgard_op_ld_attr_32i:
1113 case midgard_op_ld_attr_32u:
1114 return true;
1115 }
1116
1117 return false;
1118 }
1119
1120 static void
1121 print_load_store_arg(FILE *fp, uint8_t arg, unsigned index)
1122 {
1123 /* Try to interpret as a register */
1124 midgard_ldst_register_select sel;
1125 memcpy(&sel, &arg, sizeof(arg));
1126
1127 /* If unknown is set, we're not sure what this is or how to
1128 * interpret it. But if it's zero, we get it. */
1129
1130 if (sel.unknown) {
1131 fprintf(fp, "0x%02X", arg);
1132 return;
1133 }
1134
1135 unsigned reg = REGISTER_LDST_BASE + sel.select;
1136 char comp = components[sel.component];
1137
1138 fprintf(fp, "r%u.%c", reg, comp);
1139
1140 /* Only print a shift if it's non-zero. Shifts only make sense for the
1141 * second index. For the first, we're not sure what it means yet */
1142
1143 if (index == 1) {
1144 if (sel.shift)
1145 fprintf(fp, " << %u", sel.shift);
1146 } else {
1147 fprintf(fp, " /* %X */", sel.shift);
1148 }
1149 }
1150
1151 static void
1152 update_stats(signed *stat, unsigned address)
1153 {
1154 if (*stat >= 0)
1155 *stat = MAX2(*stat, address + 1);
1156 }
1157
1158 static void
1159 print_load_store_instr(FILE *fp, uint64_t data,
1160 unsigned tabs)
1161 {
1162 midgard_load_store_word *word = (midgard_load_store_word *) &data;
1163
1164 print_ld_st_opcode(fp, word->op);
1165
1166 unsigned address = word->address;
1167
1168 if (is_op_varying(word->op)) {
1169 print_varying_parameters(fp, word);
1170
1171 /* Do some analysis: check if direct cacess */
1172
1173 if ((word->arg_2 == 0x1E) && midg_stats.varying_count >= 0)
1174 update_stats(&midg_stats.varying_count, address);
1175 else
1176 midg_stats.varying_count = -16;
1177 } else if (is_op_attribute(word->op)) {
1178 if ((word->arg_2 == 0x1E) && midg_stats.attribute_count >= 0)
1179 update_stats(&midg_stats.attribute_count, address);
1180 else
1181 midg_stats.attribute_count = -16;
1182 }
1183
1184 fprintf(fp, " r%u", word->reg + (OP_IS_STORE(word->op) ? 26 : 0));
1185 print_mask_4(fp, word->mask, false);
1186
1187 if (!OP_IS_STORE(word->op))
1188 update_dest(word->reg);
1189
1190 bool is_ubo = OP_IS_UBO_READ(word->op);
1191
1192 if (is_ubo) {
1193 /* UBOs use their own addressing scheme */
1194
1195 int lo = word->varying_parameters >> 7;
1196 int hi = word->address;
1197
1198 /* TODO: Combine fields logically */
1199 address = (hi << 3) | lo;
1200 }
1201
1202 fprintf(fp, ", %u", address);
1203
1204 print_swizzle_vec4(fp, word->swizzle, false, false);
1205
1206 fprintf(fp, ", ");
1207
1208 if (is_ubo) {
1209 fprintf(fp, "ubo%u", word->arg_1);
1210 update_stats(&midg_stats.uniform_buffer_count, word->arg_1);
1211 } else
1212 print_load_store_arg(fp, word->arg_1, 0);
1213
1214 fprintf(fp, ", ");
1215 print_load_store_arg(fp, word->arg_2, 1);
1216 fprintf(fp, " /* %X */\n", word->varying_parameters);
1217
1218 midg_stats.instruction_count++;
1219 }
1220
1221 static void
1222 print_load_store_word(FILE *fp, uint32_t *word, unsigned tabs)
1223 {
1224 midgard_load_store *load_store = (midgard_load_store *) word;
1225
1226 if (load_store->word1 != 3) {
1227 print_load_store_instr(fp, load_store->word1, tabs);
1228 }
1229
1230 if (load_store->word2 != 3) {
1231 print_load_store_instr(fp, load_store->word2, tabs);
1232 }
1233 }
1234
1235 static void
1236 print_texture_reg_select(FILE *fp, uint8_t u, unsigned base)
1237 {
1238 midgard_tex_register_select sel;
1239 memcpy(&sel, &u, sizeof(u));
1240
1241 if (!sel.full)
1242 fprintf(fp, "h");
1243
1244 fprintf(fp, "r%u", base + sel.select);
1245
1246 unsigned component = sel.component;
1247
1248 /* Use the upper half in half-reg mode */
1249 if (sel.upper) {
1250 assert(!sel.full);
1251 component += 4;
1252 }
1253
1254 fprintf(fp, ".%c", components[component]);
1255
1256 assert(sel.zero == 0);
1257 }
1258
1259 static void
1260 print_texture_format(FILE *fp, int format)
1261 {
1262 /* Act like a modifier */
1263 fprintf(fp, ".");
1264
1265 switch (format) {
1266 DEFINE_CASE(MALI_TEX_1D, "1d");
1267 DEFINE_CASE(MALI_TEX_2D, "2d");
1268 DEFINE_CASE(MALI_TEX_3D, "3d");
1269 DEFINE_CASE(MALI_TEX_CUBE, "cube");
1270
1271 default:
1272 unreachable("Bad format");
1273 }
1274 }
1275
1276 static bool
1277 midgard_op_has_helpers(unsigned op, bool gather)
1278 {
1279 if (gather)
1280 return true;
1281
1282 switch (op) {
1283 case TEXTURE_OP_NORMAL:
1284 case TEXTURE_OP_DFDX:
1285 case TEXTURE_OP_DFDY:
1286 return true;
1287 default:
1288 return false;
1289 }
1290 }
1291
1292 static void
1293 print_texture_op(FILE *fp, unsigned op, bool gather)
1294 {
1295 /* Act like a bare name, like ESSL functions */
1296
1297 if (gather) {
1298 fprintf(fp, "textureGather");
1299
1300 unsigned component = op >> 4;
1301 unsigned bottom = op & 0xF;
1302
1303 if (bottom != 0x2)
1304 fprintf(fp, "_unk%u", bottom);
1305
1306 fprintf(fp, ".%c", components[component]);
1307 return;
1308 }
1309
1310 switch (op) {
1311 DEFINE_CASE(TEXTURE_OP_NORMAL, "texture");
1312 DEFINE_CASE(TEXTURE_OP_LOD, "textureLod");
1313 DEFINE_CASE(TEXTURE_OP_TEXEL_FETCH, "texelFetch");
1314 DEFINE_CASE(TEXTURE_OP_BARRIER, "barrier");
1315 DEFINE_CASE(TEXTURE_OP_DFDX, "dFdx");
1316 DEFINE_CASE(TEXTURE_OP_DFDY, "dFdy");
1317
1318 default:
1319 fprintf(fp, "tex_%X", op);
1320 break;
1321 }
1322 }
1323
1324 static bool
1325 texture_op_takes_bias(unsigned op)
1326 {
1327 return op == TEXTURE_OP_NORMAL;
1328 }
1329
1330 static char
1331 sampler_type_name(enum mali_sampler_type t)
1332 {
1333 switch (t) {
1334 case MALI_SAMPLER_FLOAT:
1335 return 'f';
1336 case MALI_SAMPLER_UNSIGNED:
1337 return 'u';
1338 case MALI_SAMPLER_SIGNED:
1339 return 'i';
1340 default:
1341 return '?';
1342 }
1343
1344 }
1345
1346 static void
1347 print_texture_barrier(FILE *fp, uint32_t *word)
1348 {
1349 midgard_texture_barrier_word *barrier = (midgard_texture_barrier_word *) word;
1350
1351 if (barrier->type != 0x4)
1352 fprintf(fp, "/* barrier tag %X != 0x4 */ ", barrier->type);
1353
1354 if (!barrier->cont)
1355 fprintf(fp, "/* cont missing? */");
1356
1357 if (!barrier->last)
1358 fprintf(fp, "/* last missing? */");
1359
1360 if (barrier->zero1)
1361 fprintf(fp, "/* zero1 = 0x%X */ ", barrier->zero1);
1362
1363 if (barrier->zero2)
1364 fprintf(fp, "/* zero2 = 0x%X */ ", barrier->zero2);
1365
1366 if (barrier->zero3)
1367 fprintf(fp, "/* zero3 = 0x%X */ ", barrier->zero3);
1368
1369 if (barrier->zero4)
1370 fprintf(fp, "/* zero4 = 0x%X */ ", barrier->zero4);
1371
1372 if (barrier->zero5)
1373 fprintf(fp, "/* zero4 = 0x%" PRIx64 " */ ", barrier->zero5);
1374
1375 fprintf(fp, " 0x%X\n", barrier->unknown4);
1376 }
1377
1378 #undef DEFINE_CASE
1379
1380 static void
1381 print_texture_word(FILE *fp, uint32_t *word, unsigned tabs, unsigned in_reg_base, unsigned out_reg_base)
1382 {
1383 midgard_texture_word *texture = (midgard_texture_word *) word;
1384
1385 midg_stats.helper_invocations |=
1386 midgard_op_has_helpers(texture->op, texture->is_gather);
1387
1388 /* Broad category of texture operation in question */
1389 print_texture_op(fp, texture->op, texture->is_gather);
1390
1391 /* Barriers use a dramatically different code path */
1392 if (texture->op == TEXTURE_OP_BARRIER) {
1393 print_texture_barrier(fp, word);
1394 return;
1395 } else if (texture->type == 0x4)
1396 fprintf (fp, "/* nonbarrier had tag 0x4 */ ");
1397
1398 /* Specific format in question */
1399 print_texture_format(fp, texture->format);
1400
1401 /* Instruction "modifiers" parallel the ALU instructions. */
1402
1403 if (texture->shadow)
1404 fprintf(fp, ".shadow");
1405
1406 if (texture->cont)
1407 fprintf(fp, ".cont");
1408
1409 if (texture->last)
1410 fprintf(fp, ".last");
1411
1412 /* Output modifiers are always interpreted floatly */
1413 print_outmod(fp, texture->outmod, false);
1414
1415 fprintf(fp, " %sr%u", texture->out_full ? "" : "h",
1416 out_reg_base + texture->out_reg_select);
1417 print_mask_4(fp, texture->mask, texture->out_upper);
1418 assert(!(texture->out_full && texture->out_upper));
1419 fprintf(fp, ", ");
1420
1421 /* Depending on whether we read from textures directly or indirectly,
1422 * we may be able to update our analysis */
1423
1424 if (texture->texture_register) {
1425 fprintf(fp, "texture[");
1426 print_texture_reg_select(fp, texture->texture_handle, in_reg_base);
1427 fprintf(fp, "], ");
1428
1429 /* Indirect, tut tut */
1430 midg_stats.texture_count = -16;
1431 } else {
1432 fprintf(fp, "texture%u, ", texture->texture_handle);
1433 update_stats(&midg_stats.texture_count, texture->texture_handle);
1434 }
1435
1436 /* Print the type, GL style */
1437 fprintf(fp, "%csampler", sampler_type_name(texture->sampler_type));
1438
1439 if (texture->sampler_register) {
1440 fprintf(fp, "[");
1441 print_texture_reg_select(fp, texture->sampler_handle, in_reg_base);
1442 fprintf(fp, "]");
1443
1444 midg_stats.sampler_count = -16;
1445 } else {
1446 fprintf(fp, "%u", texture->sampler_handle);
1447 update_stats(&midg_stats.sampler_count, texture->sampler_handle);
1448 }
1449
1450 print_swizzle_vec4(fp, texture->swizzle, false, false);
1451 fprintf(fp, ", %sr%u", texture->in_reg_full ? "" : "h", in_reg_base + texture->in_reg_select);
1452 assert(!(texture->in_reg_full && texture->in_reg_upper));
1453
1454 /* TODO: integrate with swizzle */
1455 if (texture->in_reg_upper)
1456 fprintf(fp, "'");
1457
1458 print_swizzle_vec4(fp, texture->in_reg_swizzle, false, false);
1459
1460 /* There is *always* an offset attached. Of
1461 * course, that offset is just immediate #0 for a
1462 * GLES call that doesn't take an offset. If there
1463 * is a non-negative non-zero offset, this is
1464 * specified in immediate offset mode, with the
1465 * values in the offset_* fields as immediates. If
1466 * this is a negative offset, we instead switch to
1467 * a register offset mode, where the offset_*
1468 * fields become register triplets */
1469
1470 if (texture->offset_register) {
1471 fprintf(fp, " + ");
1472
1473 bool full = texture->offset & 1;
1474 bool select = texture->offset & 2;
1475 bool upper = texture->offset & 4;
1476
1477 fprintf(fp, "%sr%u", full ? "" : "h", in_reg_base + select);
1478 assert(!(texture->out_full && texture->out_upper));
1479
1480 /* TODO: integrate with swizzle */
1481 if (upper)
1482 fprintf(fp, "'");
1483
1484 print_swizzle_vec4(fp, texture->offset >> 3, false, false);
1485
1486 fprintf(fp, ", ");
1487 } else if (texture->offset) {
1488 /* Only select ops allow negative immediate offsets, verify */
1489
1490 signed offset_x = (texture->offset & 0xF);
1491 signed offset_y = ((texture->offset >> 4) & 0xF);
1492 signed offset_z = ((texture->offset >> 8) & 0xF);
1493
1494 bool neg_x = offset_x < 0;
1495 bool neg_y = offset_y < 0;
1496 bool neg_z = offset_z < 0;
1497 bool any_neg = neg_x || neg_y || neg_z;
1498
1499 if (any_neg && texture->op != TEXTURE_OP_TEXEL_FETCH)
1500 fprintf(fp, "/* invalid negative */ ");
1501
1502 /* Regardless, just print the immediate offset */
1503
1504 fprintf(fp, " + <%d, %d, %d>, ", offset_x, offset_y, offset_z);
1505 } else {
1506 fprintf(fp, ", ");
1507 }
1508
1509 char lod_operand = texture_op_takes_bias(texture->op) ? '+' : '=';
1510
1511 if (texture->lod_register) {
1512 fprintf(fp, "lod %c ", lod_operand);
1513 print_texture_reg_select(fp, texture->bias, in_reg_base);
1514 fprintf(fp, ", ");
1515
1516 if (texture->bias_int)
1517 fprintf(fp, " /* bias_int = 0x%X */", texture->bias_int);
1518 } else if (texture->op == TEXTURE_OP_TEXEL_FETCH) {
1519 /* For texel fetch, the int LOD is in the fractional place and
1520 * there is no fraction / possibility of bias. We *always* have
1521 * an explicit LOD, even if it's zero. */
1522
1523 if (texture->bias_int)
1524 fprintf(fp, " /* bias_int = 0x%X */ ", texture->bias_int);
1525
1526 fprintf(fp, "lod = %u, ", texture->bias);
1527 } else if (texture->bias || texture->bias_int) {
1528 signed bias_int = texture->bias_int;
1529 float bias_frac = texture->bias / 256.0f;
1530 float bias = bias_int + bias_frac;
1531
1532 bool is_bias = texture_op_takes_bias(texture->op);
1533 char sign = (bias >= 0.0) ? '+' : '-';
1534 char operand = is_bias ? sign : '=';
1535
1536 fprintf(fp, "lod %c %f, ", operand, fabsf(bias));
1537 }
1538
1539 fprintf(fp, "\n");
1540
1541 /* While not zero in general, for these simple instructions the
1542 * following unknowns are zero, so we don't include them */
1543
1544 if (texture->unknown4 ||
1545 texture->unknownA ||
1546 texture->unknown8) {
1547 fprintf(fp, "// unknown4 = 0x%x\n", texture->unknown4);
1548 fprintf(fp, "// unknownA = 0x%x\n", texture->unknownA);
1549 fprintf(fp, "// unknown8 = 0x%x\n", texture->unknown8);
1550 }
1551
1552 midg_stats.instruction_count++;
1553 }
1554
1555 struct midgard_disasm_stats
1556 disassemble_midgard(FILE *fp, uint8_t *code, size_t size, unsigned gpu_id, gl_shader_stage stage)
1557 {
1558 uint32_t *words = (uint32_t *) code;
1559 unsigned num_words = size / 4;
1560 int tabs = 0;
1561
1562 bool branch_forward = false;
1563
1564 int last_next_tag = -1;
1565
1566 unsigned i = 0;
1567
1568 midg_tags = calloc(sizeof(midg_tags[0]), num_words);
1569
1570 /* Stats for shader-db */
1571 memset(&midg_stats, 0, sizeof(midg_stats));
1572 midg_ever_written = 0;
1573
1574 while (i < num_words) {
1575 unsigned tag = words[i] & 0xF;
1576 unsigned next_tag = (words[i] >> 4) & 0xF;
1577 fprintf(fp, "\t%X -> %X\n", tag, next_tag);
1578 unsigned num_quad_words = midgard_word_size[tag];
1579
1580 if (midg_tags[i] && midg_tags[i] != tag) {
1581 fprintf(fp, "\t/* XXX: TAG ERROR branch, got ");
1582 print_tag_short(fp, tag);
1583 fprintf(fp, " expected ");
1584 print_tag_short(fp, midg_tags[i]);
1585 fprintf(fp, " */\n");
1586 }
1587
1588 midg_tags[i] = tag;
1589
1590 /* Check the tag */
1591 if (last_next_tag > 1) {
1592 if (last_next_tag != tag) {
1593 fprintf(fp, "\t/* XXX: TAG ERROR sequence, got ");
1594 print_tag_short(fp, tag);
1595 fprintf(fp, " expected ");
1596 print_tag_short(fp, last_next_tag);
1597 fprintf(fp, " */\n");
1598 }
1599 } else {
1600 /* TODO: Check ALU case */
1601 }
1602
1603 last_next_tag = next_tag;
1604
1605 switch (midgard_word_types[tag]) {
1606 case midgard_word_type_texture: {
1607 bool interpipe_aliasing =
1608 midgard_get_quirks(gpu_id) & MIDGARD_INTERPIPE_REG_ALIASING;
1609
1610 print_texture_word(fp, &words[i], tabs,
1611 interpipe_aliasing ? 0 : REG_TEX_BASE,
1612 interpipe_aliasing ? REGISTER_LDST_BASE : REG_TEX_BASE);
1613 break;
1614 }
1615
1616 case midgard_word_type_load_store:
1617 print_load_store_word(fp, &words[i], tabs);
1618 break;
1619
1620 case midgard_word_type_alu:
1621 branch_forward = print_alu_word(fp, &words[i], num_quad_words, tabs, i + 4*num_quad_words);
1622
1623 /* Reset word static analysis state */
1624 is_embedded_constant_half = false;
1625 is_embedded_constant_int = false;
1626
1627 break;
1628
1629 default:
1630 fprintf(fp, "Unknown word type %u:\n", words[i] & 0xF);
1631 num_quad_words = 1;
1632 print_quad_word(fp, &words[i], tabs);
1633 fprintf(fp, "\n");
1634 break;
1635 }
1636
1637 /* We are parsing per bundle anyway. Add before we start
1638 * breaking out so we don't miss the final bundle. */
1639
1640 midg_stats.bundle_count++;
1641 midg_stats.quadword_count += num_quad_words;
1642
1643 fprintf(fp, "\n");
1644
1645 unsigned next = (words[i] & 0xF0) >> 4;
1646
1647 if (i < num_words && next == 1 && !branch_forward)
1648 break;
1649
1650 i += 4 * num_quad_words;
1651 }
1652
1653 free(midg_tags);
1654
1655 /* We computed work_count as max_work_registers, so add one to get the
1656 * count. If no work registers are written, you still have one work
1657 * reported, which is exactly what the hardware expects */
1658
1659 midg_stats.work_count++;
1660
1661 return midg_stats;
1662 }