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pan/mdg: Disassemble out-of-order bits
[mesa.git] / src / panfrost / midgard / disassemble.c
1 /* Author(s):
2 * Connor Abbott
3 * Alyssa Rosenzweig
4 *
5 * Copyright (c) 2013 Connor Abbott (connor@abbott.cx)
6 * Copyright (c) 2018 Alyssa Rosenzweig (alyssa@rosenzweig.io)
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #include <stdio.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <assert.h>
31 #include <inttypes.h>
32 #include <ctype.h>
33 #include <string.h>
34 #include "midgard.h"
35 #include "midgard_ops.h"
36 #include "midgard_quirks.h"
37 #include "disassemble.h"
38 #include "helpers.h"
39 #include "util/bitscan.h"
40 #include "util/half_float.h"
41 #include "util/u_math.h"
42
43 #define DEFINE_CASE(define, str) case define: { fprintf(fp, str); break; }
44
45 static unsigned *midg_tags;
46 static bool is_instruction_int = false;
47
48 /* Stats */
49
50 static struct midgard_disasm_stats midg_stats;
51
52 /* Transform an expanded writemask (duplicated 8-bit format) into its condensed
53 * form (one bit per component) */
54
55 static inline unsigned
56 condense_writemask(unsigned expanded_mask,
57 unsigned bits_per_component)
58 {
59 if (bits_per_component == 8) {
60 /* Duplicate every bit to go from 8 to 16-channel wrmask */
61 unsigned omask = 0;
62
63 for (unsigned i = 0; i < 8; ++i) {
64 if (expanded_mask & (1 << i))
65 omask |= (3 << (2 * i));
66 }
67
68 return omask;
69 }
70
71 unsigned slots_per_component = bits_per_component / 16;
72 unsigned max_comp = (16 * 8) / bits_per_component;
73 unsigned condensed_mask = 0;
74
75 for (unsigned i = 0; i < max_comp; i++) {
76 if (expanded_mask & (1 << (i * slots_per_component)))
77 condensed_mask |= (1 << i);
78 }
79
80 return condensed_mask;
81 }
82
83 static void
84 print_alu_opcode(FILE *fp, midgard_alu_op op)
85 {
86 bool int_op = false;
87
88 if (alu_opcode_props[op].name) {
89 fprintf(fp, "%s", alu_opcode_props[op].name);
90
91 int_op = midgard_is_integer_op(op);
92 } else
93 fprintf(fp, "alu_op_%02X", op);
94
95 /* For constant analysis */
96 is_instruction_int = int_op;
97 }
98
99 static void
100 print_ld_st_opcode(FILE *fp, midgard_load_store_op op)
101 {
102 if (load_store_opcode_props[op].name)
103 fprintf(fp, "%s", load_store_opcode_props[op].name);
104 else
105 fprintf(fp, "ldst_op_%02X", op);
106 }
107
108 static bool is_embedded_constant_half = false;
109 static bool is_embedded_constant_int = false;
110
111 static char
112 prefix_for_bits(unsigned bits)
113 {
114 switch (bits) {
115 case 8:
116 return 'q';
117 case 16:
118 return 'h';
119 case 64:
120 return 'd';
121 default:
122 return 0;
123 }
124 }
125
126 /* For static analysis to ensure all registers are written at least once before
127 * use along the source code path (TODO: does this break done for complex CF?)
128 */
129
130 uint16_t midg_ever_written = 0;
131
132 static void
133 print_reg(FILE *fp, unsigned reg, unsigned bits)
134 {
135 /* Perform basic static analysis for expanding constants correctly */
136
137 if (reg == 26) {
138 is_embedded_constant_int = is_instruction_int;
139 is_embedded_constant_half = (bits < 32);
140 }
141
142 unsigned uniform_reg = 23 - reg;
143 bool is_uniform = false;
144
145 /* For r8-r15, it could be a work or uniform. We distinguish based on
146 * the fact work registers are ALWAYS written before use, but uniform
147 * registers are NEVER written before use. */
148
149 if ((reg >= 8 && reg < 16) && !(midg_ever_written & (1 << reg)))
150 is_uniform = true;
151
152 /* r16-r23 are always uniform */
153
154 if (reg >= 16 && reg <= 23)
155 is_uniform = true;
156
157 /* Update the uniform count appropriately */
158
159 if (is_uniform)
160 midg_stats.uniform_count =
161 MAX2(uniform_reg + 1, midg_stats.uniform_count);
162
163 char prefix = prefix_for_bits(bits);
164
165 if (prefix)
166 fputc(prefix, fp);
167
168 fprintf(fp, "r%u", reg);
169 }
170
171 static char *outmod_names_float[4] = {
172 "",
173 ".pos",
174 ".sat_signed",
175 ".sat"
176 };
177
178 static char *outmod_names_int[4] = {
179 ".isat",
180 ".usat",
181 "",
182 ".hi"
183 };
184
185 static char *srcmod_names_int[4] = {
186 "sext(",
187 "zext(",
188 "",
189 "("
190 };
191
192 static void
193 print_outmod(FILE *fp, unsigned outmod, bool is_int)
194 {
195 fprintf(fp, "%s", is_int ? outmod_names_int[outmod] :
196 outmod_names_float[outmod]);
197 }
198
199 static void
200 print_quad_word(FILE *fp, uint32_t *words, unsigned tabs)
201 {
202 unsigned i;
203
204 for (i = 0; i < 4; i++)
205 fprintf(fp, "0x%08X%s ", words[i], i == 3 ? "" : ",");
206
207 fprintf(fp, "\n");
208 }
209
210 static const char components[16] = "xyzwefghijklmnop";
211
212 /* Helper to print 4 chars of a swizzle */
213 static void
214 print_swizzle_helper(FILE *fp, unsigned swizzle, unsigned offset)
215 {
216 for (unsigned i = 0; i < 4; ++i) {
217 unsigned c = (swizzle >> (i * 2)) & 3;
218 c += offset;
219 fprintf(fp, "%c", components[c]);
220 }
221 }
222
223 /* Helper to print 8 chars of a swizzle, duplicating over */
224 static void
225 print_swizzle_helper_8(FILE *fp, unsigned swizzle, bool upper)
226 {
227 for (unsigned i = 0; i < 4; ++i) {
228 unsigned c = (swizzle >> (i * 2)) & 3;
229 c *= 2;
230 c += upper*8;
231 fprintf(fp, "%c%c", components[c], components[c+1]);
232 }
233 }
234
235 static void
236 print_swizzle_vec16(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low,
237 midgard_dest_override override)
238 {
239 fprintf(fp, ".");
240
241 if (override == midgard_dest_override_upper) {
242 if (rep_high)
243 fprintf(fp, " /* rep_high */ ");
244 if (rep_low)
245 fprintf(fp, " /* rep_low */ ");
246
247 if (!rep_high && rep_low)
248 print_swizzle_helper_8(fp, swizzle, true);
249 else
250 print_swizzle_helper_8(fp, swizzle, false);
251 } else {
252 print_swizzle_helper_8(fp, swizzle, rep_high & 1);
253 print_swizzle_helper_8(fp, swizzle, !(rep_low & 1));
254 }
255 }
256
257 static void
258 print_swizzle_vec8(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low, bool half)
259 {
260 fprintf(fp, ".");
261
262 /* TODO: Is it possible to unify half/full? */
263
264 if (half) {
265 print_swizzle_helper(fp, swizzle, (rep_low * 8));
266 print_swizzle_helper(fp, swizzle, (rep_low * 8) + !rep_high * 4);
267 } else {
268 print_swizzle_helper(fp, swizzle, rep_high * 4);
269 print_swizzle_helper(fp, swizzle, !rep_low * 4);
270 }
271 }
272
273 static void
274 print_swizzle_vec4(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low, bool half)
275 {
276 if (rep_high)
277 fprintf(fp, " /* rep_high */ ");
278
279 if (!half && rep_low)
280 fprintf(fp, " /* rep_low */ ");
281
282 if (swizzle == 0xE4 && !half) return; /* xyzw */
283
284 fprintf(fp, ".");
285 print_swizzle_helper(fp, swizzle, rep_low * 4);
286 }
287 static void
288 print_swizzle_vec2(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low, bool half)
289 {
290 char *alphabet = "XY";
291
292 if (half) {
293 alphabet = rep_low ? "zw" : "xy";
294 } else if (rep_low)
295 fprintf(fp, " /* rep_low */ ");
296
297 if (rep_high)
298 fprintf(fp, " /* rep_high */ ");
299
300 if (swizzle == 0xE4 && !half) return; /* XY */
301
302 fprintf(fp, ".");
303
304 for (unsigned i = 0; i < 4; i += 2) {
305 unsigned a = (swizzle >> (i * 2)) & 3;
306 unsigned b = (swizzle >> ((i+1) * 2)) & 3;
307
308 /* Normally we're adjacent, but if there's an issue, don't make
309 * it ambiguous */
310
311 if (b == (a + 1))
312 fprintf(fp, "%c", alphabet[a >> 1]);
313 else
314 fprintf(fp, "[%c%c]", components[a], components[b]);
315 }
316 }
317
318 static int
319 bits_for_mode(midgard_reg_mode mode)
320 {
321 switch (mode) {
322 case midgard_reg_mode_8:
323 return 8;
324 case midgard_reg_mode_16:
325 return 16;
326 case midgard_reg_mode_32:
327 return 32;
328 case midgard_reg_mode_64:
329 return 64;
330 default:
331 unreachable("Invalid reg mode");
332 return 0;
333 }
334 }
335
336 static int
337 bits_for_mode_halved(midgard_reg_mode mode, bool half)
338 {
339 unsigned bits = bits_for_mode(mode);
340
341 if (half)
342 bits >>= 1;
343
344 return bits;
345 }
346
347 static void
348 print_scalar_constant(FILE *fp, unsigned src_binary,
349 const midgard_constants *consts,
350 midgard_scalar_alu *alu)
351 {
352 midgard_scalar_alu_src *src = (midgard_scalar_alu_src *)&src_binary;
353 assert(consts != NULL);
354
355 fprintf(fp, "#");
356 mir_print_constant_component(fp, consts, src->component,
357 src->full ?
358 midgard_reg_mode_32 : midgard_reg_mode_16,
359 false, src->mod, alu->op);
360 }
361
362 static void
363 print_vector_constants(FILE *fp, unsigned src_binary,
364 const midgard_constants *consts,
365 midgard_vector_alu *alu)
366 {
367 midgard_vector_alu_src *src = (midgard_vector_alu_src *)&src_binary;
368 unsigned bits = bits_for_mode_halved(alu->reg_mode, src->half);
369 unsigned max_comp = (sizeof(*consts) * 8) / bits;
370 unsigned comp_mask, num_comp = 0;
371
372 assert(consts);
373 assert(max_comp <= 16);
374
375 comp_mask = effective_writemask(alu, condense_writemask(alu->mask, bits));
376 num_comp = util_bitcount(comp_mask);
377
378 fprintf(fp, "<");
379 bool first = true;
380
381 for (unsigned i = 0; i < max_comp; ++i) {
382 if (!(comp_mask & (1 << i))) continue;
383
384 unsigned c = (src->swizzle >> (i * 2)) & 3;
385
386 if (bits == 16 && !src->half) {
387 if (i < 4)
388 c += (src->rep_high * 4);
389 else
390 c += (!src->rep_low * 4);
391 } else if (bits == 32 && !src->half) {
392 /* Implicitly ok */
393 } else if (bits == 8) {
394 assert (!src->half);
395 unsigned index = (i >> 1) & 3;
396 unsigned base = (src->swizzle >> (index * 2)) & 3;
397 c = base * 2;
398
399 if (i < 8)
400 c += (src->rep_high) * 8;
401 else
402 c += (!src->rep_low) * 8;
403
404 /* We work on twos, actually */
405 if (i & 1)
406 c++;
407 } else {
408 printf(" (%d%d%d)", src->rep_low, src->rep_high, src->half);
409 }
410
411 if (first)
412 first = false;
413 else
414 fprintf(fp, ", ");
415
416 mir_print_constant_component(fp, consts, c, alu->reg_mode,
417 src->half, src->mod, alu->op);
418 }
419
420 if (num_comp > 1)
421 fprintf(fp, ">");
422 }
423
424 static void
425 print_srcmod(FILE *fp, bool is_int, unsigned mod, bool scalar)
426 {
427 /* Modifiers change meaning depending on the op's context */
428
429 midgard_int_mod int_mod = mod;
430
431 if (is_int) {
432 if (scalar && mod == 2) {
433 fprintf(fp, "unk2");
434 }
435
436 fprintf(fp, "%s", srcmod_names_int[int_mod]);
437 } else {
438 if (mod & MIDGARD_FLOAT_MOD_NEG)
439 fprintf(fp, "-");
440
441 if (mod & MIDGARD_FLOAT_MOD_ABS)
442 fprintf(fp, "abs(");
443 }
444 }
445
446 static void
447 print_srcmod_end(FILE *fp, bool is_int, unsigned mod, unsigned bits)
448 {
449 /* Since we wrapped with a function-looking thing */
450
451 if (is_int && mod == midgard_int_shift)
452 fprintf(fp, ") << %u", bits);
453 else if ((is_int && (mod != midgard_int_normal))
454 || (!is_int && mod & MIDGARD_FLOAT_MOD_ABS))
455 fprintf(fp, ")");
456 }
457
458 static void
459 print_vector_src(FILE *fp, unsigned src_binary,
460 midgard_reg_mode mode, unsigned reg,
461 midgard_dest_override override, bool is_int)
462 {
463 midgard_vector_alu_src *src = (midgard_vector_alu_src *)&src_binary;
464 print_srcmod(fp, is_int, src->mod, false);
465
466 //register
467 unsigned bits = bits_for_mode_halved(mode, src->half);
468 print_reg(fp, reg, bits);
469
470 /* When the source was stepped down via `half`, rep_low means "higher
471 * half" and rep_high is never seen. When it's not native,
472 * rep_low/rep_high are for, well, replication */
473
474 if (mode == midgard_reg_mode_8) {
475 assert(!src->half);
476 print_swizzle_vec16(fp, src->swizzle, src->rep_high, src->rep_low, override);
477 } else if (mode == midgard_reg_mode_16) {
478 print_swizzle_vec8(fp, src->swizzle, src->rep_high, src->rep_low, src->half);
479 } else if (mode == midgard_reg_mode_32) {
480 print_swizzle_vec4(fp, src->swizzle, src->rep_high, src->rep_low, src->half);
481 } else if (mode == midgard_reg_mode_64) {
482 print_swizzle_vec2(fp, src->swizzle, src->rep_high, src->rep_low, src->half);
483 }
484
485 print_srcmod_end(fp, is_int, src->mod, bits);
486 }
487
488 static uint16_t
489 decode_vector_imm(unsigned src2_reg, unsigned imm)
490 {
491 uint16_t ret;
492 ret = src2_reg << 11;
493 ret |= (imm & 0x7) << 8;
494 ret |= (imm >> 3) & 0xFF;
495 return ret;
496 }
497
498 static void
499 print_immediate(FILE *fp, uint16_t imm)
500 {
501 if (is_instruction_int)
502 fprintf(fp, "#%u", imm);
503 else
504 fprintf(fp, "#%g", _mesa_half_to_float(imm));
505 }
506
507 static void
508 update_dest(unsigned reg)
509 {
510 /* We should record writes as marking this as a work register. Store
511 * the max register in work_count; we'll add one at the end */
512
513 if (reg < 16) {
514 midg_stats.work_count = MAX2(reg, midg_stats.work_count);
515 midg_ever_written |= (1 << reg);
516 }
517 }
518
519 static void
520 print_dest(FILE *fp, unsigned reg, midgard_reg_mode mode, midgard_dest_override override)
521 {
522 /* Depending on the mode and override, we determine the type of
523 * destination addressed. Absent an override, we address just the
524 * type of the operation itself */
525
526 unsigned bits = bits_for_mode(mode);
527
528 if (override != midgard_dest_override_none)
529 bits /= 2;
530
531 update_dest(reg);
532 print_reg(fp, reg, bits);
533 }
534
535 static void
536 print_mask_vec16(FILE *fp, uint8_t mask, midgard_dest_override override)
537 {
538 fprintf(fp, ".");
539
540 for (unsigned i = 0; i < 8; i++) {
541 if (mask & (1 << i))
542 fprintf(fp, "%c%c",
543 components[i*2 + 0],
544 components[i*2 + 1]);
545 }
546 }
547
548 /* For 16-bit+ masks, we read off from the 8-bit mask field. For 16-bit (vec8),
549 * it's just one bit per channel, easy peasy. For 32-bit (vec4), it's one bit
550 * per channel with one duplicate bit in the middle. For 64-bit (vec2), it's
551 * one-bit per channel with _3_ duplicate bits in the middle. Basically, just
552 * subdividing the 128-bit word in 16-bit increments. For 64-bit, we uppercase
553 * the mask to make it obvious what happened */
554
555 static void
556 print_mask(FILE *fp, uint8_t mask, unsigned bits, midgard_dest_override override)
557 {
558 if (bits == 8) {
559 print_mask_vec16(fp, mask, override);
560 return;
561 }
562
563 /* Skip 'complete' masks */
564
565 if (override == midgard_dest_override_none)
566 if (bits >= 32 && mask == 0xFF) return;
567
568 fprintf(fp, ".");
569
570 unsigned skip = (bits / 16);
571 bool uppercase = bits > 32;
572 bool tripped = false;
573
574 /* To apply an upper destination override, we "shift" the alphabet.
575 * E.g. with an upper override on 32-bit, instead of xyzw, print efgh.
576 * For upper 16-bit, instead of xyzwefgh, print ijklmnop */
577
578 const char *alphabet = components;
579
580 if (override == midgard_dest_override_upper)
581 alphabet += (128 / bits);
582
583 for (unsigned i = 0; i < 8; i += skip) {
584 bool a = (mask & (1 << i)) != 0;
585
586 for (unsigned j = 1; j < skip; ++j) {
587 bool dupe = (mask & (1 << (i + j))) != 0;
588 tripped |= (dupe != a);
589 }
590
591 if (a) {
592 char c = alphabet[i / skip];
593
594 if (uppercase)
595 c = toupper(c);
596
597 fprintf(fp, "%c", c);
598 }
599 }
600
601 if (tripped)
602 fprintf(fp, " /* %X */", mask);
603 }
604
605 /* Prints the 4-bit masks found in texture and load/store ops, as opposed to
606 * the 8-bit masks found in (vector) ALU ops. Supports texture-style 16-bit
607 * mode as well, but not load/store-style 16-bit mode. */
608
609 static void
610 print_mask_4(FILE *fp, unsigned mask, bool upper)
611 {
612 if (mask == 0xF) {
613 if (upper)
614 fprintf(fp, "'");
615
616 return;
617 }
618
619 fprintf(fp, ".");
620
621 for (unsigned i = 0; i < 4; ++i) {
622 bool a = (mask & (1 << i)) != 0;
623 if (a)
624 fprintf(fp, "%c", components[i + (upper ? 4 : 0)]);
625 }
626 }
627
628 static void
629 print_vector_field(FILE *fp, const char *name, uint16_t *words, uint16_t reg_word,
630 const midgard_constants *consts, unsigned tabs)
631 {
632 midgard_reg_info *reg_info = (midgard_reg_info *)&reg_word;
633 midgard_vector_alu *alu_field = (midgard_vector_alu *) words;
634 midgard_reg_mode mode = alu_field->reg_mode;
635 unsigned override = alu_field->dest_override;
636
637 /* For now, prefix instruction names with their unit, until we
638 * understand how this works on a deeper level */
639 fprintf(fp, "%s.", name);
640
641 print_alu_opcode(fp, alu_field->op);
642
643 /* Postfix with the size to disambiguate if necessary */
644 char postfix = prefix_for_bits(bits_for_mode(mode));
645 bool size_ambiguous = override != midgard_dest_override_none;
646
647 if (size_ambiguous)
648 fprintf(fp, "%c", postfix ? postfix : 'r');
649
650 /* Print the outmod, if there is one */
651 print_outmod(fp, alu_field->outmod,
652 midgard_is_integer_out_op(alu_field->op));
653
654 fprintf(fp, " ");
655
656 /* Mask denoting status of 8-lanes */
657 uint8_t mask = alu_field->mask;
658
659 /* First, print the destination */
660 print_dest(fp, reg_info->out_reg, mode, alu_field->dest_override);
661
662 if (override != midgard_dest_override_none) {
663 bool modeable = (mode != midgard_reg_mode_8);
664 bool known = override != 0x3; /* Unused value */
665
666 if (!(modeable && known))
667 fprintf(fp, "/* do%u */ ", override);
668 }
669
670 /* Instructions like fdot4 do *not* replicate, ensure the
671 * mask is of only a single component */
672
673 unsigned rep = GET_CHANNEL_COUNT(alu_opcode_props[alu_field->op].props);
674
675 if (rep) {
676 unsigned comp_mask = condense_writemask(mask, bits_for_mode(mode));
677 unsigned num_comp = util_bitcount(comp_mask);
678 if (num_comp != 1)
679 fprintf(fp, "/* err too many components */");
680 }
681 print_mask(fp, mask, bits_for_mode(mode), override);
682
683 fprintf(fp, ", ");
684
685 bool is_int = midgard_is_integer_op(alu_field->op);
686
687 if (reg_info->src1_reg == 26)
688 print_vector_constants(fp, alu_field->src1, consts, alu_field);
689 else
690 print_vector_src(fp, alu_field->src1, mode, reg_info->src1_reg, override, is_int);
691
692 fprintf(fp, ", ");
693
694 if (reg_info->src2_imm) {
695 uint16_t imm = decode_vector_imm(reg_info->src2_reg, alu_field->src2 >> 2);
696 print_immediate(fp, imm);
697 } else if (reg_info->src2_reg == 26) {
698 print_vector_constants(fp, alu_field->src2, consts, alu_field);
699 } else {
700 print_vector_src(fp, alu_field->src2, mode,
701 reg_info->src2_reg, override, is_int);
702 }
703
704 midg_stats.instruction_count++;
705 fprintf(fp, "\n");
706 }
707
708 static void
709 print_scalar_src(FILE *fp, bool is_int, unsigned src_binary, unsigned reg)
710 {
711 midgard_scalar_alu_src *src = (midgard_scalar_alu_src *)&src_binary;
712
713 print_srcmod(fp, is_int, src->mod, true);
714 print_reg(fp, reg, src->full ? 32 : 16);
715
716 unsigned c = src->component;
717
718 if (src->full) {
719 assert((c & 1) == 0);
720 c >>= 1;
721 }
722
723 fprintf(fp, ".%c", components[c]);
724
725 print_srcmod_end(fp, is_int, src->mod, src->full ? 32 : 16);
726 }
727
728 static uint16_t
729 decode_scalar_imm(unsigned src2_reg, unsigned imm)
730 {
731 uint16_t ret;
732 ret = src2_reg << 11;
733 ret |= (imm & 3) << 9;
734 ret |= (imm & 4) << 6;
735 ret |= (imm & 0x38) << 2;
736 ret |= imm >> 6;
737 return ret;
738 }
739
740 static void
741 print_scalar_field(FILE *fp, const char *name, uint16_t *words, uint16_t reg_word,
742 const midgard_constants *consts, unsigned tabs)
743 {
744 midgard_reg_info *reg_info = (midgard_reg_info *)&reg_word;
745 midgard_scalar_alu *alu_field = (midgard_scalar_alu *) words;
746
747 if (alu_field->unknown)
748 fprintf(fp, "scalar ALU unknown bit set\n");
749
750 fprintf(fp, "%s.", name);
751 print_alu_opcode(fp, alu_field->op);
752 print_outmod(fp, alu_field->outmod,
753 midgard_is_integer_out_op(alu_field->op));
754 fprintf(fp, " ");
755
756 bool full = alu_field->output_full;
757 update_dest(reg_info->out_reg);
758 print_reg(fp, reg_info->out_reg, full ? 32 : 16);
759 unsigned c = alu_field->output_component;
760 bool is_int = midgard_is_integer_op(alu_field->op);
761
762 if (full) {
763 assert((c & 1) == 0);
764 c >>= 1;
765 }
766
767 fprintf(fp, ".%c, ", components[c]);
768
769 if (reg_info->src1_reg == 26)
770 print_scalar_constant(fp, alu_field->src1, consts, alu_field);
771 else
772 print_scalar_src(fp, is_int, alu_field->src1, reg_info->src1_reg);
773
774 fprintf(fp, ", ");
775
776 if (reg_info->src2_imm) {
777 uint16_t imm = decode_scalar_imm(reg_info->src2_reg,
778 alu_field->src2);
779 print_immediate(fp, imm);
780 } else if (reg_info->src2_reg == 26) {
781 print_scalar_constant(fp, alu_field->src2, consts, alu_field);
782 } else
783 print_scalar_src(fp, is_int, alu_field->src2, reg_info->src2_reg);
784
785 midg_stats.instruction_count++;
786 fprintf(fp, "\n");
787 }
788
789 static void
790 print_branch_op(FILE *fp, unsigned op)
791 {
792 switch (op) {
793 case midgard_jmp_writeout_op_branch_uncond:
794 fprintf(fp, "uncond.");
795 break;
796
797 case midgard_jmp_writeout_op_branch_cond:
798 fprintf(fp, "cond.");
799 break;
800
801 case midgard_jmp_writeout_op_writeout:
802 fprintf(fp, "write.");
803 break;
804
805 case midgard_jmp_writeout_op_tilebuffer_pending:
806 fprintf(fp, "tilebuffer.");
807 break;
808
809 case midgard_jmp_writeout_op_discard:
810 fprintf(fp, "discard.");
811 break;
812
813 default:
814 fprintf(fp, "unk%u.", op);
815 break;
816 }
817 }
818
819 static void
820 print_branch_cond(FILE *fp, int cond)
821 {
822 switch (cond) {
823 case midgard_condition_write0:
824 fprintf(fp, "write0");
825 break;
826
827 case midgard_condition_false:
828 fprintf(fp, "false");
829 break;
830
831 case midgard_condition_true:
832 fprintf(fp, "true");
833 break;
834
835 case midgard_condition_always:
836 fprintf(fp, "always");
837 break;
838
839 default:
840 fprintf(fp, "unk%X", cond);
841 break;
842 }
843 }
844
845 static bool
846 print_compact_branch_writeout_field(FILE *fp, uint16_t word)
847 {
848 midgard_jmp_writeout_op op = word & 0x7;
849 midg_stats.instruction_count++;
850
851 switch (op) {
852 case midgard_jmp_writeout_op_branch_uncond: {
853 midgard_branch_uncond br_uncond;
854 memcpy((char *) &br_uncond, (char *) &word, sizeof(br_uncond));
855 fprintf(fp, "br.uncond ");
856
857 if (br_uncond.unknown != 1)
858 fprintf(fp, "unknown:%u, ", br_uncond.unknown);
859
860 if (br_uncond.offset >= 0)
861 fprintf(fp, "+");
862
863 fprintf(fp, "%d -> %s", br_uncond.offset,
864 midgard_tag_props[br_uncond.dest_tag].name);
865 fprintf(fp, "\n");
866
867 return br_uncond.offset >= 0;
868 }
869
870 case midgard_jmp_writeout_op_branch_cond:
871 case midgard_jmp_writeout_op_writeout:
872 case midgard_jmp_writeout_op_discard:
873 default: {
874 midgard_branch_cond br_cond;
875 memcpy((char *) &br_cond, (char *) &word, sizeof(br_cond));
876
877 fprintf(fp, "br.");
878
879 print_branch_op(fp, br_cond.op);
880 print_branch_cond(fp, br_cond.cond);
881
882 fprintf(fp, " ");
883
884 if (br_cond.offset >= 0)
885 fprintf(fp, "+");
886
887 fprintf(fp, "%d -> %s", br_cond.offset,
888 midgard_tag_props[br_cond.dest_tag].name);
889 fprintf(fp, "\n");
890
891 return br_cond.offset >= 0;
892 }
893 }
894
895 return false;
896 }
897
898 static bool
899 print_extended_branch_writeout_field(FILE *fp, uint8_t *words, unsigned next)
900 {
901 midgard_branch_extended br;
902 memcpy((char *) &br, (char *) words, sizeof(br));
903
904 fprintf(fp, "brx.");
905
906 print_branch_op(fp, br.op);
907
908 /* Condition codes are a LUT in the general case, but simply repeated 8 times for single-channel conditions.. Check this. */
909
910 bool single_channel = true;
911
912 for (unsigned i = 0; i < 16; i += 2) {
913 single_channel &= (((br.cond >> i) & 0x3) == (br.cond & 0x3));
914 }
915
916 if (single_channel)
917 print_branch_cond(fp, br.cond & 0x3);
918 else
919 fprintf(fp, "lut%X", br.cond);
920
921 if (br.unknown)
922 fprintf(fp, ".unknown%u", br.unknown);
923
924 fprintf(fp, " ");
925
926 if (br.offset >= 0)
927 fprintf(fp, "+");
928
929 fprintf(fp, "%d -> %s\n", br.offset,
930 midgard_tag_props[br.dest_tag].name);
931
932 unsigned I = next + br.offset * 4;
933
934 if (midg_tags[I] && midg_tags[I] != br.dest_tag) {
935 fprintf(fp, "\t/* XXX TAG ERROR: jumping to %s but tagged %s \n",
936 midgard_tag_props[br.dest_tag].name,
937 midgard_tag_props[midg_tags[I]].name);
938 }
939
940 midg_tags[I] = br.dest_tag;
941
942 midg_stats.instruction_count++;
943 return br.offset >= 0;
944 }
945
946 static unsigned
947 num_alu_fields_enabled(uint32_t control_word)
948 {
949 unsigned ret = 0;
950
951 if ((control_word >> 17) & 1)
952 ret++;
953
954 if ((control_word >> 19) & 1)
955 ret++;
956
957 if ((control_word >> 21) & 1)
958 ret++;
959
960 if ((control_word >> 23) & 1)
961 ret++;
962
963 if ((control_word >> 25) & 1)
964 ret++;
965
966 return ret;
967 }
968
969 static bool
970 print_alu_word(FILE *fp, uint32_t *words, unsigned num_quad_words,
971 unsigned tabs, unsigned next)
972 {
973 uint32_t control_word = words[0];
974 uint16_t *beginning_ptr = (uint16_t *)(words + 1);
975 unsigned num_fields = num_alu_fields_enabled(control_word);
976 uint16_t *word_ptr = beginning_ptr + num_fields;
977 unsigned num_words = 2 + num_fields;
978 const midgard_constants *consts = NULL;
979 bool branch_forward = false;
980
981 if ((control_word >> 17) & 1)
982 num_words += 3;
983
984 if ((control_word >> 19) & 1)
985 num_words += 2;
986
987 if ((control_word >> 21) & 1)
988 num_words += 3;
989
990 if ((control_word >> 23) & 1)
991 num_words += 2;
992
993 if ((control_word >> 25) & 1)
994 num_words += 3;
995
996 if ((control_word >> 26) & 1)
997 num_words += 1;
998
999 if ((control_word >> 27) & 1)
1000 num_words += 3;
1001
1002 if (num_quad_words > (num_words + 7) / 8) {
1003 assert(num_quad_words == (num_words + 15) / 8);
1004 //Assume that the extra quadword is constants
1005 consts = (midgard_constants *)(words + (4 * num_quad_words - 4));
1006 }
1007
1008 if ((control_word >> 16) & 1)
1009 fprintf(fp, "unknown bit 16 enabled\n");
1010
1011 if ((control_word >> 17) & 1) {
1012 print_vector_field(fp, "vmul", word_ptr, *beginning_ptr, consts, tabs);
1013 beginning_ptr += 1;
1014 word_ptr += 3;
1015 }
1016
1017 if ((control_word >> 18) & 1)
1018 fprintf(fp, "unknown bit 18 enabled\n");
1019
1020 if ((control_word >> 19) & 1) {
1021 print_scalar_field(fp, "sadd", word_ptr, *beginning_ptr, consts, tabs);
1022 beginning_ptr += 1;
1023 word_ptr += 2;
1024 }
1025
1026 if ((control_word >> 20) & 1)
1027 fprintf(fp, "unknown bit 20 enabled\n");
1028
1029 if ((control_word >> 21) & 1) {
1030 print_vector_field(fp, "vadd", word_ptr, *beginning_ptr, consts, tabs);
1031 beginning_ptr += 1;
1032 word_ptr += 3;
1033 }
1034
1035 if ((control_word >> 22) & 1)
1036 fprintf(fp, "unknown bit 22 enabled\n");
1037
1038 if ((control_word >> 23) & 1) {
1039 print_scalar_field(fp, "smul", word_ptr, *beginning_ptr, consts, tabs);
1040 beginning_ptr += 1;
1041 word_ptr += 2;
1042 }
1043
1044 if ((control_word >> 24) & 1)
1045 fprintf(fp, "unknown bit 24 enabled\n");
1046
1047 if ((control_word >> 25) & 1) {
1048 print_vector_field(fp, "lut", word_ptr, *beginning_ptr, consts, tabs);
1049 word_ptr += 3;
1050 }
1051
1052 if ((control_word >> 26) & 1) {
1053 branch_forward |= print_compact_branch_writeout_field(fp, *word_ptr);
1054 word_ptr += 1;
1055 }
1056
1057 if ((control_word >> 27) & 1) {
1058 branch_forward |= print_extended_branch_writeout_field(fp, (uint8_t *) word_ptr, next);
1059 word_ptr += 3;
1060 }
1061
1062 if (consts)
1063 fprintf(fp, "uconstants 0x%X, 0x%X, 0x%X, 0x%X\n",
1064 consts->u32[0], consts->u32[1],
1065 consts->u32[2], consts->u32[3]);
1066
1067 return branch_forward;
1068 }
1069
1070 static void
1071 print_varying_parameters(FILE *fp, midgard_load_store_word *word)
1072 {
1073 midgard_varying_parameter param;
1074 unsigned v = word->varying_parameters;
1075 memcpy(&param, &v, sizeof(param));
1076
1077 if (param.is_varying) {
1078 /* If a varying, there are qualifiers */
1079 if (param.flat)
1080 fprintf(fp, ".flat");
1081
1082 if (param.interpolation != midgard_interp_default) {
1083 if (param.interpolation == midgard_interp_centroid)
1084 fprintf(fp, ".centroid");
1085 else
1086 fprintf(fp, ".interp%d", param.interpolation);
1087 }
1088
1089 if (param.modifier != midgard_varying_mod_none) {
1090 if (param.modifier == midgard_varying_mod_perspective_w)
1091 fprintf(fp, ".perspectivew");
1092 else if (param.modifier == midgard_varying_mod_perspective_z)
1093 fprintf(fp, ".perspectivez");
1094 else
1095 fprintf(fp, ".mod%d", param.modifier);
1096 }
1097 } else if (param.flat || param.interpolation || param.modifier) {
1098 fprintf(fp, " /* is_varying not set but varying metadata attached */");
1099 }
1100
1101 if (param.zero0 || param.zero1 || param.zero2)
1102 fprintf(fp, " /* zero tripped, %u %u %u */ ", param.zero0, param.zero1, param.zero2);
1103 }
1104
1105 static bool
1106 is_op_varying(unsigned op)
1107 {
1108 switch (op) {
1109 case midgard_op_st_vary_16:
1110 case midgard_op_st_vary_32:
1111 case midgard_op_st_vary_32i:
1112 case midgard_op_st_vary_32u:
1113 case midgard_op_ld_vary_16:
1114 case midgard_op_ld_vary_32:
1115 case midgard_op_ld_vary_32i:
1116 case midgard_op_ld_vary_32u:
1117 return true;
1118 }
1119
1120 return false;
1121 }
1122
1123 static bool
1124 is_op_attribute(unsigned op)
1125 {
1126 switch (op) {
1127 case midgard_op_ld_attr_16:
1128 case midgard_op_ld_attr_32:
1129 case midgard_op_ld_attr_32i:
1130 case midgard_op_ld_attr_32u:
1131 return true;
1132 }
1133
1134 return false;
1135 }
1136
1137 static void
1138 print_load_store_arg(FILE *fp, uint8_t arg, unsigned index)
1139 {
1140 /* Try to interpret as a register */
1141 midgard_ldst_register_select sel;
1142 memcpy(&sel, &arg, sizeof(arg));
1143
1144 /* If unknown is set, we're not sure what this is or how to
1145 * interpret it. But if it's zero, we get it. */
1146
1147 if (sel.unknown) {
1148 fprintf(fp, "0x%02X", arg);
1149 return;
1150 }
1151
1152 unsigned reg = REGISTER_LDST_BASE + sel.select;
1153 char comp = components[sel.component];
1154
1155 fprintf(fp, "r%u.%c", reg, comp);
1156
1157 /* Only print a shift if it's non-zero. Shifts only make sense for the
1158 * second index. For the first, we're not sure what it means yet */
1159
1160 if (index == 1) {
1161 if (sel.shift)
1162 fprintf(fp, " << %u", sel.shift);
1163 } else {
1164 fprintf(fp, " /* %X */", sel.shift);
1165 }
1166 }
1167
1168 static void
1169 update_stats(signed *stat, unsigned address)
1170 {
1171 if (*stat >= 0)
1172 *stat = MAX2(*stat, address + 1);
1173 }
1174
1175 static void
1176 print_load_store_instr(FILE *fp, uint64_t data,
1177 unsigned tabs)
1178 {
1179 midgard_load_store_word *word = (midgard_load_store_word *) &data;
1180
1181 print_ld_st_opcode(fp, word->op);
1182
1183 unsigned address = word->address;
1184
1185 if (is_op_varying(word->op)) {
1186 print_varying_parameters(fp, word);
1187
1188 /* Do some analysis: check if direct cacess */
1189
1190 if ((word->arg_2 == 0x1E) && midg_stats.varying_count >= 0)
1191 update_stats(&midg_stats.varying_count, address);
1192 else
1193 midg_stats.varying_count = -16;
1194 } else if (is_op_attribute(word->op)) {
1195 if ((word->arg_2 == 0x1E) && midg_stats.attribute_count >= 0)
1196 update_stats(&midg_stats.attribute_count, address);
1197 else
1198 midg_stats.attribute_count = -16;
1199 }
1200
1201 fprintf(fp, " r%u", word->reg + (OP_IS_STORE(word->op) ? 26 : 0));
1202 print_mask_4(fp, word->mask, false);
1203
1204 if (!OP_IS_STORE(word->op))
1205 update_dest(word->reg);
1206
1207 bool is_ubo = OP_IS_UBO_READ(word->op);
1208
1209 if (is_ubo) {
1210 /* UBOs use their own addressing scheme */
1211
1212 int lo = word->varying_parameters >> 7;
1213 int hi = word->address;
1214
1215 /* TODO: Combine fields logically */
1216 address = (hi << 3) | lo;
1217 }
1218
1219 fprintf(fp, ", %u", address);
1220
1221 print_swizzle_vec4(fp, word->swizzle, false, false, false);
1222
1223 fprintf(fp, ", ");
1224
1225 if (is_ubo) {
1226 fprintf(fp, "ubo%u", word->arg_1);
1227 update_stats(&midg_stats.uniform_buffer_count, word->arg_1);
1228 } else
1229 print_load_store_arg(fp, word->arg_1, 0);
1230
1231 fprintf(fp, ", ");
1232 print_load_store_arg(fp, word->arg_2, 1);
1233 fprintf(fp, " /* %X */\n", word->varying_parameters);
1234
1235 midg_stats.instruction_count++;
1236 }
1237
1238 static void
1239 print_load_store_word(FILE *fp, uint32_t *word, unsigned tabs)
1240 {
1241 midgard_load_store *load_store = (midgard_load_store *) word;
1242
1243 if (load_store->word1 != 3) {
1244 print_load_store_instr(fp, load_store->word1, tabs);
1245 }
1246
1247 if (load_store->word2 != 3) {
1248 print_load_store_instr(fp, load_store->word2, tabs);
1249 }
1250 }
1251
1252 static void
1253 print_texture_reg_select(FILE *fp, uint8_t u, unsigned base)
1254 {
1255 midgard_tex_register_select sel;
1256 memcpy(&sel, &u, sizeof(u));
1257
1258 if (!sel.full)
1259 fprintf(fp, "h");
1260
1261 fprintf(fp, "r%u", base + sel.select);
1262
1263 unsigned component = sel.component;
1264
1265 /* Use the upper half in half-reg mode */
1266 if (sel.upper) {
1267 assert(!sel.full);
1268 component += 4;
1269 }
1270
1271 fprintf(fp, ".%c", components[component]);
1272
1273 assert(sel.zero == 0);
1274 }
1275
1276 static void
1277 print_texture_format(FILE *fp, int format)
1278 {
1279 /* Act like a modifier */
1280 fprintf(fp, ".");
1281
1282 switch (format) {
1283 DEFINE_CASE(MALI_TEX_1D, "1d");
1284 DEFINE_CASE(MALI_TEX_2D, "2d");
1285 DEFINE_CASE(MALI_TEX_3D, "3d");
1286 DEFINE_CASE(MALI_TEX_CUBE, "cube");
1287
1288 default:
1289 unreachable("Bad format");
1290 }
1291 }
1292
1293 static bool
1294 midgard_op_has_helpers(unsigned op, bool gather)
1295 {
1296 if (gather)
1297 return true;
1298
1299 switch (op) {
1300 case TEXTURE_OP_NORMAL:
1301 case TEXTURE_OP_DFDX:
1302 case TEXTURE_OP_DFDY:
1303 return true;
1304 default:
1305 return false;
1306 }
1307 }
1308
1309 static void
1310 print_texture_op(FILE *fp, unsigned op, bool gather)
1311 {
1312 /* Act like a bare name, like ESSL functions */
1313
1314 if (gather) {
1315 fprintf(fp, "textureGather");
1316
1317 unsigned component = op >> 4;
1318 unsigned bottom = op & 0xF;
1319
1320 if (bottom != 0x2)
1321 fprintf(fp, "_unk%u", bottom);
1322
1323 fprintf(fp, ".%c", components[component]);
1324 return;
1325 }
1326
1327 switch (op) {
1328 DEFINE_CASE(TEXTURE_OP_NORMAL, "texture");
1329 DEFINE_CASE(TEXTURE_OP_LOD, "textureLod");
1330 DEFINE_CASE(TEXTURE_OP_TEXEL_FETCH, "texelFetch");
1331 DEFINE_CASE(TEXTURE_OP_BARRIER, "barrier");
1332 DEFINE_CASE(TEXTURE_OP_DFDX, "dFdx");
1333 DEFINE_CASE(TEXTURE_OP_DFDY, "dFdy");
1334
1335 default:
1336 fprintf(fp, "tex_%X", op);
1337 break;
1338 }
1339 }
1340
1341 static bool
1342 texture_op_takes_bias(unsigned op)
1343 {
1344 return op == TEXTURE_OP_NORMAL;
1345 }
1346
1347 static char
1348 sampler_type_name(enum mali_sampler_type t)
1349 {
1350 switch (t) {
1351 case MALI_SAMPLER_FLOAT:
1352 return 'f';
1353 case MALI_SAMPLER_UNSIGNED:
1354 return 'u';
1355 case MALI_SAMPLER_SIGNED:
1356 return 'i';
1357 default:
1358 return '?';
1359 }
1360
1361 }
1362
1363 static void
1364 print_texture_barrier(FILE *fp, uint32_t *word)
1365 {
1366 midgard_texture_barrier_word *barrier = (midgard_texture_barrier_word *) word;
1367
1368 if (barrier->type != TAG_TEXTURE_4_BARRIER)
1369 fprintf(fp, "/* barrier tag %X != tex/bar */ ", barrier->type);
1370
1371 if (!barrier->cont)
1372 fprintf(fp, "/* cont missing? */");
1373
1374 if (!barrier->last)
1375 fprintf(fp, "/* last missing? */");
1376
1377 if (barrier->zero1)
1378 fprintf(fp, "/* zero1 = 0x%X */ ", barrier->zero1);
1379
1380 if (barrier->zero2)
1381 fprintf(fp, "/* zero2 = 0x%X */ ", barrier->zero2);
1382
1383 if (barrier->zero3)
1384 fprintf(fp, "/* zero3 = 0x%X */ ", barrier->zero3);
1385
1386 if (barrier->zero4)
1387 fprintf(fp, "/* zero4 = 0x%X */ ", barrier->zero4);
1388
1389 if (barrier->zero5)
1390 fprintf(fp, "/* zero4 = 0x%" PRIx64 " */ ", barrier->zero5);
1391
1392
1393 /* Control barriers are always implied, so include for obviousness */
1394 fprintf(fp, " control");
1395
1396 if (barrier->buffer)
1397 fprintf(fp, " | buffer");
1398
1399 if (barrier->shared)
1400 fprintf(fp, " | shared");
1401
1402 if (barrier->stack)
1403 fprintf(fp, " | stack");
1404
1405 fprintf(fp, "\n");
1406 }
1407
1408 #undef DEFINE_CASE
1409
1410 static void
1411 print_texture_word(FILE *fp, uint32_t *word, unsigned tabs, unsigned in_reg_base, unsigned out_reg_base)
1412 {
1413 midgard_texture_word *texture = (midgard_texture_word *) word;
1414
1415 midg_stats.helper_invocations |=
1416 midgard_op_has_helpers(texture->op, texture->is_gather);
1417
1418 /* Broad category of texture operation in question */
1419 print_texture_op(fp, texture->op, texture->is_gather);
1420
1421 /* Barriers use a dramatically different code path */
1422 if (texture->op == TEXTURE_OP_BARRIER) {
1423 print_texture_barrier(fp, word);
1424 return;
1425 } else if (texture->type == TAG_TEXTURE_4_BARRIER)
1426 fprintf (fp, "/* nonbarrier had tex/bar tag */ ");
1427 else if (texture->type == TAG_TEXTURE_4_VTX)
1428 fprintf (fp, ".vtx");
1429
1430 /* Specific format in question */
1431 print_texture_format(fp, texture->format);
1432
1433 /* Instruction "modifiers" parallel the ALU instructions. */
1434
1435 if (texture->shadow)
1436 fprintf(fp, ".shadow");
1437
1438 if (texture->cont)
1439 fprintf(fp, ".cont");
1440
1441 if (texture->last)
1442 fprintf(fp, ".last");
1443
1444 if (texture->out_of_order)
1445 fprintf(fp, ".ooo%u", texture->out_of_order);
1446
1447 /* Output modifiers are always interpreted floatly */
1448 print_outmod(fp, texture->outmod, false);
1449
1450 fprintf(fp, " %sr%u", texture->out_full ? "" : "h",
1451 out_reg_base + texture->out_reg_select);
1452 print_mask_4(fp, texture->mask, texture->out_upper);
1453 assert(!(texture->out_full && texture->out_upper));
1454 fprintf(fp, ", ");
1455
1456 /* Depending on whether we read from textures directly or indirectly,
1457 * we may be able to update our analysis */
1458
1459 if (texture->texture_register) {
1460 fprintf(fp, "texture[");
1461 print_texture_reg_select(fp, texture->texture_handle, in_reg_base);
1462 fprintf(fp, "], ");
1463
1464 /* Indirect, tut tut */
1465 midg_stats.texture_count = -16;
1466 } else {
1467 fprintf(fp, "texture%u, ", texture->texture_handle);
1468 update_stats(&midg_stats.texture_count, texture->texture_handle);
1469 }
1470
1471 /* Print the type, GL style */
1472 fprintf(fp, "%csampler", sampler_type_name(texture->sampler_type));
1473
1474 if (texture->sampler_register) {
1475 fprintf(fp, "[");
1476 print_texture_reg_select(fp, texture->sampler_handle, in_reg_base);
1477 fprintf(fp, "]");
1478
1479 midg_stats.sampler_count = -16;
1480 } else {
1481 fprintf(fp, "%u", texture->sampler_handle);
1482 update_stats(&midg_stats.sampler_count, texture->sampler_handle);
1483 }
1484
1485 print_swizzle_vec4(fp, texture->swizzle, false, false, false);
1486 fprintf(fp, ", %sr%u", texture->in_reg_full ? "" : "h", in_reg_base + texture->in_reg_select);
1487 assert(!(texture->in_reg_full && texture->in_reg_upper));
1488
1489 /* TODO: integrate with swizzle */
1490 if (texture->in_reg_upper)
1491 fprintf(fp, "'");
1492
1493 print_swizzle_vec4(fp, texture->in_reg_swizzle, false, false, false);
1494
1495 /* There is *always* an offset attached. Of
1496 * course, that offset is just immediate #0 for a
1497 * GLES call that doesn't take an offset. If there
1498 * is a non-negative non-zero offset, this is
1499 * specified in immediate offset mode, with the
1500 * values in the offset_* fields as immediates. If
1501 * this is a negative offset, we instead switch to
1502 * a register offset mode, where the offset_*
1503 * fields become register triplets */
1504
1505 if (texture->offset_register) {
1506 fprintf(fp, " + ");
1507
1508 bool full = texture->offset & 1;
1509 bool select = texture->offset & 2;
1510 bool upper = texture->offset & 4;
1511
1512 fprintf(fp, "%sr%u", full ? "" : "h", in_reg_base + select);
1513 assert(!(texture->out_full && texture->out_upper));
1514
1515 /* TODO: integrate with swizzle */
1516 if (upper)
1517 fprintf(fp, "'");
1518
1519 print_swizzle_vec4(fp, texture->offset >> 3, false, false, false);
1520
1521 fprintf(fp, ", ");
1522 } else if (texture->offset) {
1523 /* Only select ops allow negative immediate offsets, verify */
1524
1525 signed offset_x = (texture->offset & 0xF);
1526 signed offset_y = ((texture->offset >> 4) & 0xF);
1527 signed offset_z = ((texture->offset >> 8) & 0xF);
1528
1529 bool neg_x = offset_x < 0;
1530 bool neg_y = offset_y < 0;
1531 bool neg_z = offset_z < 0;
1532 bool any_neg = neg_x || neg_y || neg_z;
1533
1534 if (any_neg && texture->op != TEXTURE_OP_TEXEL_FETCH)
1535 fprintf(fp, "/* invalid negative */ ");
1536
1537 /* Regardless, just print the immediate offset */
1538
1539 fprintf(fp, " + <%d, %d, %d>, ", offset_x, offset_y, offset_z);
1540 } else {
1541 fprintf(fp, ", ");
1542 }
1543
1544 char lod_operand = texture_op_takes_bias(texture->op) ? '+' : '=';
1545
1546 if (texture->lod_register) {
1547 fprintf(fp, "lod %c ", lod_operand);
1548 print_texture_reg_select(fp, texture->bias, in_reg_base);
1549 fprintf(fp, ", ");
1550
1551 if (texture->bias_int)
1552 fprintf(fp, " /* bias_int = 0x%X */", texture->bias_int);
1553 } else if (texture->op == TEXTURE_OP_TEXEL_FETCH) {
1554 /* For texel fetch, the int LOD is in the fractional place and
1555 * there is no fraction. We *always* have an explicit LOD, even
1556 * if it's zero. */
1557
1558 if (texture->bias_int)
1559 fprintf(fp, " /* bias_int = 0x%X */ ", texture->bias_int);
1560
1561 fprintf(fp, "lod = %u, ", texture->bias);
1562 } else if (texture->bias || texture->bias_int) {
1563 signed bias_int = texture->bias_int;
1564 float bias_frac = texture->bias / 256.0f;
1565 float bias = bias_int + bias_frac;
1566
1567 bool is_bias = texture_op_takes_bias(texture->op);
1568 char sign = (bias >= 0.0) ? '+' : '-';
1569 char operand = is_bias ? sign : '=';
1570
1571 fprintf(fp, "lod %c %f, ", operand, fabsf(bias));
1572 }
1573
1574 fprintf(fp, "\n");
1575
1576 /* While not zero in general, for these simple instructions the
1577 * following unknowns are zero, so we don't include them */
1578
1579 if (texture->unknown4 ||
1580 texture->unknown8) {
1581 fprintf(fp, "// unknown4 = 0x%x\n", texture->unknown4);
1582 fprintf(fp, "// unknown8 = 0x%x\n", texture->unknown8);
1583 }
1584
1585 midg_stats.instruction_count++;
1586 }
1587
1588 struct midgard_disasm_stats
1589 disassemble_midgard(FILE *fp, uint8_t *code, size_t size, unsigned gpu_id, gl_shader_stage stage)
1590 {
1591 uint32_t *words = (uint32_t *) code;
1592 unsigned num_words = size / 4;
1593 int tabs = 0;
1594
1595 bool branch_forward = false;
1596
1597 int last_next_tag = -1;
1598
1599 unsigned i = 0;
1600
1601 midg_tags = calloc(sizeof(midg_tags[0]), num_words);
1602
1603 /* Stats for shader-db */
1604 memset(&midg_stats, 0, sizeof(midg_stats));
1605 midg_ever_written = 0;
1606
1607 while (i < num_words) {
1608 unsigned tag = words[i] & 0xF;
1609 unsigned next_tag = (words[i] >> 4) & 0xF;
1610 unsigned num_quad_words = midgard_tag_props[tag].size;
1611
1612 if (midg_tags[i] && midg_tags[i] != tag) {
1613 fprintf(fp, "\t/* XXX: TAG ERROR branch, got %s expected %s */\n",
1614 midgard_tag_props[tag].name,
1615 midgard_tag_props[midg_tags[i]].name);
1616 }
1617
1618 midg_tags[i] = tag;
1619
1620 /* Check the tag. The idea is to ensure that next_tag is
1621 * *always* recoverable from the disassembly, such that we may
1622 * safely omit printing next_tag. To show this, we first
1623 * consider that next tags are semantically off-byone -- we end
1624 * up parsing tag n during step n+1. So, we ensure after we're
1625 * done disassembling the next tag of the final bundle is BREAK
1626 * and warn otherwise. We also ensure that the next tag is
1627 * never INVALID. Beyond that, since the last tag is checked
1628 * outside the loop, we can check one tag prior. If equal to
1629 * the current tag (which is unique), we're done. Otherwise, we
1630 * print if that tag was > TAG_BREAK, which implies the tag was
1631 * not TAG_BREAK or TAG_INVALID. But we already checked for
1632 * TAG_INVALID, so it's just if the last tag was TAG_BREAK that
1633 * we're silent. So we throw in a print for break-next on at
1634 * the end of the bundle (if it's not the final bundle, which
1635 * we already check for above), disambiguating this case as
1636 * well. Hence in all cases we are unambiguous, QED. */
1637
1638 if (next_tag == TAG_INVALID)
1639 fprintf(fp, "\t/* XXX: invalid next tag */\n");
1640
1641 if (last_next_tag > TAG_BREAK && last_next_tag != tag) {
1642 fprintf(fp, "\t/* XXX: TAG ERROR sequence, got %s expexted %s */\n",
1643 midgard_tag_props[tag].name,
1644 midgard_tag_props[last_next_tag].name);
1645 }
1646
1647 last_next_tag = next_tag;
1648
1649 /* Tags are unique in the following way:
1650 *
1651 * INVALID, BREAK, UNKNOWN_*: verbosely printed
1652 * TEXTURE_4_BARRIER: verified by barrier/!barrier op
1653 * TEXTURE_4_VTX: .vtx tag printed
1654 * TEXTURE_4: tetxure lack of barriers or .vtx
1655 * TAG_LOAD_STORE_4: only load/store
1656 * TAG_ALU_4/8/12/16: by number of instructions/constants
1657 * TAG_ALU_4_8/12/16_WRITEOUT: ^^ with .writeout tag
1658 */
1659
1660 switch (tag) {
1661 case TAG_TEXTURE_4_VTX ... TAG_TEXTURE_4_BARRIER: {
1662 bool interpipe_aliasing =
1663 midgard_get_quirks(gpu_id) & MIDGARD_INTERPIPE_REG_ALIASING;
1664
1665 print_texture_word(fp, &words[i], tabs,
1666 interpipe_aliasing ? 0 : REG_TEX_BASE,
1667 interpipe_aliasing ? REGISTER_LDST_BASE : REG_TEX_BASE);
1668 break;
1669 }
1670
1671 case TAG_LOAD_STORE_4:
1672 print_load_store_word(fp, &words[i], tabs);
1673 break;
1674
1675 case TAG_ALU_4 ... TAG_ALU_16_WRITEOUT:
1676 branch_forward = print_alu_word(fp, &words[i], num_quad_words, tabs, i + 4*num_quad_words);
1677
1678 /* Reset word static analysis state */
1679 is_embedded_constant_half = false;
1680 is_embedded_constant_int = false;
1681
1682 /* TODO: infer/verify me */
1683 if (tag >= TAG_ALU_4_WRITEOUT)
1684 fprintf(fp, "writeout\n");
1685
1686 break;
1687
1688 default:
1689 fprintf(fp, "Unknown word type %u:\n", words[i] & 0xF);
1690 num_quad_words = 1;
1691 print_quad_word(fp, &words[i], tabs);
1692 fprintf(fp, "\n");
1693 break;
1694 }
1695
1696 /* We are parsing per bundle anyway. Add before we start
1697 * breaking out so we don't miss the final bundle. */
1698
1699 midg_stats.bundle_count++;
1700 midg_stats.quadword_count += num_quad_words;
1701
1702 /* Include a synthetic "break" instruction at the end of the
1703 * bundle to signify that if, absent a branch, the shader
1704 * execution will stop here. Stop disassembly at such a break
1705 * based on a heuristic */
1706
1707 if (next_tag == TAG_BREAK) {
1708 if (branch_forward) {
1709 fprintf(fp, "break\n");
1710 } else {
1711 fprintf(fp, "\n");
1712 break;
1713 }
1714 }
1715
1716 fprintf(fp, "\n");
1717
1718 i += 4 * num_quad_words;
1719 }
1720
1721 if (last_next_tag != TAG_BREAK) {
1722 fprintf(fp, "/* XXX: shader ended with tag %s */\n",
1723 midgard_tag_props[last_next_tag].name);
1724 }
1725
1726 free(midg_tags);
1727
1728 /* We computed work_count as max_work_registers, so add one to get the
1729 * count. If no work registers are written, you still have one work
1730 * reported, which is exactly what the hardware expects */
1731
1732 midg_stats.work_count++;
1733
1734 return midg_stats;
1735 }