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pan/midgard: Identify stack barrier flag
[mesa.git] / src / panfrost / midgard / disassemble.c
1 /* Author(s):
2 * Connor Abbott
3 * Alyssa Rosenzweig
4 *
5 * Copyright (c) 2013 Connor Abbott (connor@abbott.cx)
6 * Copyright (c) 2018 Alyssa Rosenzweig (alyssa@rosenzweig.io)
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #include <stdio.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <assert.h>
31 #include <inttypes.h>
32 #include <ctype.h>
33 #include <string.h>
34 #include "midgard.h"
35 #include "midgard_ops.h"
36 #include "midgard_quirks.h"
37 #include "disassemble.h"
38 #include "helpers.h"
39 #include "util/bitscan.h"
40 #include "util/half_float.h"
41 #include "util/u_math.h"
42
43 #define DEFINE_CASE(define, str) case define: { fprintf(fp, str); break; }
44
45 static unsigned *midg_tags;
46 static bool is_instruction_int = false;
47
48 /* Stats */
49
50 static struct midgard_disasm_stats midg_stats;
51
52 static void
53 print_alu_opcode(FILE *fp, midgard_alu_op op)
54 {
55 bool int_op = false;
56
57 if (alu_opcode_props[op].name) {
58 fprintf(fp, "%s", alu_opcode_props[op].name);
59
60 int_op = midgard_is_integer_op(op);
61 } else
62 fprintf(fp, "alu_op_%02X", op);
63
64 /* For constant analysis */
65 is_instruction_int = int_op;
66 }
67
68 static void
69 print_ld_st_opcode(FILE *fp, midgard_load_store_op op)
70 {
71 if (load_store_opcode_props[op].name)
72 fprintf(fp, "%s", load_store_opcode_props[op].name);
73 else
74 fprintf(fp, "ldst_op_%02X", op);
75 }
76
77 static bool is_embedded_constant_half = false;
78 static bool is_embedded_constant_int = false;
79
80 static char
81 prefix_for_bits(unsigned bits)
82 {
83 switch (bits) {
84 case 8:
85 return 'q';
86 case 16:
87 return 'h';
88 case 64:
89 return 'd';
90 default:
91 return 0;
92 }
93 }
94
95 /* For static analysis to ensure all registers are written at least once before
96 * use along the source code path (TODO: does this break done for complex CF?)
97 */
98
99 uint16_t midg_ever_written = 0;
100
101 static void
102 print_reg(FILE *fp, unsigned reg, unsigned bits)
103 {
104 /* Perform basic static analysis for expanding constants correctly */
105
106 if (reg == 26) {
107 is_embedded_constant_int = is_instruction_int;
108 is_embedded_constant_half = (bits < 32);
109 }
110
111 unsigned uniform_reg = 23 - reg;
112 bool is_uniform = false;
113
114 /* For r8-r15, it could be a work or uniform. We distinguish based on
115 * the fact work registers are ALWAYS written before use, but uniform
116 * registers are NEVER written before use. */
117
118 if ((reg >= 8 && reg < 16) && !(midg_ever_written & (1 << reg)))
119 is_uniform = true;
120
121 /* r16-r23 are always uniform */
122
123 if (reg >= 16 && reg <= 23)
124 is_uniform = true;
125
126 /* Update the uniform count appropriately */
127
128 if (is_uniform)
129 midg_stats.uniform_count =
130 MAX2(uniform_reg + 1, midg_stats.uniform_count);
131
132 char prefix = prefix_for_bits(bits);
133
134 if (prefix)
135 fputc(prefix, fp);
136
137 fprintf(fp, "r%u", reg);
138 }
139
140 static char *outmod_names_float[4] = {
141 "",
142 ".pos",
143 ".unk2",
144 ".sat"
145 };
146
147 static char *outmod_names_int[4] = {
148 ".isat",
149 ".usat",
150 "",
151 ".hi"
152 };
153
154 static char *srcmod_names_int[4] = {
155 "sext(",
156 "zext(",
157 "",
158 "("
159 };
160
161 static void
162 print_outmod(FILE *fp, unsigned outmod, bool is_int)
163 {
164 fprintf(fp, "%s", is_int ? outmod_names_int[outmod] :
165 outmod_names_float[outmod]);
166 }
167
168 static void
169 print_quad_word(FILE *fp, uint32_t *words, unsigned tabs)
170 {
171 unsigned i;
172
173 for (i = 0; i < 4; i++)
174 fprintf(fp, "0x%08X%s ", words[i], i == 3 ? "" : ",");
175
176 fprintf(fp, "\n");
177 }
178
179 static const char components[16] = "xyzwefghijklmnop";
180
181 /* Helper to print 4 chars of a swizzle */
182 static void
183 print_swizzle_helper(FILE *fp, unsigned swizzle, unsigned offset)
184 {
185 for (unsigned i = 0; i < 4; ++i) {
186 unsigned c = (swizzle >> (i * 2)) & 3;
187 c += offset;
188 fprintf(fp, "%c", components[c]);
189 }
190 }
191
192 /* Helper to print 8 chars of a swizzle, duplicating over */
193 static void
194 print_swizzle_helper_8(FILE *fp, unsigned swizzle, bool upper)
195 {
196 for (unsigned i = 0; i < 4; ++i) {
197 unsigned c = (swizzle >> (i * 2)) & 3;
198 c *= 2;
199 c += upper*8;
200 fprintf(fp, "%c%c", components[c], components[c+1]);
201 }
202 }
203
204 static void
205 print_swizzle_vec16(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low,
206 midgard_dest_override override)
207 {
208 fprintf(fp, ".");
209
210 if (override == midgard_dest_override_upper) {
211 if (rep_high)
212 fprintf(fp, " /* rep_high */ ");
213 if (rep_low)
214 fprintf(fp, " /* rep_low */ ");
215
216 if (!rep_high && rep_low)
217 print_swizzle_helper_8(fp, swizzle, true);
218 else
219 print_swizzle_helper_8(fp, swizzle, false);
220 } else {
221 print_swizzle_helper_8(fp, swizzle, rep_high & 1);
222 print_swizzle_helper_8(fp, swizzle, !(rep_low & 1));
223 }
224 }
225
226 static void
227 print_swizzle_vec8(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low, bool half)
228 {
229 fprintf(fp, ".");
230
231 /* TODO: Is it possible to unify half/full? */
232
233 if (half) {
234 print_swizzle_helper(fp, swizzle, (rep_low * 8));
235 print_swizzle_helper(fp, swizzle, (rep_low * 8) + !rep_high * 4);
236 } else {
237 print_swizzle_helper(fp, swizzle, rep_high * 4);
238 print_swizzle_helper(fp, swizzle, !rep_low * 4);
239 }
240 }
241
242 static void
243 print_swizzle_vec4(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low, bool half)
244 {
245 if (rep_high)
246 fprintf(fp, " /* rep_high */ ");
247
248 if (!half && rep_low)
249 fprintf(fp, " /* rep_low */ ");
250
251 if (swizzle == 0xE4 && !half) return; /* xyzw */
252
253 fprintf(fp, ".");
254 print_swizzle_helper(fp, swizzle, rep_low * 4);
255 }
256 static void
257 print_swizzle_vec2(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low, bool half)
258 {
259 char *alphabet = "XY";
260
261 if (half) {
262 alphabet = rep_low ? "zw" : "xy";
263 } else if (rep_low)
264 fprintf(fp, " /* rep_low */ ");
265
266 if (rep_high)
267 fprintf(fp, " /* rep_high */ ");
268
269 if (swizzle == 0xE4 && !half) return; /* XY */
270
271 fprintf(fp, ".");
272
273 for (unsigned i = 0; i < 4; i += 2) {
274 unsigned a = (swizzle >> (i * 2)) & 3;
275 unsigned b = (swizzle >> ((i+1) * 2)) & 3;
276
277 /* Normally we're adjacent, but if there's an issue, don't make
278 * it ambiguous */
279
280 if (b == (a + 1))
281 fprintf(fp, "%c", alphabet[a >> 1]);
282 else
283 fprintf(fp, "[%c%c]", components[a], components[b]);
284 }
285 }
286
287 static int
288 bits_for_mode(midgard_reg_mode mode)
289 {
290 switch (mode) {
291 case midgard_reg_mode_8:
292 return 8;
293 case midgard_reg_mode_16:
294 return 16;
295 case midgard_reg_mode_32:
296 return 32;
297 case midgard_reg_mode_64:
298 return 64;
299 default:
300 unreachable("Invalid reg mode");
301 return 0;
302 }
303 }
304
305 static int
306 bits_for_mode_halved(midgard_reg_mode mode, bool half)
307 {
308 unsigned bits = bits_for_mode(mode);
309
310 if (half)
311 bits >>= 1;
312
313 return bits;
314 }
315
316 static void
317 print_scalar_constant(FILE *fp, unsigned src_binary,
318 const midgard_constants *consts,
319 midgard_scalar_alu *alu)
320 {
321 midgard_scalar_alu_src *src = (midgard_scalar_alu_src *)&src_binary;
322 unsigned mod = 0;
323
324 assert(consts != NULL);
325
326 if (!midgard_is_integer_op(alu->op)) {
327 if (src->abs)
328 mod |= MIDGARD_FLOAT_MOD_ABS;
329 if (src->negate)
330 mod |= MIDGARD_FLOAT_MOD_NEG;
331 } else {
332 mod = midgard_int_normal;
333 }
334
335 fprintf(fp, "#");
336 mir_print_constant_component(fp, consts, src->component,
337 src->full ?
338 midgard_reg_mode_32 : midgard_reg_mode_16,
339 false, mod, alu->op);
340 }
341
342 static void
343 print_vector_constants(FILE *fp, unsigned src_binary,
344 const midgard_constants *consts,
345 midgard_vector_alu *alu)
346 {
347 midgard_vector_alu_src *src = (midgard_vector_alu_src *)&src_binary;
348 unsigned bits = bits_for_mode_halved(alu->reg_mode, src->half);
349 unsigned max_comp = MIN2((sizeof(*consts) * 8) / bits, 8);
350 unsigned comp_mask, num_comp = 0;
351
352 assert(consts);
353
354 comp_mask = effective_writemask(alu, condense_writemask(alu->mask, bits));
355 num_comp = util_bitcount(comp_mask);
356
357 fprintf(fp, "#");
358 if (num_comp > 1)
359 fprintf(fp, "vec%d(", num_comp);
360
361 bool first = true;
362
363 for (unsigned i = 0; i < max_comp; ++i) {
364 if (!(comp_mask & (1 << i))) continue;
365
366 unsigned c = (src->swizzle >> (i * 2)) & 3;
367
368 if (first)
369 first = false;
370 else
371 fprintf(fp, ", ");
372
373 mir_print_constant_component(fp, consts, c, alu->reg_mode,
374 src->half, src->mod, alu->op);
375 }
376
377 if (num_comp > 1)
378 fprintf(fp, ")");
379 }
380
381 static void
382 print_vector_src(FILE *fp, unsigned src_binary,
383 midgard_reg_mode mode, unsigned reg,
384 midgard_dest_override override, bool is_int)
385 {
386 midgard_vector_alu_src *src = (midgard_vector_alu_src *)&src_binary;
387
388 /* Modifiers change meaning depending on the op's context */
389
390 midgard_int_mod int_mod = src->mod;
391
392 if (is_int) {
393 fprintf(fp, "%s", srcmod_names_int[int_mod]);
394 } else {
395 if (src->mod & MIDGARD_FLOAT_MOD_NEG)
396 fprintf(fp, "-");
397
398 if (src->mod & MIDGARD_FLOAT_MOD_ABS)
399 fprintf(fp, "abs(");
400 }
401
402 //register
403 unsigned bits = bits_for_mode_halved(mode, src->half);
404 print_reg(fp, reg, bits);
405
406 /* When the source was stepped down via `half`, rep_low means "higher
407 * half" and rep_high is never seen. When it's not native,
408 * rep_low/rep_high are for, well, replication */
409
410 if (mode == midgard_reg_mode_8) {
411 assert(!src->half);
412 print_swizzle_vec16(fp, src->swizzle, src->rep_high, src->rep_low, override);
413 } else if (mode == midgard_reg_mode_16) {
414 print_swizzle_vec8(fp, src->swizzle, src->rep_high, src->rep_low, src->half);
415 } else if (mode == midgard_reg_mode_32) {
416 print_swizzle_vec4(fp, src->swizzle, src->rep_high, src->rep_low, src->half);
417 } else if (mode == midgard_reg_mode_64) {
418 print_swizzle_vec2(fp, src->swizzle, src->rep_high, src->rep_low, src->half);
419 }
420
421 /* Since we wrapped with a function-looking thing */
422
423 if (is_int && int_mod == midgard_int_shift)
424 fprintf(fp, ") << %u", bits);
425 else if ((is_int && (int_mod != midgard_int_normal))
426 || (!is_int && src->mod & MIDGARD_FLOAT_MOD_ABS))
427 fprintf(fp, ")");
428 }
429
430 static uint16_t
431 decode_vector_imm(unsigned src2_reg, unsigned imm)
432 {
433 uint16_t ret;
434 ret = src2_reg << 11;
435 ret |= (imm & 0x7) << 8;
436 ret |= (imm >> 3) & 0xFF;
437 return ret;
438 }
439
440 static void
441 print_immediate(FILE *fp, uint16_t imm)
442 {
443 if (is_instruction_int)
444 fprintf(fp, "#%u", imm);
445 else
446 fprintf(fp, "#%g", _mesa_half_to_float(imm));
447 }
448
449 static void
450 update_dest(unsigned reg)
451 {
452 /* We should record writes as marking this as a work register. Store
453 * the max register in work_count; we'll add one at the end */
454
455 if (reg < 16) {
456 midg_stats.work_count = MAX2(reg, midg_stats.work_count);
457 midg_ever_written |= (1 << reg);
458 }
459 }
460
461 static void
462 print_dest(FILE *fp, unsigned reg, midgard_reg_mode mode, midgard_dest_override override)
463 {
464 /* Depending on the mode and override, we determine the type of
465 * destination addressed. Absent an override, we address just the
466 * type of the operation itself */
467
468 unsigned bits = bits_for_mode(mode);
469
470 if (override != midgard_dest_override_none)
471 bits /= 2;
472
473 update_dest(reg);
474 print_reg(fp, reg, bits);
475 }
476
477 static void
478 print_mask_vec16(FILE *fp, uint8_t mask, midgard_dest_override override)
479 {
480 fprintf(fp, ".");
481
482 for (unsigned i = 0; i < 8; i++) {
483 if (mask & (1 << i))
484 fprintf(fp, "%c%c",
485 components[i*2 + 0],
486 components[i*2 + 1]);
487 }
488 }
489
490 /* For 16-bit+ masks, we read off from the 8-bit mask field. For 16-bit (vec8),
491 * it's just one bit per channel, easy peasy. For 32-bit (vec4), it's one bit
492 * per channel with one duplicate bit in the middle. For 64-bit (vec2), it's
493 * one-bit per channel with _3_ duplicate bits in the middle. Basically, just
494 * subdividing the 128-bit word in 16-bit increments. For 64-bit, we uppercase
495 * the mask to make it obvious what happened */
496
497 static void
498 print_mask(FILE *fp, uint8_t mask, unsigned bits, midgard_dest_override override)
499 {
500 if (bits == 8) {
501 print_mask_vec16(fp, mask, override);
502 return;
503 }
504
505 /* Skip 'complete' masks */
506
507 if (override == midgard_dest_override_none)
508 if (bits >= 32 && mask == 0xFF) return;
509
510 fprintf(fp, ".");
511
512 unsigned skip = (bits / 16);
513 bool uppercase = bits > 32;
514 bool tripped = false;
515
516 /* To apply an upper destination override, we "shift" the alphabet.
517 * E.g. with an upper override on 32-bit, instead of xyzw, print efgh.
518 * For upper 16-bit, instead of xyzwefgh, print ijklmnop */
519
520 const char *alphabet = components;
521
522 if (override == midgard_dest_override_upper)
523 alphabet += (128 / bits);
524
525 for (unsigned i = 0; i < 8; i += skip) {
526 bool a = (mask & (1 << i)) != 0;
527
528 for (unsigned j = 1; j < skip; ++j) {
529 bool dupe = (mask & (1 << (i + j))) != 0;
530 tripped |= (dupe != a);
531 }
532
533 if (a) {
534 char c = alphabet[i / skip];
535
536 if (uppercase)
537 c = toupper(c);
538
539 fprintf(fp, "%c", c);
540 }
541 }
542
543 if (tripped)
544 fprintf(fp, " /* %X */", mask);
545 }
546
547 /* Prints the 4-bit masks found in texture and load/store ops, as opposed to
548 * the 8-bit masks found in (vector) ALU ops. Supports texture-style 16-bit
549 * mode as well, but not load/store-style 16-bit mode. */
550
551 static void
552 print_mask_4(FILE *fp, unsigned mask, bool upper)
553 {
554 if (mask == 0xF) {
555 if (upper)
556 fprintf(fp, "'");
557
558 return;
559 }
560
561 fprintf(fp, ".");
562
563 for (unsigned i = 0; i < 4; ++i) {
564 bool a = (mask & (1 << i)) != 0;
565 if (a)
566 fprintf(fp, "%c", components[i + (upper ? 4 : 0)]);
567 }
568 }
569
570 static void
571 print_vector_field(FILE *fp, const char *name, uint16_t *words, uint16_t reg_word,
572 const midgard_constants *consts, unsigned tabs)
573 {
574 midgard_reg_info *reg_info = (midgard_reg_info *)&reg_word;
575 midgard_vector_alu *alu_field = (midgard_vector_alu *) words;
576 midgard_reg_mode mode = alu_field->reg_mode;
577 unsigned override = alu_field->dest_override;
578
579 /* For now, prefix instruction names with their unit, until we
580 * understand how this works on a deeper level */
581 fprintf(fp, "%s.", name);
582
583 print_alu_opcode(fp, alu_field->op);
584
585 /* Postfix with the size to disambiguate if necessary */
586 char postfix = prefix_for_bits(bits_for_mode(mode));
587 bool size_ambiguous = override != midgard_dest_override_none;
588
589 if (size_ambiguous)
590 fprintf(fp, "%c", postfix ? postfix : 'r');
591
592 /* Print the outmod, if there is one */
593 print_outmod(fp, alu_field->outmod,
594 midgard_is_integer_out_op(alu_field->op));
595
596 fprintf(fp, " ");
597
598 /* Mask denoting status of 8-lanes */
599 uint8_t mask = alu_field->mask;
600
601 /* First, print the destination */
602 print_dest(fp, reg_info->out_reg, mode, alu_field->dest_override);
603
604 if (override != midgard_dest_override_none) {
605 bool modeable = (mode != midgard_reg_mode_8);
606 bool known = override != 0x3; /* Unused value */
607
608 if (!(modeable && known))
609 fprintf(fp, "/* do%u */ ", override);
610 }
611
612 print_mask(fp, mask, bits_for_mode(mode), override);
613
614 fprintf(fp, ", ");
615
616 bool is_int = midgard_is_integer_op(alu_field->op);
617
618 if (reg_info->src1_reg == 26)
619 print_vector_constants(fp, alu_field->src1, consts, alu_field);
620 else
621 print_vector_src(fp, alu_field->src1, mode, reg_info->src1_reg, override, is_int);
622
623 fprintf(fp, ", ");
624
625 if (reg_info->src2_imm) {
626 uint16_t imm = decode_vector_imm(reg_info->src2_reg, alu_field->src2 >> 2);
627 print_immediate(fp, imm);
628 } else if (reg_info->src2_reg == 26) {
629 print_vector_constants(fp, alu_field->src2, consts, alu_field);
630 } else {
631 print_vector_src(fp, alu_field->src2, mode,
632 reg_info->src2_reg, override, is_int);
633 }
634
635 midg_stats.instruction_count++;
636 fprintf(fp, "\n");
637 }
638
639 static void
640 print_scalar_src(FILE *fp, unsigned src_binary, unsigned reg)
641 {
642 midgard_scalar_alu_src *src = (midgard_scalar_alu_src *)&src_binary;
643
644 if (src->negate)
645 fprintf(fp, "-");
646
647 if (src->abs)
648 fprintf(fp, "abs(");
649
650 print_reg(fp, reg, src->full ? 32 : 16);
651
652 unsigned c = src->component;
653
654 if (src->full) {
655 assert((c & 1) == 0);
656 c >>= 1;
657 }
658
659 fprintf(fp, ".%c", components[c]);
660
661 if (src->abs)
662 fprintf(fp, ")");
663
664 }
665
666 static uint16_t
667 decode_scalar_imm(unsigned src2_reg, unsigned imm)
668 {
669 uint16_t ret;
670 ret = src2_reg << 11;
671 ret |= (imm & 3) << 9;
672 ret |= (imm & 4) << 6;
673 ret |= (imm & 0x38) << 2;
674 ret |= imm >> 6;
675 return ret;
676 }
677
678 static void
679 print_scalar_field(FILE *fp, const char *name, uint16_t *words, uint16_t reg_word,
680 const midgard_constants *consts, unsigned tabs)
681 {
682 midgard_reg_info *reg_info = (midgard_reg_info *)&reg_word;
683 midgard_scalar_alu *alu_field = (midgard_scalar_alu *) words;
684
685 if (alu_field->unknown)
686 fprintf(fp, "scalar ALU unknown bit set\n");
687
688 fprintf(fp, "%s.", name);
689 print_alu_opcode(fp, alu_field->op);
690 print_outmod(fp, alu_field->outmod,
691 midgard_is_integer_out_op(alu_field->op));
692 fprintf(fp, " ");
693
694 bool full = alu_field->output_full;
695 update_dest(reg_info->out_reg);
696 print_reg(fp, reg_info->out_reg, full ? 32 : 16);
697 unsigned c = alu_field->output_component;
698
699 if (full) {
700 assert((c & 1) == 0);
701 c >>= 1;
702 }
703
704 fprintf(fp, ".%c, ", components[c]);
705
706 if (reg_info->src1_reg == 26)
707 print_scalar_constant(fp, alu_field->src1, consts, alu_field);
708 else
709 print_scalar_src(fp, alu_field->src1, reg_info->src1_reg);
710
711 fprintf(fp, ", ");
712
713 if (reg_info->src2_imm) {
714 uint16_t imm = decode_scalar_imm(reg_info->src2_reg,
715 alu_field->src2);
716 print_immediate(fp, imm);
717 } else if (reg_info->src2_reg == 26) {
718 print_scalar_constant(fp, alu_field->src2, consts, alu_field);
719 } else
720 print_scalar_src(fp, alu_field->src2, reg_info->src2_reg);
721
722 midg_stats.instruction_count++;
723 fprintf(fp, "\n");
724 }
725
726 static void
727 print_branch_op(FILE *fp, unsigned op)
728 {
729 switch (op) {
730 case midgard_jmp_writeout_op_branch_uncond:
731 fprintf(fp, "uncond.");
732 break;
733
734 case midgard_jmp_writeout_op_branch_cond:
735 fprintf(fp, "cond.");
736 break;
737
738 case midgard_jmp_writeout_op_writeout:
739 fprintf(fp, "write.");
740 break;
741
742 case midgard_jmp_writeout_op_tilebuffer_pending:
743 fprintf(fp, "tilebuffer.");
744 break;
745
746 case midgard_jmp_writeout_op_discard:
747 fprintf(fp, "discard.");
748 break;
749
750 default:
751 fprintf(fp, "unk%u.", op);
752 break;
753 }
754 }
755
756 static void
757 print_branch_cond(FILE *fp, int cond)
758 {
759 switch (cond) {
760 case midgard_condition_write0:
761 fprintf(fp, "write0");
762 break;
763
764 case midgard_condition_false:
765 fprintf(fp, "false");
766 break;
767
768 case midgard_condition_true:
769 fprintf(fp, "true");
770 break;
771
772 case midgard_condition_always:
773 fprintf(fp, "always");
774 break;
775
776 default:
777 fprintf(fp, "unk%X", cond);
778 break;
779 }
780 }
781
782 static bool
783 print_compact_branch_writeout_field(FILE *fp, uint16_t word)
784 {
785 midgard_jmp_writeout_op op = word & 0x7;
786 midg_stats.instruction_count++;
787
788 switch (op) {
789 case midgard_jmp_writeout_op_branch_uncond: {
790 midgard_branch_uncond br_uncond;
791 memcpy((char *) &br_uncond, (char *) &word, sizeof(br_uncond));
792 fprintf(fp, "br.uncond ");
793
794 if (br_uncond.unknown != 1)
795 fprintf(fp, "unknown:%u, ", br_uncond.unknown);
796
797 if (br_uncond.offset >= 0)
798 fprintf(fp, "+");
799
800 fprintf(fp, "%d -> %s", br_uncond.offset,
801 midgard_tag_props[br_uncond.dest_tag].name);
802 fprintf(fp, "\n");
803
804 return br_uncond.offset >= 0;
805 }
806
807 case midgard_jmp_writeout_op_branch_cond:
808 case midgard_jmp_writeout_op_writeout:
809 case midgard_jmp_writeout_op_discard:
810 default: {
811 midgard_branch_cond br_cond;
812 memcpy((char *) &br_cond, (char *) &word, sizeof(br_cond));
813
814 fprintf(fp, "br.");
815
816 print_branch_op(fp, br_cond.op);
817 print_branch_cond(fp, br_cond.cond);
818
819 fprintf(fp, " ");
820
821 if (br_cond.offset >= 0)
822 fprintf(fp, "+");
823
824 fprintf(fp, "%d -> %s", br_cond.offset,
825 midgard_tag_props[br_cond.dest_tag].name);
826 fprintf(fp, "\n");
827
828 return br_cond.offset >= 0;
829 }
830 }
831
832 return false;
833 }
834
835 static bool
836 print_extended_branch_writeout_field(FILE *fp, uint8_t *words, unsigned next)
837 {
838 midgard_branch_extended br;
839 memcpy((char *) &br, (char *) words, sizeof(br));
840
841 fprintf(fp, "brx.");
842
843 print_branch_op(fp, br.op);
844
845 /* Condition codes are a LUT in the general case, but simply repeated 8 times for single-channel conditions.. Check this. */
846
847 bool single_channel = true;
848
849 for (unsigned i = 0; i < 16; i += 2) {
850 single_channel &= (((br.cond >> i) & 0x3) == (br.cond & 0x3));
851 }
852
853 if (single_channel)
854 print_branch_cond(fp, br.cond & 0x3);
855 else
856 fprintf(fp, "lut%X", br.cond);
857
858 if (br.unknown)
859 fprintf(fp, ".unknown%u", br.unknown);
860
861 fprintf(fp, " ");
862
863 if (br.offset >= 0)
864 fprintf(fp, "+");
865
866 fprintf(fp, "%d -> %s\n", br.offset,
867 midgard_tag_props[br.dest_tag].name);
868
869 unsigned I = next + br.offset * 4;
870
871 if (midg_tags[I] && midg_tags[I] != br.dest_tag) {
872 fprintf(fp, "\t/* XXX TAG ERROR: jumping to %s but tagged %s \n",
873 midgard_tag_props[br.dest_tag].name,
874 midgard_tag_props[midg_tags[I]].name);
875 }
876
877 midg_tags[I] = br.dest_tag;
878
879 midg_stats.instruction_count++;
880 return br.offset >= 0;
881 }
882
883 static unsigned
884 num_alu_fields_enabled(uint32_t control_word)
885 {
886 unsigned ret = 0;
887
888 if ((control_word >> 17) & 1)
889 ret++;
890
891 if ((control_word >> 19) & 1)
892 ret++;
893
894 if ((control_word >> 21) & 1)
895 ret++;
896
897 if ((control_word >> 23) & 1)
898 ret++;
899
900 if ((control_word >> 25) & 1)
901 ret++;
902
903 return ret;
904 }
905
906 static bool
907 print_alu_word(FILE *fp, uint32_t *words, unsigned num_quad_words,
908 unsigned tabs, unsigned next)
909 {
910 uint32_t control_word = words[0];
911 uint16_t *beginning_ptr = (uint16_t *)(words + 1);
912 unsigned num_fields = num_alu_fields_enabled(control_word);
913 uint16_t *word_ptr = beginning_ptr + num_fields;
914 unsigned num_words = 2 + num_fields;
915 const midgard_constants *consts = NULL;
916 bool branch_forward = false;
917
918 if ((control_word >> 17) & 1)
919 num_words += 3;
920
921 if ((control_word >> 19) & 1)
922 num_words += 2;
923
924 if ((control_word >> 21) & 1)
925 num_words += 3;
926
927 if ((control_word >> 23) & 1)
928 num_words += 2;
929
930 if ((control_word >> 25) & 1)
931 num_words += 3;
932
933 if ((control_word >> 26) & 1)
934 num_words += 1;
935
936 if ((control_word >> 27) & 1)
937 num_words += 3;
938
939 if (num_quad_words > (num_words + 7) / 8) {
940 assert(num_quad_words == (num_words + 15) / 8);
941 //Assume that the extra quadword is constants
942 consts = (midgard_constants *)(words + (4 * num_quad_words - 4));
943 }
944
945 if ((control_word >> 16) & 1)
946 fprintf(fp, "unknown bit 16 enabled\n");
947
948 if ((control_word >> 17) & 1) {
949 print_vector_field(fp, "vmul", word_ptr, *beginning_ptr, consts, tabs);
950 beginning_ptr += 1;
951 word_ptr += 3;
952 }
953
954 if ((control_word >> 18) & 1)
955 fprintf(fp, "unknown bit 18 enabled\n");
956
957 if ((control_word >> 19) & 1) {
958 print_scalar_field(fp, "sadd", word_ptr, *beginning_ptr, consts, tabs);
959 beginning_ptr += 1;
960 word_ptr += 2;
961 }
962
963 if ((control_word >> 20) & 1)
964 fprintf(fp, "unknown bit 20 enabled\n");
965
966 if ((control_word >> 21) & 1) {
967 print_vector_field(fp, "vadd", word_ptr, *beginning_ptr, consts, tabs);
968 beginning_ptr += 1;
969 word_ptr += 3;
970 }
971
972 if ((control_word >> 22) & 1)
973 fprintf(fp, "unknown bit 22 enabled\n");
974
975 if ((control_word >> 23) & 1) {
976 print_scalar_field(fp, "smul", word_ptr, *beginning_ptr, consts, tabs);
977 beginning_ptr += 1;
978 word_ptr += 2;
979 }
980
981 if ((control_word >> 24) & 1)
982 fprintf(fp, "unknown bit 24 enabled\n");
983
984 if ((control_word >> 25) & 1) {
985 print_vector_field(fp, "lut", word_ptr, *beginning_ptr, consts, tabs);
986 word_ptr += 3;
987 }
988
989 if ((control_word >> 26) & 1) {
990 branch_forward |= print_compact_branch_writeout_field(fp, *word_ptr);
991 word_ptr += 1;
992 }
993
994 if ((control_word >> 27) & 1) {
995 branch_forward |= print_extended_branch_writeout_field(fp, (uint8_t *) word_ptr, next);
996 word_ptr += 3;
997 }
998
999 if (consts)
1000 fprintf(fp, "uconstants 0x%X, 0x%X, 0x%X, 0x%X\n",
1001 consts->u32[0], consts->u32[1],
1002 consts->u32[2], consts->u32[3]);
1003
1004 return branch_forward;
1005 }
1006
1007 static void
1008 print_varying_parameters(FILE *fp, midgard_load_store_word *word)
1009 {
1010 midgard_varying_parameter param;
1011 unsigned v = word->varying_parameters;
1012 memcpy(&param, &v, sizeof(param));
1013
1014 if (param.is_varying) {
1015 /* If a varying, there are qualifiers */
1016 if (param.flat)
1017 fprintf(fp, ".flat");
1018
1019 if (param.interpolation != midgard_interp_default) {
1020 if (param.interpolation == midgard_interp_centroid)
1021 fprintf(fp, ".centroid");
1022 else
1023 fprintf(fp, ".interp%d", param.interpolation);
1024 }
1025
1026 if (param.modifier != midgard_varying_mod_none) {
1027 if (param.modifier == midgard_varying_mod_perspective_w)
1028 fprintf(fp, ".perspectivew");
1029 else if (param.modifier == midgard_varying_mod_perspective_z)
1030 fprintf(fp, ".perspectivez");
1031 else
1032 fprintf(fp, ".mod%d", param.modifier);
1033 }
1034 } else if (param.flat || param.interpolation || param.modifier) {
1035 fprintf(fp, " /* is_varying not set but varying metadata attached */");
1036 }
1037
1038 if (param.zero0 || param.zero1 || param.zero2)
1039 fprintf(fp, " /* zero tripped, %u %u %u */ ", param.zero0, param.zero1, param.zero2);
1040 }
1041
1042 static bool
1043 is_op_varying(unsigned op)
1044 {
1045 switch (op) {
1046 case midgard_op_st_vary_16:
1047 case midgard_op_st_vary_32:
1048 case midgard_op_st_vary_32i:
1049 case midgard_op_st_vary_32u:
1050 case midgard_op_ld_vary_16:
1051 case midgard_op_ld_vary_32:
1052 case midgard_op_ld_vary_32i:
1053 case midgard_op_ld_vary_32u:
1054 return true;
1055 }
1056
1057 return false;
1058 }
1059
1060 static bool
1061 is_op_attribute(unsigned op)
1062 {
1063 switch (op) {
1064 case midgard_op_ld_attr_16:
1065 case midgard_op_ld_attr_32:
1066 case midgard_op_ld_attr_32i:
1067 case midgard_op_ld_attr_32u:
1068 return true;
1069 }
1070
1071 return false;
1072 }
1073
1074 static void
1075 print_load_store_arg(FILE *fp, uint8_t arg, unsigned index)
1076 {
1077 /* Try to interpret as a register */
1078 midgard_ldst_register_select sel;
1079 memcpy(&sel, &arg, sizeof(arg));
1080
1081 /* If unknown is set, we're not sure what this is or how to
1082 * interpret it. But if it's zero, we get it. */
1083
1084 if (sel.unknown) {
1085 fprintf(fp, "0x%02X", arg);
1086 return;
1087 }
1088
1089 unsigned reg = REGISTER_LDST_BASE + sel.select;
1090 char comp = components[sel.component];
1091
1092 fprintf(fp, "r%u.%c", reg, comp);
1093
1094 /* Only print a shift if it's non-zero. Shifts only make sense for the
1095 * second index. For the first, we're not sure what it means yet */
1096
1097 if (index == 1) {
1098 if (sel.shift)
1099 fprintf(fp, " << %u", sel.shift);
1100 } else {
1101 fprintf(fp, " /* %X */", sel.shift);
1102 }
1103 }
1104
1105 static void
1106 update_stats(signed *stat, unsigned address)
1107 {
1108 if (*stat >= 0)
1109 *stat = MAX2(*stat, address + 1);
1110 }
1111
1112 static void
1113 print_load_store_instr(FILE *fp, uint64_t data,
1114 unsigned tabs)
1115 {
1116 midgard_load_store_word *word = (midgard_load_store_word *) &data;
1117
1118 print_ld_st_opcode(fp, word->op);
1119
1120 unsigned address = word->address;
1121
1122 if (is_op_varying(word->op)) {
1123 print_varying_parameters(fp, word);
1124
1125 /* Do some analysis: check if direct cacess */
1126
1127 if ((word->arg_2 == 0x1E) && midg_stats.varying_count >= 0)
1128 update_stats(&midg_stats.varying_count, address);
1129 else
1130 midg_stats.varying_count = -16;
1131 } else if (is_op_attribute(word->op)) {
1132 if ((word->arg_2 == 0x1E) && midg_stats.attribute_count >= 0)
1133 update_stats(&midg_stats.attribute_count, address);
1134 else
1135 midg_stats.attribute_count = -16;
1136 }
1137
1138 fprintf(fp, " r%u", word->reg + (OP_IS_STORE(word->op) ? 26 : 0));
1139 print_mask_4(fp, word->mask, false);
1140
1141 if (!OP_IS_STORE(word->op))
1142 update_dest(word->reg);
1143
1144 bool is_ubo = OP_IS_UBO_READ(word->op);
1145
1146 if (is_ubo) {
1147 /* UBOs use their own addressing scheme */
1148
1149 int lo = word->varying_parameters >> 7;
1150 int hi = word->address;
1151
1152 /* TODO: Combine fields logically */
1153 address = (hi << 3) | lo;
1154 }
1155
1156 fprintf(fp, ", %u", address);
1157
1158 print_swizzle_vec4(fp, word->swizzle, false, false, false);
1159
1160 fprintf(fp, ", ");
1161
1162 if (is_ubo) {
1163 fprintf(fp, "ubo%u", word->arg_1);
1164 update_stats(&midg_stats.uniform_buffer_count, word->arg_1);
1165 } else
1166 print_load_store_arg(fp, word->arg_1, 0);
1167
1168 fprintf(fp, ", ");
1169 print_load_store_arg(fp, word->arg_2, 1);
1170 fprintf(fp, " /* %X */\n", word->varying_parameters);
1171
1172 midg_stats.instruction_count++;
1173 }
1174
1175 static void
1176 print_load_store_word(FILE *fp, uint32_t *word, unsigned tabs)
1177 {
1178 midgard_load_store *load_store = (midgard_load_store *) word;
1179
1180 if (load_store->word1 != 3) {
1181 print_load_store_instr(fp, load_store->word1, tabs);
1182 }
1183
1184 if (load_store->word2 != 3) {
1185 print_load_store_instr(fp, load_store->word2, tabs);
1186 }
1187 }
1188
1189 static void
1190 print_texture_reg_select(FILE *fp, uint8_t u, unsigned base)
1191 {
1192 midgard_tex_register_select sel;
1193 memcpy(&sel, &u, sizeof(u));
1194
1195 if (!sel.full)
1196 fprintf(fp, "h");
1197
1198 fprintf(fp, "r%u", base + sel.select);
1199
1200 unsigned component = sel.component;
1201
1202 /* Use the upper half in half-reg mode */
1203 if (sel.upper) {
1204 assert(!sel.full);
1205 component += 4;
1206 }
1207
1208 fprintf(fp, ".%c", components[component]);
1209
1210 assert(sel.zero == 0);
1211 }
1212
1213 static void
1214 print_texture_format(FILE *fp, int format)
1215 {
1216 /* Act like a modifier */
1217 fprintf(fp, ".");
1218
1219 switch (format) {
1220 DEFINE_CASE(MALI_TEX_1D, "1d");
1221 DEFINE_CASE(MALI_TEX_2D, "2d");
1222 DEFINE_CASE(MALI_TEX_3D, "3d");
1223 DEFINE_CASE(MALI_TEX_CUBE, "cube");
1224
1225 default:
1226 unreachable("Bad format");
1227 }
1228 }
1229
1230 static bool
1231 midgard_op_has_helpers(unsigned op, bool gather)
1232 {
1233 if (gather)
1234 return true;
1235
1236 switch (op) {
1237 case TEXTURE_OP_NORMAL:
1238 case TEXTURE_OP_DFDX:
1239 case TEXTURE_OP_DFDY:
1240 return true;
1241 default:
1242 return false;
1243 }
1244 }
1245
1246 static void
1247 print_texture_op(FILE *fp, unsigned op, bool gather)
1248 {
1249 /* Act like a bare name, like ESSL functions */
1250
1251 if (gather) {
1252 fprintf(fp, "textureGather");
1253
1254 unsigned component = op >> 4;
1255 unsigned bottom = op & 0xF;
1256
1257 if (bottom != 0x2)
1258 fprintf(fp, "_unk%u", bottom);
1259
1260 fprintf(fp, ".%c", components[component]);
1261 return;
1262 }
1263
1264 switch (op) {
1265 DEFINE_CASE(TEXTURE_OP_NORMAL, "texture");
1266 DEFINE_CASE(TEXTURE_OP_LOD, "textureLod");
1267 DEFINE_CASE(TEXTURE_OP_TEXEL_FETCH, "texelFetch");
1268 DEFINE_CASE(TEXTURE_OP_BARRIER, "barrier");
1269 DEFINE_CASE(TEXTURE_OP_DFDX, "dFdx");
1270 DEFINE_CASE(TEXTURE_OP_DFDY, "dFdy");
1271
1272 default:
1273 fprintf(fp, "tex_%X", op);
1274 break;
1275 }
1276 }
1277
1278 static bool
1279 texture_op_takes_bias(unsigned op)
1280 {
1281 return op == TEXTURE_OP_NORMAL;
1282 }
1283
1284 static char
1285 sampler_type_name(enum mali_sampler_type t)
1286 {
1287 switch (t) {
1288 case MALI_SAMPLER_FLOAT:
1289 return 'f';
1290 case MALI_SAMPLER_UNSIGNED:
1291 return 'u';
1292 case MALI_SAMPLER_SIGNED:
1293 return 'i';
1294 default:
1295 return '?';
1296 }
1297
1298 }
1299
1300 static void
1301 print_texture_barrier(FILE *fp, uint32_t *word)
1302 {
1303 midgard_texture_barrier_word *barrier = (midgard_texture_barrier_word *) word;
1304
1305 if (barrier->type != TAG_TEXTURE_4_BARRIER)
1306 fprintf(fp, "/* barrier tag %X != tex/bar */ ", barrier->type);
1307
1308 if (!barrier->cont)
1309 fprintf(fp, "/* cont missing? */");
1310
1311 if (!barrier->last)
1312 fprintf(fp, "/* last missing? */");
1313
1314 if (barrier->zero1)
1315 fprintf(fp, "/* zero1 = 0x%X */ ", barrier->zero1);
1316
1317 if (barrier->zero2)
1318 fprintf(fp, "/* zero2 = 0x%X */ ", barrier->zero2);
1319
1320 if (barrier->zero3)
1321 fprintf(fp, "/* zero3 = 0x%X */ ", barrier->zero3);
1322
1323 if (barrier->zero4)
1324 fprintf(fp, "/* zero4 = 0x%X */ ", barrier->zero4);
1325
1326 if (barrier->zero5)
1327 fprintf(fp, "/* zero4 = 0x%" PRIx64 " */ ", barrier->zero5);
1328
1329
1330 /* Control barriers are always implied, so include for obviousness */
1331 fprintf(fp, " control");
1332
1333 if (barrier->buffer)
1334 fprintf(fp, " | buffer");
1335
1336 if (barrier->shared)
1337 fprintf(fp, " | shared");
1338
1339 if (barrier->stack)
1340 fprintf(fp, " | stack");
1341
1342 fprintf(fp, "\n");
1343 }
1344
1345 #undef DEFINE_CASE
1346
1347 static void
1348 print_texture_word(FILE *fp, uint32_t *word, unsigned tabs, unsigned in_reg_base, unsigned out_reg_base)
1349 {
1350 midgard_texture_word *texture = (midgard_texture_word *) word;
1351
1352 midg_stats.helper_invocations |=
1353 midgard_op_has_helpers(texture->op, texture->is_gather);
1354
1355 /* Broad category of texture operation in question */
1356 print_texture_op(fp, texture->op, texture->is_gather);
1357
1358 /* Barriers use a dramatically different code path */
1359 if (texture->op == TEXTURE_OP_BARRIER) {
1360 print_texture_barrier(fp, word);
1361 return;
1362 } else if (texture->type == TAG_TEXTURE_4_BARRIER)
1363 fprintf (fp, "/* nonbarrier had tex/bar tag */ ");
1364 else if (texture->type == TAG_TEXTURE_4_VTX)
1365 fprintf (fp, ".vtx");
1366
1367 /* Specific format in question */
1368 print_texture_format(fp, texture->format);
1369
1370 /* Instruction "modifiers" parallel the ALU instructions. */
1371
1372 if (texture->shadow)
1373 fprintf(fp, ".shadow");
1374
1375 if (texture->cont)
1376 fprintf(fp, ".cont");
1377
1378 if (texture->last)
1379 fprintf(fp, ".last");
1380
1381 if (texture->barrier_buffer)
1382 fprintf(fp, ".barrier_buffer /* XXX */");
1383
1384 if (texture->barrier_shared)
1385 fprintf(fp, ".barrier_shared /* XXX */");
1386
1387 /* Output modifiers are always interpreted floatly */
1388 print_outmod(fp, texture->outmod, false);
1389
1390 fprintf(fp, " %sr%u", texture->out_full ? "" : "h",
1391 out_reg_base + texture->out_reg_select);
1392 print_mask_4(fp, texture->mask, texture->out_upper);
1393 assert(!(texture->out_full && texture->out_upper));
1394 fprintf(fp, ", ");
1395
1396 /* Depending on whether we read from textures directly or indirectly,
1397 * we may be able to update our analysis */
1398
1399 if (texture->texture_register) {
1400 fprintf(fp, "texture[");
1401 print_texture_reg_select(fp, texture->texture_handle, in_reg_base);
1402 fprintf(fp, "], ");
1403
1404 /* Indirect, tut tut */
1405 midg_stats.texture_count = -16;
1406 } else {
1407 fprintf(fp, "texture%u, ", texture->texture_handle);
1408 update_stats(&midg_stats.texture_count, texture->texture_handle);
1409 }
1410
1411 /* Print the type, GL style */
1412 fprintf(fp, "%csampler", sampler_type_name(texture->sampler_type));
1413
1414 if (texture->sampler_register) {
1415 fprintf(fp, "[");
1416 print_texture_reg_select(fp, texture->sampler_handle, in_reg_base);
1417 fprintf(fp, "]");
1418
1419 midg_stats.sampler_count = -16;
1420 } else {
1421 fprintf(fp, "%u", texture->sampler_handle);
1422 update_stats(&midg_stats.sampler_count, texture->sampler_handle);
1423 }
1424
1425 print_swizzle_vec4(fp, texture->swizzle, false, false, false);
1426 fprintf(fp, ", %sr%u", texture->in_reg_full ? "" : "h", in_reg_base + texture->in_reg_select);
1427 assert(!(texture->in_reg_full && texture->in_reg_upper));
1428
1429 /* TODO: integrate with swizzle */
1430 if (texture->in_reg_upper)
1431 fprintf(fp, "'");
1432
1433 print_swizzle_vec4(fp, texture->in_reg_swizzle, false, false, false);
1434
1435 /* There is *always* an offset attached. Of
1436 * course, that offset is just immediate #0 for a
1437 * GLES call that doesn't take an offset. If there
1438 * is a non-negative non-zero offset, this is
1439 * specified in immediate offset mode, with the
1440 * values in the offset_* fields as immediates. If
1441 * this is a negative offset, we instead switch to
1442 * a register offset mode, where the offset_*
1443 * fields become register triplets */
1444
1445 if (texture->offset_register) {
1446 fprintf(fp, " + ");
1447
1448 bool full = texture->offset & 1;
1449 bool select = texture->offset & 2;
1450 bool upper = texture->offset & 4;
1451
1452 fprintf(fp, "%sr%u", full ? "" : "h", in_reg_base + select);
1453 assert(!(texture->out_full && texture->out_upper));
1454
1455 /* TODO: integrate with swizzle */
1456 if (upper)
1457 fprintf(fp, "'");
1458
1459 print_swizzle_vec4(fp, texture->offset >> 3, false, false, false);
1460
1461 fprintf(fp, ", ");
1462 } else if (texture->offset) {
1463 /* Only select ops allow negative immediate offsets, verify */
1464
1465 signed offset_x = (texture->offset & 0xF);
1466 signed offset_y = ((texture->offset >> 4) & 0xF);
1467 signed offset_z = ((texture->offset >> 8) & 0xF);
1468
1469 bool neg_x = offset_x < 0;
1470 bool neg_y = offset_y < 0;
1471 bool neg_z = offset_z < 0;
1472 bool any_neg = neg_x || neg_y || neg_z;
1473
1474 if (any_neg && texture->op != TEXTURE_OP_TEXEL_FETCH)
1475 fprintf(fp, "/* invalid negative */ ");
1476
1477 /* Regardless, just print the immediate offset */
1478
1479 fprintf(fp, " + <%d, %d, %d>, ", offset_x, offset_y, offset_z);
1480 } else {
1481 fprintf(fp, ", ");
1482 }
1483
1484 char lod_operand = texture_op_takes_bias(texture->op) ? '+' : '=';
1485
1486 if (texture->lod_register) {
1487 fprintf(fp, "lod %c ", lod_operand);
1488 print_texture_reg_select(fp, texture->bias, in_reg_base);
1489 fprintf(fp, ", ");
1490
1491 if (texture->bias_int)
1492 fprintf(fp, " /* bias_int = 0x%X */", texture->bias_int);
1493 } else if (texture->op == TEXTURE_OP_TEXEL_FETCH) {
1494 /* For texel fetch, the int LOD is in the fractional place and
1495 * there is no fraction / possibility of bias. We *always* have
1496 * an explicit LOD, even if it's zero. */
1497
1498 if (texture->bias_int)
1499 fprintf(fp, " /* bias_int = 0x%X */ ", texture->bias_int);
1500
1501 fprintf(fp, "lod = %u, ", texture->bias);
1502 } else if (texture->bias || texture->bias_int) {
1503 signed bias_int = texture->bias_int;
1504 float bias_frac = texture->bias / 256.0f;
1505 float bias = bias_int + bias_frac;
1506
1507 bool is_bias = texture_op_takes_bias(texture->op);
1508 char sign = (bias >= 0.0) ? '+' : '-';
1509 char operand = is_bias ? sign : '=';
1510
1511 fprintf(fp, "lod %c %f, ", operand, fabsf(bias));
1512 }
1513
1514 fprintf(fp, "\n");
1515
1516 /* While not zero in general, for these simple instructions the
1517 * following unknowns are zero, so we don't include them */
1518
1519 if (texture->unknown4 ||
1520 texture->unknown8) {
1521 fprintf(fp, "// unknown4 = 0x%x\n", texture->unknown4);
1522 fprintf(fp, "// unknown8 = 0x%x\n", texture->unknown8);
1523 }
1524
1525 midg_stats.instruction_count++;
1526 }
1527
1528 struct midgard_disasm_stats
1529 disassemble_midgard(FILE *fp, uint8_t *code, size_t size, unsigned gpu_id, gl_shader_stage stage)
1530 {
1531 uint32_t *words = (uint32_t *) code;
1532 unsigned num_words = size / 4;
1533 int tabs = 0;
1534
1535 bool branch_forward = false;
1536
1537 int last_next_tag = -1;
1538
1539 unsigned i = 0;
1540
1541 midg_tags = calloc(sizeof(midg_tags[0]), num_words);
1542
1543 /* Stats for shader-db */
1544 memset(&midg_stats, 0, sizeof(midg_stats));
1545 midg_ever_written = 0;
1546
1547 while (i < num_words) {
1548 unsigned tag = words[i] & 0xF;
1549 unsigned next_tag = (words[i] >> 4) & 0xF;
1550 unsigned num_quad_words = midgard_tag_props[tag].size;
1551
1552 if (midg_tags[i] && midg_tags[i] != tag) {
1553 fprintf(fp, "\t/* XXX: TAG ERROR branch, got %s expected %s */\n",
1554 midgard_tag_props[tag].name,
1555 midgard_tag_props[midg_tags[i]].name);
1556 }
1557
1558 midg_tags[i] = tag;
1559
1560 /* Check the tag. The idea is to ensure that next_tag is
1561 * *always* recoverable from the disassembly, such that we may
1562 * safely omit printing next_tag. To show this, we first
1563 * consider that next tags are semantically off-byone -- we end
1564 * up parsing tag n during step n+1. So, we ensure after we're
1565 * done disassembling the next tag of the final bundle is BREAK
1566 * and warn otherwise. We also ensure that the next tag is
1567 * never INVALID. Beyond that, since the last tag is checked
1568 * outside the loop, we can check one tag prior. If equal to
1569 * the current tag (which is unique), we're done. Otherwise, we
1570 * print if that tag was > TAG_BREAK, which implies the tag was
1571 * not TAG_BREAK or TAG_INVALID. But we already checked for
1572 * TAG_INVALID, so it's just if the last tag was TAG_BREAK that
1573 * we're silent. So we throw in a print for break-next on at
1574 * the end of the bundle (if it's not the final bundle, which
1575 * we already check for above), disambiguating this case as
1576 * well. Hence in all cases we are unambiguous, QED. */
1577
1578 if (next_tag == TAG_INVALID)
1579 fprintf(fp, "\t/* XXX: invalid next tag */\n");
1580
1581 if (last_next_tag > TAG_BREAK && last_next_tag != tag) {
1582 fprintf(fp, "\t/* XXX: TAG ERROR sequence, got %s expexted %s */\n",
1583 midgard_tag_props[tag].name,
1584 midgard_tag_props[last_next_tag].name);
1585 }
1586
1587 last_next_tag = next_tag;
1588
1589 /* Tags are unique in the following way:
1590 *
1591 * INVALID, BREAK, UNKNOWN_*: verbosely printed
1592 * TEXTURE_4_BARRIER: verified by barrier/!barrier op
1593 * TEXTURE_4_VTX: .vtx tag printed
1594 * TEXTURE_4: tetxure lack of barriers or .vtx
1595 * TAG_LOAD_STORE_4: only load/store
1596 * TAG_ALU_4/8/12/16: by number of instructions/constants
1597 * TAG_ALU_4_8/12/16_WRITEOUT: ^^ with .writeout tag
1598 */
1599
1600 switch (tag) {
1601 case TAG_TEXTURE_4_VTX ... TAG_TEXTURE_4_BARRIER: {
1602 bool interpipe_aliasing =
1603 midgard_get_quirks(gpu_id) & MIDGARD_INTERPIPE_REG_ALIASING;
1604
1605 print_texture_word(fp, &words[i], tabs,
1606 interpipe_aliasing ? 0 : REG_TEX_BASE,
1607 interpipe_aliasing ? REGISTER_LDST_BASE : REG_TEX_BASE);
1608 break;
1609 }
1610
1611 case TAG_LOAD_STORE_4:
1612 print_load_store_word(fp, &words[i], tabs);
1613 break;
1614
1615 case TAG_ALU_4 ... TAG_ALU_16_WRITEOUT:
1616 branch_forward = print_alu_word(fp, &words[i], num_quad_words, tabs, i + 4*num_quad_words);
1617
1618 /* Reset word static analysis state */
1619 is_embedded_constant_half = false;
1620 is_embedded_constant_int = false;
1621
1622 /* TODO: infer/verify me */
1623 if (tag >= TAG_ALU_4_WRITEOUT)
1624 fprintf(fp, "writeout\n");
1625
1626 break;
1627
1628 default:
1629 fprintf(fp, "Unknown word type %u:\n", words[i] & 0xF);
1630 num_quad_words = 1;
1631 print_quad_word(fp, &words[i], tabs);
1632 fprintf(fp, "\n");
1633 break;
1634 }
1635
1636 /* We are parsing per bundle anyway. Add before we start
1637 * breaking out so we don't miss the final bundle. */
1638
1639 midg_stats.bundle_count++;
1640 midg_stats.quadword_count += num_quad_words;
1641
1642 /* Include a synthetic "break" instruction at the end of the
1643 * bundle to signify that if, absent a branch, the shader
1644 * execution will stop here. Stop disassembly at such a break
1645 * based on a heuristic */
1646
1647 if (next_tag == TAG_BREAK) {
1648 if (branch_forward) {
1649 fprintf(fp, "break\n");
1650 } else {
1651 fprintf(fp, "\n");
1652 break;
1653 }
1654 }
1655
1656 fprintf(fp, "\n");
1657
1658 i += 4 * num_quad_words;
1659 }
1660
1661 if (last_next_tag != TAG_BREAK) {
1662 fprintf(fp, "/* XXX: shader ended with tag %s */\n",
1663 midgard_tag_props[last_next_tag].name);
1664 }
1665
1666 free(midg_tags);
1667
1668 /* We computed work_count as max_work_registers, so add one to get the
1669 * count. If no work registers are written, you still have one work
1670 * reported, which is exactly what the hardware expects */
1671
1672 midg_stats.work_count++;
1673
1674 return midg_stats;
1675 }