5 * Copyright (c) 2013 Connor Abbott (connor@abbott.cx)
6 * Copyright (c) 2018 Alyssa Rosenzweig (alyssa@rosenzweig.io)
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
35 #include "midgard_ops.h"
36 #include "midgard_quirks.h"
37 #include "disassemble.h"
39 #include "util/bitscan.h"
40 #include "util/half_float.h"
41 #include "util/u_math.h"
43 #define DEFINE_CASE(define, str) case define: { fprintf(fp, str); break; }
45 static unsigned *midg_tags
;
46 static bool is_instruction_int
= false;
50 static struct midgard_disasm_stats midg_stats
;
52 /* Prints a short form of the tag for branching, the minimum needed to be
53 * legible and unambiguous */
56 print_tag_short(FILE *fp
, unsigned tag
)
58 switch (midgard_word_types
[tag
]) {
59 case midgard_word_type_texture
:
60 fprintf(fp
, "tex/%X", tag
);
63 case midgard_word_type_load_store
:
67 case midgard_word_type_alu
:
68 fprintf(fp
, "alu%u/%X", midgard_word_size
[tag
], tag
);
72 fprintf(fp
, "%s%X", (tag
> 0) ? "" : "unk", tag
);
78 print_alu_opcode(FILE *fp
, midgard_alu_op op
)
82 if (alu_opcode_props
[op
].name
) {
83 fprintf(fp
, "%s", alu_opcode_props
[op
].name
);
85 int_op
= midgard_is_integer_op(op
);
87 fprintf(fp
, "alu_op_%02X", op
);
89 /* For constant analysis */
90 is_instruction_int
= int_op
;
94 print_ld_st_opcode(FILE *fp
, midgard_load_store_op op
)
96 if (load_store_opcode_props
[op
].name
)
97 fprintf(fp
, "%s", load_store_opcode_props
[op
].name
);
99 fprintf(fp
, "ldst_op_%02X", op
);
102 static bool is_embedded_constant_half
= false;
103 static bool is_embedded_constant_int
= false;
106 prefix_for_bits(unsigned bits
)
120 /* For static analysis to ensure all registers are written at least once before
121 * use along the source code path (TODO: does this break done for complex CF?)
124 uint16_t midg_ever_written
= 0;
127 print_reg(FILE *fp
, unsigned reg
, unsigned bits
)
129 /* Perform basic static analysis for expanding constants correctly */
132 is_embedded_constant_int
= is_instruction_int
;
133 is_embedded_constant_half
= (bits
< 32);
136 unsigned uniform_reg
= 23 - reg
;
137 bool is_uniform
= false;
139 /* For r8-r15, it could be a work or uniform. We distinguish based on
140 * the fact work registers are ALWAYS written before use, but uniform
141 * registers are NEVER written before use. */
143 if ((reg
>= 8 && reg
< 16) && !(midg_ever_written
& (1 << reg
)))
146 /* r16-r23 are always uniform */
148 if (reg
>= 16 && reg
<= 23)
151 /* Update the uniform count appropriately */
154 midg_stats
.uniform_count
=
155 MAX2(uniform_reg
+ 1, midg_stats
.uniform_count
);
157 char prefix
= prefix_for_bits(bits
);
162 fprintf(fp
, "r%u", reg
);
165 static char *outmod_names_float
[4] = {
172 static char *outmod_names_int
[4] = {
179 static char *srcmod_names_int
[4] = {
187 print_outmod(FILE *fp
, unsigned outmod
, bool is_int
)
189 fprintf(fp
, "%s", is_int
? outmod_names_int
[outmod
] :
190 outmod_names_float
[outmod
]);
194 print_quad_word(FILE *fp
, uint32_t *words
, unsigned tabs
)
198 for (i
= 0; i
< 4; i
++)
199 fprintf(fp
, "0x%08X%s ", words
[i
], i
== 3 ? "" : ",");
204 static const char components
[16] = "xyzwefghijklmnop";
206 /* Helper to print 4 chars of a swizzle */
208 print_swizzle_helper(FILE *fp
, unsigned swizzle
, unsigned offset
)
210 for (unsigned i
= 0; i
< 4; ++i
) {
211 unsigned c
= (swizzle
>> (i
* 2)) & 3;
213 fprintf(fp
, "%c", components
[c
]);
217 /* Helper to print 8 chars of a swizzle, duplicating over */
219 print_swizzle_helper_8(FILE *fp
, unsigned swizzle
, bool upper
)
221 for (unsigned i
= 0; i
< 4; ++i
) {
222 unsigned c
= (swizzle
>> (i
* 2)) & 3;
225 fprintf(fp
, "%c%c", components
[c
], components
[c
+1]);
230 print_swizzle_vec16(FILE *fp
, unsigned swizzle
, bool rep_high
, bool rep_low
,
231 midgard_dest_override override
)
235 if (override
== midgard_dest_override_upper
) {
237 fprintf(fp
, " /* rep_high */ ");
239 fprintf(fp
, " /* rep_low */ ");
241 if (!rep_high
&& rep_low
)
242 print_swizzle_helper_8(fp
, swizzle
, true);
244 print_swizzle_helper_8(fp
, swizzle
, false);
246 print_swizzle_helper_8(fp
, swizzle
, rep_high
& 1);
247 print_swizzle_helper_8(fp
, swizzle
, !(rep_low
& 1));
252 print_swizzle_vec8(FILE *fp
, unsigned swizzle
, bool rep_high
, bool rep_low
, bool half
)
256 /* TODO: Is it possible to unify half/full? */
259 print_swizzle_helper(fp
, swizzle
, (rep_low
* 8));
260 print_swizzle_helper(fp
, swizzle
, (rep_low
* 8) + !rep_high
* 4);
262 print_swizzle_helper(fp
, swizzle
, rep_high
* 4);
263 print_swizzle_helper(fp
, swizzle
, !rep_low
* 4);
268 print_swizzle_vec4(FILE *fp
, unsigned swizzle
, bool rep_high
, bool rep_low
, bool half
)
271 fprintf(fp
, " /* rep_high */ ");
273 if (!half
&& rep_low
)
274 fprintf(fp
, " /* rep_low */ ");
276 if (swizzle
== 0xE4 && !half
) return; /* xyzw */
279 print_swizzle_helper(fp
, swizzle
, rep_low
* 4);
282 print_swizzle_vec2(FILE *fp
, unsigned swizzle
, bool rep_high
, bool rep_low
, bool half
)
284 char *alphabet
= "XY";
287 alphabet
= rep_low
? "zw" : "xy";
289 fprintf(fp
, " /* rep_low */ ");
292 fprintf(fp
, " /* rep_high */ ");
294 if (swizzle
== 0xE4 && !half
) return; /* XY */
298 for (unsigned i
= 0; i
< 4; i
+= 2) {
299 unsigned a
= (swizzle
>> (i
* 2)) & 3;
300 unsigned b
= (swizzle
>> ((i
+1) * 2)) & 3;
302 /* Normally we're adjacent, but if there's an issue, don't make
306 fprintf(fp
, "%c", alphabet
[a
>> 1]);
308 fprintf(fp
, "[%c%c]", components
[a
], components
[b
]);
313 bits_for_mode(midgard_reg_mode mode
)
316 case midgard_reg_mode_8
:
318 case midgard_reg_mode_16
:
320 case midgard_reg_mode_32
:
322 case midgard_reg_mode_64
:
325 unreachable("Invalid reg mode");
331 bits_for_mode_halved(midgard_reg_mode mode
, bool half
)
333 unsigned bits
= bits_for_mode(mode
);
342 print_scalar_constant(FILE *fp
, unsigned src_binary
,
343 const midgard_constants
*consts
,
344 midgard_scalar_alu
*alu
)
346 midgard_scalar_alu_src
*src
= (midgard_scalar_alu_src
*)&src_binary
;
349 assert(consts
!= NULL
);
351 if (!midgard_is_integer_op(alu
->op
)) {
353 mod
|= MIDGARD_FLOAT_MOD_ABS
;
355 mod
|= MIDGARD_FLOAT_MOD_NEG
;
357 mod
= midgard_int_normal
;
361 mir_print_constant_component(fp
, consts
, src
->component
,
363 midgard_reg_mode_32
: midgard_reg_mode_16
,
364 false, mod
, alu
->op
);
368 print_vector_constants(FILE *fp
, unsigned src_binary
,
369 const midgard_constants
*consts
,
370 midgard_vector_alu
*alu
)
372 midgard_vector_alu_src
*src
= (midgard_vector_alu_src
*)&src_binary
;
373 unsigned bits
= bits_for_mode_halved(alu
->reg_mode
, src
->half
);
374 unsigned max_comp
= MIN2((sizeof(*consts
) * 8) / bits
, 8);
375 unsigned comp_mask
, num_comp
= 0;
379 comp_mask
= effective_writemask(alu
, condense_writemask(alu
->mask
, bits
));
380 num_comp
= util_bitcount(comp_mask
);
384 fprintf(fp
, "vec%d(", num_comp
);
388 for (unsigned i
= 0; i
< max_comp
; ++i
) {
389 if (!(comp_mask
& (1 << i
))) continue;
391 unsigned c
= (src
->swizzle
>> (i
* 2)) & 3;
398 mir_print_constant_component(fp
, consts
, c
, alu
->reg_mode
,
399 src
->half
, src
->mod
, alu
->op
);
407 print_vector_src(FILE *fp
, unsigned src_binary
,
408 midgard_reg_mode mode
, unsigned reg
,
409 midgard_dest_override override
, bool is_int
)
411 midgard_vector_alu_src
*src
= (midgard_vector_alu_src
*)&src_binary
;
413 /* Modifiers change meaning depending on the op's context */
415 midgard_int_mod int_mod
= src
->mod
;
418 fprintf(fp
, "%s", srcmod_names_int
[int_mod
]);
420 if (src
->mod
& MIDGARD_FLOAT_MOD_NEG
)
423 if (src
->mod
& MIDGARD_FLOAT_MOD_ABS
)
428 unsigned bits
= bits_for_mode_halved(mode
, src
->half
);
429 print_reg(fp
, reg
, bits
);
431 /* When the source was stepped down via `half`, rep_low means "higher
432 * half" and rep_high is never seen. When it's not native,
433 * rep_low/rep_high are for, well, replication */
435 if (mode
== midgard_reg_mode_8
) {
437 print_swizzle_vec16(fp
, src
->swizzle
, src
->rep_high
, src
->rep_low
, override
);
438 } else if (mode
== midgard_reg_mode_16
) {
439 print_swizzle_vec8(fp
, src
->swizzle
, src
->rep_high
, src
->rep_low
, src
->half
);
440 } else if (mode
== midgard_reg_mode_32
) {
441 print_swizzle_vec4(fp
, src
->swizzle
, src
->rep_high
, src
->rep_low
, src
->half
);
442 } else if (mode
== midgard_reg_mode_64
) {
443 print_swizzle_vec2(fp
, src
->swizzle
, src
->rep_high
, src
->rep_low
, src
->half
);
446 /* Since we wrapped with a function-looking thing */
448 if (is_int
&& int_mod
== midgard_int_shift
)
449 fprintf(fp
, ") << %u", bits
);
450 else if ((is_int
&& (int_mod
!= midgard_int_normal
))
451 || (!is_int
&& src
->mod
& MIDGARD_FLOAT_MOD_ABS
))
456 decode_vector_imm(unsigned src2_reg
, unsigned imm
)
459 ret
= src2_reg
<< 11;
460 ret
|= (imm
& 0x7) << 8;
461 ret
|= (imm
>> 3) & 0xFF;
466 print_immediate(FILE *fp
, uint16_t imm
)
468 if (is_instruction_int
)
469 fprintf(fp
, "#%u", imm
);
471 fprintf(fp
, "#%g", _mesa_half_to_float(imm
));
475 update_dest(unsigned reg
)
477 /* We should record writes as marking this as a work register. Store
478 * the max register in work_count; we'll add one at the end */
481 midg_stats
.work_count
= MAX2(reg
, midg_stats
.work_count
);
482 midg_ever_written
|= (1 << reg
);
487 print_dest(FILE *fp
, unsigned reg
, midgard_reg_mode mode
, midgard_dest_override override
)
489 /* Depending on the mode and override, we determine the type of
490 * destination addressed. Absent an override, we address just the
491 * type of the operation itself */
493 unsigned bits
= bits_for_mode(mode
);
495 if (override
!= midgard_dest_override_none
)
499 print_reg(fp
, reg
, bits
);
503 print_mask_vec16(FILE *fp
, uint8_t mask
, midgard_dest_override override
)
507 for (unsigned i
= 0; i
< 8; i
++) {
511 components
[i
*2 + 1]);
515 /* For 16-bit+ masks, we read off from the 8-bit mask field. For 16-bit (vec8),
516 * it's just one bit per channel, easy peasy. For 32-bit (vec4), it's one bit
517 * per channel with one duplicate bit in the middle. For 64-bit (vec2), it's
518 * one-bit per channel with _3_ duplicate bits in the middle. Basically, just
519 * subdividing the 128-bit word in 16-bit increments. For 64-bit, we uppercase
520 * the mask to make it obvious what happened */
523 print_mask(FILE *fp
, uint8_t mask
, unsigned bits
, midgard_dest_override override
)
526 print_mask_vec16(fp
, mask
, override
);
530 /* Skip 'complete' masks */
532 if (override
== midgard_dest_override_none
)
533 if (bits
>= 32 && mask
== 0xFF) return;
537 unsigned skip
= (bits
/ 16);
538 bool uppercase
= bits
> 32;
539 bool tripped
= false;
541 /* To apply an upper destination override, we "shift" the alphabet.
542 * E.g. with an upper override on 32-bit, instead of xyzw, print efgh.
543 * For upper 16-bit, instead of xyzwefgh, print ijklmnop */
545 const char *alphabet
= components
;
547 if (override
== midgard_dest_override_upper
)
548 alphabet
+= (128 / bits
);
550 for (unsigned i
= 0; i
< 8; i
+= skip
) {
551 bool a
= (mask
& (1 << i
)) != 0;
553 for (unsigned j
= 1; j
< skip
; ++j
) {
554 bool dupe
= (mask
& (1 << (i
+ j
))) != 0;
555 tripped
|= (dupe
!= a
);
559 char c
= alphabet
[i
/ skip
];
564 fprintf(fp
, "%c", c
);
569 fprintf(fp
, " /* %X */", mask
);
572 /* Prints the 4-bit masks found in texture and load/store ops, as opposed to
573 * the 8-bit masks found in (vector) ALU ops. Supports texture-style 16-bit
574 * mode as well, but not load/store-style 16-bit mode. */
577 print_mask_4(FILE *fp
, unsigned mask
, bool upper
)
588 for (unsigned i
= 0; i
< 4; ++i
) {
589 bool a
= (mask
& (1 << i
)) != 0;
591 fprintf(fp
, "%c", components
[i
+ (upper
? 4 : 0)]);
596 print_vector_field(FILE *fp
, const char *name
, uint16_t *words
, uint16_t reg_word
,
597 const midgard_constants
*consts
, unsigned tabs
)
599 midgard_reg_info
*reg_info
= (midgard_reg_info
*)®_word
;
600 midgard_vector_alu
*alu_field
= (midgard_vector_alu
*) words
;
601 midgard_reg_mode mode
= alu_field
->reg_mode
;
602 unsigned override
= alu_field
->dest_override
;
604 /* For now, prefix instruction names with their unit, until we
605 * understand how this works on a deeper level */
606 fprintf(fp
, "%s.", name
);
608 print_alu_opcode(fp
, alu_field
->op
);
610 /* Postfix with the size to disambiguate if necessary */
611 char postfix
= prefix_for_bits(bits_for_mode(mode
));
612 bool size_ambiguous
= override
!= midgard_dest_override_none
;
615 fprintf(fp
, "%c", postfix
? postfix
: 'r');
617 /* Print the outmod, if there is one */
618 print_outmod(fp
, alu_field
->outmod
,
619 midgard_is_integer_out_op(alu_field
->op
));
623 /* Mask denoting status of 8-lanes */
624 uint8_t mask
= alu_field
->mask
;
626 /* First, print the destination */
627 print_dest(fp
, reg_info
->out_reg
, mode
, alu_field
->dest_override
);
629 if (override
!= midgard_dest_override_none
) {
630 bool modeable
= (mode
!= midgard_reg_mode_8
);
631 bool known
= override
!= 0x3; /* Unused value */
633 if (!(modeable
&& known
))
634 fprintf(fp
, "/* do%u */ ", override
);
637 print_mask(fp
, mask
, bits_for_mode(mode
), override
);
641 bool is_int
= midgard_is_integer_op(alu_field
->op
);
643 if (reg_info
->src1_reg
== 26)
644 print_vector_constants(fp
, alu_field
->src1
, consts
, alu_field
);
646 print_vector_src(fp
, alu_field
->src1
, mode
, reg_info
->src1_reg
, override
, is_int
);
650 if (reg_info
->src2_imm
) {
651 uint16_t imm
= decode_vector_imm(reg_info
->src2_reg
, alu_field
->src2
>> 2);
652 print_immediate(fp
, imm
);
653 } else if (reg_info
->src2_reg
== 26) {
654 print_vector_constants(fp
, alu_field
->src2
, consts
, alu_field
);
656 print_vector_src(fp
, alu_field
->src2
, mode
,
657 reg_info
->src2_reg
, override
, is_int
);
660 midg_stats
.instruction_count
++;
665 print_scalar_src(FILE *fp
, unsigned src_binary
, unsigned reg
)
667 midgard_scalar_alu_src
*src
= (midgard_scalar_alu_src
*)&src_binary
;
675 print_reg(fp
, reg
, src
->full
? 32 : 16);
677 unsigned c
= src
->component
;
680 assert((c
& 1) == 0);
684 fprintf(fp
, ".%c", components
[c
]);
692 decode_scalar_imm(unsigned src2_reg
, unsigned imm
)
695 ret
= src2_reg
<< 11;
696 ret
|= (imm
& 3) << 9;
697 ret
|= (imm
& 4) << 6;
698 ret
|= (imm
& 0x38) << 2;
704 print_scalar_field(FILE *fp
, const char *name
, uint16_t *words
, uint16_t reg_word
,
705 const midgard_constants
*consts
, unsigned tabs
)
707 midgard_reg_info
*reg_info
= (midgard_reg_info
*)®_word
;
708 midgard_scalar_alu
*alu_field
= (midgard_scalar_alu
*) words
;
710 if (alu_field
->unknown
)
711 fprintf(fp
, "scalar ALU unknown bit set\n");
713 fprintf(fp
, "%s.", name
);
714 print_alu_opcode(fp
, alu_field
->op
);
715 print_outmod(fp
, alu_field
->outmod
,
716 midgard_is_integer_out_op(alu_field
->op
));
719 bool full
= alu_field
->output_full
;
720 update_dest(reg_info
->out_reg
);
721 print_reg(fp
, reg_info
->out_reg
, full
? 32 : 16);
722 unsigned c
= alu_field
->output_component
;
725 assert((c
& 1) == 0);
729 fprintf(fp
, ".%c, ", components
[c
]);
731 if (reg_info
->src1_reg
== 26)
732 print_scalar_constant(fp
, alu_field
->src1
, consts
, alu_field
);
734 print_scalar_src(fp
, alu_field
->src1
, reg_info
->src1_reg
);
738 if (reg_info
->src2_imm
) {
739 uint16_t imm
= decode_scalar_imm(reg_info
->src2_reg
,
741 print_immediate(fp
, imm
);
742 } else if (reg_info
->src2_reg
== 26) {
743 print_scalar_constant(fp
, alu_field
->src2
, consts
, alu_field
);
745 print_scalar_src(fp
, alu_field
->src2
, reg_info
->src2_reg
);
747 midg_stats
.instruction_count
++;
752 print_branch_op(FILE *fp
, unsigned op
)
755 case midgard_jmp_writeout_op_branch_uncond
:
756 fprintf(fp
, "uncond.");
759 case midgard_jmp_writeout_op_branch_cond
:
760 fprintf(fp
, "cond.");
763 case midgard_jmp_writeout_op_writeout
:
764 fprintf(fp
, "write.");
767 case midgard_jmp_writeout_op_tilebuffer_pending
:
768 fprintf(fp
, "tilebuffer.");
771 case midgard_jmp_writeout_op_discard
:
772 fprintf(fp
, "discard.");
776 fprintf(fp
, "unk%u.", op
);
782 print_branch_cond(FILE *fp
, int cond
)
785 case midgard_condition_write0
:
786 fprintf(fp
, "write0");
789 case midgard_condition_false
:
790 fprintf(fp
, "false");
793 case midgard_condition_true
:
797 case midgard_condition_always
:
798 fprintf(fp
, "always");
802 fprintf(fp
, "unk%X", cond
);
808 print_compact_branch_writeout_field(FILE *fp
, uint16_t word
)
810 midgard_jmp_writeout_op op
= word
& 0x7;
811 midg_stats
.instruction_count
++;
814 case midgard_jmp_writeout_op_branch_uncond
: {
815 midgard_branch_uncond br_uncond
;
816 memcpy((char *) &br_uncond
, (char *) &word
, sizeof(br_uncond
));
817 fprintf(fp
, "br.uncond ");
819 if (br_uncond
.unknown
!= 1)
820 fprintf(fp
, "unknown:%u, ", br_uncond
.unknown
);
822 if (br_uncond
.offset
>= 0)
825 fprintf(fp
, "%d -> ", br_uncond
.offset
);
826 print_tag_short(fp
, br_uncond
.dest_tag
);
829 return br_uncond
.offset
>= 0;
832 case midgard_jmp_writeout_op_branch_cond
:
833 case midgard_jmp_writeout_op_writeout
:
834 case midgard_jmp_writeout_op_discard
:
836 midgard_branch_cond br_cond
;
837 memcpy((char *) &br_cond
, (char *) &word
, sizeof(br_cond
));
841 print_branch_op(fp
, br_cond
.op
);
842 print_branch_cond(fp
, br_cond
.cond
);
846 if (br_cond
.offset
>= 0)
849 fprintf(fp
, "%d -> ", br_cond
.offset
);
850 print_tag_short(fp
, br_cond
.dest_tag
);
853 return br_cond
.offset
>= 0;
861 print_extended_branch_writeout_field(FILE *fp
, uint8_t *words
, unsigned next
)
863 midgard_branch_extended br
;
864 memcpy((char *) &br
, (char *) words
, sizeof(br
));
868 print_branch_op(fp
, br
.op
);
870 /* Condition codes are a LUT in the general case, but simply repeated 8 times for single-channel conditions.. Check this. */
872 bool single_channel
= true;
874 for (unsigned i
= 0; i
< 16; i
+= 2) {
875 single_channel
&= (((br
.cond
>> i
) & 0x3) == (br
.cond
& 0x3));
879 print_branch_cond(fp
, br
.cond
& 0x3);
881 fprintf(fp
, "lut%X", br
.cond
);
884 fprintf(fp
, ".unknown%u", br
.unknown
);
891 fprintf(fp
, "%d -> ", br
.offset
);
892 print_tag_short(fp
, br
.dest_tag
);
895 unsigned I
= next
+ br
.offset
* 4;
897 if (midg_tags
[I
] && midg_tags
[I
] != br
.dest_tag
) {
898 fprintf(fp
, "\t/* XXX TAG ERROR: jumping to ");
899 print_tag_short(fp
, br
.dest_tag
);
900 fprintf(fp
, " but tagged ");
901 print_tag_short(fp
, midg_tags
[I
]);
902 fprintf(fp
, " */\n");
905 midg_tags
[I
] = br
.dest_tag
;
907 midg_stats
.instruction_count
++;
908 return br
.offset
>= 0;
912 num_alu_fields_enabled(uint32_t control_word
)
916 if ((control_word
>> 17) & 1)
919 if ((control_word
>> 19) & 1)
922 if ((control_word
>> 21) & 1)
925 if ((control_word
>> 23) & 1)
928 if ((control_word
>> 25) & 1)
935 print_alu_word(FILE *fp
, uint32_t *words
, unsigned num_quad_words
,
936 unsigned tabs
, unsigned next
)
938 uint32_t control_word
= words
[0];
939 uint16_t *beginning_ptr
= (uint16_t *)(words
+ 1);
940 unsigned num_fields
= num_alu_fields_enabled(control_word
);
941 uint16_t *word_ptr
= beginning_ptr
+ num_fields
;
942 unsigned num_words
= 2 + num_fields
;
943 const midgard_constants
*consts
= NULL
;
944 bool branch_forward
= false;
946 if ((control_word
>> 17) & 1)
949 if ((control_word
>> 19) & 1)
952 if ((control_word
>> 21) & 1)
955 if ((control_word
>> 23) & 1)
958 if ((control_word
>> 25) & 1)
961 if ((control_word
>> 26) & 1)
964 if ((control_word
>> 27) & 1)
967 if (num_quad_words
> (num_words
+ 7) / 8) {
968 assert(num_quad_words
== (num_words
+ 15) / 8);
969 //Assume that the extra quadword is constants
970 consts
= (midgard_constants
*)(words
+ (4 * num_quad_words
- 4));
973 if ((control_word
>> 16) & 1)
974 fprintf(fp
, "unknown bit 16 enabled\n");
976 if ((control_word
>> 17) & 1) {
977 print_vector_field(fp
, "vmul", word_ptr
, *beginning_ptr
, consts
, tabs
);
982 if ((control_word
>> 18) & 1)
983 fprintf(fp
, "unknown bit 18 enabled\n");
985 if ((control_word
>> 19) & 1) {
986 print_scalar_field(fp
, "sadd", word_ptr
, *beginning_ptr
, consts
, tabs
);
991 if ((control_word
>> 20) & 1)
992 fprintf(fp
, "unknown bit 20 enabled\n");
994 if ((control_word
>> 21) & 1) {
995 print_vector_field(fp
, "vadd", word_ptr
, *beginning_ptr
, consts
, tabs
);
1000 if ((control_word
>> 22) & 1)
1001 fprintf(fp
, "unknown bit 22 enabled\n");
1003 if ((control_word
>> 23) & 1) {
1004 print_scalar_field(fp
, "smul", word_ptr
, *beginning_ptr
, consts
, tabs
);
1009 if ((control_word
>> 24) & 1)
1010 fprintf(fp
, "unknown bit 24 enabled\n");
1012 if ((control_word
>> 25) & 1) {
1013 print_vector_field(fp
, "lut", word_ptr
, *beginning_ptr
, consts
, tabs
);
1017 if ((control_word
>> 26) & 1) {
1018 branch_forward
|= print_compact_branch_writeout_field(fp
, *word_ptr
);
1022 if ((control_word
>> 27) & 1) {
1023 branch_forward
|= print_extended_branch_writeout_field(fp
, (uint8_t *) word_ptr
, next
);
1028 fprintf(fp
, "uconstants 0x%X, 0x%X, 0x%X, 0x%X\n",
1029 consts
->u32
[0], consts
->u32
[1],
1030 consts
->u32
[2], consts
->u32
[3]);
1032 return branch_forward
;
1036 print_varying_parameters(FILE *fp
, midgard_load_store_word
*word
)
1038 midgard_varying_parameter param
;
1039 unsigned v
= word
->varying_parameters
;
1040 memcpy(¶m
, &v
, sizeof(param
));
1042 if (param
.is_varying
) {
1043 /* If a varying, there are qualifiers */
1045 fprintf(fp
, ".flat");
1047 if (param
.interpolation
!= midgard_interp_default
) {
1048 if (param
.interpolation
== midgard_interp_centroid
)
1049 fprintf(fp
, ".centroid");
1051 fprintf(fp
, ".interp%d", param
.interpolation
);
1054 if (param
.modifier
!= midgard_varying_mod_none
) {
1055 if (param
.modifier
== midgard_varying_mod_perspective_w
)
1056 fprintf(fp
, ".perspectivew");
1057 else if (param
.modifier
== midgard_varying_mod_perspective_z
)
1058 fprintf(fp
, ".perspectivez");
1060 fprintf(fp
, ".mod%d", param
.modifier
);
1062 } else if (param
.flat
|| param
.interpolation
|| param
.modifier
) {
1063 fprintf(fp
, " /* is_varying not set but varying metadata attached */");
1066 if (param
.zero0
|| param
.zero1
|| param
.zero2
)
1067 fprintf(fp
, " /* zero tripped, %u %u %u */ ", param
.zero0
, param
.zero1
, param
.zero2
);
1071 is_op_varying(unsigned op
)
1074 case midgard_op_st_vary_16
:
1075 case midgard_op_st_vary_32
:
1076 case midgard_op_st_vary_32i
:
1077 case midgard_op_st_vary_32u
:
1078 case midgard_op_ld_vary_16
:
1079 case midgard_op_ld_vary_32
:
1080 case midgard_op_ld_vary_32i
:
1081 case midgard_op_ld_vary_32u
:
1089 is_op_attribute(unsigned op
)
1092 case midgard_op_ld_attr_16
:
1093 case midgard_op_ld_attr_32
:
1094 case midgard_op_ld_attr_32i
:
1095 case midgard_op_ld_attr_32u
:
1103 print_load_store_arg(FILE *fp
, uint8_t arg
, unsigned index
)
1105 /* Try to interpret as a register */
1106 midgard_ldst_register_select sel
;
1107 memcpy(&sel
, &arg
, sizeof(arg
));
1109 /* If unknown is set, we're not sure what this is or how to
1110 * interpret it. But if it's zero, we get it. */
1113 fprintf(fp
, "0x%02X", arg
);
1117 unsigned reg
= REGISTER_LDST_BASE
+ sel
.select
;
1118 char comp
= components
[sel
.component
];
1120 fprintf(fp
, "r%u.%c", reg
, comp
);
1122 /* Only print a shift if it's non-zero. Shifts only make sense for the
1123 * second index. For the first, we're not sure what it means yet */
1127 fprintf(fp
, " << %u", sel
.shift
);
1129 fprintf(fp
, " /* %X */", sel
.shift
);
1134 update_stats(signed *stat
, unsigned address
)
1137 *stat
= MAX2(*stat
, address
+ 1);
1141 print_load_store_instr(FILE *fp
, uint64_t data
,
1144 midgard_load_store_word
*word
= (midgard_load_store_word
*) &data
;
1146 print_ld_st_opcode(fp
, word
->op
);
1148 unsigned address
= word
->address
;
1150 if (is_op_varying(word
->op
)) {
1151 print_varying_parameters(fp
, word
);
1153 /* Do some analysis: check if direct cacess */
1155 if ((word
->arg_2
== 0x1E) && midg_stats
.varying_count
>= 0)
1156 update_stats(&midg_stats
.varying_count
, address
);
1158 midg_stats
.varying_count
= -16;
1159 } else if (is_op_attribute(word
->op
)) {
1160 if ((word
->arg_2
== 0x1E) && midg_stats
.attribute_count
>= 0)
1161 update_stats(&midg_stats
.attribute_count
, address
);
1163 midg_stats
.attribute_count
= -16;
1166 fprintf(fp
, " r%u", word
->reg
+ (OP_IS_STORE(word
->op
) ? 26 : 0));
1167 print_mask_4(fp
, word
->mask
, false);
1169 if (!OP_IS_STORE(word
->op
))
1170 update_dest(word
->reg
);
1172 bool is_ubo
= OP_IS_UBO_READ(word
->op
);
1175 /* UBOs use their own addressing scheme */
1177 int lo
= word
->varying_parameters
>> 7;
1178 int hi
= word
->address
;
1180 /* TODO: Combine fields logically */
1181 address
= (hi
<< 3) | lo
;
1184 fprintf(fp
, ", %u", address
);
1186 print_swizzle_vec4(fp
, word
->swizzle
, false, false, false);
1191 fprintf(fp
, "ubo%u", word
->arg_1
);
1192 update_stats(&midg_stats
.uniform_buffer_count
, word
->arg_1
);
1194 print_load_store_arg(fp
, word
->arg_1
, 0);
1197 print_load_store_arg(fp
, word
->arg_2
, 1);
1198 fprintf(fp
, " /* %X */\n", word
->varying_parameters
);
1200 midg_stats
.instruction_count
++;
1204 print_load_store_word(FILE *fp
, uint32_t *word
, unsigned tabs
)
1206 midgard_load_store
*load_store
= (midgard_load_store
*) word
;
1208 if (load_store
->word1
!= 3) {
1209 print_load_store_instr(fp
, load_store
->word1
, tabs
);
1212 if (load_store
->word2
!= 3) {
1213 print_load_store_instr(fp
, load_store
->word2
, tabs
);
1218 print_texture_reg_select(FILE *fp
, uint8_t u
, unsigned base
)
1220 midgard_tex_register_select sel
;
1221 memcpy(&sel
, &u
, sizeof(u
));
1226 fprintf(fp
, "r%u", base
+ sel
.select
);
1228 unsigned component
= sel
.component
;
1230 /* Use the upper half in half-reg mode */
1236 fprintf(fp
, ".%c", components
[component
]);
1238 assert(sel
.zero
== 0);
1242 print_texture_format(FILE *fp
, int format
)
1244 /* Act like a modifier */
1248 DEFINE_CASE(MALI_TEX_1D
, "1d");
1249 DEFINE_CASE(MALI_TEX_2D
, "2d");
1250 DEFINE_CASE(MALI_TEX_3D
, "3d");
1251 DEFINE_CASE(MALI_TEX_CUBE
, "cube");
1254 unreachable("Bad format");
1259 midgard_op_has_helpers(unsigned op
, bool gather
)
1265 case TEXTURE_OP_NORMAL
:
1266 case TEXTURE_OP_DFDX
:
1267 case TEXTURE_OP_DFDY
:
1275 print_texture_op(FILE *fp
, unsigned op
, bool gather
)
1277 /* Act like a bare name, like ESSL functions */
1280 fprintf(fp
, "textureGather");
1282 unsigned component
= op
>> 4;
1283 unsigned bottom
= op
& 0xF;
1286 fprintf(fp
, "_unk%u", bottom
);
1288 fprintf(fp
, ".%c", components
[component
]);
1293 DEFINE_CASE(TEXTURE_OP_NORMAL
, "texture");
1294 DEFINE_CASE(TEXTURE_OP_LOD
, "textureLod");
1295 DEFINE_CASE(TEXTURE_OP_TEXEL_FETCH
, "texelFetch");
1296 DEFINE_CASE(TEXTURE_OP_BARRIER
, "barrier");
1297 DEFINE_CASE(TEXTURE_OP_DFDX
, "dFdx");
1298 DEFINE_CASE(TEXTURE_OP_DFDY
, "dFdy");
1301 fprintf(fp
, "tex_%X", op
);
1307 texture_op_takes_bias(unsigned op
)
1309 return op
== TEXTURE_OP_NORMAL
;
1313 sampler_type_name(enum mali_sampler_type t
)
1316 case MALI_SAMPLER_FLOAT
:
1318 case MALI_SAMPLER_UNSIGNED
:
1320 case MALI_SAMPLER_SIGNED
:
1329 print_texture_barrier(FILE *fp
, uint32_t *word
)
1331 midgard_texture_barrier_word
*barrier
= (midgard_texture_barrier_word
*) word
;
1333 if (barrier
->type
!= 0x4)
1334 fprintf(fp
, "/* barrier tag %X != 0x4 */ ", barrier
->type
);
1337 fprintf(fp
, "/* cont missing? */");
1340 fprintf(fp
, "/* last missing? */");
1343 fprintf(fp
, "/* zero1 = 0x%X */ ", barrier
->zero1
);
1346 fprintf(fp
, "/* zero2 = 0x%X */ ", barrier
->zero2
);
1349 fprintf(fp
, "/* zero3 = 0x%X */ ", barrier
->zero3
);
1352 fprintf(fp
, "/* zero4 = 0x%X */ ", barrier
->zero4
);
1355 fprintf(fp
, "/* zero4 = 0x%" PRIx64
" */ ", barrier
->zero5
);
1358 /* Control barriers are always implied, so include for obviousness */
1359 fprintf(fp
, " control");
1361 if (barrier
->buffer
)
1362 fprintf(fp
, " | buffer");
1364 if (barrier
->shared
)
1365 fprintf(fp
, " | shared");
1373 print_texture_word(FILE *fp
, uint32_t *word
, unsigned tabs
, unsigned in_reg_base
, unsigned out_reg_base
)
1375 midgard_texture_word
*texture
= (midgard_texture_word
*) word
;
1377 midg_stats
.helper_invocations
|=
1378 midgard_op_has_helpers(texture
->op
, texture
->is_gather
);
1380 /* Broad category of texture operation in question */
1381 print_texture_op(fp
, texture
->op
, texture
->is_gather
);
1383 /* Barriers use a dramatically different code path */
1384 if (texture
->op
== TEXTURE_OP_BARRIER
) {
1385 print_texture_barrier(fp
, word
);
1387 } else if (texture
->type
== 0x4)
1388 fprintf (fp
, "/* nonbarrier had tag 0x4 */ ");
1390 /* Specific format in question */
1391 print_texture_format(fp
, texture
->format
);
1393 /* Instruction "modifiers" parallel the ALU instructions. */
1395 if (texture
->shadow
)
1396 fprintf(fp
, ".shadow");
1399 fprintf(fp
, ".cont");
1402 fprintf(fp
, ".last");
1404 if (texture
->barrier_buffer
)
1405 fprintf(fp
, ".barrier_buffer /* XXX */");
1407 if (texture
->barrier_shared
)
1408 fprintf(fp
, ".barrier_shared /* XXX */");
1410 /* Output modifiers are always interpreted floatly */
1411 print_outmod(fp
, texture
->outmod
, false);
1413 fprintf(fp
, " %sr%u", texture
->out_full
? "" : "h",
1414 out_reg_base
+ texture
->out_reg_select
);
1415 print_mask_4(fp
, texture
->mask
, texture
->out_upper
);
1416 assert(!(texture
->out_full
&& texture
->out_upper
));
1419 /* Depending on whether we read from textures directly or indirectly,
1420 * we may be able to update our analysis */
1422 if (texture
->texture_register
) {
1423 fprintf(fp
, "texture[");
1424 print_texture_reg_select(fp
, texture
->texture_handle
, in_reg_base
);
1427 /* Indirect, tut tut */
1428 midg_stats
.texture_count
= -16;
1430 fprintf(fp
, "texture%u, ", texture
->texture_handle
);
1431 update_stats(&midg_stats
.texture_count
, texture
->texture_handle
);
1434 /* Print the type, GL style */
1435 fprintf(fp
, "%csampler", sampler_type_name(texture
->sampler_type
));
1437 if (texture
->sampler_register
) {
1439 print_texture_reg_select(fp
, texture
->sampler_handle
, in_reg_base
);
1442 midg_stats
.sampler_count
= -16;
1444 fprintf(fp
, "%u", texture
->sampler_handle
);
1445 update_stats(&midg_stats
.sampler_count
, texture
->sampler_handle
);
1448 print_swizzle_vec4(fp
, texture
->swizzle
, false, false, false);
1449 fprintf(fp
, ", %sr%u", texture
->in_reg_full
? "" : "h", in_reg_base
+ texture
->in_reg_select
);
1450 assert(!(texture
->in_reg_full
&& texture
->in_reg_upper
));
1452 /* TODO: integrate with swizzle */
1453 if (texture
->in_reg_upper
)
1456 print_swizzle_vec4(fp
, texture
->in_reg_swizzle
, false, false, false);
1458 /* There is *always* an offset attached. Of
1459 * course, that offset is just immediate #0 for a
1460 * GLES call that doesn't take an offset. If there
1461 * is a non-negative non-zero offset, this is
1462 * specified in immediate offset mode, with the
1463 * values in the offset_* fields as immediates. If
1464 * this is a negative offset, we instead switch to
1465 * a register offset mode, where the offset_*
1466 * fields become register triplets */
1468 if (texture
->offset_register
) {
1471 bool full
= texture
->offset
& 1;
1472 bool select
= texture
->offset
& 2;
1473 bool upper
= texture
->offset
& 4;
1475 fprintf(fp
, "%sr%u", full
? "" : "h", in_reg_base
+ select
);
1476 assert(!(texture
->out_full
&& texture
->out_upper
));
1478 /* TODO: integrate with swizzle */
1482 print_swizzle_vec4(fp
, texture
->offset
>> 3, false, false, false);
1485 } else if (texture
->offset
) {
1486 /* Only select ops allow negative immediate offsets, verify */
1488 signed offset_x
= (texture
->offset
& 0xF);
1489 signed offset_y
= ((texture
->offset
>> 4) & 0xF);
1490 signed offset_z
= ((texture
->offset
>> 8) & 0xF);
1492 bool neg_x
= offset_x
< 0;
1493 bool neg_y
= offset_y
< 0;
1494 bool neg_z
= offset_z
< 0;
1495 bool any_neg
= neg_x
|| neg_y
|| neg_z
;
1497 if (any_neg
&& texture
->op
!= TEXTURE_OP_TEXEL_FETCH
)
1498 fprintf(fp
, "/* invalid negative */ ");
1500 /* Regardless, just print the immediate offset */
1502 fprintf(fp
, " + <%d, %d, %d>, ", offset_x
, offset_y
, offset_z
);
1507 char lod_operand
= texture_op_takes_bias(texture
->op
) ? '+' : '=';
1509 if (texture
->lod_register
) {
1510 fprintf(fp
, "lod %c ", lod_operand
);
1511 print_texture_reg_select(fp
, texture
->bias
, in_reg_base
);
1514 if (texture
->bias_int
)
1515 fprintf(fp
, " /* bias_int = 0x%X */", texture
->bias_int
);
1516 } else if (texture
->op
== TEXTURE_OP_TEXEL_FETCH
) {
1517 /* For texel fetch, the int LOD is in the fractional place and
1518 * there is no fraction / possibility of bias. We *always* have
1519 * an explicit LOD, even if it's zero. */
1521 if (texture
->bias_int
)
1522 fprintf(fp
, " /* bias_int = 0x%X */ ", texture
->bias_int
);
1524 fprintf(fp
, "lod = %u, ", texture
->bias
);
1525 } else if (texture
->bias
|| texture
->bias_int
) {
1526 signed bias_int
= texture
->bias_int
;
1527 float bias_frac
= texture
->bias
/ 256.0f
;
1528 float bias
= bias_int
+ bias_frac
;
1530 bool is_bias
= texture_op_takes_bias(texture
->op
);
1531 char sign
= (bias
>= 0.0) ? '+' : '-';
1532 char operand
= is_bias
? sign
: '=';
1534 fprintf(fp
, "lod %c %f, ", operand
, fabsf(bias
));
1539 /* While not zero in general, for these simple instructions the
1540 * following unknowns are zero, so we don't include them */
1542 if (texture
->unknown4
||
1543 texture
->unknown8
) {
1544 fprintf(fp
, "// unknown4 = 0x%x\n", texture
->unknown4
);
1545 fprintf(fp
, "// unknown8 = 0x%x\n", texture
->unknown8
);
1548 midg_stats
.instruction_count
++;
1551 struct midgard_disasm_stats
1552 disassemble_midgard(FILE *fp
, uint8_t *code
, size_t size
, unsigned gpu_id
, gl_shader_stage stage
)
1554 uint32_t *words
= (uint32_t *) code
;
1555 unsigned num_words
= size
/ 4;
1558 bool branch_forward
= false;
1560 int last_next_tag
= -1;
1564 midg_tags
= calloc(sizeof(midg_tags
[0]), num_words
);
1566 /* Stats for shader-db */
1567 memset(&midg_stats
, 0, sizeof(midg_stats
));
1568 midg_ever_written
= 0;
1570 while (i
< num_words
) {
1571 unsigned tag
= words
[i
] & 0xF;
1572 unsigned next_tag
= (words
[i
] >> 4) & 0xF;
1573 fprintf(fp
, "\t%X -> %X\n", tag
, next_tag
);
1574 unsigned num_quad_words
= midgard_word_size
[tag
];
1576 if (midg_tags
[i
] && midg_tags
[i
] != tag
) {
1577 fprintf(fp
, "\t/* XXX: TAG ERROR branch, got ");
1578 print_tag_short(fp
, tag
);
1579 fprintf(fp
, " expected ");
1580 print_tag_short(fp
, midg_tags
[i
]);
1581 fprintf(fp
, " */\n");
1587 if (last_next_tag
> 1) {
1588 if (last_next_tag
!= tag
) {
1589 fprintf(fp
, "\t/* XXX: TAG ERROR sequence, got ");
1590 print_tag_short(fp
, tag
);
1591 fprintf(fp
, " expected ");
1592 print_tag_short(fp
, last_next_tag
);
1593 fprintf(fp
, " */\n");
1596 /* TODO: Check ALU case */
1599 last_next_tag
= next_tag
;
1601 switch (midgard_word_types
[tag
]) {
1602 case midgard_word_type_texture
: {
1603 bool interpipe_aliasing
=
1604 midgard_get_quirks(gpu_id
) & MIDGARD_INTERPIPE_REG_ALIASING
;
1606 print_texture_word(fp
, &words
[i
], tabs
,
1607 interpipe_aliasing
? 0 : REG_TEX_BASE
,
1608 interpipe_aliasing
? REGISTER_LDST_BASE
: REG_TEX_BASE
);
1612 case midgard_word_type_load_store
:
1613 print_load_store_word(fp
, &words
[i
], tabs
);
1616 case midgard_word_type_alu
:
1617 branch_forward
= print_alu_word(fp
, &words
[i
], num_quad_words
, tabs
, i
+ 4*num_quad_words
);
1619 /* Reset word static analysis state */
1620 is_embedded_constant_half
= false;
1621 is_embedded_constant_int
= false;
1626 fprintf(fp
, "Unknown word type %u:\n", words
[i
] & 0xF);
1628 print_quad_word(fp
, &words
[i
], tabs
);
1633 /* We are parsing per bundle anyway. Add before we start
1634 * breaking out so we don't miss the final bundle. */
1636 midg_stats
.bundle_count
++;
1637 midg_stats
.quadword_count
+= num_quad_words
;
1641 unsigned next
= (words
[i
] & 0xF0) >> 4;
1643 if (i
< num_words
&& next
== 1 && !branch_forward
)
1646 i
+= 4 * num_quad_words
;
1651 /* We computed work_count as max_work_registers, so add one to get the
1652 * count. If no work registers are written, you still have one work
1653 * reported, which is exactly what the hardware expects */
1655 midg_stats
.work_count
++;