5 * Copyright (c) 2013 Connor Abbott (connor@abbott.cx)
6 * Copyright (c) 2018 Alyssa Rosenzweig (alyssa@rosenzweig.io)
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
35 #include "midgard-parse.h"
36 #include "midgard_ops.h"
37 #include "midgard_quirks.h"
38 #include "disassemble.h"
40 #include "util/half_float.h"
41 #include "util/u_math.h"
43 #define DEFINE_CASE(define, str) case define: { printf(str); break; }
45 static unsigned *midg_tags
;
46 static bool is_instruction_int
= false;
50 static struct midgard_disasm_stats midg_stats
;
52 /* Prints a short form of the tag for branching, the minimum needed to be
53 * legible and unambiguous */
56 print_tag_short(unsigned tag
)
58 switch (midgard_word_types
[tag
]) {
59 case midgard_word_type_texture
:
60 printf("tex/%X", tag
);
63 case midgard_word_type_load_store
:
67 case midgard_word_type_alu
:
68 printf("alu%u/%X", midgard_word_size
[tag
], tag
);
72 printf("%s%X", (tag
> 0) ? "" : "unk", tag
);
78 print_alu_opcode(midgard_alu_op op
)
82 if (alu_opcode_props
[op
].name
) {
83 printf("%s", alu_opcode_props
[op
].name
);
85 int_op
= midgard_is_integer_op(op
);
87 printf("alu_op_%02X", op
);
89 /* For constant analysis */
90 is_instruction_int
= int_op
;
94 print_ld_st_opcode(midgard_load_store_op op
)
96 if (load_store_opcode_props
[op
].name
)
97 printf("%s", load_store_opcode_props
[op
].name
);
99 printf("ldst_op_%02X", op
);
102 static bool is_embedded_constant_half
= false;
103 static bool is_embedded_constant_int
= false;
106 prefix_for_bits(unsigned bits
)
120 /* For static analysis to ensure all registers are written at least once before
121 * use along the source code path (TODO: does this break done for complex CF?)
124 uint16_t midg_ever_written
= 0;
127 print_reg(unsigned reg
, unsigned bits
)
129 /* Perform basic static analysis for expanding constants correctly */
132 is_embedded_constant_int
= is_instruction_int
;
133 is_embedded_constant_half
= (bits
< 32);
136 unsigned uniform_reg
= 23 - reg
;
137 bool is_uniform
= false;
139 /* For r8-r15, it could be a work or uniform. We distinguish based on
140 * the fact work registers are ALWAYS written before use, but uniform
141 * registers are NEVER written before use. */
143 if ((reg
>= 8 && reg
< 16) && !(midg_ever_written
& (1 << reg
)))
146 /* r16-r23 are always uniform */
148 if (reg
>= 16 && reg
<= 23)
151 /* Update the uniform count appropriately */
154 midg_stats
.uniform_count
=
155 MAX2(uniform_reg
+ 1, midg_stats
.uniform_count
);
157 char prefix
= prefix_for_bits(bits
);
165 static char *outmod_names_float
[4] = {
172 static char *outmod_names_int
[4] = {
179 static char *srcmod_names_int
[4] = {
187 print_outmod(unsigned outmod
, bool is_int
)
189 printf("%s", is_int
? outmod_names_int
[outmod
] :
190 outmod_names_float
[outmod
]);
194 print_quad_word(uint32_t *words
, unsigned tabs
)
198 for (i
= 0; i
< 4; i
++)
199 printf("0x%08X%s ", words
[i
], i
== 3 ? "" : ",");
204 static const char components
[16] = "xyzwefghijklmnop";
206 /* Helper to print 4 chars of a swizzle */
208 print_swizzle_helper(unsigned swizzle
, bool upper
)
210 for (unsigned i
= 0; i
< 4; ++i
) {
211 unsigned c
= (swizzle
>> (i
* 2)) & 3;
213 printf("%c", components
[c
]);
217 /* Helper to print 8 chars of a swizzle, duplicating over */
219 print_swizzle_helper_8(unsigned swizzle
, bool upper
)
221 for (unsigned i
= 0; i
< 4; ++i
) {
222 unsigned c
= (swizzle
>> (i
* 2)) & 3;
225 printf("%c%c", components
[c
], components
[c
+1]);
230 print_swizzle_vec16(unsigned swizzle
, bool rep_high
, bool rep_low
,
231 midgard_dest_override override
)
235 if (override
== midgard_dest_override_upper
) {
237 printf(" /* rep_high */ ");
239 printf(" /* rep_low */ ");
241 if (!rep_high
&& rep_low
)
242 print_swizzle_helper_8(swizzle
, true);
244 print_swizzle_helper_8(swizzle
, false);
246 print_swizzle_helper_8(swizzle
, rep_high
& 1);
247 print_swizzle_helper_8(swizzle
, !(rep_low
& 1));
252 print_swizzle_vec8(unsigned swizzle
, bool rep_high
, bool rep_low
)
256 print_swizzle_helper(swizzle
, rep_high
& 1);
257 print_swizzle_helper(swizzle
, !(rep_low
& 1));
261 print_swizzle_vec4(unsigned swizzle
, bool rep_high
, bool rep_low
)
264 printf(" /* rep_high */ ");
266 printf(" /* rep_low */ ");
268 if (swizzle
== 0xE4) return; /* xyzw */
271 print_swizzle_helper(swizzle
, 0);
274 print_swizzle_vec2(unsigned swizzle
, bool rep_high
, bool rep_low
)
277 printf(" /* rep_high */ ");
279 printf(" /* rep_low */ ");
281 if (swizzle
== 0xE4) return; /* XY */
285 for (unsigned i
= 0; i
< 4; i
+= 2) {
286 unsigned a
= (swizzle
>> (i
* 2)) & 3;
287 unsigned b
= (swizzle
>> ((i
+1) * 2)) & 3;
289 /* Normally we're adjacent, but if there's an issue, don't make
293 printf("[%c%c]", components
[a
], components
[b
]);
295 printf("%c", components
[a
>> 1]);
296 else if (b
== (a
+ 1))
297 printf("%c", "XY"[a
>> 1]);
299 printf("[%c%c]", components
[a
], components
[b
]);
304 bits_for_mode(midgard_reg_mode mode
)
307 case midgard_reg_mode_8
:
309 case midgard_reg_mode_16
:
311 case midgard_reg_mode_32
:
313 case midgard_reg_mode_64
:
316 unreachable("Invalid reg mode");
322 bits_for_mode_halved(midgard_reg_mode mode
, bool half
)
324 unsigned bits
= bits_for_mode(mode
);
333 print_vector_src(unsigned src_binary
,
334 midgard_reg_mode mode
, unsigned reg
,
335 midgard_dest_override override
, bool is_int
)
337 midgard_vector_alu_src
*src
= (midgard_vector_alu_src
*)&src_binary
;
339 /* Modifiers change meaning depending on the op's context */
341 midgard_int_mod int_mod
= src
->mod
;
344 printf("%s", srcmod_names_int
[int_mod
]);
346 if (src
->mod
& MIDGARD_FLOAT_MOD_NEG
)
349 if (src
->mod
& MIDGARD_FLOAT_MOD_ABS
)
354 unsigned bits
= bits_for_mode_halved(mode
, src
->half
);
355 print_reg(reg
, bits
);
359 /* When the mode of the instruction is itself 16-bit,
360 * rep_low/high work more or less as expected. But if the mode
361 * is 32-bit and we're stepping down, you only have vec4 and
362 * the meaning shifts to rep_low as higher-half and rep_high is
363 * never seen. TODO: are other modes similar? */
365 if (mode
== midgard_reg_mode_32
) {
367 print_swizzle_helper(src
->swizzle
, src
->rep_low
);
368 assert(!src
->rep_high
);
370 print_swizzle_vec8(src
->swizzle
, src
->rep_high
, src
->rep_low
);
372 } else if (bits
== 8)
373 print_swizzle_vec16(src
->swizzle
, src
->rep_high
, src
->rep_low
, override
);
375 print_swizzle_vec4(src
->swizzle
, src
->rep_high
, src
->rep_low
);
377 print_swizzle_vec2(src
->swizzle
, src
->rep_high
, src
->rep_low
);
379 /* Since we wrapped with a function-looking thing */
381 if (is_int
&& int_mod
== midgard_int_shift
)
382 printf(") << %u", bits
);
383 else if ((is_int
&& (int_mod
!= midgard_int_normal
))
384 || (!is_int
&& src
->mod
& MIDGARD_FLOAT_MOD_ABS
))
389 decode_vector_imm(unsigned src2_reg
, unsigned imm
)
392 ret
= src2_reg
<< 11;
393 ret
|= (imm
& 0x7) << 8;
394 ret
|= (imm
>> 3) & 0xFF;
399 print_immediate(uint16_t imm
)
401 if (is_instruction_int
)
404 printf("#%g", _mesa_half_to_float(imm
));
408 update_dest(unsigned reg
)
410 /* We should record writes as marking this as a work register. Store
411 * the max register in work_count; we'll add one at the end */
414 midg_stats
.work_count
= MAX2(reg
, midg_stats
.work_count
);
415 midg_ever_written
|= (1 << reg
);
420 print_dest(unsigned reg
, midgard_reg_mode mode
, midgard_dest_override override
)
422 /* Depending on the mode and override, we determine the type of
423 * destination addressed. Absent an override, we address just the
424 * type of the operation itself */
426 unsigned bits
= bits_for_mode(mode
);
428 if (override
!= midgard_dest_override_none
)
432 print_reg(reg
, bits
);
436 print_mask_vec16(uint8_t mask
, midgard_dest_override override
)
440 for (unsigned i
= 0; i
< 8; i
++) {
444 components
[i
*2 + 1]);
448 /* For 16-bit+ masks, we read off from the 8-bit mask field. For 16-bit (vec8),
449 * it's just one bit per channel, easy peasy. For 32-bit (vec4), it's one bit
450 * per channel with one duplicate bit in the middle. For 64-bit (vec2), it's
451 * one-bit per channel with _3_ duplicate bits in the middle. Basically, just
452 * subdividing the 128-bit word in 16-bit increments. For 64-bit, we uppercase
453 * the mask to make it obvious what happened */
456 print_mask(uint8_t mask
, unsigned bits
, midgard_dest_override override
)
459 print_mask_vec16(mask
, override
);
463 /* Skip 'complete' masks */
465 if (override
== midgard_dest_override_none
) {
466 if (bits
>= 32 && mask
== 0xFF) return;
471 else if (mask
== 0xF0) {
480 unsigned skip
= (bits
/ 16);
481 bool uppercase
= bits
> 32;
482 bool tripped
= false;
484 /* To apply an upper destination override, we "shift" the alphabet.
485 * E.g. with an upper override on 32-bit, instead of xyzw, print efgh.
486 * For upper 16-bit, instead of xyzwefgh, print ijklmnop */
488 const char *alphabet
= components
;
490 if (override
== midgard_dest_override_upper
)
491 alphabet
+= (128 / bits
);
493 for (unsigned i
= 0; i
< 8; i
+= skip
) {
494 bool a
= (mask
& (1 << i
)) != 0;
496 for (unsigned j
= 1; j
< skip
; ++j
) {
497 bool dupe
= (mask
& (1 << (i
+ j
))) != 0;
498 tripped
|= (dupe
!= a
);
502 char c
= alphabet
[i
/ skip
];
512 printf(" /* %X */", mask
);
515 /* Prints the 4-bit masks found in texture and load/store ops, as opposed to
516 * the 8-bit masks found in (vector) ALU ops. Supports texture-style 16-bit
517 * mode as well, but not load/store-style 16-bit mode. */
520 print_mask_4(unsigned mask
, bool upper
)
531 for (unsigned i
= 0; i
< 4; ++i
) {
532 bool a
= (mask
& (1 << i
)) != 0;
534 printf("%c", components
[i
+ (upper
? 4 : 0)]);
539 print_vector_field(const char *name
, uint16_t *words
, uint16_t reg_word
,
542 midgard_reg_info
*reg_info
= (midgard_reg_info
*)®_word
;
543 midgard_vector_alu
*alu_field
= (midgard_vector_alu
*) words
;
544 midgard_reg_mode mode
= alu_field
->reg_mode
;
545 unsigned override
= alu_field
->dest_override
;
547 /* For now, prefix instruction names with their unit, until we
548 * understand how this works on a deeper level */
551 print_alu_opcode(alu_field
->op
);
553 /* Postfix with the size to disambiguate if necessary */
554 char postfix
= prefix_for_bits(bits_for_mode(mode
));
555 bool size_ambiguous
= override
!= midgard_dest_override_none
;
558 printf("%c", postfix
? postfix
: 'r');
560 /* Print the outmod, if there is one */
561 print_outmod(alu_field
->outmod
,
562 midgard_is_integer_out_op(alu_field
->op
));
566 /* Mask denoting status of 8-lanes */
567 uint8_t mask
= alu_field
->mask
;
569 /* First, print the destination */
570 print_dest(reg_info
->out_reg
, mode
, alu_field
->dest_override
);
572 if (override
!= midgard_dest_override_none
) {
573 bool modeable
= (mode
!= midgard_reg_mode_8
);
574 bool known
= override
!= 0x3; /* Unused value */
576 if (!(modeable
&& known
))
577 printf("/* do%u */ ", override
);
580 print_mask(mask
, bits_for_mode(mode
), override
);
584 bool is_int
= midgard_is_integer_op(alu_field
->op
);
585 print_vector_src(alu_field
->src1
, mode
, reg_info
->src1_reg
, override
, is_int
);
589 if (reg_info
->src2_imm
) {
590 uint16_t imm
= decode_vector_imm(reg_info
->src2_reg
, alu_field
->src2
>> 2);
591 print_immediate(imm
);
593 print_vector_src(alu_field
->src2
, mode
,
594 reg_info
->src2_reg
, override
, is_int
);
597 midg_stats
.instruction_count
++;
602 print_scalar_src(unsigned src_binary
, unsigned reg
)
604 midgard_scalar_alu_src
*src
= (midgard_scalar_alu_src
*)&src_binary
;
612 print_reg(reg
, src
->full
? 32 : 16);
614 unsigned c
= src
->component
;
617 assert((c
& 1) == 0);
621 printf(".%c", components
[c
]);
629 decode_scalar_imm(unsigned src2_reg
, unsigned imm
)
632 ret
= src2_reg
<< 11;
633 ret
|= (imm
& 3) << 9;
634 ret
|= (imm
& 4) << 6;
635 ret
|= (imm
& 0x38) << 2;
641 print_scalar_field(const char *name
, uint16_t *words
, uint16_t reg_word
,
644 midgard_reg_info
*reg_info
= (midgard_reg_info
*)®_word
;
645 midgard_scalar_alu
*alu_field
= (midgard_scalar_alu
*) words
;
647 if (alu_field
->unknown
)
648 printf("scalar ALU unknown bit set\n");
651 print_alu_opcode(alu_field
->op
);
652 print_outmod(alu_field
->outmod
,
653 midgard_is_integer_out_op(alu_field
->op
));
656 bool full
= alu_field
->output_full
;
657 update_dest(reg_info
->out_reg
);
658 print_reg(reg_info
->out_reg
, full
? 32 : 16);
659 unsigned c
= alu_field
->output_component
;
662 assert((c
& 1) == 0);
666 printf(".%c, ", components
[c
]);
668 print_scalar_src(alu_field
->src1
, reg_info
->src1_reg
);
672 if (reg_info
->src2_imm
) {
673 uint16_t imm
= decode_scalar_imm(reg_info
->src2_reg
,
675 print_immediate(imm
);
677 print_scalar_src(alu_field
->src2
, reg_info
->src2_reg
);
679 midg_stats
.instruction_count
++;
684 print_branch_op(unsigned op
)
687 case midgard_jmp_writeout_op_branch_uncond
:
691 case midgard_jmp_writeout_op_branch_cond
:
695 case midgard_jmp_writeout_op_writeout
:
699 case midgard_jmp_writeout_op_tilebuffer_pending
:
700 printf("tilebuffer.");
703 case midgard_jmp_writeout_op_discard
:
708 printf("unk%u.", op
);
714 print_branch_cond(int cond
)
717 case midgard_condition_write0
:
721 case midgard_condition_false
:
725 case midgard_condition_true
:
729 case midgard_condition_always
:
734 printf("unk%X", cond
);
740 print_compact_branch_writeout_field(uint16_t word
)
742 midgard_jmp_writeout_op op
= word
& 0x7;
745 case midgard_jmp_writeout_op_branch_uncond
: {
746 midgard_branch_uncond br_uncond
;
747 memcpy((char *) &br_uncond
, (char *) &word
, sizeof(br_uncond
));
748 printf("br.uncond ");
750 if (br_uncond
.unknown
!= 1)
751 printf("unknown:%u, ", br_uncond
.unknown
);
753 if (br_uncond
.offset
>= 0)
756 printf("%d -> ", br_uncond
.offset
);
757 print_tag_short(br_uncond
.dest_tag
);
763 case midgard_jmp_writeout_op_branch_cond
:
764 case midgard_jmp_writeout_op_writeout
:
765 case midgard_jmp_writeout_op_discard
:
767 midgard_branch_cond br_cond
;
768 memcpy((char *) &br_cond
, (char *) &word
, sizeof(br_cond
));
772 print_branch_op(br_cond
.op
);
773 print_branch_cond(br_cond
.cond
);
777 if (br_cond
.offset
>= 0)
780 printf("%d -> ", br_cond
.offset
);
781 print_tag_short(br_cond
.dest_tag
);
788 midg_stats
.instruction_count
++;
792 print_extended_branch_writeout_field(uint8_t *words
, unsigned next
)
794 midgard_branch_extended br
;
795 memcpy((char *) &br
, (char *) words
, sizeof(br
));
799 print_branch_op(br
.op
);
801 /* Condition codes are a LUT in the general case, but simply repeated 8 times for single-channel conditions.. Check this. */
803 bool single_channel
= true;
805 for (unsigned i
= 0; i
< 16; i
+= 2) {
806 single_channel
&= (((br
.cond
>> i
) & 0x3) == (br
.cond
& 0x3));
810 print_branch_cond(br
.cond
& 0x3);
812 printf("lut%X", br
.cond
);
815 printf(".unknown%u", br
.unknown
);
822 printf("%d -> ", br
.offset
);
823 print_tag_short(br
.dest_tag
);
826 unsigned I
= next
+ br
.offset
* 4;
828 if (midg_tags
[I
] && midg_tags
[I
] != br
.dest_tag
) {
829 printf("\t/* XXX TAG ERROR: jumping to ");
830 print_tag_short(br
.dest_tag
);
831 printf(" but tagged ");
832 print_tag_short(midg_tags
[I
]);
836 midg_tags
[I
] = br
.dest_tag
;
838 midg_stats
.instruction_count
++;
842 num_alu_fields_enabled(uint32_t control_word
)
846 if ((control_word
>> 17) & 1)
849 if ((control_word
>> 19) & 1)
852 if ((control_word
>> 21) & 1)
855 if ((control_word
>> 23) & 1)
858 if ((control_word
>> 25) & 1)
865 float_bitcast(uint32_t integer
)
877 print_alu_word(uint32_t *words
, unsigned num_quad_words
,
878 unsigned tabs
, unsigned next
)
880 uint32_t control_word
= words
[0];
881 uint16_t *beginning_ptr
= (uint16_t *)(words
+ 1);
882 unsigned num_fields
= num_alu_fields_enabled(control_word
);
883 uint16_t *word_ptr
= beginning_ptr
+ num_fields
;
884 unsigned num_words
= 2 + num_fields
;
886 if ((control_word
>> 16) & 1)
887 printf("unknown bit 16 enabled\n");
889 if ((control_word
>> 17) & 1) {
890 print_vector_field("vmul", word_ptr
, *beginning_ptr
, tabs
);
896 if ((control_word
>> 18) & 1)
897 printf("unknown bit 18 enabled\n");
899 if ((control_word
>> 19) & 1) {
900 print_scalar_field("sadd", word_ptr
, *beginning_ptr
, tabs
);
906 if ((control_word
>> 20) & 1)
907 printf("unknown bit 20 enabled\n");
909 if ((control_word
>> 21) & 1) {
910 print_vector_field("vadd", word_ptr
, *beginning_ptr
, tabs
);
916 if ((control_word
>> 22) & 1)
917 printf("unknown bit 22 enabled\n");
919 if ((control_word
>> 23) & 1) {
920 print_scalar_field("smul", word_ptr
, *beginning_ptr
, tabs
);
926 if ((control_word
>> 24) & 1)
927 printf("unknown bit 24 enabled\n");
929 if ((control_word
>> 25) & 1) {
930 print_vector_field("lut", word_ptr
, *beginning_ptr
, tabs
);
935 if ((control_word
>> 26) & 1) {
936 print_compact_branch_writeout_field(*word_ptr
);
941 if ((control_word
>> 27) & 1) {
942 print_extended_branch_writeout_field((uint8_t *) word_ptr
, next
);
947 if (num_quad_words
> (num_words
+ 7) / 8) {
948 assert(num_quad_words
== (num_words
+ 15) / 8);
949 //Assume that the extra quadword is constants
950 void *consts
= words
+ (4 * num_quad_words
- 4);
952 if (is_embedded_constant_int
) {
953 if (is_embedded_constant_half
) {
954 int16_t *sconsts
= (int16_t *) consts
;
955 printf("sconstants %d, %d, %d, %d\n",
961 uint32_t *iconsts
= (uint32_t *) consts
;
962 printf("iconstants 0x%X, 0x%X, 0x%X, 0x%X\n",
969 if (is_embedded_constant_half
) {
970 uint16_t *hconsts
= (uint16_t *) consts
;
971 printf("hconstants %g, %g, %g, %g\n",
972 _mesa_half_to_float(hconsts
[0]),
973 _mesa_half_to_float(hconsts
[1]),
974 _mesa_half_to_float(hconsts
[2]),
975 _mesa_half_to_float(hconsts
[3]));
977 uint32_t *fconsts
= (uint32_t *) consts
;
978 printf("fconstants %g, %g, %g, %g\n",
979 float_bitcast(fconsts
[0]),
980 float_bitcast(fconsts
[1]),
981 float_bitcast(fconsts
[2]),
982 float_bitcast(fconsts
[3]));
990 print_varying_parameters(midgard_load_store_word
*word
)
992 midgard_varying_parameter param
;
993 unsigned v
= word
->varying_parameters
;
994 memcpy(¶m
, &v
, sizeof(param
));
996 if (param
.is_varying
) {
997 /* If a varying, there are qualifiers */
1001 if (param
.interpolation
!= midgard_interp_default
) {
1002 if (param
.interpolation
== midgard_interp_centroid
)
1003 printf(".centroid");
1005 printf(".interp%d", param
.interpolation
);
1008 if (param
.modifier
!= midgard_varying_mod_none
) {
1009 if (param
.modifier
== midgard_varying_mod_perspective_w
)
1010 printf(".perspectivew");
1011 else if (param
.modifier
== midgard_varying_mod_perspective_z
)
1012 printf(".perspectivez");
1014 printf(".mod%d", param
.modifier
);
1016 } else if (param
.flat
|| param
.interpolation
|| param
.modifier
) {
1017 printf(" /* is_varying not set but varying metadata attached */");
1020 if (param
.zero0
|| param
.zero1
|| param
.zero2
)
1021 printf(" /* zero tripped, %u %u %u */ ", param
.zero0
, param
.zero1
, param
.zero2
);
1025 is_op_varying(unsigned op
)
1028 case midgard_op_st_vary_16
:
1029 case midgard_op_st_vary_32
:
1030 case midgard_op_st_vary_32i
:
1031 case midgard_op_st_vary_32u
:
1032 case midgard_op_ld_vary_16
:
1033 case midgard_op_ld_vary_32
:
1034 case midgard_op_ld_vary_32i
:
1035 case midgard_op_ld_vary_32u
:
1043 is_op_attribute(unsigned op
)
1046 case midgard_op_ld_attr_16
:
1047 case midgard_op_ld_attr_32
:
1048 case midgard_op_ld_attr_32i
:
1049 case midgard_op_ld_attr_32u
:
1057 print_load_store_arg(uint8_t arg
, unsigned index
)
1059 /* Try to interpret as a register */
1060 midgard_ldst_register_select sel
;
1061 memcpy(&sel
, &arg
, sizeof(arg
));
1063 /* If unknown is set, we're not sure what this is or how to
1064 * interpret it. But if it's zero, we get it. */
1067 printf("0x%02X", arg
);
1071 unsigned reg
= REGISTER_LDST_BASE
+ sel
.select
;
1072 char comp
= components
[sel
.component
];
1074 printf("r%u.%c", reg
, comp
);
1076 /* Only print a shift if it's non-zero. Shifts only make sense for the
1077 * second index. For the first, we're not sure what it means yet */
1081 printf(" << %u", sel
.shift
);
1083 printf(" /* %X */", sel
.shift
);
1088 update_stats(signed *stat
, unsigned address
)
1091 *stat
= MAX2(*stat
, address
+ 1);
1095 print_load_store_instr(uint64_t data
,
1098 midgard_load_store_word
*word
= (midgard_load_store_word
*) &data
;
1100 print_ld_st_opcode(word
->op
);
1102 unsigned address
= word
->address
;
1104 if (is_op_varying(word
->op
)) {
1105 print_varying_parameters(word
);
1107 /* Do some analysis: check if direct cacess */
1109 if ((word
->arg_2
== 0x1E) && midg_stats
.varying_count
>= 0)
1110 update_stats(&midg_stats
.varying_count
, address
);
1112 midg_stats
.varying_count
= -16;
1113 } else if (is_op_attribute(word
->op
)) {
1114 if ((word
->arg_2
== 0x1E) && midg_stats
.attribute_count
>= 0)
1115 update_stats(&midg_stats
.attribute_count
, address
);
1117 midg_stats
.attribute_count
= -16;
1120 printf(" r%u", word
->reg
);
1121 print_mask_4(word
->mask
, false);
1123 if (!OP_IS_STORE(word
->op
))
1124 update_dest(word
->reg
);
1126 bool is_ubo
= OP_IS_UBO_READ(word
->op
);
1129 /* UBOs use their own addressing scheme */
1131 int lo
= word
->varying_parameters
>> 7;
1132 int hi
= word
->address
;
1134 /* TODO: Combine fields logically */
1135 address
= (hi
<< 3) | lo
;
1138 printf(", %u", address
);
1140 print_swizzle_vec4(word
->swizzle
, false, false);
1145 printf("ubo%u", word
->arg_1
);
1146 update_stats(&midg_stats
.uniform_buffer_count
, word
->arg_1
);
1148 print_load_store_arg(word
->arg_1
, 0);
1151 print_load_store_arg(word
->arg_2
, 1);
1152 printf(" /* %X */\n", word
->varying_parameters
);
1154 midg_stats
.instruction_count
++;
1158 print_load_store_word(uint32_t *word
, unsigned tabs
)
1160 midgard_load_store
*load_store
= (midgard_load_store
*) word
;
1162 if (load_store
->word1
!= 3) {
1163 print_load_store_instr(load_store
->word1
, tabs
);
1166 if (load_store
->word2
!= 3) {
1167 print_load_store_instr(load_store
->word2
, tabs
);
1172 print_texture_reg_select(uint8_t u
, unsigned base
)
1174 midgard_tex_register_select sel
;
1175 memcpy(&sel
, &u
, sizeof(u
));
1180 printf("r%u", base
+ sel
.select
);
1182 unsigned component
= sel
.component
;
1184 /* Use the upper half in half-reg mode */
1190 printf(".%c", components
[component
]);
1192 assert(sel
.zero
== 0);
1196 print_texture_format(int format
)
1198 /* Act like a modifier */
1202 DEFINE_CASE(MALI_TEX_1D
, "1d");
1203 DEFINE_CASE(MALI_TEX_2D
, "2d");
1204 DEFINE_CASE(MALI_TEX_3D
, "3d");
1205 DEFINE_CASE(MALI_TEX_CUBE
, "cube");
1208 unreachable("Bad format");
1213 midgard_op_has_helpers(unsigned op
, bool gather
)
1219 case TEXTURE_OP_NORMAL
:
1220 case TEXTURE_OP_DFDX
:
1221 case TEXTURE_OP_DFDY
:
1229 print_texture_op(unsigned op
, bool gather
)
1231 /* Act like a bare name, like ESSL functions */
1234 printf("textureGather");
1236 unsigned component
= op
>> 4;
1237 unsigned bottom
= op
& 0xF;
1240 printf("_unk%u", bottom
);
1242 printf(".%c", components
[component
]);
1247 DEFINE_CASE(TEXTURE_OP_NORMAL
, "texture");
1248 DEFINE_CASE(TEXTURE_OP_LOD
, "textureLod");
1249 DEFINE_CASE(TEXTURE_OP_TEXEL_FETCH
, "texelFetch");
1250 DEFINE_CASE(TEXTURE_OP_DFDX
, "dFdx");
1251 DEFINE_CASE(TEXTURE_OP_DFDY
, "dFdy");
1254 printf("tex_%X", op
);
1260 texture_op_takes_bias(unsigned op
)
1262 return op
== TEXTURE_OP_NORMAL
;
1266 sampler_type_name(enum mali_sampler_type t
)
1269 case MALI_SAMPLER_FLOAT
:
1271 case MALI_SAMPLER_UNSIGNED
:
1273 case MALI_SAMPLER_SIGNED
:
1284 print_texture_word(uint32_t *word
, unsigned tabs
, unsigned in_reg_base
, unsigned out_reg_base
)
1286 midgard_texture_word
*texture
= (midgard_texture_word
*) word
;
1288 midg_stats
.helper_invocations
|=
1289 midgard_op_has_helpers(texture
->op
, texture
->is_gather
);
1291 /* Broad category of texture operation in question */
1292 print_texture_op(texture
->op
, texture
->is_gather
);
1294 /* Specific format in question */
1295 print_texture_format(texture
->format
);
1297 /* Instruction "modifiers" parallel the ALU instructions. */
1299 if (texture
->shadow
)
1308 /* Output modifiers are always interpreted floatly */
1309 print_outmod(texture
->outmod
, false);
1311 printf(" %sr%u", texture
->out_full
? "" : "h",
1312 out_reg_base
+ texture
->out_reg_select
);
1313 print_mask_4(texture
->mask
, texture
->out_upper
);
1314 assert(!(texture
->out_full
&& texture
->out_upper
));
1317 /* Depending on whether we read from textures directly or indirectly,
1318 * we may be able to update our analysis */
1320 if (texture
->texture_register
) {
1322 print_texture_reg_select(texture
->texture_handle
, in_reg_base
);
1325 /* Indirect, tut tut */
1326 midg_stats
.texture_count
= -16;
1328 printf("texture%u, ", texture
->texture_handle
);
1329 update_stats(&midg_stats
.texture_count
, texture
->texture_handle
);
1332 /* Print the type, GL style */
1333 printf("%csampler", sampler_type_name(texture
->sampler_type
));
1335 if (texture
->sampler_register
) {
1337 print_texture_reg_select(texture
->sampler_handle
, in_reg_base
);
1340 midg_stats
.sampler_count
= -16;
1342 printf("%u", texture
->sampler_handle
);
1343 update_stats(&midg_stats
.sampler_count
, texture
->sampler_handle
);
1346 print_swizzle_vec4(texture
->swizzle
, false, false);
1347 printf(", %sr%u", texture
->in_reg_full
? "" : "h", in_reg_base
+ texture
->in_reg_select
);
1348 assert(!(texture
->in_reg_full
&& texture
->in_reg_upper
));
1350 /* TODO: integrate with swizzle */
1351 if (texture
->in_reg_upper
)
1354 print_swizzle_vec4(texture
->in_reg_swizzle
, false, false);
1356 /* There is *always* an offset attached. Of
1357 * course, that offset is just immediate #0 for a
1358 * GLES call that doesn't take an offset. If there
1359 * is a non-negative non-zero offset, this is
1360 * specified in immediate offset mode, with the
1361 * values in the offset_* fields as immediates. If
1362 * this is a negative offset, we instead switch to
1363 * a register offset mode, where the offset_*
1364 * fields become register triplets */
1366 if (texture
->offset_register
) {
1369 bool full
= texture
->offset_x
& 1;
1370 bool select
= texture
->offset_x
& 2;
1371 bool upper
= texture
->offset_x
& 4;
1373 printf("%sr%u", full
? "" : "h", in_reg_base
+ select
);
1374 assert(!(texture
->out_full
&& texture
->out_upper
));
1376 /* TODO: integrate with swizzle */
1380 /* The less questions you ask, the better. */
1382 unsigned swizzle_lo
, swizzle_hi
;
1383 unsigned orig_y
= texture
->offset_y
;
1384 unsigned orig_z
= texture
->offset_z
;
1386 memcpy(&swizzle_lo
, &orig_y
, sizeof(unsigned));
1387 memcpy(&swizzle_hi
, &orig_z
, sizeof(unsigned));
1389 /* Duplicate hi swizzle over */
1390 assert(swizzle_hi
< 4);
1391 swizzle_hi
= (swizzle_hi
<< 2) | swizzle_hi
;
1393 unsigned swiz
= (swizzle_lo
<< 4) | swizzle_hi
;
1394 unsigned reversed
= util_bitreverse(swiz
) >> 24;
1395 print_swizzle_vec4(reversed
, false, false);
1398 } else if (texture
->offset_x
|| texture
->offset_y
|| texture
->offset_z
) {
1399 /* Only select ops allow negative immediate offsets, verify */
1401 bool neg_x
= texture
->offset_x
< 0;
1402 bool neg_y
= texture
->offset_y
< 0;
1403 bool neg_z
= texture
->offset_z
< 0;
1404 bool any_neg
= neg_x
|| neg_y
|| neg_z
;
1406 if (any_neg
&& texture
->op
!= TEXTURE_OP_TEXEL_FETCH
)
1407 printf("/* invalid negative */ ");
1409 /* Regardless, just print the immediate offset */
1411 printf(" + <%d, %d, %d>, ",
1419 char lod_operand
= texture_op_takes_bias(texture
->op
) ? '+' : '=';
1421 if (texture
->lod_register
) {
1422 printf("lod %c ", lod_operand
);
1423 print_texture_reg_select(texture
->bias
, in_reg_base
);
1426 if (texture
->bias_int
)
1427 printf(" /* bias_int = 0x%X */", texture
->bias_int
);
1428 } else if (texture
->op
== TEXTURE_OP_TEXEL_FETCH
) {
1429 /* For texel fetch, the int LOD is in the fractional place and
1430 * there is no fraction / possibility of bias. We *always* have
1431 * an explicit LOD, even if it's zero. */
1433 if (texture
->bias_int
)
1434 printf(" /* bias_int = 0x%X */ ", texture
->bias_int
);
1436 printf("lod = %u, ", texture
->bias
);
1437 } else if (texture
->bias
|| texture
->bias_int
) {
1438 signed bias_int
= texture
->bias_int
;
1439 float bias_frac
= texture
->bias
/ 256.0f
;
1440 float bias
= bias_int
+ bias_frac
;
1442 bool is_bias
= texture_op_takes_bias(texture
->op
);
1443 char sign
= (bias
>= 0.0) ? '+' : '-';
1444 char operand
= is_bias
? sign
: '=';
1446 printf("lod %c %f, ", operand
, fabsf(bias
));
1451 /* While not zero in general, for these simple instructions the
1452 * following unknowns are zero, so we don't include them */
1454 if (texture
->unknown4
||
1455 texture
->unknownA
||
1456 texture
->unknown8
) {
1457 printf("// unknown4 = 0x%x\n", texture
->unknown4
);
1458 printf("// unknownA = 0x%x\n", texture
->unknownA
);
1459 printf("// unknown8 = 0x%x\n", texture
->unknown8
);
1462 midg_stats
.instruction_count
++;
1465 struct midgard_disasm_stats
1466 disassemble_midgard(uint8_t *code
, size_t size
, unsigned gpu_id
, gl_shader_stage stage
)
1468 uint32_t *words
= (uint32_t *) code
;
1469 unsigned num_words
= size
/ 4;
1472 bool prefetch_flag
= false;
1474 int last_next_tag
= -1;
1478 midg_tags
= calloc(sizeof(midg_tags
[0]), num_words
);
1480 /* Stats for shader-db */
1481 memset(&midg_stats
, 0, sizeof(midg_stats
));
1482 midg_ever_written
= 0;
1484 while (i
< num_words
) {
1485 unsigned tag
= words
[i
] & 0xF;
1486 unsigned next_tag
= (words
[i
] >> 4) & 0xF;
1487 unsigned num_quad_words
= midgard_word_size
[tag
];
1489 if (midg_tags
[i
] && midg_tags
[i
] != tag
) {
1490 printf("\t/* XXX: TAG ERROR branch, got ");
1491 print_tag_short(tag
);
1492 printf(" expected ");
1493 print_tag_short(midg_tags
[i
]);
1500 if (last_next_tag
> 1) {
1501 if (last_next_tag
!= tag
) {
1502 printf("\t/* XXX: TAG ERROR sequence, got ");
1503 print_tag_short(tag
);
1504 printf(" expected ");
1505 print_tag_short(last_next_tag
);
1509 /* TODO: Check ALU case */
1512 last_next_tag
= next_tag
;
1514 switch (midgard_word_types
[tag
]) {
1515 case midgard_word_type_texture
: {
1516 bool interpipe_aliasing
=
1517 midgard_get_quirks(gpu_id
) & MIDGARD_INTERPIPE_REG_ALIASING
;
1519 print_texture_word(&words
[i
], tabs
,
1520 interpipe_aliasing
? 0 : REG_TEX_BASE
,
1521 interpipe_aliasing
? REGISTER_LDST_BASE
: REG_TEX_BASE
);
1525 case midgard_word_type_load_store
:
1526 print_load_store_word(&words
[i
], tabs
);
1529 case midgard_word_type_alu
:
1530 print_alu_word(&words
[i
], num_quad_words
, tabs
, i
+ 4*num_quad_words
);
1532 /* Reset word static analysis state */
1533 is_embedded_constant_half
= false;
1534 is_embedded_constant_int
= false;
1539 printf("Unknown word type %u:\n", words
[i
] & 0xF);
1541 print_quad_word(&words
[i
], tabs
);
1546 /* We are parsing per bundle anyway. Add before we start
1547 * breaking out so we don't miss the final bundle. */
1549 midg_stats
.bundle_count
++;
1550 midg_stats
.quadword_count
+= num_quad_words
;
1552 if (prefetch_flag
&& midgard_word_types
[tag
] == midgard_word_type_alu
)
1557 unsigned next
= (words
[i
] & 0xF0) >> 4;
1559 /* Break based on instruction prefetch flag */
1561 if (i
< num_words
&& next
== 1) {
1562 prefetch_flag
= true;
1564 if (midgard_word_types
[words
[i
] & 0xF] != midgard_word_type_alu
)
1568 i
+= 4 * num_quad_words
;
1571 /* We computed work_count as max_work_registers, so add one to get the
1572 * count. If no work registers are written, you still have one work
1573 * reported, which is exactly what the hardware expects */
1575 midg_stats
.work_count
++;