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pan/midgard: Disassemble barrier instructions
[mesa.git] / src / panfrost / midgard / disassemble.c
1 /* Author(s):
2 * Connor Abbott
3 * Alyssa Rosenzweig
4 *
5 * Copyright (c) 2013 Connor Abbott (connor@abbott.cx)
6 * Copyright (c) 2018 Alyssa Rosenzweig (alyssa@rosenzweig.io)
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #include <stdio.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <assert.h>
31 #include <inttypes.h>
32 #include <ctype.h>
33 #include <string.h>
34 #include "midgard.h"
35 #include "midgard_ops.h"
36 #include "midgard_quirks.h"
37 #include "disassemble.h"
38 #include "helpers.h"
39 #include "util/half_float.h"
40 #include "util/u_math.h"
41
42 #define DEFINE_CASE(define, str) case define: { fprintf(fp, str); break; }
43
44 static unsigned *midg_tags;
45 static bool is_instruction_int = false;
46
47 /* Stats */
48
49 static struct midgard_disasm_stats midg_stats;
50
51 /* Prints a short form of the tag for branching, the minimum needed to be
52 * legible and unambiguous */
53
54 static void
55 print_tag_short(FILE *fp, unsigned tag)
56 {
57 switch (midgard_word_types[tag]) {
58 case midgard_word_type_texture:
59 fprintf(fp, "tex/%X", tag);
60 break;
61
62 case midgard_word_type_load_store:
63 fprintf(fp, "ldst");
64 break;
65
66 case midgard_word_type_alu:
67 fprintf(fp, "alu%u/%X", midgard_word_size[tag], tag);
68 break;
69
70 default:
71 fprintf(fp, "%s%X", (tag > 0) ? "" : "unk", tag);
72 break;
73 }
74 }
75
76 static void
77 print_alu_opcode(FILE *fp, midgard_alu_op op)
78 {
79 bool int_op = false;
80
81 if (alu_opcode_props[op].name) {
82 fprintf(fp, "%s", alu_opcode_props[op].name);
83
84 int_op = midgard_is_integer_op(op);
85 } else
86 fprintf(fp, "alu_op_%02X", op);
87
88 /* For constant analysis */
89 is_instruction_int = int_op;
90 }
91
92 static void
93 print_ld_st_opcode(FILE *fp, midgard_load_store_op op)
94 {
95 if (load_store_opcode_props[op].name)
96 fprintf(fp, "%s", load_store_opcode_props[op].name);
97 else
98 fprintf(fp, "ldst_op_%02X", op);
99 }
100
101 static bool is_embedded_constant_half = false;
102 static bool is_embedded_constant_int = false;
103
104 static char
105 prefix_for_bits(unsigned bits)
106 {
107 switch (bits) {
108 case 8:
109 return 'q';
110 case 16:
111 return 'h';
112 case 64:
113 return 'd';
114 default:
115 return 0;
116 }
117 }
118
119 /* For static analysis to ensure all registers are written at least once before
120 * use along the source code path (TODO: does this break done for complex CF?)
121 */
122
123 uint16_t midg_ever_written = 0;
124
125 static void
126 print_reg(FILE *fp, unsigned reg, unsigned bits)
127 {
128 /* Perform basic static analysis for expanding constants correctly */
129
130 if (reg == 26) {
131 is_embedded_constant_int = is_instruction_int;
132 is_embedded_constant_half = (bits < 32);
133 }
134
135 unsigned uniform_reg = 23 - reg;
136 bool is_uniform = false;
137
138 /* For r8-r15, it could be a work or uniform. We distinguish based on
139 * the fact work registers are ALWAYS written before use, but uniform
140 * registers are NEVER written before use. */
141
142 if ((reg >= 8 && reg < 16) && !(midg_ever_written & (1 << reg)))
143 is_uniform = true;
144
145 /* r16-r23 are always uniform */
146
147 if (reg >= 16 && reg <= 23)
148 is_uniform = true;
149
150 /* Update the uniform count appropriately */
151
152 if (is_uniform)
153 midg_stats.uniform_count =
154 MAX2(uniform_reg + 1, midg_stats.uniform_count);
155
156 char prefix = prefix_for_bits(bits);
157
158 if (prefix)
159 putchar(prefix);
160
161 fprintf(fp, "r%u", reg);
162 }
163
164 static char *outmod_names_float[4] = {
165 "",
166 ".pos",
167 ".unk2",
168 ".sat"
169 };
170
171 static char *outmod_names_int[4] = {
172 ".isat",
173 ".usat",
174 "",
175 ".hi"
176 };
177
178 static char *srcmod_names_int[4] = {
179 "sext(",
180 "zext(",
181 "",
182 "("
183 };
184
185 static void
186 print_outmod(FILE *fp, unsigned outmod, bool is_int)
187 {
188 fprintf(fp, "%s", is_int ? outmod_names_int[outmod] :
189 outmod_names_float[outmod]);
190 }
191
192 static void
193 print_quad_word(FILE *fp, uint32_t *words, unsigned tabs)
194 {
195 unsigned i;
196
197 for (i = 0; i < 4; i++)
198 fprintf(fp, "0x%08X%s ", words[i], i == 3 ? "" : ",");
199
200 fprintf(fp, "\n");
201 }
202
203 static const char components[16] = "xyzwefghijklmnop";
204
205 /* Helper to print 4 chars of a swizzle */
206 static void
207 print_swizzle_helper(FILE *fp, unsigned swizzle, bool upper)
208 {
209 for (unsigned i = 0; i < 4; ++i) {
210 unsigned c = (swizzle >> (i * 2)) & 3;
211 c += upper*4;
212 fprintf(fp, "%c", components[c]);
213 }
214 }
215
216 /* Helper to print 8 chars of a swizzle, duplicating over */
217 static void
218 print_swizzle_helper_8(FILE *fp, unsigned swizzle, bool upper)
219 {
220 for (unsigned i = 0; i < 4; ++i) {
221 unsigned c = (swizzle >> (i * 2)) & 3;
222 c *= 2;
223 c += upper*8;
224 fprintf(fp, "%c%c", components[c], components[c+1]);
225 }
226 }
227
228 static void
229 print_swizzle_vec16(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low,
230 midgard_dest_override override)
231 {
232 fprintf(fp, ".");
233
234 if (override == midgard_dest_override_upper) {
235 if (rep_high)
236 fprintf(fp, " /* rep_high */ ");
237 if (rep_low)
238 fprintf(fp, " /* rep_low */ ");
239
240 if (!rep_high && rep_low)
241 print_swizzle_helper_8(fp, swizzle, true);
242 else
243 print_swizzle_helper_8(fp, swizzle, false);
244 } else {
245 print_swizzle_helper_8(fp, swizzle, rep_high & 1);
246 print_swizzle_helper_8(fp, swizzle, !(rep_low & 1));
247 }
248 }
249
250 static void
251 print_swizzle_vec8(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low)
252 {
253 fprintf(fp, ".");
254
255 print_swizzle_helper(fp, swizzle, rep_high & 1);
256 print_swizzle_helper(fp, swizzle, !(rep_low & 1));
257 }
258
259 static void
260 print_swizzle_vec4(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low)
261 {
262 if (rep_high)
263 fprintf(fp, " /* rep_high */ ");
264 if (rep_low)
265 fprintf(fp, " /* rep_low */ ");
266
267 if (swizzle == 0xE4) return; /* xyzw */
268
269 fprintf(fp, ".");
270 print_swizzle_helper(fp, swizzle, 0);
271 }
272 static void
273 print_swizzle_vec2(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low)
274 {
275 if (rep_high)
276 fprintf(fp, " /* rep_high */ ");
277 if (rep_low)
278 fprintf(fp, " /* rep_low */ ");
279
280 if (swizzle == 0xE4) return; /* XY */
281
282 fprintf(fp, ".");
283
284 for (unsigned i = 0; i < 4; i += 2) {
285 unsigned a = (swizzle >> (i * 2)) & 3;
286 unsigned b = (swizzle >> ((i+1) * 2)) & 3;
287
288 /* Normally we're adjacent, but if there's an issue, don't make
289 * it ambiguous */
290
291 if (a & 0x1)
292 fprintf(fp, "[%c%c]", components[a], components[b]);
293 else if (a == b)
294 fprintf(fp, "%c", components[a >> 1]);
295 else if (b == (a + 1))
296 fprintf(fp, "%c", "XY"[a >> 1]);
297 else
298 fprintf(fp, "[%c%c]", components[a], components[b]);
299 }
300 }
301
302 static int
303 bits_for_mode(midgard_reg_mode mode)
304 {
305 switch (mode) {
306 case midgard_reg_mode_8:
307 return 8;
308 case midgard_reg_mode_16:
309 return 16;
310 case midgard_reg_mode_32:
311 return 32;
312 case midgard_reg_mode_64:
313 return 64;
314 default:
315 unreachable("Invalid reg mode");
316 return 0;
317 }
318 }
319
320 static int
321 bits_for_mode_halved(midgard_reg_mode mode, bool half)
322 {
323 unsigned bits = bits_for_mode(mode);
324
325 if (half)
326 bits >>= 1;
327
328 return bits;
329 }
330
331 static void
332 print_vector_src(FILE *fp, unsigned src_binary,
333 midgard_reg_mode mode, unsigned reg,
334 midgard_dest_override override, bool is_int)
335 {
336 midgard_vector_alu_src *src = (midgard_vector_alu_src *)&src_binary;
337
338 /* Modifiers change meaning depending on the op's context */
339
340 midgard_int_mod int_mod = src->mod;
341
342 if (is_int) {
343 fprintf(fp, "%s", srcmod_names_int[int_mod]);
344 } else {
345 if (src->mod & MIDGARD_FLOAT_MOD_NEG)
346 fprintf(fp, "-");
347
348 if (src->mod & MIDGARD_FLOAT_MOD_ABS)
349 fprintf(fp, "abs(");
350 }
351
352 //register
353 unsigned bits = bits_for_mode_halved(mode, src->half);
354 print_reg(fp, reg, bits);
355
356 //swizzle
357 if (bits == 16) {
358 /* When the mode of the instruction is itself 16-bit,
359 * rep_low/high work more or less as expected. But if the mode
360 * is 32-bit and we're stepping down, you only have vec4 and
361 * the meaning shifts to rep_low as higher-half and rep_high is
362 * never seen. TODO: are other modes similar? */
363
364 if (mode == midgard_reg_mode_32) {
365 fprintf(fp, ".");
366 print_swizzle_helper(fp, src->swizzle, src->rep_low);
367 assert(!src->rep_high);
368 } else {
369 print_swizzle_vec8(fp, src->swizzle, src->rep_high, src->rep_low);
370 }
371 } else if (bits == 8)
372 print_swizzle_vec16(fp, src->swizzle, src->rep_high, src->rep_low, override);
373 else if (bits == 32)
374 print_swizzle_vec4(fp, src->swizzle, src->rep_high, src->rep_low);
375 else if (bits == 64)
376 print_swizzle_vec2(fp, src->swizzle, src->rep_high, src->rep_low);
377
378 /* Since we wrapped with a function-looking thing */
379
380 if (is_int && int_mod == midgard_int_shift)
381 fprintf(fp, ") << %u", bits);
382 else if ((is_int && (int_mod != midgard_int_normal))
383 || (!is_int && src->mod & MIDGARD_FLOAT_MOD_ABS))
384 fprintf(fp, ")");
385 }
386
387 static uint16_t
388 decode_vector_imm(unsigned src2_reg, unsigned imm)
389 {
390 uint16_t ret;
391 ret = src2_reg << 11;
392 ret |= (imm & 0x7) << 8;
393 ret |= (imm >> 3) & 0xFF;
394 return ret;
395 }
396
397 static void
398 print_immediate(FILE *fp, uint16_t imm)
399 {
400 if (is_instruction_int)
401 fprintf(fp, "#%u", imm);
402 else
403 fprintf(fp, "#%g", _mesa_half_to_float(imm));
404 }
405
406 static void
407 update_dest(unsigned reg)
408 {
409 /* We should record writes as marking this as a work register. Store
410 * the max register in work_count; we'll add one at the end */
411
412 if (reg < 16) {
413 midg_stats.work_count = MAX2(reg, midg_stats.work_count);
414 midg_ever_written |= (1 << reg);
415 }
416 }
417
418 static void
419 print_dest(FILE *fp, unsigned reg, midgard_reg_mode mode, midgard_dest_override override)
420 {
421 /* Depending on the mode and override, we determine the type of
422 * destination addressed. Absent an override, we address just the
423 * type of the operation itself */
424
425 unsigned bits = bits_for_mode(mode);
426
427 if (override != midgard_dest_override_none)
428 bits /= 2;
429
430 update_dest(reg);
431 print_reg(fp, reg, bits);
432 }
433
434 static void
435 print_mask_vec16(FILE *fp, uint8_t mask, midgard_dest_override override)
436 {
437 fprintf(fp, ".");
438
439 for (unsigned i = 0; i < 8; i++) {
440 if (mask & (1 << i))
441 fprintf(fp, "%c%c",
442 components[i*2 + 0],
443 components[i*2 + 1]);
444 }
445 }
446
447 /* For 16-bit+ masks, we read off from the 8-bit mask field. For 16-bit (vec8),
448 * it's just one bit per channel, easy peasy. For 32-bit (vec4), it's one bit
449 * per channel with one duplicate bit in the middle. For 64-bit (vec2), it's
450 * one-bit per channel with _3_ duplicate bits in the middle. Basically, just
451 * subdividing the 128-bit word in 16-bit increments. For 64-bit, we uppercase
452 * the mask to make it obvious what happened */
453
454 static void
455 print_mask(FILE *fp, uint8_t mask, unsigned bits, midgard_dest_override override)
456 {
457 if (bits == 8) {
458 print_mask_vec16(fp, mask, override);
459 return;
460 }
461
462 /* Skip 'complete' masks */
463
464 if (override == midgard_dest_override_none) {
465 if (bits >= 32 && mask == 0xFF) return;
466
467 if (bits == 16) {
468 if (mask == 0x0F)
469 return;
470 else if (mask == 0xF0) {
471 fprintf(fp, "'");
472 return;
473 }
474 }
475 }
476
477 fprintf(fp, ".");
478
479 unsigned skip = (bits / 16);
480 bool uppercase = bits > 32;
481 bool tripped = false;
482
483 /* To apply an upper destination override, we "shift" the alphabet.
484 * E.g. with an upper override on 32-bit, instead of xyzw, print efgh.
485 * For upper 16-bit, instead of xyzwefgh, print ijklmnop */
486
487 const char *alphabet = components;
488
489 if (override == midgard_dest_override_upper)
490 alphabet += (128 / bits);
491
492 for (unsigned i = 0; i < 8; i += skip) {
493 bool a = (mask & (1 << i)) != 0;
494
495 for (unsigned j = 1; j < skip; ++j) {
496 bool dupe = (mask & (1 << (i + j))) != 0;
497 tripped |= (dupe != a);
498 }
499
500 if (a) {
501 char c = alphabet[i / skip];
502
503 if (uppercase)
504 c = toupper(c);
505
506 fprintf(fp, "%c", c);
507 }
508 }
509
510 if (tripped)
511 fprintf(fp, " /* %X */", mask);
512 }
513
514 /* Prints the 4-bit masks found in texture and load/store ops, as opposed to
515 * the 8-bit masks found in (vector) ALU ops. Supports texture-style 16-bit
516 * mode as well, but not load/store-style 16-bit mode. */
517
518 static void
519 print_mask_4(FILE *fp, unsigned mask, bool upper)
520 {
521 if (mask == 0xF) {
522 if (upper)
523 fprintf(fp, "'");
524
525 return;
526 }
527
528 fprintf(fp, ".");
529
530 for (unsigned i = 0; i < 4; ++i) {
531 bool a = (mask & (1 << i)) != 0;
532 if (a)
533 fprintf(fp, "%c", components[i + (upper ? 4 : 0)]);
534 }
535 }
536
537 static void
538 print_vector_field(FILE *fp, const char *name, uint16_t *words, uint16_t reg_word,
539 unsigned tabs)
540 {
541 midgard_reg_info *reg_info = (midgard_reg_info *)&reg_word;
542 midgard_vector_alu *alu_field = (midgard_vector_alu *) words;
543 midgard_reg_mode mode = alu_field->reg_mode;
544 unsigned override = alu_field->dest_override;
545
546 /* For now, prefix instruction names with their unit, until we
547 * understand how this works on a deeper level */
548 fprintf(fp, "%s.", name);
549
550 print_alu_opcode(fp, alu_field->op);
551
552 /* Postfix with the size to disambiguate if necessary */
553 char postfix = prefix_for_bits(bits_for_mode(mode));
554 bool size_ambiguous = override != midgard_dest_override_none;
555
556 if (size_ambiguous)
557 fprintf(fp, "%c", postfix ? postfix : 'r');
558
559 /* Print the outmod, if there is one */
560 print_outmod(fp, alu_field->outmod,
561 midgard_is_integer_out_op(alu_field->op));
562
563 fprintf(fp, " ");
564
565 /* Mask denoting status of 8-lanes */
566 uint8_t mask = alu_field->mask;
567
568 /* First, print the destination */
569 print_dest(fp, reg_info->out_reg, mode, alu_field->dest_override);
570
571 if (override != midgard_dest_override_none) {
572 bool modeable = (mode != midgard_reg_mode_8);
573 bool known = override != 0x3; /* Unused value */
574
575 if (!(modeable && known))
576 fprintf(fp, "/* do%u */ ", override);
577 }
578
579 print_mask(fp, mask, bits_for_mode(mode), override);
580
581 fprintf(fp, ", ");
582
583 bool is_int = midgard_is_integer_op(alu_field->op);
584 print_vector_src(fp, alu_field->src1, mode, reg_info->src1_reg, override, is_int);
585
586 fprintf(fp, ", ");
587
588 if (reg_info->src2_imm) {
589 uint16_t imm = decode_vector_imm(reg_info->src2_reg, alu_field->src2 >> 2);
590 print_immediate(fp, imm);
591 } else {
592 print_vector_src(fp, alu_field->src2, mode,
593 reg_info->src2_reg, override, is_int);
594 }
595
596 midg_stats.instruction_count++;
597 fprintf(fp, "\n");
598 }
599
600 static void
601 print_scalar_src(FILE *fp, unsigned src_binary, unsigned reg)
602 {
603 midgard_scalar_alu_src *src = (midgard_scalar_alu_src *)&src_binary;
604
605 if (src->negate)
606 fprintf(fp, "-");
607
608 if (src->abs)
609 fprintf(fp, "abs(");
610
611 print_reg(fp, reg, src->full ? 32 : 16);
612
613 unsigned c = src->component;
614
615 if (src->full) {
616 assert((c & 1) == 0);
617 c >>= 1;
618 }
619
620 fprintf(fp, ".%c", components[c]);
621
622 if (src->abs)
623 fprintf(fp, ")");
624
625 }
626
627 static uint16_t
628 decode_scalar_imm(unsigned src2_reg, unsigned imm)
629 {
630 uint16_t ret;
631 ret = src2_reg << 11;
632 ret |= (imm & 3) << 9;
633 ret |= (imm & 4) << 6;
634 ret |= (imm & 0x38) << 2;
635 ret |= imm >> 6;
636 return ret;
637 }
638
639 static void
640 print_scalar_field(FILE *fp, const char *name, uint16_t *words, uint16_t reg_word,
641 unsigned tabs)
642 {
643 midgard_reg_info *reg_info = (midgard_reg_info *)&reg_word;
644 midgard_scalar_alu *alu_field = (midgard_scalar_alu *) words;
645
646 if (alu_field->unknown)
647 fprintf(fp, "scalar ALU unknown bit set\n");
648
649 fprintf(fp, "%s.", name);
650 print_alu_opcode(fp, alu_field->op);
651 print_outmod(fp, alu_field->outmod,
652 midgard_is_integer_out_op(alu_field->op));
653 fprintf(fp, " ");
654
655 bool full = alu_field->output_full;
656 update_dest(reg_info->out_reg);
657 print_reg(fp, reg_info->out_reg, full ? 32 : 16);
658 unsigned c = alu_field->output_component;
659
660 if (full) {
661 assert((c & 1) == 0);
662 c >>= 1;
663 }
664
665 fprintf(fp, ".%c, ", components[c]);
666
667 print_scalar_src(fp, alu_field->src1, reg_info->src1_reg);
668
669 fprintf(fp, ", ");
670
671 if (reg_info->src2_imm) {
672 uint16_t imm = decode_scalar_imm(reg_info->src2_reg,
673 alu_field->src2);
674 print_immediate(fp, imm);
675 } else
676 print_scalar_src(fp, alu_field->src2, reg_info->src2_reg);
677
678 midg_stats.instruction_count++;
679 fprintf(fp, "\n");
680 }
681
682 static void
683 print_branch_op(FILE *fp, unsigned op)
684 {
685 switch (op) {
686 case midgard_jmp_writeout_op_branch_uncond:
687 fprintf(fp, "uncond.");
688 break;
689
690 case midgard_jmp_writeout_op_branch_cond:
691 fprintf(fp, "cond.");
692 break;
693
694 case midgard_jmp_writeout_op_writeout:
695 fprintf(fp, "write.");
696 break;
697
698 case midgard_jmp_writeout_op_tilebuffer_pending:
699 fprintf(fp, "tilebuffer.");
700 break;
701
702 case midgard_jmp_writeout_op_discard:
703 fprintf(fp, "discard.");
704 break;
705
706 default:
707 fprintf(fp, "unk%u.", op);
708 break;
709 }
710 }
711
712 static void
713 print_branch_cond(FILE *fp, int cond)
714 {
715 switch (cond) {
716 case midgard_condition_write0:
717 fprintf(fp, "write0");
718 break;
719
720 case midgard_condition_false:
721 fprintf(fp, "false");
722 break;
723
724 case midgard_condition_true:
725 fprintf(fp, "true");
726 break;
727
728 case midgard_condition_always:
729 fprintf(fp, "always");
730 break;
731
732 default:
733 fprintf(fp, "unk%X", cond);
734 break;
735 }
736 }
737
738 static bool
739 print_compact_branch_writeout_field(FILE *fp, uint16_t word)
740 {
741 midgard_jmp_writeout_op op = word & 0x7;
742 midg_stats.instruction_count++;
743
744 switch (op) {
745 case midgard_jmp_writeout_op_branch_uncond: {
746 midgard_branch_uncond br_uncond;
747 memcpy((char *) &br_uncond, (char *) &word, sizeof(br_uncond));
748 fprintf(fp, "br.uncond ");
749
750 if (br_uncond.unknown != 1)
751 fprintf(fp, "unknown:%u, ", br_uncond.unknown);
752
753 if (br_uncond.offset >= 0)
754 fprintf(fp, "+");
755
756 fprintf(fp, "%d -> ", br_uncond.offset);
757 print_tag_short(fp, br_uncond.dest_tag);
758 fprintf(fp, "\n");
759
760 return br_uncond.offset >= 0;
761 }
762
763 case midgard_jmp_writeout_op_branch_cond:
764 case midgard_jmp_writeout_op_writeout:
765 case midgard_jmp_writeout_op_discard:
766 default: {
767 midgard_branch_cond br_cond;
768 memcpy((char *) &br_cond, (char *) &word, sizeof(br_cond));
769
770 fprintf(fp, "br.");
771
772 print_branch_op(fp, br_cond.op);
773 print_branch_cond(fp, br_cond.cond);
774
775 fprintf(fp, " ");
776
777 if (br_cond.offset >= 0)
778 fprintf(fp, "+");
779
780 fprintf(fp, "%d -> ", br_cond.offset);
781 print_tag_short(fp, br_cond.dest_tag);
782 fprintf(fp, "\n");
783
784 return br_cond.offset >= 0;
785 }
786 }
787
788 return false;
789 }
790
791 static bool
792 print_extended_branch_writeout_field(FILE *fp, uint8_t *words, unsigned next)
793 {
794 midgard_branch_extended br;
795 memcpy((char *) &br, (char *) words, sizeof(br));
796
797 fprintf(fp, "brx.");
798
799 print_branch_op(fp, br.op);
800
801 /* Condition codes are a LUT in the general case, but simply repeated 8 times for single-channel conditions.. Check this. */
802
803 bool single_channel = true;
804
805 for (unsigned i = 0; i < 16; i += 2) {
806 single_channel &= (((br.cond >> i) & 0x3) == (br.cond & 0x3));
807 }
808
809 if (single_channel)
810 print_branch_cond(fp, br.cond & 0x3);
811 else
812 fprintf(fp, "lut%X", br.cond);
813
814 if (br.unknown)
815 fprintf(fp, ".unknown%u", br.unknown);
816
817 fprintf(fp, " ");
818
819 if (br.offset >= 0)
820 fprintf(fp, "+");
821
822 fprintf(fp, "%d -> ", br.offset);
823 print_tag_short(fp, br.dest_tag);
824 fprintf(fp, "\n");
825
826 unsigned I = next + br.offset * 4;
827
828 if (midg_tags[I] && midg_tags[I] != br.dest_tag) {
829 fprintf(fp, "\t/* XXX TAG ERROR: jumping to ");
830 print_tag_short(fp, br.dest_tag);
831 fprintf(fp, " but tagged ");
832 print_tag_short(fp, midg_tags[I]);
833 fprintf(fp, " */\n");
834 }
835
836 midg_tags[I] = br.dest_tag;
837
838 midg_stats.instruction_count++;
839 return br.offset >= 0;
840 }
841
842 static unsigned
843 num_alu_fields_enabled(uint32_t control_word)
844 {
845 unsigned ret = 0;
846
847 if ((control_word >> 17) & 1)
848 ret++;
849
850 if ((control_word >> 19) & 1)
851 ret++;
852
853 if ((control_word >> 21) & 1)
854 ret++;
855
856 if ((control_word >> 23) & 1)
857 ret++;
858
859 if ((control_word >> 25) & 1)
860 ret++;
861
862 return ret;
863 }
864
865 static float
866 float_bitcast(uint32_t integer)
867 {
868 union {
869 uint32_t i;
870 float f;
871 } v;
872
873 v.i = integer;
874 return v.f;
875 }
876
877 static bool
878 print_alu_word(FILE *fp, uint32_t *words, unsigned num_quad_words,
879 unsigned tabs, unsigned next)
880 {
881 uint32_t control_word = words[0];
882 uint16_t *beginning_ptr = (uint16_t *)(words + 1);
883 unsigned num_fields = num_alu_fields_enabled(control_word);
884 uint16_t *word_ptr = beginning_ptr + num_fields;
885 unsigned num_words = 2 + num_fields;
886 bool branch_forward = false;
887
888 if ((control_word >> 16) & 1)
889 fprintf(fp, "unknown bit 16 enabled\n");
890
891 if ((control_word >> 17) & 1) {
892 print_vector_field(fp, "vmul", word_ptr, *beginning_ptr, tabs);
893 beginning_ptr += 1;
894 word_ptr += 3;
895 num_words += 3;
896 }
897
898 if ((control_word >> 18) & 1)
899 fprintf(fp, "unknown bit 18 enabled\n");
900
901 if ((control_word >> 19) & 1) {
902 print_scalar_field(fp, "sadd", word_ptr, *beginning_ptr, tabs);
903 beginning_ptr += 1;
904 word_ptr += 2;
905 num_words += 2;
906 }
907
908 if ((control_word >> 20) & 1)
909 fprintf(fp, "unknown bit 20 enabled\n");
910
911 if ((control_word >> 21) & 1) {
912 print_vector_field(fp, "vadd", word_ptr, *beginning_ptr, tabs);
913 beginning_ptr += 1;
914 word_ptr += 3;
915 num_words += 3;
916 }
917
918 if ((control_word >> 22) & 1)
919 fprintf(fp, "unknown bit 22 enabled\n");
920
921 if ((control_word >> 23) & 1) {
922 print_scalar_field(fp, "smul", word_ptr, *beginning_ptr, tabs);
923 beginning_ptr += 1;
924 word_ptr += 2;
925 num_words += 2;
926 }
927
928 if ((control_word >> 24) & 1)
929 fprintf(fp, "unknown bit 24 enabled\n");
930
931 if ((control_word >> 25) & 1) {
932 print_vector_field(fp, "lut", word_ptr, *beginning_ptr, tabs);
933 word_ptr += 3;
934 num_words += 3;
935 }
936
937 if ((control_word >> 26) & 1) {
938 branch_forward |= print_compact_branch_writeout_field(fp, *word_ptr);
939 word_ptr += 1;
940 num_words += 1;
941 }
942
943 if ((control_word >> 27) & 1) {
944 branch_forward |= print_extended_branch_writeout_field(fp, (uint8_t *) word_ptr, next);
945 word_ptr += 3;
946 num_words += 3;
947 }
948
949 if (num_quad_words > (num_words + 7) / 8) {
950 assert(num_quad_words == (num_words + 15) / 8);
951 //Assume that the extra quadword is constants
952 void *consts = words + (4 * num_quad_words - 4);
953
954 if (is_embedded_constant_int) {
955 if (is_embedded_constant_half) {
956 int16_t *sconsts = (int16_t *) consts;
957 fprintf(fp, "sconstants %d, %d, %d, %d\n",
958 sconsts[0],
959 sconsts[1],
960 sconsts[2],
961 sconsts[3]);
962 } else {
963 uint32_t *iconsts = (uint32_t *) consts;
964 fprintf(fp, "iconstants 0x%X, 0x%X, 0x%X, 0x%X\n",
965 iconsts[0],
966 iconsts[1],
967 iconsts[2],
968 iconsts[3]);
969 }
970 } else {
971 if (is_embedded_constant_half) {
972 uint16_t *hconsts = (uint16_t *) consts;
973 fprintf(fp, "hconstants %g, %g, %g, %g\n",
974 _mesa_half_to_float(hconsts[0]),
975 _mesa_half_to_float(hconsts[1]),
976 _mesa_half_to_float(hconsts[2]),
977 _mesa_half_to_float(hconsts[3]));
978 } else {
979 uint32_t *fconsts = (uint32_t *) consts;
980 fprintf(fp, "fconstants %g, %g, %g, %g\n",
981 float_bitcast(fconsts[0]),
982 float_bitcast(fconsts[1]),
983 float_bitcast(fconsts[2]),
984 float_bitcast(fconsts[3]));
985 }
986
987 }
988 }
989
990 return branch_forward;
991 }
992
993 static void
994 print_varying_parameters(FILE *fp, midgard_load_store_word *word)
995 {
996 midgard_varying_parameter param;
997 unsigned v = word->varying_parameters;
998 memcpy(&param, &v, sizeof(param));
999
1000 if (param.is_varying) {
1001 /* If a varying, there are qualifiers */
1002 if (param.flat)
1003 fprintf(fp, ".flat");
1004
1005 if (param.interpolation != midgard_interp_default) {
1006 if (param.interpolation == midgard_interp_centroid)
1007 fprintf(fp, ".centroid");
1008 else
1009 fprintf(fp, ".interp%d", param.interpolation);
1010 }
1011
1012 if (param.modifier != midgard_varying_mod_none) {
1013 if (param.modifier == midgard_varying_mod_perspective_w)
1014 fprintf(fp, ".perspectivew");
1015 else if (param.modifier == midgard_varying_mod_perspective_z)
1016 fprintf(fp, ".perspectivez");
1017 else
1018 fprintf(fp, ".mod%d", param.modifier);
1019 }
1020 } else if (param.flat || param.interpolation || param.modifier) {
1021 fprintf(fp, " /* is_varying not set but varying metadata attached */");
1022 }
1023
1024 if (param.zero0 || param.zero1 || param.zero2)
1025 fprintf(fp, " /* zero tripped, %u %u %u */ ", param.zero0, param.zero1, param.zero2);
1026 }
1027
1028 static bool
1029 is_op_varying(unsigned op)
1030 {
1031 switch (op) {
1032 case midgard_op_st_vary_16:
1033 case midgard_op_st_vary_32:
1034 case midgard_op_st_vary_32i:
1035 case midgard_op_st_vary_32u:
1036 case midgard_op_ld_vary_16:
1037 case midgard_op_ld_vary_32:
1038 case midgard_op_ld_vary_32i:
1039 case midgard_op_ld_vary_32u:
1040 return true;
1041 }
1042
1043 return false;
1044 }
1045
1046 static bool
1047 is_op_attribute(unsigned op)
1048 {
1049 switch (op) {
1050 case midgard_op_ld_attr_16:
1051 case midgard_op_ld_attr_32:
1052 case midgard_op_ld_attr_32i:
1053 case midgard_op_ld_attr_32u:
1054 return true;
1055 }
1056
1057 return false;
1058 }
1059
1060 static void
1061 print_load_store_arg(FILE *fp, uint8_t arg, unsigned index)
1062 {
1063 /* Try to interpret as a register */
1064 midgard_ldst_register_select sel;
1065 memcpy(&sel, &arg, sizeof(arg));
1066
1067 /* If unknown is set, we're not sure what this is or how to
1068 * interpret it. But if it's zero, we get it. */
1069
1070 if (sel.unknown) {
1071 fprintf(fp, "0x%02X", arg);
1072 return;
1073 }
1074
1075 unsigned reg = REGISTER_LDST_BASE + sel.select;
1076 char comp = components[sel.component];
1077
1078 fprintf(fp, "r%u.%c", reg, comp);
1079
1080 /* Only print a shift if it's non-zero. Shifts only make sense for the
1081 * second index. For the first, we're not sure what it means yet */
1082
1083 if (index == 1) {
1084 if (sel.shift)
1085 fprintf(fp, " << %u", sel.shift);
1086 } else {
1087 fprintf(fp, " /* %X */", sel.shift);
1088 }
1089 }
1090
1091 static void
1092 update_stats(signed *stat, unsigned address)
1093 {
1094 if (*stat >= 0)
1095 *stat = MAX2(*stat, address + 1);
1096 }
1097
1098 static void
1099 print_load_store_instr(FILE *fp, uint64_t data,
1100 unsigned tabs)
1101 {
1102 midgard_load_store_word *word = (midgard_load_store_word *) &data;
1103
1104 print_ld_st_opcode(fp, word->op);
1105
1106 unsigned address = word->address;
1107
1108 if (is_op_varying(word->op)) {
1109 print_varying_parameters(fp, word);
1110
1111 /* Do some analysis: check if direct cacess */
1112
1113 if ((word->arg_2 == 0x1E) && midg_stats.varying_count >= 0)
1114 update_stats(&midg_stats.varying_count, address);
1115 else
1116 midg_stats.varying_count = -16;
1117 } else if (is_op_attribute(word->op)) {
1118 if ((word->arg_2 == 0x1E) && midg_stats.attribute_count >= 0)
1119 update_stats(&midg_stats.attribute_count, address);
1120 else
1121 midg_stats.attribute_count = -16;
1122 }
1123
1124 fprintf(fp, " r%u", word->reg + (OP_IS_STORE(word->op) ? 26 : 0));
1125 print_mask_4(fp, word->mask, false);
1126
1127 if (!OP_IS_STORE(word->op))
1128 update_dest(word->reg);
1129
1130 bool is_ubo = OP_IS_UBO_READ(word->op);
1131
1132 if (is_ubo) {
1133 /* UBOs use their own addressing scheme */
1134
1135 int lo = word->varying_parameters >> 7;
1136 int hi = word->address;
1137
1138 /* TODO: Combine fields logically */
1139 address = (hi << 3) | lo;
1140 }
1141
1142 fprintf(fp, ", %u", address);
1143
1144 print_swizzle_vec4(fp, word->swizzle, false, false);
1145
1146 fprintf(fp, ", ");
1147
1148 if (is_ubo) {
1149 fprintf(fp, "ubo%u", word->arg_1);
1150 update_stats(&midg_stats.uniform_buffer_count, word->arg_1);
1151 } else
1152 print_load_store_arg(fp, word->arg_1, 0);
1153
1154 fprintf(fp, ", ");
1155 print_load_store_arg(fp, word->arg_2, 1);
1156 fprintf(fp, " /* %X */\n", word->varying_parameters);
1157
1158 midg_stats.instruction_count++;
1159 }
1160
1161 static void
1162 print_load_store_word(FILE *fp, uint32_t *word, unsigned tabs)
1163 {
1164 midgard_load_store *load_store = (midgard_load_store *) word;
1165
1166 if (load_store->word1 != 3) {
1167 print_load_store_instr(fp, load_store->word1, tabs);
1168 }
1169
1170 if (load_store->word2 != 3) {
1171 print_load_store_instr(fp, load_store->word2, tabs);
1172 }
1173 }
1174
1175 static void
1176 print_texture_reg_select(FILE *fp, uint8_t u, unsigned base)
1177 {
1178 midgard_tex_register_select sel;
1179 memcpy(&sel, &u, sizeof(u));
1180
1181 if (!sel.full)
1182 fprintf(fp, "h");
1183
1184 fprintf(fp, "r%u", base + sel.select);
1185
1186 unsigned component = sel.component;
1187
1188 /* Use the upper half in half-reg mode */
1189 if (sel.upper) {
1190 assert(!sel.full);
1191 component += 4;
1192 }
1193
1194 fprintf(fp, ".%c", components[component]);
1195
1196 assert(sel.zero == 0);
1197 }
1198
1199 static void
1200 print_texture_format(FILE *fp, int format)
1201 {
1202 /* Act like a modifier */
1203 fprintf(fp, ".");
1204
1205 switch (format) {
1206 DEFINE_CASE(MALI_TEX_1D, "1d");
1207 DEFINE_CASE(MALI_TEX_2D, "2d");
1208 DEFINE_CASE(MALI_TEX_3D, "3d");
1209 DEFINE_CASE(MALI_TEX_CUBE, "cube");
1210
1211 default:
1212 unreachable("Bad format");
1213 }
1214 }
1215
1216 static bool
1217 midgard_op_has_helpers(unsigned op, bool gather)
1218 {
1219 if (gather)
1220 return true;
1221
1222 switch (op) {
1223 case TEXTURE_OP_NORMAL:
1224 case TEXTURE_OP_DFDX:
1225 case TEXTURE_OP_DFDY:
1226 return true;
1227 default:
1228 return false;
1229 }
1230 }
1231
1232 static void
1233 print_texture_op(FILE *fp, unsigned op, bool gather)
1234 {
1235 /* Act like a bare name, like ESSL functions */
1236
1237 if (gather) {
1238 fprintf(fp, "textureGather");
1239
1240 unsigned component = op >> 4;
1241 unsigned bottom = op & 0xF;
1242
1243 if (bottom != 0x2)
1244 fprintf(fp, "_unk%u", bottom);
1245
1246 fprintf(fp, ".%c", components[component]);
1247 return;
1248 }
1249
1250 switch (op) {
1251 DEFINE_CASE(TEXTURE_OP_NORMAL, "texture");
1252 DEFINE_CASE(TEXTURE_OP_LOD, "textureLod");
1253 DEFINE_CASE(TEXTURE_OP_TEXEL_FETCH, "texelFetch");
1254 DEFINE_CASE(TEXTURE_OP_BARRIER, "barrier");
1255 DEFINE_CASE(TEXTURE_OP_DFDX, "dFdx");
1256 DEFINE_CASE(TEXTURE_OP_DFDY, "dFdy");
1257
1258 default:
1259 fprintf(fp, "tex_%X", op);
1260 break;
1261 }
1262 }
1263
1264 static bool
1265 texture_op_takes_bias(unsigned op)
1266 {
1267 return op == TEXTURE_OP_NORMAL;
1268 }
1269
1270 static char
1271 sampler_type_name(enum mali_sampler_type t)
1272 {
1273 switch (t) {
1274 case MALI_SAMPLER_FLOAT:
1275 return 'f';
1276 case MALI_SAMPLER_UNSIGNED:
1277 return 'u';
1278 case MALI_SAMPLER_SIGNED:
1279 return 'i';
1280 default:
1281 return '?';
1282 }
1283
1284 }
1285
1286 static void
1287 print_texture_barrier(FILE *fp, uint32_t *word)
1288 {
1289 midgard_texture_barrier_word *barrier = (midgard_texture_barrier_word *) word;
1290
1291 if (!barrier->cont)
1292 fprintf(fp, "/* cont missing? */");
1293
1294 if (!barrier->last)
1295 fprintf(fp, "/* last missing? */");
1296
1297 if (barrier->zero1)
1298 fprintf(fp, "/* zero1 = 0x%X */ ", barrier->zero1);
1299
1300 if (barrier->zero2)
1301 fprintf(fp, "/* zero2 = 0x%X */ ", barrier->zero2);
1302
1303 if (barrier->zero3)
1304 fprintf(fp, "/* zero3 = 0x%X */ ", barrier->zero3);
1305
1306 if (barrier->zero4)
1307 fprintf(fp, "/* zero4 = 0x%X */ ", barrier->zero4);
1308
1309 if (barrier->zero5)
1310 fprintf(fp, "/* zero4 = 0x%" PRIx64 " */ ", barrier->zero5);
1311
1312 fprintf(fp, " 0x%X\n", barrier->unknown4);
1313 }
1314
1315 #undef DEFINE_CASE
1316
1317 static void
1318 print_texture_word(FILE *fp, uint32_t *word, unsigned tabs, unsigned in_reg_base, unsigned out_reg_base)
1319 {
1320 midgard_texture_word *texture = (midgard_texture_word *) word;
1321
1322 midg_stats.helper_invocations |=
1323 midgard_op_has_helpers(texture->op, texture->is_gather);
1324
1325 /* Broad category of texture operation in question */
1326 print_texture_op(fp, texture->op, texture->is_gather);
1327
1328 /* Barriers use a dramatically different code path */
1329 if (texture->op == TEXTURE_OP_BARRIER) {
1330 print_texture_barrier(fp, word);
1331 return;
1332 }
1333
1334 /* Specific format in question */
1335 print_texture_format(fp, texture->format);
1336
1337 /* Instruction "modifiers" parallel the ALU instructions. */
1338
1339 if (texture->shadow)
1340 fprintf(fp, ".shadow");
1341
1342 if (texture->cont)
1343 fprintf(fp, ".cont");
1344
1345 if (texture->last)
1346 fprintf(fp, ".last");
1347
1348 /* Output modifiers are always interpreted floatly */
1349 print_outmod(fp, texture->outmod, false);
1350
1351 fprintf(fp, " %sr%u", texture->out_full ? "" : "h",
1352 out_reg_base + texture->out_reg_select);
1353 print_mask_4(fp, texture->mask, texture->out_upper);
1354 assert(!(texture->out_full && texture->out_upper));
1355 fprintf(fp, ", ");
1356
1357 /* Depending on whether we read from textures directly or indirectly,
1358 * we may be able to update our analysis */
1359
1360 if (texture->texture_register) {
1361 fprintf(fp, "texture[");
1362 print_texture_reg_select(fp, texture->texture_handle, in_reg_base);
1363 fprintf(fp, "], ");
1364
1365 /* Indirect, tut tut */
1366 midg_stats.texture_count = -16;
1367 } else {
1368 fprintf(fp, "texture%u, ", texture->texture_handle);
1369 update_stats(&midg_stats.texture_count, texture->texture_handle);
1370 }
1371
1372 /* Print the type, GL style */
1373 fprintf(fp, "%csampler", sampler_type_name(texture->sampler_type));
1374
1375 if (texture->sampler_register) {
1376 fprintf(fp, "[");
1377 print_texture_reg_select(fp, texture->sampler_handle, in_reg_base);
1378 fprintf(fp, "]");
1379
1380 midg_stats.sampler_count = -16;
1381 } else {
1382 fprintf(fp, "%u", texture->sampler_handle);
1383 update_stats(&midg_stats.sampler_count, texture->sampler_handle);
1384 }
1385
1386 print_swizzle_vec4(fp, texture->swizzle, false, false);
1387 fprintf(fp, ", %sr%u", texture->in_reg_full ? "" : "h", in_reg_base + texture->in_reg_select);
1388 assert(!(texture->in_reg_full && texture->in_reg_upper));
1389
1390 /* TODO: integrate with swizzle */
1391 if (texture->in_reg_upper)
1392 fprintf(fp, "'");
1393
1394 print_swizzle_vec4(fp, texture->in_reg_swizzle, false, false);
1395
1396 /* There is *always* an offset attached. Of
1397 * course, that offset is just immediate #0 for a
1398 * GLES call that doesn't take an offset. If there
1399 * is a non-negative non-zero offset, this is
1400 * specified in immediate offset mode, with the
1401 * values in the offset_* fields as immediates. If
1402 * this is a negative offset, we instead switch to
1403 * a register offset mode, where the offset_*
1404 * fields become register triplets */
1405
1406 if (texture->offset_register) {
1407 fprintf(fp, " + ");
1408
1409 bool full = texture->offset & 1;
1410 bool select = texture->offset & 2;
1411 bool upper = texture->offset & 4;
1412
1413 fprintf(fp, "%sr%u", full ? "" : "h", in_reg_base + select);
1414 assert(!(texture->out_full && texture->out_upper));
1415
1416 /* TODO: integrate with swizzle */
1417 if (upper)
1418 fprintf(fp, "'");
1419
1420 print_swizzle_vec4(fp, texture->offset >> 3, false, false);
1421
1422 fprintf(fp, ", ");
1423 } else if (texture->offset) {
1424 /* Only select ops allow negative immediate offsets, verify */
1425
1426 signed offset_x = (texture->offset & 0xF);
1427 signed offset_y = ((texture->offset >> 4) & 0xF);
1428 signed offset_z = ((texture->offset >> 8) & 0xF);
1429
1430 bool neg_x = offset_x < 0;
1431 bool neg_y = offset_y < 0;
1432 bool neg_z = offset_z < 0;
1433 bool any_neg = neg_x || neg_y || neg_z;
1434
1435 if (any_neg && texture->op != TEXTURE_OP_TEXEL_FETCH)
1436 fprintf(fp, "/* invalid negative */ ");
1437
1438 /* Regardless, just print the immediate offset */
1439
1440 fprintf(fp, " + <%d, %d, %d>, ", offset_x, offset_y, offset_z);
1441 } else {
1442 fprintf(fp, ", ");
1443 }
1444
1445 char lod_operand = texture_op_takes_bias(texture->op) ? '+' : '=';
1446
1447 if (texture->lod_register) {
1448 fprintf(fp, "lod %c ", lod_operand);
1449 print_texture_reg_select(fp, texture->bias, in_reg_base);
1450 fprintf(fp, ", ");
1451
1452 if (texture->bias_int)
1453 fprintf(fp, " /* bias_int = 0x%X */", texture->bias_int);
1454 } else if (texture->op == TEXTURE_OP_TEXEL_FETCH) {
1455 /* For texel fetch, the int LOD is in the fractional place and
1456 * there is no fraction / possibility of bias. We *always* have
1457 * an explicit LOD, even if it's zero. */
1458
1459 if (texture->bias_int)
1460 fprintf(fp, " /* bias_int = 0x%X */ ", texture->bias_int);
1461
1462 fprintf(fp, "lod = %u, ", texture->bias);
1463 } else if (texture->bias || texture->bias_int) {
1464 signed bias_int = texture->bias_int;
1465 float bias_frac = texture->bias / 256.0f;
1466 float bias = bias_int + bias_frac;
1467
1468 bool is_bias = texture_op_takes_bias(texture->op);
1469 char sign = (bias >= 0.0) ? '+' : '-';
1470 char operand = is_bias ? sign : '=';
1471
1472 fprintf(fp, "lod %c %f, ", operand, fabsf(bias));
1473 }
1474
1475 fprintf(fp, "\n");
1476
1477 /* While not zero in general, for these simple instructions the
1478 * following unknowns are zero, so we don't include them */
1479
1480 if (texture->unknown4 ||
1481 texture->unknownA ||
1482 texture->unknown8) {
1483 fprintf(fp, "// unknown4 = 0x%x\n", texture->unknown4);
1484 fprintf(fp, "// unknownA = 0x%x\n", texture->unknownA);
1485 fprintf(fp, "// unknown8 = 0x%x\n", texture->unknown8);
1486 }
1487
1488 midg_stats.instruction_count++;
1489 }
1490
1491 struct midgard_disasm_stats
1492 disassemble_midgard(FILE *fp, uint8_t *code, size_t size, unsigned gpu_id, gl_shader_stage stage)
1493 {
1494 uint32_t *words = (uint32_t *) code;
1495 unsigned num_words = size / 4;
1496 int tabs = 0;
1497
1498 bool branch_forward = false;
1499
1500 int last_next_tag = -1;
1501
1502 unsigned i = 0;
1503
1504 midg_tags = calloc(sizeof(midg_tags[0]), num_words);
1505
1506 /* Stats for shader-db */
1507 memset(&midg_stats, 0, sizeof(midg_stats));
1508 midg_ever_written = 0;
1509
1510 while (i < num_words) {
1511 unsigned tag = words[i] & 0xF;
1512 unsigned next_tag = (words[i] >> 4) & 0xF;
1513 fprintf(fp, "\t%X -> %X\n", tag, next_tag);
1514 unsigned num_quad_words = midgard_word_size[tag];
1515
1516 if (midg_tags[i] && midg_tags[i] != tag) {
1517 fprintf(fp, "\t/* XXX: TAG ERROR branch, got ");
1518 print_tag_short(fp, tag);
1519 fprintf(fp, " expected ");
1520 print_tag_short(fp, midg_tags[i]);
1521 fprintf(fp, " */\n");
1522 }
1523
1524 midg_tags[i] = tag;
1525
1526 /* Check the tag */
1527 if (last_next_tag > 1) {
1528 if (last_next_tag != tag) {
1529 fprintf(fp, "\t/* XXX: TAG ERROR sequence, got ");
1530 print_tag_short(fp, tag);
1531 fprintf(fp, " expected ");
1532 print_tag_short(fp, last_next_tag);
1533 fprintf(fp, " */\n");
1534 }
1535 } else {
1536 /* TODO: Check ALU case */
1537 }
1538
1539 last_next_tag = next_tag;
1540
1541 switch (midgard_word_types[tag]) {
1542 case midgard_word_type_texture: {
1543 bool interpipe_aliasing =
1544 midgard_get_quirks(gpu_id) & MIDGARD_INTERPIPE_REG_ALIASING;
1545
1546 print_texture_word(fp, &words[i], tabs,
1547 interpipe_aliasing ? 0 : REG_TEX_BASE,
1548 interpipe_aliasing ? REGISTER_LDST_BASE : REG_TEX_BASE);
1549 break;
1550 }
1551
1552 case midgard_word_type_load_store:
1553 print_load_store_word(fp, &words[i], tabs);
1554 break;
1555
1556 case midgard_word_type_alu:
1557 branch_forward = print_alu_word(fp, &words[i], num_quad_words, tabs, i + 4*num_quad_words);
1558
1559 /* Reset word static analysis state */
1560 is_embedded_constant_half = false;
1561 is_embedded_constant_int = false;
1562
1563 break;
1564
1565 default:
1566 fprintf(fp, "Unknown word type %u:\n", words[i] & 0xF);
1567 num_quad_words = 1;
1568 print_quad_word(fp, &words[i], tabs);
1569 fprintf(fp, "\n");
1570 break;
1571 }
1572
1573 /* We are parsing per bundle anyway. Add before we start
1574 * breaking out so we don't miss the final bundle. */
1575
1576 midg_stats.bundle_count++;
1577 midg_stats.quadword_count += num_quad_words;
1578
1579 fprintf(fp, "\n");
1580
1581 unsigned next = (words[i] & 0xF0) >> 4;
1582
1583 if (i < num_words && next == 1 && !branch_forward)
1584 break;
1585
1586 i += 4 * num_quad_words;
1587 }
1588
1589 free(midg_tags);
1590
1591 /* We computed work_count as max_work_registers, so add one to get the
1592 * count. If no work registers are written, you still have one work
1593 * reported, which is exactly what the hardware expects */
1594
1595 midg_stats.work_count++;
1596
1597 return midg_stats;
1598 }