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pan/midgard: Fix printing of half-registers in texture ops
[mesa.git] / src / panfrost / midgard / disassemble.c
1 /* Author(s):
2 * Connor Abbott
3 * Alyssa Rosenzweig
4 *
5 * Copyright (c) 2013 Connor Abbott (connor@abbott.cx)
6 * Copyright (c) 2018 Alyssa Rosenzweig (alyssa@rosenzweig.io)
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #include <stdio.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <assert.h>
31 #include <inttypes.h>
32 #include <ctype.h>
33 #include <string.h>
34 #include "midgard.h"
35 #include "midgard-parse.h"
36 #include "midgard_ops.h"
37 #include "disassemble.h"
38 #include "helpers.h"
39 #include "util/half_float.h"
40 #include "util/u_math.h"
41
42 #define DEFINE_CASE(define, str) case define: { printf(str); break; }
43
44 static unsigned *midg_tags;
45 static bool is_instruction_int = false;
46
47 /* Stats */
48
49 static struct midgard_disasm_stats midg_stats;
50
51 /* Prints a short form of the tag for branching, the minimum needed to be
52 * legible and unambiguous */
53
54 static void
55 print_tag_short(unsigned tag)
56 {
57 switch (midgard_word_types[tag]) {
58 case midgard_word_type_texture:
59 printf("tex/%X", tag);
60 break;
61
62 case midgard_word_type_load_store:
63 printf("ldst");
64 break;
65
66 case midgard_word_type_alu:
67 printf("alu%u/%X", midgard_word_size[tag], tag);
68 break;
69
70 default:
71 printf("%s%X", (tag > 0) ? "" : "unk", tag);
72 break;
73 }
74 }
75
76 static void
77 print_alu_opcode(midgard_alu_op op)
78 {
79 bool int_op = false;
80
81 if (alu_opcode_props[op].name) {
82 printf("%s", alu_opcode_props[op].name);
83
84 int_op = midgard_is_integer_op(op);
85 } else
86 printf("alu_op_%02X", op);
87
88 /* For constant analysis */
89 is_instruction_int = int_op;
90 }
91
92 static void
93 print_ld_st_opcode(midgard_load_store_op op)
94 {
95 if (load_store_opcode_props[op].name)
96 printf("%s", load_store_opcode_props[op].name);
97 else
98 printf("ldst_op_%02X", op);
99 }
100
101 static bool is_embedded_constant_half = false;
102 static bool is_embedded_constant_int = false;
103
104 static char
105 prefix_for_bits(unsigned bits)
106 {
107 switch (bits) {
108 case 8:
109 return 'q';
110 case 16:
111 return 'h';
112 case 64:
113 return 'd';
114 default:
115 return 0;
116 }
117 }
118
119 /* For static analysis to ensure all registers are written at least once before
120 * use along the source code path (TODO: does this break done for complex CF?)
121 */
122
123 uint16_t midg_ever_written = 0;
124
125 static void
126 print_reg(unsigned reg, unsigned bits)
127 {
128 /* Perform basic static analysis for expanding constants correctly */
129
130 if (reg == 26) {
131 is_embedded_constant_int = is_instruction_int;
132 is_embedded_constant_half = (bits < 32);
133 }
134
135 unsigned uniform_reg = 23 - reg;
136 bool is_uniform = false;
137
138 /* For r8-r15, it could be a work or uniform. We distinguish based on
139 * the fact work registers are ALWAYS written before use, but uniform
140 * registers are NEVER written before use. */
141
142 if ((reg >= 8 && reg < 16) && !(midg_ever_written & (1 << reg)))
143 is_uniform = true;
144
145 /* r16-r23 are always uniform */
146
147 if (reg >= 16 && reg <= 23)
148 is_uniform = true;
149
150 /* Update the uniform count appropriately */
151
152 if (is_uniform)
153 midg_stats.uniform_count =
154 MAX2(uniform_reg + 1, midg_stats.uniform_count);
155
156 char prefix = prefix_for_bits(bits);
157
158 if (prefix)
159 putchar(prefix);
160
161 printf("r%u", reg);
162 }
163
164 static char *outmod_names_float[4] = {
165 "",
166 ".pos",
167 ".unk2",
168 ".sat"
169 };
170
171 static char *outmod_names_int[4] = {
172 ".isat",
173 ".usat",
174 "",
175 ".hi"
176 };
177
178 static char *srcmod_names_int[4] = {
179 "sext(",
180 "zext(",
181 "",
182 "("
183 };
184
185 static void
186 print_outmod(unsigned outmod, bool is_int)
187 {
188 printf("%s", is_int ? outmod_names_int[outmod] :
189 outmod_names_float[outmod]);
190 }
191
192 static void
193 print_quad_word(uint32_t *words, unsigned tabs)
194 {
195 unsigned i;
196
197 for (i = 0; i < 4; i++)
198 printf("0x%08X%s ", words[i], i == 3 ? "" : ",");
199
200 printf("\n");
201 }
202
203 static const char components[16] = "xyzwefghijklmnop";
204
205 /* Helper to print 4 chars of a swizzle */
206 static void
207 print_swizzle_helper(unsigned swizzle, bool upper)
208 {
209 for (unsigned i = 0; i < 4; ++i) {
210 unsigned c = (swizzle >> (i * 2)) & 3;
211 c += upper*4;
212 printf("%c", components[c]);
213 }
214 }
215
216 /* Helper to print 8 chars of a swizzle, duplicating over */
217 static void
218 print_swizzle_helper_8(unsigned swizzle, bool upper)
219 {
220 for (unsigned i = 0; i < 4; ++i) {
221 unsigned c = (swizzle >> (i * 2)) & 3;
222 c *= 2;
223 c += upper*8;
224 printf("%c%c", components[c], components[c+1]);
225 }
226 }
227
228 static void
229 print_swizzle_vec16(unsigned swizzle, bool rep_high, bool rep_low,
230 midgard_dest_override override)
231 {
232 printf(".");
233
234 if (override == midgard_dest_override_upper) {
235 if (rep_high)
236 printf(" /* rep_high */ ");
237 if (rep_low)
238 printf(" /* rep_low */ ");
239
240 if (!rep_high && rep_low)
241 print_swizzle_helper_8(swizzle, true);
242 else
243 print_swizzle_helper_8(swizzle, false);
244 } else {
245 print_swizzle_helper_8(swizzle, rep_high & 1);
246 print_swizzle_helper_8(swizzle, !(rep_low & 1));
247 }
248 }
249
250 static void
251 print_swizzle_vec8(unsigned swizzle, bool rep_high, bool rep_low)
252 {
253 printf(".");
254
255 print_swizzle_helper(swizzle, rep_high & 1);
256 print_swizzle_helper(swizzle, !(rep_low & 1));
257 }
258
259 static void
260 print_swizzle_vec4(unsigned swizzle, bool rep_high, bool rep_low)
261 {
262 if (rep_high)
263 printf(" /* rep_high */ ");
264 if (rep_low)
265 printf(" /* rep_low */ ");
266
267 if (swizzle == 0xE4) return; /* xyzw */
268
269 printf(".");
270 print_swizzle_helper(swizzle, 0);
271 }
272 static void
273 print_swizzle_vec2(unsigned swizzle, bool rep_high, bool rep_low)
274 {
275 if (rep_high)
276 printf(" /* rep_high */ ");
277 if (rep_low)
278 printf(" /* rep_low */ ");
279
280 if (swizzle == 0xE4) return; /* XY */
281
282 printf(".");
283
284 for (unsigned i = 0; i < 4; i += 2) {
285 unsigned a = (swizzle >> (i * 2)) & 3;
286 unsigned b = (swizzle >> ((i+1) * 2)) & 3;
287
288 /* Normally we're adjacent, but if there's an issue, don't make
289 * it ambiguous */
290
291 if (a & 0x1)
292 printf("[%c%c]", components[a], components[b]);
293 else if (a == b)
294 printf("%c", components[a >> 1]);
295 else if (b == (a + 1))
296 printf("%c", "XY"[a >> 1]);
297 else
298 printf("[%c%c]", components[a], components[b]);
299 }
300 }
301
302 static int
303 bits_for_mode(midgard_reg_mode mode)
304 {
305 switch (mode) {
306 case midgard_reg_mode_8:
307 return 8;
308 case midgard_reg_mode_16:
309 return 16;
310 case midgard_reg_mode_32:
311 return 32;
312 case midgard_reg_mode_64:
313 return 64;
314 default:
315 unreachable("Invalid reg mode");
316 return 0;
317 }
318 }
319
320 static int
321 bits_for_mode_halved(midgard_reg_mode mode, bool half)
322 {
323 unsigned bits = bits_for_mode(mode);
324
325 if (half)
326 bits >>= 1;
327
328 return bits;
329 }
330
331 static void
332 print_vector_src(unsigned src_binary,
333 midgard_reg_mode mode, unsigned reg,
334 midgard_dest_override override, bool is_int)
335 {
336 midgard_vector_alu_src *src = (midgard_vector_alu_src *)&src_binary;
337
338 /* Modifiers change meaning depending on the op's context */
339
340 midgard_int_mod int_mod = src->mod;
341
342 if (is_int) {
343 printf("%s", srcmod_names_int[int_mod]);
344 } else {
345 if (src->mod & MIDGARD_FLOAT_MOD_NEG)
346 printf("-");
347
348 if (src->mod & MIDGARD_FLOAT_MOD_ABS)
349 printf("abs(");
350 }
351
352 //register
353 unsigned bits = bits_for_mode_halved(mode, src->half);
354 print_reg(reg, bits);
355
356 //swizzle
357 if (bits == 16)
358 print_swizzle_vec8(src->swizzle, src->rep_high, src->rep_low);
359 else if (bits == 8)
360 print_swizzle_vec16(src->swizzle, src->rep_high, src->rep_low, override);
361 else if (bits == 32)
362 print_swizzle_vec4(src->swizzle, src->rep_high, src->rep_low);
363 else if (bits == 64)
364 print_swizzle_vec2(src->swizzle, src->rep_high, src->rep_low);
365
366 /* Since we wrapped with a function-looking thing */
367
368 if (is_int && int_mod == midgard_int_shift)
369 printf(") << %u", bits);
370 else if ((is_int && (int_mod != midgard_int_normal))
371 || (!is_int && src->mod & MIDGARD_FLOAT_MOD_ABS))
372 printf(")");
373 }
374
375 static uint16_t
376 decode_vector_imm(unsigned src2_reg, unsigned imm)
377 {
378 uint16_t ret;
379 ret = src2_reg << 11;
380 ret |= (imm & 0x7) << 8;
381 ret |= (imm >> 3) & 0xFF;
382 return ret;
383 }
384
385 static void
386 print_immediate(uint16_t imm)
387 {
388 if (is_instruction_int)
389 printf("#%u", imm);
390 else
391 printf("#%g", _mesa_half_to_float(imm));
392 }
393
394 static void
395 update_dest(unsigned reg)
396 {
397 /* We should record writes as marking this as a work register. Store
398 * the max register in work_count; we'll add one at the end */
399
400 if (reg < 16) {
401 midg_stats.work_count = MAX2(reg, midg_stats.work_count);
402 midg_ever_written |= (1 << reg);
403 }
404 }
405
406 static void
407 print_dest(unsigned reg, midgard_reg_mode mode, midgard_dest_override override)
408 {
409 /* Depending on the mode and override, we determine the type of
410 * destination addressed. Absent an override, we address just the
411 * type of the operation itself */
412
413 unsigned bits = bits_for_mode(mode);
414
415 if (override != midgard_dest_override_none)
416 bits /= 2;
417
418 update_dest(reg);
419 print_reg(reg, bits);
420 }
421
422 static void
423 print_mask_vec16(uint8_t mask, midgard_dest_override override)
424 {
425 printf(".");
426
427 for (unsigned i = 0; i < 8; i++) {
428 if (mask & (1 << i))
429 printf("%c%c",
430 components[i*2 + 0],
431 components[i*2 + 1]);
432 }
433 }
434
435 /* For 16-bit+ masks, we read off from the 8-bit mask field. For 16-bit (vec8),
436 * it's just one bit per channel, easy peasy. For 32-bit (vec4), it's one bit
437 * per channel with one duplicate bit in the middle. For 64-bit (vec2), it's
438 * one-bit per channel with _3_ duplicate bits in the middle. Basically, just
439 * subdividing the 128-bit word in 16-bit increments. For 64-bit, we uppercase
440 * the mask to make it obvious what happened */
441
442 static void
443 print_mask(uint8_t mask, unsigned bits, midgard_dest_override override)
444 {
445 if (bits == 8) {
446 print_mask_vec16(mask, override);
447 return;
448 }
449
450 /* Skip 'complete' masks */
451
452 if (override == midgard_dest_override_none) {
453 if (bits >= 32 && mask == 0xFF) return;
454
455 if (bits == 16) {
456 if (mask == 0x0F)
457 return;
458 else if (mask == 0xF0) {
459 printf("'");
460 return;
461 }
462 }
463 }
464
465 printf(".");
466
467 unsigned skip = (bits / 16);
468 bool uppercase = bits > 32;
469 bool tripped = false;
470
471 /* To apply an upper destination override, we "shift" the alphabet.
472 * E.g. with an upper override on 32-bit, instead of xyzw, print efgh.
473 * For upper 16-bit, instead of xyzwefgh, print ijklmnop */
474
475 const char *alphabet = components;
476
477 if (override == midgard_dest_override_upper) {
478 unsigned components = 128 / bits;
479 alphabet += components;
480 }
481
482 for (unsigned i = 0; i < 8; i += skip) {
483 bool a = (mask & (1 << i)) != 0;
484
485 for (unsigned j = 1; j < skip; ++j) {
486 bool dupe = (mask & (1 << (i + j))) != 0;
487 tripped |= (dupe != a);
488 }
489
490 if (a) {
491 char c = alphabet[i / skip];
492
493 if (uppercase)
494 c = toupper(c);
495
496 printf("%c", c);
497 }
498 }
499
500 if (tripped)
501 printf(" /* %X */", mask);
502 }
503
504 /* Prints the 4-bit masks found in texture and load/store ops, as opposed to
505 * the 8-bit masks found in (vector) ALU ops. Supports texture-style 16-bit
506 * mode as well, but not load/store-style 16-bit mode. */
507
508 static void
509 print_mask_4(unsigned mask, bool upper)
510 {
511 if (mask == 0xF) {
512 if (upper)
513 printf("'");
514
515 return;
516 }
517
518 printf(".");
519
520 for (unsigned i = 0; i < 4; ++i) {
521 bool a = (mask & (1 << i)) != 0;
522 if (a)
523 printf("%c", components[i + (upper ? 4 : 0)]);
524 }
525 }
526
527 static void
528 print_vector_field(const char *name, uint16_t *words, uint16_t reg_word,
529 unsigned tabs)
530 {
531 midgard_reg_info *reg_info = (midgard_reg_info *)&reg_word;
532 midgard_vector_alu *alu_field = (midgard_vector_alu *) words;
533 midgard_reg_mode mode = alu_field->reg_mode;
534 unsigned override = alu_field->dest_override;
535
536 /* For now, prefix instruction names with their unit, until we
537 * understand how this works on a deeper level */
538 printf("%s.", name);
539
540 print_alu_opcode(alu_field->op);
541
542 /* Postfix with the size to disambiguate if necessary */
543 char postfix = prefix_for_bits(bits_for_mode(mode));
544 bool size_ambiguous = override != midgard_dest_override_none;
545
546 if (size_ambiguous)
547 printf("%c", postfix ? postfix : 'r');
548
549 /* Print the outmod, if there is one */
550 print_outmod(alu_field->outmod,
551 midgard_is_integer_out_op(alu_field->op));
552
553 printf(" ");
554
555 /* Mask denoting status of 8-lanes */
556 uint8_t mask = alu_field->mask;
557
558 /* First, print the destination */
559 print_dest(reg_info->out_reg, mode, alu_field->dest_override);
560
561 if (override != midgard_dest_override_none) {
562 bool modeable = (mode != midgard_reg_mode_8);
563 bool known = override != 0x3; /* Unused value */
564
565 if (!(modeable && known))
566 printf("/* do%u */ ", override);
567 }
568
569 print_mask(mask, bits_for_mode(mode), override);
570
571 printf(", ");
572
573 bool is_int = midgard_is_integer_op(alu_field->op);
574 print_vector_src(alu_field->src1, mode, reg_info->src1_reg, override, is_int);
575
576 printf(", ");
577
578 if (reg_info->src2_imm) {
579 uint16_t imm = decode_vector_imm(reg_info->src2_reg, alu_field->src2 >> 2);
580 print_immediate(imm);
581 } else {
582 print_vector_src(alu_field->src2, mode,
583 reg_info->src2_reg, override, is_int);
584 }
585
586 midg_stats.instruction_count++;
587 printf("\n");
588 }
589
590 static void
591 print_scalar_src(unsigned src_binary, unsigned reg)
592 {
593 midgard_scalar_alu_src *src = (midgard_scalar_alu_src *)&src_binary;
594
595 if (src->negate)
596 printf("-");
597
598 if (src->abs)
599 printf("abs(");
600
601 print_reg(reg, src->full ? 32 : 16);
602
603 unsigned c = src->component;
604
605 if (src->full) {
606 assert((c & 1) == 0);
607 c >>= 1;
608 }
609
610 printf(".%c", components[c]);
611
612 if (src->abs)
613 printf(")");
614
615 }
616
617 static uint16_t
618 decode_scalar_imm(unsigned src2_reg, unsigned imm)
619 {
620 uint16_t ret;
621 ret = src2_reg << 11;
622 ret |= (imm & 3) << 9;
623 ret |= (imm & 4) << 6;
624 ret |= (imm & 0x38) << 2;
625 ret |= imm >> 6;
626 return ret;
627 }
628
629 static void
630 print_scalar_field(const char *name, uint16_t *words, uint16_t reg_word,
631 unsigned tabs)
632 {
633 midgard_reg_info *reg_info = (midgard_reg_info *)&reg_word;
634 midgard_scalar_alu *alu_field = (midgard_scalar_alu *) words;
635
636 if (alu_field->unknown)
637 printf("scalar ALU unknown bit set\n");
638
639 printf("%s.", name);
640 print_alu_opcode(alu_field->op);
641 print_outmod(alu_field->outmod,
642 midgard_is_integer_out_op(alu_field->op));
643 printf(" ");
644
645 bool full = alu_field->output_full;
646 update_dest(reg_info->out_reg);
647 print_reg(reg_info->out_reg, full ? 32 : 16);
648 unsigned c = alu_field->output_component;
649
650 if (full) {
651 assert((c & 1) == 0);
652 c >>= 1;
653 }
654
655 printf(".%c, ", components[c]);
656
657 print_scalar_src(alu_field->src1, reg_info->src1_reg);
658
659 printf(", ");
660
661 if (reg_info->src2_imm) {
662 uint16_t imm = decode_scalar_imm(reg_info->src2_reg,
663 alu_field->src2);
664 print_immediate(imm);
665 } else
666 print_scalar_src(alu_field->src2, reg_info->src2_reg);
667
668 midg_stats.instruction_count++;
669 printf("\n");
670 }
671
672 static void
673 print_branch_op(unsigned op)
674 {
675 switch (op) {
676 case midgard_jmp_writeout_op_branch_uncond:
677 printf("uncond.");
678 break;
679
680 case midgard_jmp_writeout_op_branch_cond:
681 printf("cond.");
682 break;
683
684 case midgard_jmp_writeout_op_writeout:
685 printf("write.");
686 break;
687
688 case midgard_jmp_writeout_op_tilebuffer_pending:
689 printf("tilebuffer.");
690 break;
691
692 case midgard_jmp_writeout_op_discard:
693 printf("discard.");
694 break;
695
696 default:
697 printf("unk%u.", op);
698 break;
699 }
700 }
701
702 static void
703 print_branch_cond(int cond)
704 {
705 switch (cond) {
706 case midgard_condition_write0:
707 printf("write0");
708 break;
709
710 case midgard_condition_false:
711 printf("false");
712 break;
713
714 case midgard_condition_true:
715 printf("true");
716 break;
717
718 case midgard_condition_always:
719 printf("always");
720 break;
721
722 default:
723 printf("unk%X", cond);
724 break;
725 }
726 }
727
728 static void
729 print_compact_branch_writeout_field(uint16_t word)
730 {
731 midgard_jmp_writeout_op op = word & 0x7;
732
733 switch (op) {
734 case midgard_jmp_writeout_op_branch_uncond: {
735 midgard_branch_uncond br_uncond;
736 memcpy((char *) &br_uncond, (char *) &word, sizeof(br_uncond));
737 printf("br.uncond ");
738
739 if (br_uncond.unknown != 1)
740 printf("unknown:%u, ", br_uncond.unknown);
741
742 if (br_uncond.offset >= 0)
743 printf("+");
744
745 printf("%d -> ", br_uncond.offset);
746 print_tag_short(br_uncond.dest_tag);
747 printf("\n");
748
749 break;
750 }
751
752 case midgard_jmp_writeout_op_branch_cond:
753 case midgard_jmp_writeout_op_writeout:
754 case midgard_jmp_writeout_op_discard:
755 default: {
756 midgard_branch_cond br_cond;
757 memcpy((char *) &br_cond, (char *) &word, sizeof(br_cond));
758
759 printf("br.");
760
761 print_branch_op(br_cond.op);
762 print_branch_cond(br_cond.cond);
763
764 printf(" ");
765
766 if (br_cond.offset >= 0)
767 printf("+");
768
769 printf("%d -> ", br_cond.offset);
770 print_tag_short(br_cond.dest_tag);
771 printf("\n");
772
773 break;
774 }
775 }
776
777 midg_stats.instruction_count++;
778 }
779
780 static void
781 print_extended_branch_writeout_field(uint8_t *words, unsigned next)
782 {
783 midgard_branch_extended br;
784 memcpy((char *) &br, (char *) words, sizeof(br));
785
786 printf("brx.");
787
788 print_branch_op(br.op);
789
790 /* Condition codes are a LUT in the general case, but simply repeated 8 times for single-channel conditions.. Check this. */
791
792 bool single_channel = true;
793
794 for (unsigned i = 0; i < 16; i += 2) {
795 single_channel &= (((br.cond >> i) & 0x3) == (br.cond & 0x3));
796 }
797
798 if (single_channel)
799 print_branch_cond(br.cond & 0x3);
800 else
801 printf("lut%X", br.cond);
802
803 if (br.unknown)
804 printf(".unknown%u", br.unknown);
805
806 printf(" ");
807
808 if (br.offset >= 0)
809 printf("+");
810
811 printf("%d -> ", br.offset);
812 print_tag_short(br.dest_tag);
813 printf("\n");
814
815 unsigned I = next + br.offset * 4;
816
817 if (midg_tags[I] && midg_tags[I] != br.dest_tag) {
818 printf("\t/* XXX TAG ERROR: jumping to ");
819 print_tag_short(br.dest_tag);
820 printf(" but tagged ");
821 print_tag_short(midg_tags[I]);
822 printf(" */\n");
823 }
824
825 midg_tags[I] = br.dest_tag;
826
827 midg_stats.instruction_count++;
828 }
829
830 static unsigned
831 num_alu_fields_enabled(uint32_t control_word)
832 {
833 unsigned ret = 0;
834
835 if ((control_word >> 17) & 1)
836 ret++;
837
838 if ((control_word >> 19) & 1)
839 ret++;
840
841 if ((control_word >> 21) & 1)
842 ret++;
843
844 if ((control_word >> 23) & 1)
845 ret++;
846
847 if ((control_word >> 25) & 1)
848 ret++;
849
850 return ret;
851 }
852
853 static float
854 float_bitcast(uint32_t integer)
855 {
856 union {
857 uint32_t i;
858 float f;
859 } v;
860
861 v.i = integer;
862 return v.f;
863 }
864
865 static void
866 print_alu_word(uint32_t *words, unsigned num_quad_words,
867 unsigned tabs, unsigned next)
868 {
869 uint32_t control_word = words[0];
870 uint16_t *beginning_ptr = (uint16_t *)(words + 1);
871 unsigned num_fields = num_alu_fields_enabled(control_word);
872 uint16_t *word_ptr = beginning_ptr + num_fields;
873 unsigned num_words = 2 + num_fields;
874
875 if ((control_word >> 16) & 1)
876 printf("unknown bit 16 enabled\n");
877
878 if ((control_word >> 17) & 1) {
879 print_vector_field("vmul", word_ptr, *beginning_ptr, tabs);
880 beginning_ptr += 1;
881 word_ptr += 3;
882 num_words += 3;
883 }
884
885 if ((control_word >> 18) & 1)
886 printf("unknown bit 18 enabled\n");
887
888 if ((control_word >> 19) & 1) {
889 print_scalar_field("sadd", word_ptr, *beginning_ptr, tabs);
890 beginning_ptr += 1;
891 word_ptr += 2;
892 num_words += 2;
893 }
894
895 if ((control_word >> 20) & 1)
896 printf("unknown bit 20 enabled\n");
897
898 if ((control_word >> 21) & 1) {
899 print_vector_field("vadd", word_ptr, *beginning_ptr, tabs);
900 beginning_ptr += 1;
901 word_ptr += 3;
902 num_words += 3;
903 }
904
905 if ((control_word >> 22) & 1)
906 printf("unknown bit 22 enabled\n");
907
908 if ((control_word >> 23) & 1) {
909 print_scalar_field("smul", word_ptr, *beginning_ptr, tabs);
910 beginning_ptr += 1;
911 word_ptr += 2;
912 num_words += 2;
913 }
914
915 if ((control_word >> 24) & 1)
916 printf("unknown bit 24 enabled\n");
917
918 if ((control_word >> 25) & 1) {
919 print_vector_field("lut", word_ptr, *beginning_ptr, tabs);
920 word_ptr += 3;
921 num_words += 3;
922 }
923
924 if ((control_word >> 26) & 1) {
925 print_compact_branch_writeout_field(*word_ptr);
926 word_ptr += 1;
927 num_words += 1;
928 }
929
930 if ((control_word >> 27) & 1) {
931 print_extended_branch_writeout_field((uint8_t *) word_ptr, next);
932 word_ptr += 3;
933 num_words += 3;
934 }
935
936 if (num_quad_words > (num_words + 7) / 8) {
937 assert(num_quad_words == (num_words + 15) / 8);
938 //Assume that the extra quadword is constants
939 void *consts = words + (4 * num_quad_words - 4);
940
941 if (is_embedded_constant_int) {
942 if (is_embedded_constant_half) {
943 int16_t *sconsts = (int16_t *) consts;
944 printf("sconstants %d, %d, %d, %d\n",
945 sconsts[0],
946 sconsts[1],
947 sconsts[2],
948 sconsts[3]);
949 } else {
950 uint32_t *iconsts = (uint32_t *) consts;
951 printf("iconstants 0x%X, 0x%X, 0x%X, 0x%X\n",
952 iconsts[0],
953 iconsts[1],
954 iconsts[2],
955 iconsts[3]);
956 }
957 } else {
958 if (is_embedded_constant_half) {
959 uint16_t *hconsts = (uint16_t *) consts;
960 printf("hconstants %g, %g, %g, %g\n",
961 _mesa_half_to_float(hconsts[0]),
962 _mesa_half_to_float(hconsts[1]),
963 _mesa_half_to_float(hconsts[2]),
964 _mesa_half_to_float(hconsts[3]));
965 } else {
966 uint32_t *fconsts = (uint32_t *) consts;
967 printf("fconstants %g, %g, %g, %g\n",
968 float_bitcast(fconsts[0]),
969 float_bitcast(fconsts[1]),
970 float_bitcast(fconsts[2]),
971 float_bitcast(fconsts[3]));
972 }
973
974 }
975 }
976 }
977
978 static void
979 print_varying_parameters(midgard_load_store_word *word)
980 {
981 midgard_varying_parameter param;
982 unsigned v = word->varying_parameters;
983 memcpy(&param, &v, sizeof(param));
984
985 if (param.is_varying) {
986 /* If a varying, there are qualifiers */
987 if (param.flat)
988 printf(".flat");
989
990 if (param.interpolation != midgard_interp_default) {
991 if (param.interpolation == midgard_interp_centroid)
992 printf(".centroid");
993 else
994 printf(".interp%d", param.interpolation);
995 }
996
997 if (param.modifier != midgard_varying_mod_none) {
998 if (param.modifier == midgard_varying_mod_perspective_w)
999 printf(".perspectivew");
1000 else if (param.modifier == midgard_varying_mod_perspective_z)
1001 printf(".perspectivez");
1002 else
1003 printf(".mod%d", param.modifier);
1004 }
1005 } else if (param.flat || param.interpolation || param.modifier) {
1006 printf(" /* is_varying not set but varying metadata attached */");
1007 }
1008
1009 if (param.zero0 || param.zero1 || param.zero2)
1010 printf(" /* zero tripped, %u %u %u */ ", param.zero0, param.zero1, param.zero2);
1011 }
1012
1013 static bool
1014 is_op_varying(unsigned op)
1015 {
1016 switch (op) {
1017 case midgard_op_st_vary_16:
1018 case midgard_op_st_vary_32:
1019 case midgard_op_st_vary_32i:
1020 case midgard_op_st_vary_32u:
1021 case midgard_op_ld_vary_16:
1022 case midgard_op_ld_vary_32:
1023 case midgard_op_ld_vary_32i:
1024 case midgard_op_ld_vary_32u:
1025 return true;
1026 }
1027
1028 return false;
1029 }
1030
1031 static bool
1032 is_op_attribute(unsigned op)
1033 {
1034 switch (op) {
1035 case midgard_op_ld_attr_16:
1036 case midgard_op_ld_attr_32:
1037 case midgard_op_ld_attr_32i:
1038 case midgard_op_ld_attr_32u:
1039 return true;
1040 }
1041
1042 return false;
1043 }
1044
1045 static void
1046 print_load_store_arg(uint8_t arg, unsigned index)
1047 {
1048 /* Try to interpret as a register */
1049 midgard_ldst_register_select sel;
1050 memcpy(&sel, &arg, sizeof(arg));
1051
1052 /* If unknown is set, we're not sure what this is or how to
1053 * interpret it. But if it's zero, we get it. */
1054
1055 if (sel.unknown) {
1056 printf("0x%02X", arg);
1057 return;
1058 }
1059
1060 unsigned reg = REGISTER_LDST_BASE + sel.select;
1061 char comp = components[sel.component];
1062
1063 printf("r%u.%c", reg, comp);
1064
1065 /* Only print a shift if it's non-zero. Shifts only make sense for the
1066 * second index. For the first, we're not sure what it means yet */
1067
1068 if (index == 1) {
1069 if (sel.shift)
1070 printf(" << %u", sel.shift);
1071 } else {
1072 printf(" /* %X */", sel.shift);
1073 }
1074 }
1075
1076 static void
1077 update_stats(signed *stat, unsigned address)
1078 {
1079 if (*stat >= 0)
1080 *stat = MAX2(*stat, address + 1);
1081 }
1082
1083 static void
1084 print_load_store_instr(uint64_t data,
1085 unsigned tabs)
1086 {
1087 midgard_load_store_word *word = (midgard_load_store_word *) &data;
1088
1089 print_ld_st_opcode(word->op);
1090
1091 unsigned address = word->address;
1092
1093 if (is_op_varying(word->op)) {
1094 print_varying_parameters(word);
1095
1096 /* Do some analysis: check if direct cacess */
1097
1098 if ((word->arg_2 == 0x1E) && midg_stats.varying_count >= 0)
1099 update_stats(&midg_stats.varying_count, address);
1100 else
1101 midg_stats.varying_count = -16;
1102 } else if (is_op_attribute(word->op)) {
1103 if ((word->arg_2 == 0x1E) && midg_stats.attribute_count >= 0)
1104 update_stats(&midg_stats.attribute_count, address);
1105 else
1106 midg_stats.attribute_count = -16;
1107 }
1108
1109 printf(" r%u", word->reg);
1110 print_mask_4(word->mask, false);
1111
1112 if (!OP_IS_STORE(word->op))
1113 update_dest(word->reg);
1114
1115 bool is_ubo = OP_IS_UBO_READ(word->op);
1116
1117 if (is_ubo) {
1118 /* UBOs use their own addressing scheme */
1119
1120 int lo = word->varying_parameters >> 7;
1121 int hi = word->address;
1122
1123 /* TODO: Combine fields logically */
1124 address = (hi << 3) | lo;
1125 }
1126
1127 printf(", %u", address);
1128
1129 print_swizzle_vec4(word->swizzle, false, false);
1130
1131 printf(", ");
1132
1133 if (is_ubo) {
1134 printf("ubo%u", word->arg_1);
1135 update_stats(&midg_stats.uniform_buffer_count, word->arg_1);
1136 } else
1137 print_load_store_arg(word->arg_1, 0);
1138
1139 printf(", ");
1140 print_load_store_arg(word->arg_2, 1);
1141 printf(" /* %X */\n", word->varying_parameters);
1142
1143 midg_stats.instruction_count++;
1144 }
1145
1146 static void
1147 print_load_store_word(uint32_t *word, unsigned tabs)
1148 {
1149 midgard_load_store *load_store = (midgard_load_store *) word;
1150
1151 if (load_store->word1 != 3) {
1152 print_load_store_instr(load_store->word1, tabs);
1153 }
1154
1155 if (load_store->word2 != 3) {
1156 print_load_store_instr(load_store->word2, tabs);
1157 }
1158 }
1159
1160 static void
1161 print_texture_reg_select(uint8_t u)
1162 {
1163 midgard_tex_register_select sel;
1164 memcpy(&sel, &u, sizeof(u));
1165
1166 if (!sel.full)
1167 printf("h");
1168
1169 printf("r%u", REG_TEX_BASE + sel.select);
1170
1171 unsigned component = sel.component;
1172
1173 /* Use the upper half in half-reg mode */
1174 if (sel.upper) {
1175 assert(!sel.full);
1176 component += 4;
1177 }
1178
1179 printf(".%c", components[component]);
1180
1181 assert(sel.zero == 0);
1182 }
1183
1184 static void
1185 print_texture_format(int format)
1186 {
1187 /* Act like a modifier */
1188 printf(".");
1189
1190 switch (format) {
1191 DEFINE_CASE(MALI_TEX_1D, "1d");
1192 DEFINE_CASE(MALI_TEX_2D, "2d");
1193 DEFINE_CASE(MALI_TEX_3D, "3d");
1194 DEFINE_CASE(MALI_TEX_CUBE, "cube");
1195
1196 default:
1197 unreachable("Bad format");
1198 }
1199 }
1200
1201 static bool
1202 midgard_op_has_helpers(unsigned op, bool gather)
1203 {
1204 if (gather)
1205 return true;
1206
1207 switch (op) {
1208 case TEXTURE_OP_NORMAL:
1209 case TEXTURE_OP_DFDX:
1210 case TEXTURE_OP_DFDY:
1211 return true;
1212 default:
1213 return false;
1214 }
1215 }
1216
1217 static void
1218 print_texture_op(unsigned op, bool gather)
1219 {
1220 /* Act like a bare name, like ESSL functions */
1221
1222 if (gather) {
1223 printf("textureGather");
1224
1225 unsigned component = op >> 4;
1226 unsigned bottom = op & 0xF;
1227
1228 if (bottom != 0x2)
1229 printf("_unk%u", bottom);
1230
1231 printf(".%c", components[component]);
1232 return;
1233 }
1234
1235 switch (op) {
1236 DEFINE_CASE(TEXTURE_OP_NORMAL, "texture");
1237 DEFINE_CASE(TEXTURE_OP_LOD, "textureLod");
1238 DEFINE_CASE(TEXTURE_OP_TEXEL_FETCH, "texelFetch");
1239 DEFINE_CASE(TEXTURE_OP_DFDX, "dFdx");
1240 DEFINE_CASE(TEXTURE_OP_DFDY, "dFdy");
1241
1242 default:
1243 printf("tex_%X", op);
1244 break;
1245 }
1246 }
1247
1248 static bool
1249 texture_op_takes_bias(unsigned op)
1250 {
1251 return op == TEXTURE_OP_NORMAL;
1252 }
1253
1254 static char
1255 sampler_type_name(enum mali_sampler_type t)
1256 {
1257 switch (t) {
1258 case MALI_SAMPLER_FLOAT:
1259 return 'f';
1260 case MALI_SAMPLER_UNSIGNED:
1261 return 'u';
1262 case MALI_SAMPLER_SIGNED:
1263 return 'i';
1264 default:
1265 return '?';
1266 }
1267
1268 }
1269
1270 #undef DEFINE_CASE
1271
1272 static void
1273 print_texture_word(uint32_t *word, unsigned tabs)
1274 {
1275 midgard_texture_word *texture = (midgard_texture_word *) word;
1276
1277 midg_stats.helper_invocations |=
1278 midgard_op_has_helpers(texture->op, texture->is_gather);
1279
1280 /* Broad category of texture operation in question */
1281 print_texture_op(texture->op, texture->is_gather);
1282
1283 /* Specific format in question */
1284 print_texture_format(texture->format);
1285
1286 /* Instruction "modifiers" parallel the ALU instructions. */
1287
1288 if (texture->shadow)
1289 printf(".shadow");
1290
1291 if (texture->cont)
1292 printf(".cont");
1293
1294 if (texture->last)
1295 printf(".last");
1296
1297 /* Output modifiers are always interpreted floatly */
1298 print_outmod(texture->outmod, false);
1299
1300 printf(" %sr%d", texture->out_full ? "" : "h",
1301 REG_TEX_BASE + texture->out_reg_select);
1302 print_mask_4(texture->mask, texture->out_upper);
1303 assert(!(texture->out_full && texture->out_upper));
1304 printf(", ");
1305
1306 /* Depending on whether we read from textures directly or indirectly,
1307 * we may be able to update our analysis */
1308
1309 if (texture->texture_register) {
1310 printf("texture[");
1311 print_texture_reg_select(texture->texture_handle);
1312 printf("], ");
1313
1314 /* Indirect, tut tut */
1315 midg_stats.texture_count = -16;
1316 } else {
1317 printf("texture%u, ", texture->texture_handle);
1318 update_stats(&midg_stats.texture_count, texture->texture_handle);
1319 }
1320
1321 /* Print the type, GL style */
1322 printf("%csampler", sampler_type_name(texture->sampler_type));
1323
1324 if (texture->sampler_register) {
1325 printf("[");
1326 print_texture_reg_select(texture->sampler_handle);
1327 printf("]");
1328
1329 midg_stats.sampler_count = -16;
1330 } else {
1331 printf("%u", texture->sampler_handle);
1332 update_stats(&midg_stats.sampler_count, texture->sampler_handle);
1333 }
1334
1335 print_swizzle_vec4(texture->swizzle, false, false);
1336 printf(", %sr%d", texture->in_reg_full ? "" : "h", REG_TEX_BASE + texture->in_reg_select);
1337 assert(!(texture->in_reg_full && texture->in_reg_upper));
1338
1339 /* TODO: integrate with swizzle */
1340 if (texture->in_reg_upper)
1341 printf("'");
1342
1343 print_swizzle_vec4(texture->in_reg_swizzle, false, false);
1344
1345 /* There is *always* an offset attached. Of
1346 * course, that offset is just immediate #0 for a
1347 * GLES call that doesn't take an offset. If there
1348 * is a non-negative non-zero offset, this is
1349 * specified in immediate offset mode, with the
1350 * values in the offset_* fields as immediates. If
1351 * this is a negative offset, we instead switch to
1352 * a register offset mode, where the offset_*
1353 * fields become register triplets */
1354
1355 if (texture->offset_register) {
1356 printf(" + ");
1357
1358 bool full = texture->offset_x & 1;
1359 bool select = texture->offset_x & 2;
1360 bool upper = texture->offset_x & 4;
1361
1362 printf("%sr%d", full ? "" : "h", REG_TEX_BASE + select);
1363 assert(!(texture->out_full && texture->out_upper));
1364
1365 /* TODO: integrate with swizzle */
1366 if (upper)
1367 printf("'");
1368
1369 /* The less questions you ask, the better. */
1370
1371 unsigned swizzle_lo, swizzle_hi;
1372 unsigned orig_y = texture->offset_y;
1373 unsigned orig_z = texture->offset_z;
1374
1375 memcpy(&swizzle_lo, &orig_y, sizeof(unsigned));
1376 memcpy(&swizzle_hi, &orig_z, sizeof(unsigned));
1377
1378 /* Duplicate hi swizzle over */
1379 assert(swizzle_hi < 4);
1380 swizzle_hi = (swizzle_hi << 2) | swizzle_hi;
1381
1382 unsigned swiz = (swizzle_lo << 4) | swizzle_hi;
1383 unsigned reversed = util_bitreverse(swiz) >> 24;
1384 print_swizzle_vec4(reversed, false, false);
1385
1386 printf(", ");
1387 } else if (texture->offset_x || texture->offset_y || texture->offset_z) {
1388 /* Only select ops allow negative immediate offsets, verify */
1389
1390 bool neg_x = texture->offset_x < 0;
1391 bool neg_y = texture->offset_y < 0;
1392 bool neg_z = texture->offset_z < 0;
1393 bool any_neg = neg_x || neg_y || neg_z;
1394
1395 if (any_neg && texture->op != TEXTURE_OP_TEXEL_FETCH)
1396 printf("/* invalid negative */ ");
1397
1398 /* Regardless, just print the immediate offset */
1399
1400 printf(" + <%d, %d, %d>, ",
1401 texture->offset_x,
1402 texture->offset_y,
1403 texture->offset_z);
1404 } else {
1405 printf(", ");
1406 }
1407
1408 char lod_operand = texture_op_takes_bias(texture->op) ? '+' : '=';
1409
1410 if (texture->lod_register) {
1411 printf("lod %c ", lod_operand);
1412 print_texture_reg_select(texture->bias);
1413 printf(", ");
1414
1415 if (texture->bias_int)
1416 printf(" /* bias_int = 0x%X */", texture->bias_int);
1417 } else if (texture->op == TEXTURE_OP_TEXEL_FETCH) {
1418 /* For texel fetch, the int LOD is in the fractional place and
1419 * there is no fraction / possibility of bias. We *always* have
1420 * an explicit LOD, even if it's zero. */
1421
1422 if (texture->bias_int)
1423 printf(" /* bias_int = 0x%X */ ", texture->bias_int);
1424
1425 printf("lod = %u, ", texture->bias);
1426 } else if (texture->bias || texture->bias_int) {
1427 signed bias_int = texture->bias_int;
1428 float bias_frac = texture->bias / 256.0f;
1429 float bias = bias_int + bias_frac;
1430
1431 bool is_bias = texture_op_takes_bias(texture->op);
1432 char sign = (bias >= 0.0) ? '+' : '-';
1433 char operand = is_bias ? sign : '=';
1434
1435 printf("lod %c %f, ", operand, fabsf(bias));
1436 }
1437
1438 printf("\n");
1439
1440 /* While not zero in general, for these simple instructions the
1441 * following unknowns are zero, so we don't include them */
1442
1443 if (texture->unknown4 ||
1444 texture->unknownA ||
1445 texture->unknown8) {
1446 printf("// unknown4 = 0x%x\n", texture->unknown4);
1447 printf("// unknownA = 0x%x\n", texture->unknownA);
1448 printf("// unknown8 = 0x%x\n", texture->unknown8);
1449 }
1450
1451 midg_stats.instruction_count++;
1452 }
1453
1454 struct midgard_disasm_stats
1455 disassemble_midgard(uint8_t *code, size_t size, unsigned gpu_id)
1456 {
1457 uint32_t *words = (uint32_t *) code;
1458 unsigned num_words = size / 4;
1459 int tabs = 0;
1460
1461 bool prefetch_flag = false;
1462
1463 int last_next_tag = -1;
1464
1465 unsigned i = 0;
1466
1467 midg_tags = calloc(sizeof(midg_tags[0]), num_words);
1468
1469 /* Stats for shader-db */
1470 memset(&midg_stats, 0, sizeof(midg_stats));
1471 midg_ever_written = 0;
1472
1473 while (i < num_words) {
1474 unsigned tag = words[i] & 0xF;
1475 unsigned next_tag = (words[i] >> 4) & 0xF;
1476 unsigned num_quad_words = midgard_word_size[tag];
1477
1478 if (midg_tags[i] && midg_tags[i] != tag) {
1479 printf("\t/* XXX: TAG ERROR branch, got ");
1480 print_tag_short(tag);
1481 printf(" expected ");
1482 print_tag_short(midg_tags[i]);
1483 printf(" */\n");
1484 }
1485
1486 midg_tags[i] = tag;
1487
1488 /* Check the tag */
1489 if (last_next_tag > 1) {
1490 if (last_next_tag != tag) {
1491 printf("\t/* XXX: TAG ERROR sequence, got ");
1492 print_tag_short(tag);
1493 printf(" expected ");
1494 print_tag_short(last_next_tag);
1495 printf(" */\n");
1496 }
1497 } else {
1498 /* TODO: Check ALU case */
1499 }
1500
1501 last_next_tag = next_tag;
1502
1503 switch (midgard_word_types[tag]) {
1504 case midgard_word_type_texture:
1505 print_texture_word(&words[i], tabs);
1506 break;
1507
1508 case midgard_word_type_load_store:
1509 print_load_store_word(&words[i], tabs);
1510 break;
1511
1512 case midgard_word_type_alu:
1513 print_alu_word(&words[i], num_quad_words, tabs, i + 4*num_quad_words);
1514
1515 /* Reset word static analysis state */
1516 is_embedded_constant_half = false;
1517 is_embedded_constant_int = false;
1518
1519 break;
1520
1521 default:
1522 printf("Unknown word type %u:\n", words[i] & 0xF);
1523 num_quad_words = 1;
1524 print_quad_word(&words[i], tabs);
1525 printf("\n");
1526 break;
1527 }
1528
1529 if (prefetch_flag && midgard_word_types[tag] == midgard_word_type_alu)
1530 break;
1531
1532 printf("\n");
1533
1534 unsigned next = (words[i] & 0xF0) >> 4;
1535
1536 /* We are parsing per bundle anyway */
1537 midg_stats.bundle_count++;
1538 midg_stats.quadword_count += num_quad_words;
1539
1540 /* Break based on instruction prefetch flag */
1541
1542 if (i < num_words && next == 1) {
1543 prefetch_flag = true;
1544
1545 if (midgard_word_types[words[i] & 0xF] != midgard_word_type_alu)
1546 break;
1547 }
1548
1549 i += 4 * num_quad_words;
1550 }
1551
1552 /* We computed work_count as max_work_registers, so add one to get the
1553 * count. If no work registers are written, you still have one work
1554 * reported, which is exactly what the hardware expects */
1555
1556 midg_stats.work_count++;
1557
1558 return midg_stats;
1559 }