src/panfrost/midgard/helpers.h

   1 /* Copyright (c) 2018-2019 Alyssa Rosenzweig (alyssa@rosenzweig.io)
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a copy
   4  * of this software and associated documentation files (the "Software"), to deal
   5  * in the Software without restriction, including without limitation the rights
   6  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   7  * copies of the Software, and to permit persons to whom the Software is
   8  * furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice shall be included in
  11  * all copies or substantial portions of the Software.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  16  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  18  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  19  * THE SOFTWARE.
  20  */
  21
  22 #ifndef __MDG_HELPERS_H
  23 #define __MDG_HELPERS_H
  24
  25 #include "util/macros.h"
  26 #include <string.h>
  27
  28 #define OP_IS_LOAD_VARY_F(op) (\
  29                 op == midgard_op_ld_vary_16 || \
  30                 op == midgard_op_ld_vary_32 \
  31         )
  32
  33 #define OP_IS_STORE_VARY(op) (\
  34                 op == midgard_op_st_vary_16 || \
  35                 op == midgard_op_st_vary_32 || \
  36                 op == midgard_op_st_vary_32u || \
  37                 op == midgard_op_st_vary_32i \
  38         )
  39
  40 #define OP_IS_STORE_R26(op) (\
  41                 OP_IS_STORE_VARY(op) || \
  42                 op == midgard_op_st_char || \
  43                 op == midgard_op_st_char2 || \
  44                 op == midgard_op_st_char4 || \
  45                 op == midgard_op_st_short4 || \
  46                 op == midgard_op_st_int4 \
  47         )
  48
  49 #define OP_IS_STORE(op) (\
  50                 OP_IS_STORE_VARY(op) || \
  51                 op == midgard_op_st_cubemap_coords \
  52         )
  53
  54 #define OP_IS_PROJECTION(op) ( \
  55                 op == midgard_op_ldst_perspective_division_z || \
  56                 op == midgard_op_ldst_perspective_division_w \
  57         )
  58
  59 #define OP_IS_R27_ONLY(op) ( \
  60                 OP_IS_PROJECTION(op) || \
  61                 op == midgard_op_st_cubemap_coords \
  62         )
  63
  64 #define OP_IS_MOVE(op) ( \
  65                 op == midgard_alu_op_fmov || \
  66                 op == midgard_alu_op_imov \
  67         )
  68
  69 #define OP_IS_UBO_READ(op) ( \
  70                 op == midgard_op_ld_uniform_32  || \
  71                 op == midgard_op_ld_uniform_16  || \
  72                 op == midgard_op_ld_uniform_32i \
  73         )
  74
  75 #define OP_IS_CSEL(op) ( \
  76                 op == midgard_alu_op_icsel || \
  77                 op == midgard_alu_op_icsel_v || \
  78                 op == midgard_alu_op_fcsel_v || \
  79                 op == midgard_alu_op_fcsel \
  80         )
  81
  82 #define OP_IS_DERIVATIVE(op) ( \
  83                 op == TEXTURE_OP_DFDX || \
  84                 op == TEXTURE_OP_DFDY \
  85         )
  86
  87 /* ALU control words are single bit fields with a lot of space */
  88
  89 #define ALU_ENAB_VEC_MUL  (1 << 17)
  90 #define ALU_ENAB_SCAL_ADD  (1 << 19)
  91 #define ALU_ENAB_VEC_ADD  (1 << 21)
  92 #define ALU_ENAB_SCAL_MUL  (1 << 23)
  93 #define ALU_ENAB_VEC_LUT  (1 << 25)
  94 #define ALU_ENAB_BR_COMPACT (1 << 26)
  95 #define ALU_ENAB_BRANCH   (1 << 27)
  96
  97 /* Other opcode properties that don't conflict with the ALU_ENABs, non-ISA */
  98
  99 /* Denotes an opcode that takes a vector input with a fixed-number of
 100  * channels, but outputs to only a single output channel, like dot products.
 101  * For these, to determine the effective mask, this quirk can be set. We have
 102  * an intentional off-by-one (a la MALI_POSITIVE), since 0-channel makes no
 103  * sense but we need to fit 4 channels in 2-bits. Similarly, 1-channel doesn't
 104  * make sense (since then why are we quirked?), so that corresponds to "no
 105  * count set" */
 106
 107 #define OP_CHANNEL_COUNT(c) ((c - 1) << 0)
 108 #define GET_CHANNEL_COUNT(c) ((c & (0x3 << 0)) ? ((c & (0x3 << 0)) + 1) : 0)
 109
 110 /* For instructions that take a single argument, normally the first argument
 111  * slot is used for the argument and the second slot is a dummy #0 constant.
 112  * However, there are exceptions: instructions like fmov store their argument
 113  * in the _second_ slot and store a dummy r24 in the first slot, designated by
 114  * QUIRK_FLIPPED_R24 */
 115
 116 #define QUIRK_FLIPPED_R24 (1 << 2)
 117
 118 /* Is the op commutative? */
 119 #define OP_COMMUTES (1 << 3)
 120
 121 /* Does the op convert types between int- and float- space (i2f/f2u/etc) */
 122 #define OP_TYPE_CONVERT (1 << 4)
 123
 124 /* Vector-independant shorthands for the above; these numbers are arbitrary and
 125  * not from the ISA. Convert to the above with unit_enum_to_midgard */
 126
 127 #define UNIT_MUL 0
 128 #define UNIT_ADD 1
 129 #define UNIT_LUT 2
 130
 131 /* 4-bit type tags */
 132
 133 #define TAG_TEXTURE_4_VTX 0x2
 134 #define TAG_TEXTURE_4 0x3
 135 #define TAG_LOAD_STORE_4 0x5
 136 #define TAG_ALU_4 0x8
 137 #define TAG_ALU_8 0x9
 138 #define TAG_ALU_12 0xA
 139 #define TAG_ALU_16 0xB
 140
 141 static inline int
 142 quadword_size(int tag)
 143 {
 144         switch (tag) {
 145         case TAG_ALU_4:
 146         case TAG_LOAD_STORE_4:
 147         case TAG_TEXTURE_4:
 148         case TAG_TEXTURE_4_VTX:
 149                 return 1;
 150         case TAG_ALU_8:
 151                 return 2;
 152         case TAG_ALU_12:
 153                 return 3;
 154         case TAG_ALU_16:
 155                 return 4;
 156         default:
 157                 unreachable("Unknown tag");
 158         }
 159 }
 160
 161 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 ||  \
 162                      tag == TAG_ALU_12 || tag == TAG_ALU_16)
 163
 164 /* Special register aliases */
 165
 166 #define MAX_WORK_REGISTERS 16
 167
 168 /* Uniforms are begin at (REGISTER_UNIFORMS - uniform_count) */
 169 #define REGISTER_UNIFORMS 24
 170
 171 #define REGISTER_UNUSED 24
 172 #define REGISTER_CONSTANT 26
 173 #define REGISTER_LDST_BASE 26
 174 #define REGISTER_TEXTURE_BASE 28
 175 #define REGISTER_SELECT 31
 176
 177 /* SSA helper aliases to mimic the registers. UNUSED_0 encoded as an inline
 178  * constant. UNUSED_1 encoded as REGISTER_UNUSED */
 179
 180 #define SSA_UNUSED_0 0
 181 #define SSA_UNUSED_1 -2
 182
 183 #define SSA_FIXED_SHIFT 24
 184 #define SSA_FIXED_REGISTER(reg) (((1 + (reg)) << SSA_FIXED_SHIFT) | 1)
 185 #define SSA_REG_FROM_FIXED(reg) ((((reg) & ~1) >> SSA_FIXED_SHIFT) - 1)
 186 #define SSA_FIXED_MINIMUM SSA_FIXED_REGISTER(0)
 187
 188 /* Swizzle support */
 189
 190 #define SWIZZLE(A, B, C, D) ((D << 6) | (C << 4) | (B << 2) | (A << 0))
 191 #define SWIZZLE_FROM_ARRAY(r) SWIZZLE(r[0], r[1], r[2], r[3])
 192 #define COMPONENT_X 0x0
 193 #define COMPONENT_Y 0x1
 194 #define COMPONENT_Z 0x2
 195 #define COMPONENT_W 0x3
 196
 197 #define SWIZZLE_XXXX SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X)
 198 #define SWIZZLE_XYXX SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_X)
 199 #define SWIZZLE_XYZX SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_X)
 200 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
 201 #define SWIZZLE_XYXZ SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_Z)
 202 #define SWIZZLE_XYZZ SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_Z)
 203 #define SWIZZLE_XXXY SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_Y)
 204 #define SWIZZLE_ZZZW SWIZZLE(COMPONENT_Z, COMPONENT_Z, COMPONENT_Z, COMPONENT_W)
 205 #define SWIZZLE_ZWWW SWIZZLE(COMPONENT_Z, COMPONENT_W, COMPONENT_W, COMPONENT_W)
 206 #define SWIZZLE_WWWW SWIZZLE(COMPONENT_W, COMPONENT_W, COMPONENT_W, COMPONENT_W)
 207
 208 static inline unsigned
 209 swizzle_of(unsigned comp)
 210 {
 211         switch (comp) {
 212         case 1:
 213                 return SWIZZLE_XXXX;
 214         case 2:
 215                 return SWIZZLE_XYXX;
 216         case 3:
 217                 return SWIZZLE_XYZX;
 218         case 4:
 219                 return SWIZZLE_XYZW;
 220         default:
 221                 unreachable("Invalid component count");
 222         }
 223 }
 224
 225 static inline unsigned
 226 mask_of(unsigned nr_comp)
 227 {
 228         return (1 << nr_comp) - 1;
 229 }
 230
 231
 232 /* See ISA notes */
 233
 234 #define LDST_NOP (3)
 235
 236 /* There are five ALU units: VMUL, VADD, SMUL, SADD, LUT. A given opcode is
 237  * implemented on some subset of these units (or occassionally all of them).
 238  * This table encodes a bit mask of valid units for each opcode, so the
 239  * scheduler can figure where to plonk the instruction. */
 240
 241 /* Shorthands for each unit */
 242 #define UNIT_VMUL ALU_ENAB_VEC_MUL
 243 #define UNIT_SADD ALU_ENAB_SCAL_ADD
 244 #define UNIT_VADD ALU_ENAB_VEC_ADD
 245 #define UNIT_SMUL ALU_ENAB_SCAL_MUL
 246 #define UNIT_VLUT ALU_ENAB_VEC_LUT
 247
 248 /* Shorthands for usual combinations of units */
 249
 250 #define UNITS_MUL (UNIT_VMUL | UNIT_SMUL)
 251 #define UNITS_ADD (UNIT_VADD | UNIT_SADD)
 252 #define UNITS_MOST (UNITS_MUL | UNITS_ADD)
 253 #define UNITS_ALL (UNITS_MOST | UNIT_VLUT)
 254 #define UNITS_SCALAR (UNIT_SADD | UNIT_SMUL)
 255 #define UNITS_VECTOR (UNIT_VMUL | UNIT_VADD)
 256 #define UNITS_ANY_VECTOR (UNITS_VECTOR | UNIT_VLUT)
 257
 258 struct mir_op_props {
 259         const char *name;
 260         unsigned props;
 261 };
 262
 263 /* This file is common, so don't define the tables themselves. #include
 264  * midgard_op.h if you need that, or edit midgard_ops.c directly */
 265
 266 /* Duplicate bits to convert a 4-bit writemask to duplicated 8-bit format,
 267  * which is used for 32-bit vector units */
 268
 269 static inline unsigned
 270 expand_writemask_32(unsigned mask)
 271 {
 272         unsigned o = 0;
 273
 274         for (int i = 0; i < 4; ++i)
 275                 if (mask & (1 << i))
 276                         o |= (3 << (2 * i));
 277
 278         return o;
 279 }
 280
 281 /* Coerce structs to integer */
 282
 283 static inline unsigned
 284 vector_alu_srco_unsigned(midgard_vector_alu_src src)
 285 {
 286         unsigned u;
 287         memcpy(&u, &src, sizeof(src));
 288         return u;
 289 }
 290
 291 static inline midgard_vector_alu_src
 292 vector_alu_from_unsigned(unsigned u)
 293 {
 294         midgard_vector_alu_src s;
 295         memcpy(&s, &u, sizeof(s));
 296         return s;
 297 }
 298
 299 /* Composes two swizzles */
 300 static inline unsigned
 301 pan_compose_swizzle(unsigned left, unsigned right)
 302 {
 303         unsigned out = 0;
 304
 305         for (unsigned c = 0; c < 4; ++c) {
 306                 unsigned s = (left >> (2*c)) & 0x3;
 307                 unsigned q = (right >> (2*s)) & 0x3;
 308
 309                 out |= (q << (2*c));
 310         }
 311
 312         return out;
 313 }
 314
 315 /* Applies a swizzle to an ALU source */
 316
 317 static inline unsigned
 318 vector_alu_apply_swizzle(unsigned src, unsigned swizzle)
 319 {
 320         midgard_vector_alu_src s =
 321                 vector_alu_from_unsigned(src);
 322
 323         s.swizzle = pan_compose_swizzle(s.swizzle, swizzle);
 324
 325         return vector_alu_srco_unsigned(s);
 326 }
 327
 328 /* Checks for an xyzw.. swizzle, given a mask */
 329
 330 static inline bool
 331 mir_is_simple_swizzle(unsigned swizzle, unsigned mask)
 332 {
 333         for (unsigned i = 0; i < 16; ++i) {
 334                 if (!(mask & (1 << i))) continue;
 335
 336                 if (((swizzle >> (2 * i)) & 0x3) != i)
 337                         return false;
 338         }
 339
 340         return true;
 341 }
 342
 343 #endif