src/panfrost/midgard/helpers.h

   1 /* Copyright (c) 2018-2019 Alyssa Rosenzweig (alyssa@rosenzweig.io)
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a copy
   4  * of this software and associated documentation files (the "Software"), to deal
   5  * in the Software without restriction, including without limitation the rights
   6  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   7  * copies of the Software, and to permit persons to whom the Software is
   8  * furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice shall be included in
  11  * all copies or substantial portions of the Software.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  16  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  18  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  19  * THE SOFTWARE.
  20  */
  21
  22 #ifndef __MDG_HELPERS_H
  23 #define __MDG_HELPERS_H
  24
  25 #include "util/macros.h"
  26 #include <string.h>
  27
  28 #define OP_IS_LOAD_VARY_F(op) (\
  29                 op == midgard_op_ld_vary_16 || \
  30                 op == midgard_op_ld_vary_32 \
  31         )
  32
  33 #define OP_IS_PROJECTION(op) ( \
  34                 op == midgard_op_ldst_perspective_division_z || \
  35                 op == midgard_op_ldst_perspective_division_w \
  36         )
  37
  38 #define OP_IS_VEC4_ONLY(op) ( \
  39                 OP_IS_PROJECTION(op) || \
  40                 op == midgard_op_ld_cubemap_coords \
  41         )
  42
  43 #define OP_IS_MOVE(op) ( \
  44                 op == midgard_alu_op_fmov || \
  45                 op == midgard_alu_op_imov \
  46         )
  47
  48 #define OP_IS_UBO_READ(op) ( \
  49                 op == midgard_op_ld_ubo_char  || \
  50                 op == midgard_op_ld_ubo_char2  || \
  51                 op == midgard_op_ld_ubo_char4  || \
  52                 op == midgard_op_ld_ubo_short4  || \
  53                 op == midgard_op_ld_ubo_int4 \
  54         )
  55
  56 #define OP_IS_CSEL_V(op) ( \
  57                 op == midgard_alu_op_icsel_v || \
  58                 op == midgard_alu_op_fcsel_v \
  59         )
  60
  61 #define OP_IS_CSEL(op) ( \
  62                 OP_IS_CSEL_V(op) || \
  63                 op == midgard_alu_op_icsel || \
  64                 op == midgard_alu_op_fcsel \
  65         )
  66
  67 #define OP_IS_DERIVATIVE(op) ( \
  68                 op == TEXTURE_OP_DFDX || \
  69                 op == TEXTURE_OP_DFDY \
  70         )
  71
  72 /* ALU control words are single bit fields with a lot of space */
  73
  74 #define ALU_ENAB_VEC_MUL  (1 << 17)
  75 #define ALU_ENAB_SCAL_ADD  (1 << 19)
  76 #define ALU_ENAB_VEC_ADD  (1 << 21)
  77 #define ALU_ENAB_SCAL_MUL  (1 << 23)
  78 #define ALU_ENAB_VEC_LUT  (1 << 25)
  79 #define ALU_ENAB_BR_COMPACT (1 << 26)
  80 #define ALU_ENAB_BRANCH   (1 << 27)
  81
  82 /* Other opcode properties that don't conflict with the ALU_ENABs, non-ISA */
  83
  84 /* Denotes an opcode that takes a vector input with a fixed-number of
  85  * channels, but outputs to only a single output channel, like dot products.
  86  * For these, to determine the effective mask, this quirk can be set. We have
  87  * an intentional off-by-one (a la MALI_POSITIVE), since 0-channel makes no
  88  * sense but we need to fit 4 channels in 2-bits. Similarly, 1-channel doesn't
  89  * make sense (since then why are we quirked?), so that corresponds to "no
  90  * count set" */
  91
  92 #define OP_CHANNEL_COUNT(c) ((c - 1) << 0)
  93 #define GET_CHANNEL_COUNT(c) ((c & (0x3 << 0)) ? ((c & (0x3 << 0)) + 1) : 0)
  94
  95 /* For instructions that take a single argument, normally the first argument
  96  * slot is used for the argument and the second slot is a dummy #0 constant.
  97  * However, there are exceptions: instructions like fmov store their argument
  98  * in the _second_ slot and store a dummy r24 in the first slot, designated by
  99  * QUIRK_FLIPPED_R24 */
 100
 101 #define QUIRK_FLIPPED_R24 (1 << 2)
 102
 103 /* Is the op commutative? */
 104 #define OP_COMMUTES (1 << 3)
 105
 106 /* Does the op convert types between int- and float- space (i2f/f2u/etc) */
 107 #define OP_TYPE_CONVERT (1 << 4)
 108
 109 /* Vector-independant shorthands for the above; these numbers are arbitrary and
 110  * not from the ISA. Convert to the above with unit_enum_to_midgard */
 111
 112 #define UNIT_MUL 0
 113 #define UNIT_ADD 1
 114 #define UNIT_LUT 2
 115
 116 /* 4-bit type tags */
 117
 118 #define TAG_TEXTURE_4_VTX 0x2
 119 #define TAG_TEXTURE_4 0x3
 120 #define TAG_LOAD_STORE_4 0x5
 121 #define TAG_ALU_4 0x8
 122 #define TAG_ALU_8 0x9
 123 #define TAG_ALU_12 0xA
 124 #define TAG_ALU_16 0xB
 125
 126 static inline int
 127 quadword_size(int tag)
 128 {
 129         switch (tag) {
 130         case TAG_ALU_4:
 131         case TAG_LOAD_STORE_4:
 132         case TAG_TEXTURE_4:
 133         case TAG_TEXTURE_4_VTX:
 134                 return 1;
 135         case TAG_ALU_8:
 136                 return 2;
 137         case TAG_ALU_12:
 138                 return 3;
 139         case TAG_ALU_16:
 140                 return 4;
 141         default:
 142                 unreachable("Unknown tag");
 143         }
 144 }
 145
 146 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 ||  \
 147                      tag == TAG_ALU_12 || tag == TAG_ALU_16)
 148
 149 /* Special register aliases */
 150
 151 #define MAX_WORK_REGISTERS 16
 152
 153 /* Uniforms are begin at (REGISTER_UNIFORMS - uniform_count) */
 154 #define REGISTER_UNIFORMS 24
 155
 156 #define REGISTER_UNUSED 24
 157 #define REGISTER_CONSTANT 26
 158 #define REGISTER_LDST_BASE 26
 159 #define REGISTER_TEXTURE_BASE 28
 160 #define REGISTER_SELECT 31
 161
 162 /* SSA helper aliases to mimic the registers. */
 163
 164 #define SSA_UNUSED ~0
 165 #define SSA_FIXED_SHIFT 24
 166 #define SSA_FIXED_REGISTER(reg) (((1 + (reg)) << SSA_FIXED_SHIFT) | 1)
 167 #define SSA_REG_FROM_FIXED(reg) ((((reg) & ~1) >> SSA_FIXED_SHIFT) - 1)
 168 #define SSA_FIXED_MINIMUM SSA_FIXED_REGISTER(0)
 169
 170 #define COMPONENT_X 0x0
 171 #define COMPONENT_Y 0x1
 172 #define COMPONENT_Z 0x2
 173 #define COMPONENT_W 0x3
 174
 175 #define SWIZZLE_IDENTITY { \
 176         { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, \
 177         { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, \
 178         { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 } \
 179 }
 180
 181 #define SWIZZLE_IDENTITY_4 { \
 182         { 0, 1, 2, 3, 0, 0, 0, 0, 0, 0,  0,  0,  0,  0,  0,  0 }, \
 183         { 0, 1, 2, 3, 0, 0, 0, 0, 0, 0,  0,  0,  0,  0,  0,  0 }, \
 184         { 0, 1, 2, 3, 0, 0, 0, 0, 0, 0,  0,  0,  0,  0,  0,  0 }, \
 185 }
 186
 187 static inline unsigned
 188 mask_of(unsigned nr_comp)
 189 {
 190         return (1 << nr_comp) - 1;
 191 }
 192
 193 /* See ISA notes */
 194
 195 #define LDST_NOP (3)
 196
 197 /* There are five ALU units: VMUL, VADD, SMUL, SADD, LUT. A given opcode is
 198  * implemented on some subset of these units (or occassionally all of them).
 199  * This table encodes a bit mask of valid units for each opcode, so the
 200  * scheduler can figure where to plonk the instruction. */
 201
 202 /* Shorthands for each unit */
 203 #define UNIT_VMUL ALU_ENAB_VEC_MUL
 204 #define UNIT_SADD ALU_ENAB_SCAL_ADD
 205 #define UNIT_VADD ALU_ENAB_VEC_ADD
 206 #define UNIT_SMUL ALU_ENAB_SCAL_MUL
 207 #define UNIT_VLUT ALU_ENAB_VEC_LUT
 208
 209 /* Shorthands for usual combinations of units */
 210
 211 #define UNITS_MUL (UNIT_VMUL | UNIT_SMUL)
 212 #define UNITS_ADD (UNIT_VADD | UNIT_SADD)
 213 #define UNITS_MOST (UNITS_MUL | UNITS_ADD)
 214 #define UNITS_ALL (UNITS_MOST | UNIT_VLUT)
 215 #define UNITS_SCALAR (UNIT_SADD | UNIT_SMUL)
 216 #define UNITS_VECTOR (UNIT_VMUL | UNIT_VADD)
 217 #define UNITS_ANY_VECTOR (UNITS_VECTOR | UNIT_VLUT)
 218
 219 struct mir_op_props {
 220         const char *name;
 221         unsigned props;
 222 };
 223
 224 /* For load/store */
 225
 226 struct mir_ldst_op_props {
 227         const char *name;
 228         unsigned props;
 229 };
 230
 231 /* Lower 2-bits are a midgard_reg_mode */
 232 #define GET_LDST_SIZE(c) (c & 3)
 233
 234 /* Store (so the primary register is a source, not a destination */
 235 #define LDST_STORE (1 << 2)
 236
 237 /* Mask has special meaning and should not be manipulated directly */
 238 #define LDST_SPECIAL_MASK (1 << 3)
 239
 240 /* Non-store operation has side effects and should not be eliminated even if
 241  * its mask is 0 */
 242 #define LDST_SIDE_FX (1 << 4)
 243
 244 /* This file is common, so don't define the tables themselves. #include
 245  * midgard_op.h if you need that, or edit midgard_ops.c directly */
 246
 247 /* Duplicate bits to convert a 4-bit writemask to duplicated 8-bit format,
 248  * which is used for 32-bit vector units */
 249
 250 static inline unsigned
 251 expand_writemask_32(unsigned mask)
 252 {
 253         unsigned o = 0;
 254
 255         for (int i = 0; i < 4; ++i)
 256                 if (mask & (1 << i))
 257                         o |= (3 << (2 * i));
 258
 259         return o;
 260 }
 261
 262 /* Coerce structs to integer */
 263
 264 static inline unsigned
 265 vector_alu_srco_unsigned(midgard_vector_alu_src src)
 266 {
 267         unsigned u;
 268         memcpy(&u, &src, sizeof(src));
 269         return u;
 270 }
 271
 272 static inline midgard_vector_alu_src
 273 vector_alu_from_unsigned(unsigned u)
 274 {
 275         midgard_vector_alu_src s;
 276         memcpy(&s, &u, sizeof(s));
 277         return s;
 278 }
 279
 280 static inline void
 281 mir_compose_swizzle(unsigned *left, unsigned *right, unsigned *final_out)
 282 {
 283         unsigned out[16];
 284
 285         for (unsigned c = 0; c < 16; ++c)
 286                 out[c] = right[left[c]];
 287
 288         memcpy(final_out, out, sizeof(out));
 289 }
 290
 291 /* Checks for an xyzw.. swizzle, given a mask */
 292
 293 static inline bool
 294 mir_is_simple_swizzle(unsigned *swizzle, unsigned mask)
 295 {
 296         for (unsigned i = 0; i < 16; ++i) {
 297                 if (!(mask & (1 << i))) continue;
 298
 299                 if (swizzle[i] != i)
 300                         return false;
 301         }
 302
 303         return true;
 304 }
 305
 306 /* Packs a load/store argument */
 307
 308 static inline uint8_t
 309 midgard_ldst_reg(unsigned reg, unsigned component)
 310 {
 311         assert((reg == REGISTER_LDST_BASE) || (reg == REGISTER_LDST_BASE + 1));
 312
 313         midgard_ldst_register_select sel = {
 314                 .component = component,
 315                 .select = reg - 26
 316         };
 317
 318         uint8_t packed;
 319         memcpy(&packed, &sel, sizeof(packed));
 320
 321         return packed;
 322 }
 323
 324 /* Unpacks a load/store argument */
 325
 326 static inline midgard_ldst_register_select
 327 midgard_ldst_select(uint8_t u)
 328 {
 329         midgard_ldst_register_select sel;
 330         memcpy(&sel, &u, sizeof(u));
 331         return sel;
 332 }
 333
 334 static inline uint8_t
 335 midgard_ldst_pack(midgard_ldst_register_select sel)
 336 {
 337         uint8_t packed;
 338         memcpy(&packed, &sel, sizeof(packed));
 339         return packed;
 340 }
 341
 342 #endif