src/panfrost/midgard/helpers.h

   1 /* Copyright (c) 2018-2019 Alyssa Rosenzweig (alyssa@rosenzweig.io)
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a copy
   4  * of this software and associated documentation files (the "Software"), to deal
   5  * in the Software without restriction, including without limitation the rights
   6  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   7  * copies of the Software, and to permit persons to whom the Software is
   8  * furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice shall be included in
  11  * all copies or substantial portions of the Software.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  16  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  18  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  19  * THE SOFTWARE.
  20  */
  21
  22 #ifndef __MDG_HELPERS_H
  23 #define __MDG_HELPERS_H
  24
  25 #include "util/macros.h"
  26 #include <string.h>
  27
  28 #define OP_IS_LOAD_VARY_F(op) (\
  29                 op == midgard_op_ld_vary_16 || \
  30                 op == midgard_op_ld_vary_32 \
  31         )
  32
  33 #define OP_IS_STORE_VARY(op) (\
  34                 op == midgard_op_st_vary_16 || \
  35                 op == midgard_op_st_vary_32 || \
  36                 op == midgard_op_st_vary_32u || \
  37                 op == midgard_op_st_vary_32i \
  38         )
  39
  40 #define OP_IS_STORE_R26(op) (\
  41                 OP_IS_STORE_VARY(op) || \
  42                 op == midgard_op_st_char || \
  43                 op == midgard_op_st_char2 || \
  44                 op == midgard_op_st_char4 || \
  45                 op == midgard_op_st_short4 || \
  46                 op == midgard_op_st_int4 \
  47         )
  48
  49 #define OP_IS_STORE(op) (\
  50                 OP_IS_STORE_R26(op) \
  51         )
  52
  53 #define OP_IS_PROJECTION(op) ( \
  54                 op == midgard_op_ldst_perspective_division_z || \
  55                 op == midgard_op_ldst_perspective_division_w \
  56         )
  57
  58 #define OP_IS_VEC4_ONLY(op) ( \
  59                 OP_IS_PROJECTION(op) || \
  60                 op == midgard_op_ld_cubemap_coords \
  61         )
  62
  63 #define OP_IS_MOVE(op) ( \
  64                 op == midgard_alu_op_fmov || \
  65                 op == midgard_alu_op_imov \
  66         )
  67
  68 #define OP_IS_UBO_READ(op) ( \
  69                 op == midgard_op_ld_ubo_char  || \
  70                 op == midgard_op_ld_ubo_char2  || \
  71                 op == midgard_op_ld_ubo_char4  || \
  72                 op == midgard_op_ld_ubo_short4  || \
  73                 op == midgard_op_ld_ubo_int4 \
  74         )
  75
  76 #define OP_IS_CSEL_V(op) ( \
  77                 op == midgard_alu_op_icsel_v || \
  78                 op == midgard_alu_op_fcsel_v \
  79         )
  80
  81 #define OP_IS_CSEL(op) ( \
  82                 OP_IS_CSEL_V(op) || \
  83                 op == midgard_alu_op_icsel || \
  84                 op == midgard_alu_op_fcsel \
  85         )
  86
  87 #define OP_IS_DERIVATIVE(op) ( \
  88                 op == TEXTURE_OP_DFDX || \
  89                 op == TEXTURE_OP_DFDY \
  90         )
  91
  92 /* ALU control words are single bit fields with a lot of space */
  93
  94 #define ALU_ENAB_VEC_MUL  (1 << 17)
  95 #define ALU_ENAB_SCAL_ADD  (1 << 19)
  96 #define ALU_ENAB_VEC_ADD  (1 << 21)
  97 #define ALU_ENAB_SCAL_MUL  (1 << 23)
  98 #define ALU_ENAB_VEC_LUT  (1 << 25)
  99 #define ALU_ENAB_BR_COMPACT (1 << 26)
 100 #define ALU_ENAB_BRANCH   (1 << 27)
 101
 102 /* Other opcode properties that don't conflict with the ALU_ENABs, non-ISA */
 103
 104 /* Denotes an opcode that takes a vector input with a fixed-number of
 105  * channels, but outputs to only a single output channel, like dot products.
 106  * For these, to determine the effective mask, this quirk can be set. We have
 107  * an intentional off-by-one (a la MALI_POSITIVE), since 0-channel makes no
 108  * sense but we need to fit 4 channels in 2-bits. Similarly, 1-channel doesn't
 109  * make sense (since then why are we quirked?), so that corresponds to "no
 110  * count set" */
 111
 112 #define OP_CHANNEL_COUNT(c) ((c - 1) << 0)
 113 #define GET_CHANNEL_COUNT(c) ((c & (0x3 << 0)) ? ((c & (0x3 << 0)) + 1) : 0)
 114
 115 /* For instructions that take a single argument, normally the first argument
 116  * slot is used for the argument and the second slot is a dummy #0 constant.
 117  * However, there are exceptions: instructions like fmov store their argument
 118  * in the _second_ slot and store a dummy r24 in the first slot, designated by
 119  * QUIRK_FLIPPED_R24 */
 120
 121 #define QUIRK_FLIPPED_R24 (1 << 2)
 122
 123 /* Is the op commutative? */
 124 #define OP_COMMUTES (1 << 3)
 125
 126 /* Does the op convert types between int- and float- space (i2f/f2u/etc) */
 127 #define OP_TYPE_CONVERT (1 << 4)
 128
 129 /* Vector-independant shorthands for the above; these numbers are arbitrary and
 130  * not from the ISA. Convert to the above with unit_enum_to_midgard */
 131
 132 #define UNIT_MUL 0
 133 #define UNIT_ADD 1
 134 #define UNIT_LUT 2
 135
 136 /* 4-bit type tags */
 137
 138 #define TAG_TEXTURE_4_VTX 0x2
 139 #define TAG_TEXTURE_4 0x3
 140 #define TAG_LOAD_STORE_4 0x5
 141 #define TAG_ALU_4 0x8
 142 #define TAG_ALU_8 0x9
 143 #define TAG_ALU_12 0xA
 144 #define TAG_ALU_16 0xB
 145
 146 static inline int
 147 quadword_size(int tag)
 148 {
 149         switch (tag) {
 150         case TAG_ALU_4:
 151         case TAG_LOAD_STORE_4:
 152         case TAG_TEXTURE_4:
 153         case TAG_TEXTURE_4_VTX:
 154                 return 1;
 155         case TAG_ALU_8:
 156                 return 2;
 157         case TAG_ALU_12:
 158                 return 3;
 159         case TAG_ALU_16:
 160                 return 4;
 161         default:
 162                 unreachable("Unknown tag");
 163         }
 164 }
 165
 166 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 ||  \
 167                      tag == TAG_ALU_12 || tag == TAG_ALU_16)
 168
 169 /* Special register aliases */
 170
 171 #define MAX_WORK_REGISTERS 16
 172
 173 /* Uniforms are begin at (REGISTER_UNIFORMS - uniform_count) */
 174 #define REGISTER_UNIFORMS 24
 175
 176 #define REGISTER_UNUSED 24
 177 #define REGISTER_CONSTANT 26
 178 #define REGISTER_LDST_BASE 26
 179 #define REGISTER_TEXTURE_BASE 28
 180 #define REGISTER_SELECT 31
 181
 182 /* SSA helper aliases to mimic the registers. */
 183
 184 #define SSA_UNUSED ~0
 185 #define SSA_FIXED_SHIFT 24
 186 #define SSA_FIXED_REGISTER(reg) (((1 + (reg)) << SSA_FIXED_SHIFT) | 1)
 187 #define SSA_REG_FROM_FIXED(reg) ((((reg) & ~1) >> SSA_FIXED_SHIFT) - 1)
 188 #define SSA_FIXED_MINIMUM SSA_FIXED_REGISTER(0)
 189
 190 /* Swizzle support */
 191
 192 #define SWIZZLE(A, B, C, D) (((D) << 6) | ((C) << 4) | ((B) << 2) | ((A) << 0))
 193 #define SWIZZLE_FROM_ARRAY(r) SWIZZLE(r[0], r[1], r[2], r[3])
 194 #define COMPONENT_X 0x0
 195 #define COMPONENT_Y 0x1
 196 #define COMPONENT_Z 0x2
 197 #define COMPONENT_W 0x3
 198
 199 #define SWIZZLE_XXXX SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X)
 200 #define SWIZZLE_XYXX SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_X)
 201 #define SWIZZLE_XYZX SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_X)
 202 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
 203 #define SWIZZLE_XYXZ SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_Z)
 204 #define SWIZZLE_XYZZ SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_Z)
 205 #define SWIZZLE_XXXY SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_Y)
 206 #define SWIZZLE_ZZZW SWIZZLE(COMPONENT_Z, COMPONENT_Z, COMPONENT_Z, COMPONENT_W)
 207 #define SWIZZLE_ZWWW SWIZZLE(COMPONENT_Z, COMPONENT_W, COMPONENT_W, COMPONENT_W)
 208 #define SWIZZLE_WWWW SWIZZLE(COMPONENT_W, COMPONENT_W, COMPONENT_W, COMPONENT_W)
 209
 210 static inline unsigned
 211 swizzle_of(unsigned comp)
 212 {
 213         switch (comp) {
 214         case 1:
 215                 return SWIZZLE_XXXX;
 216         case 2:
 217                 return SWIZZLE_XYXX;
 218         case 3:
 219                 return SWIZZLE_XYZX;
 220         case 4:
 221                 return SWIZZLE_XYZW;
 222         default:
 223                 unreachable("Invalid component count");
 224         }
 225 }
 226
 227 static inline unsigned
 228 mask_of(unsigned nr_comp)
 229 {
 230         return (1 << nr_comp) - 1;
 231 }
 232
 233
 234 /* See ISA notes */
 235
 236 #define LDST_NOP (3)
 237
 238 /* There are five ALU units: VMUL, VADD, SMUL, SADD, LUT. A given opcode is
 239  * implemented on some subset of these units (or occassionally all of them).
 240  * This table encodes a bit mask of valid units for each opcode, so the
 241  * scheduler can figure where to plonk the instruction. */
 242
 243 /* Shorthands for each unit */
 244 #define UNIT_VMUL ALU_ENAB_VEC_MUL
 245 #define UNIT_SADD ALU_ENAB_SCAL_ADD
 246 #define UNIT_VADD ALU_ENAB_VEC_ADD
 247 #define UNIT_SMUL ALU_ENAB_SCAL_MUL
 248 #define UNIT_VLUT ALU_ENAB_VEC_LUT
 249
 250 /* Shorthands for usual combinations of units */
 251
 252 #define UNITS_MUL (UNIT_VMUL | UNIT_SMUL)
 253 #define UNITS_ADD (UNIT_VADD | UNIT_SADD)
 254 #define UNITS_MOST (UNITS_MUL | UNITS_ADD)
 255 #define UNITS_ALL (UNITS_MOST | UNIT_VLUT)
 256 #define UNITS_SCALAR (UNIT_SADD | UNIT_SMUL)
 257 #define UNITS_VECTOR (UNIT_VMUL | UNIT_VADD)
 258 #define UNITS_ANY_VECTOR (UNITS_VECTOR | UNIT_VLUT)
 259
 260 struct mir_op_props {
 261         const char *name;
 262         unsigned props;
 263 };
 264
 265 /* This file is common, so don't define the tables themselves. #include
 266  * midgard_op.h if you need that, or edit midgard_ops.c directly */
 267
 268 /* Duplicate bits to convert a 4-bit writemask to duplicated 8-bit format,
 269  * which is used for 32-bit vector units */
 270
 271 static inline unsigned
 272 expand_writemask_32(unsigned mask)
 273 {
 274         unsigned o = 0;
 275
 276         for (int i = 0; i < 4; ++i)
 277                 if (mask & (1 << i))
 278                         o |= (3 << (2 * i));
 279
 280         return o;
 281 }
 282
 283 /* Coerce structs to integer */
 284
 285 static inline unsigned
 286 vector_alu_srco_unsigned(midgard_vector_alu_src src)
 287 {
 288         unsigned u;
 289         memcpy(&u, &src, sizeof(src));
 290         return u;
 291 }
 292
 293 static inline midgard_vector_alu_src
 294 vector_alu_from_unsigned(unsigned u)
 295 {
 296         midgard_vector_alu_src s;
 297         memcpy(&s, &u, sizeof(s));
 298         return s;
 299 }
 300
 301 /* Composes two swizzles */
 302 static inline unsigned
 303 pan_compose_swizzle(unsigned left, unsigned right)
 304 {
 305         unsigned out = 0;
 306
 307         for (unsigned c = 0; c < 4; ++c) {
 308                 unsigned s = (left >> (2*c)) & 0x3;
 309                 unsigned q = (right >> (2*s)) & 0x3;
 310
 311                 out |= (q << (2*c));
 312         }
 313
 314         return out;
 315 }
 316
 317 /* Applies a swizzle to an ALU source */
 318
 319 static inline unsigned
 320 vector_alu_apply_swizzle(unsigned src, unsigned swizzle)
 321 {
 322         midgard_vector_alu_src s =
 323                 vector_alu_from_unsigned(src);
 324
 325         s.swizzle = pan_compose_swizzle(s.swizzle, swizzle);
 326
 327         return vector_alu_srco_unsigned(s);
 328 }
 329
 330 /* Checks for an xyzw.. swizzle, given a mask */
 331
 332 static inline bool
 333 mir_is_simple_swizzle(unsigned swizzle, unsigned mask)
 334 {
 335         for (unsigned i = 0; i < 16; ++i) {
 336                 if (!(mask & (1 << i))) continue;
 337
 338                 if (((swizzle >> (2 * i)) & 0x3) != i)
 339                         return false;
 340         }
 341
 342         return true;
 343 }
 344
 345 /* Packs a load/store argument */
 346
 347 static inline uint8_t
 348 midgard_ldst_reg(unsigned reg, unsigned component)
 349 {
 350         assert((reg == REGISTER_LDST_BASE) || (reg == REGISTER_LDST_BASE + 1));
 351
 352         midgard_ldst_register_select sel = {
 353                 .component = component,
 354                 .select = reg - 26
 355         };
 356
 357         uint8_t packed;
 358         memcpy(&packed, &sel, sizeof(packed));
 359
 360         return packed;
 361 }
 362
 363 /* Unpacks a load/store argument */
 364
 365 static inline midgard_ldst_register_select
 366 midgard_ldst_select(uint8_t u)
 367 {
 368         midgard_ldst_register_select sel;
 369         memcpy(&sel, &u, sizeof(u));
 370         return sel;
 371 }
 372
 373 static inline uint8_t
 374 midgard_ldst_pack(midgard_ldst_register_select sel)
 375 {
 376         uint8_t packed;
 377         memcpy(&packed, &sel, sizeof(packed));
 378         return packed;
 379 }
 380
 381 /* Gets a swizzle like yyyy and returns y */
 382
 383 static inline unsigned
 384 swizzle_to_component(unsigned swizzle)
 385 {
 386         unsigned c = swizzle & 3;
 387         assert(((swizzle >> 2) & 3) == c);
 388         assert(((swizzle >> 4) & 3) == c);
 389         assert(((swizzle >> 6) & 3) == c);
 390         return  c;
 391 }
 392
 393
 394 static inline unsigned
 395 component_to_swizzle(unsigned c, unsigned count)
 396 {
 397         switch (count) {
 398         case 1:
 399                 return SWIZZLE(c, c, c, c);
 400         case 2:
 401                 return SWIZZLE(c, c + 1, c + 1, c + 1);
 402         case 3:
 403                 return SWIZZLE(c, c + 1, c + 2, c + 2);
 404         case 4:
 405                 return SWIZZLE(c, c + 1, c + 2, c + 3);
 406         default:
 407                 unreachable("Invalid component count");
 408         }
 409 }
 410
 411 #endif