src/panfrost/midgard/helpers.h

   1 /* Copyright (c) 2018-2019 Alyssa Rosenzweig (alyssa@rosenzweig.io)
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a copy
   4  * of this software and associated documentation files (the "Software"), to deal
   5  * in the Software without restriction, including without limitation the rights
   6  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   7  * copies of the Software, and to permit persons to whom the Software is
   8  * furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice shall be included in
  11  * all copies or substantial portions of the Software.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  16  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  18  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  19  * THE SOFTWARE.
  20  */
  21
  22 #ifndef __MDG_HELPERS_H
  23 #define __MDG_HELPERS_H
  24
  25 #include "util/macros.h"
  26 #include <string.h>
  27
  28 #define OP_IS_STORE_VARY(op) (\
  29                 op == midgard_op_st_vary_16 || \
  30                 op == midgard_op_st_vary_32 || \
  31                 op == midgard_op_st_vary_32u || \
  32                 op == midgard_op_st_vary_32i \
  33         )
  34
  35 #define OP_IS_STORE_R26(op) (\
  36                 OP_IS_STORE_VARY(op) || \
  37                 op == midgard_op_st_char || \
  38                 op == midgard_op_st_char2 || \
  39                 op == midgard_op_st_char4 || \
  40                 op == midgard_op_st_short4 || \
  41                 op == midgard_op_st_int4 \
  42         )
  43
  44 #define OP_IS_STORE(op) (\
  45                 OP_IS_STORE_VARY(op) || \
  46                 op == midgard_op_st_cubemap_coords \
  47         )
  48
  49 #define OP_IS_MOVE(op) ( \
  50                 op == midgard_alu_op_fmov || \
  51                 op == midgard_alu_op_imov \
  52         )
  53
  54 #define OP_IS_UBO_READ(op) ( \
  55                 op == midgard_op_ld_uniform_32  || \
  56                 op == midgard_op_ld_uniform_16  || \
  57                 op == midgard_op_ld_uniform_32i \
  58         )
  59
  60 #define OP_IS_CSEL(op) ( \
  61                 op == midgard_alu_op_icsel || \
  62                 op == midgard_alu_op_icsel_v || \
  63                 op == midgard_alu_op_fcsel_v || \
  64                 op == midgard_alu_op_fcsel \
  65         )
  66
  67 /* ALU control words are single bit fields with a lot of space */
  68
  69 #define ALU_ENAB_VEC_MUL  (1 << 17)
  70 #define ALU_ENAB_SCAL_ADD  (1 << 19)
  71 #define ALU_ENAB_VEC_ADD  (1 << 21)
  72 #define ALU_ENAB_SCAL_MUL  (1 << 23)
  73 #define ALU_ENAB_VEC_LUT  (1 << 25)
  74 #define ALU_ENAB_BR_COMPACT (1 << 26)
  75 #define ALU_ENAB_BRANCH   (1 << 27)
  76
  77 /* Other opcode properties that don't conflict with the ALU_ENABs, non-ISA */
  78
  79 /* Denotes an opcode that takes a vector input with a fixed-number of
  80  * channels, but outputs to only a single output channel, like dot products.
  81  * For these, to determine the effective mask, this quirk can be set. We have
  82  * an intentional off-by-one (a la MALI_POSITIVE), since 0-channel makes no
  83  * sense but we need to fit 4 channels in 2-bits. Similarly, 1-channel doesn't
  84  * make sense (since then why are we quirked?), so that corresponds to "no
  85  * count set" */
  86
  87 #define OP_CHANNEL_COUNT(c) ((c - 1) << 0)
  88 #define GET_CHANNEL_COUNT(c) ((c & (0x3 << 0)) ? ((c & (0x3 << 0)) + 1) : 0)
  89
  90 /* For instructions that take a single argument, normally the first argument
  91  * slot is used for the argument and the second slot is a dummy #0 constant.
  92  * However, there are exceptions: instructions like fmov store their argument
  93  * in the _second_ slot and store a dummy r24 in the first slot, designated by
  94  * QUIRK_FLIPPED_R24 */
  95
  96 #define QUIRK_FLIPPED_R24 (1 << 2)
  97
  98 /* Is the op commutative? */
  99 #define OP_COMMUTES (1 << 3)
 100
 101 /* Does the op convert types between int- and float- space (i2f/f2u/etc) */
 102 #define OP_TYPE_CONVERT (1 << 4)
 103
 104 /* Vector-independant shorthands for the above; these numbers are arbitrary and
 105  * not from the ISA. Convert to the above with unit_enum_to_midgard */
 106
 107 #define UNIT_MUL 0
 108 #define UNIT_ADD 1
 109 #define UNIT_LUT 2
 110
 111 /* 4-bit type tags */
 112
 113 #define TAG_TEXTURE_4_VTX 0x2
 114 #define TAG_TEXTURE_4 0x3
 115 #define TAG_LOAD_STORE_4 0x5
 116 #define TAG_ALU_4 0x8
 117 #define TAG_ALU_8 0x9
 118 #define TAG_ALU_12 0xA
 119 #define TAG_ALU_16 0xB
 120
 121 static inline int
 122 quadword_size(int tag)
 123 {
 124         switch (tag) {
 125         case TAG_ALU_4:
 126         case TAG_LOAD_STORE_4:
 127         case TAG_TEXTURE_4:
 128         case TAG_TEXTURE_4_VTX:
 129                 return 1;
 130         case TAG_ALU_8:
 131                 return 2;
 132         case TAG_ALU_12:
 133                 return 3;
 134         case TAG_ALU_16:
 135                 return 4;
 136         default:
 137                 unreachable("Unknown tag");
 138         }
 139 }
 140
 141 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 ||  \
 142                      tag == TAG_ALU_12 || tag == TAG_ALU_16)
 143
 144 /* Special register aliases */
 145
 146 #define MAX_WORK_REGISTERS 16
 147
 148 /* Uniforms are begin at (REGISTER_UNIFORMS - uniform_count) */
 149 #define REGISTER_UNIFORMS 24
 150
 151 #define REGISTER_UNUSED 24
 152 #define REGISTER_CONSTANT 26
 153 #define REGISTER_VARYING_BASE 26
 154 #define REGISTER_OFFSET 27
 155 #define REGISTER_TEXTURE_BASE 28
 156 #define REGISTER_SELECT 31
 157
 158 /* SSA helper aliases to mimic the registers. UNUSED_0 encoded as an inline
 159  * constant. UNUSED_1 encoded as REGISTER_UNUSED */
 160
 161 #define SSA_UNUSED_0 0
 162 #define SSA_UNUSED_1 -2
 163
 164 #define SSA_FIXED_SHIFT 24
 165 #define SSA_FIXED_REGISTER(reg) ((1 + reg) << SSA_FIXED_SHIFT)
 166 #define SSA_REG_FROM_FIXED(reg) ((reg >> SSA_FIXED_SHIFT) - 1)
 167 #define SSA_FIXED_MINIMUM SSA_FIXED_REGISTER(0)
 168
 169 /* Swizzle support */
 170
 171 #define SWIZZLE(A, B, C, D) ((D << 6) | (C << 4) | (B << 2) | (A << 0))
 172 #define SWIZZLE_FROM_ARRAY(r) SWIZZLE(r[0], r[1], r[2], r[3])
 173 #define COMPONENT_X 0x0
 174 #define COMPONENT_Y 0x1
 175 #define COMPONENT_Z 0x2
 176 #define COMPONENT_W 0x3
 177
 178 #define SWIZZLE_XXXX SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X)
 179 #define SWIZZLE_XYXX SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_X)
 180 #define SWIZZLE_XYZX SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_X)
 181 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
 182 #define SWIZZLE_XYXZ SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_Z)
 183 #define SWIZZLE_XYZZ SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_Z)
 184 #define SWIZZLE_WWWW SWIZZLE(COMPONENT_W, COMPONENT_W, COMPONENT_W, COMPONENT_W)
 185
 186 static inline unsigned
 187 swizzle_of(unsigned comp)
 188 {
 189         switch (comp) {
 190         case 1:
 191                 return SWIZZLE_XXXX;
 192         case 2:
 193                 return SWIZZLE_XYXX;
 194         case 3:
 195                 return SWIZZLE_XYZX;
 196         case 4:
 197                 return SWIZZLE_XYZW;
 198         default:
 199                 unreachable("Invalid component count");
 200         }
 201 }
 202
 203 static inline unsigned
 204 mask_of(unsigned nr_comp)
 205 {
 206         return (1 << nr_comp) - 1;
 207 }
 208
 209
 210 /* See ISA notes */
 211
 212 #define LDST_NOP (3)
 213
 214 /* There are five ALU units: VMUL, VADD, SMUL, SADD, LUT. A given opcode is
 215  * implemented on some subset of these units (or occassionally all of them).
 216  * This table encodes a bit mask of valid units for each opcode, so the
 217  * scheduler can figure where to plonk the instruction. */
 218
 219 /* Shorthands for each unit */
 220 #define UNIT_VMUL ALU_ENAB_VEC_MUL
 221 #define UNIT_SADD ALU_ENAB_SCAL_ADD
 222 #define UNIT_VADD ALU_ENAB_VEC_ADD
 223 #define UNIT_SMUL ALU_ENAB_SCAL_MUL
 224 #define UNIT_VLUT ALU_ENAB_VEC_LUT
 225
 226 /* Shorthands for usual combinations of units */
 227
 228 #define UNITS_MUL (UNIT_VMUL | UNIT_SMUL)
 229 #define UNITS_ADD (UNIT_VADD | UNIT_SADD)
 230 #define UNITS_MOST (UNITS_MUL | UNITS_ADD)
 231 #define UNITS_ALL (UNITS_MOST | UNIT_VLUT)
 232 #define UNITS_SCALAR (UNIT_SADD | UNIT_SMUL)
 233 #define UNITS_VECTOR (UNIT_VMUL | UNIT_VADD)
 234 #define UNITS_ANY_VECTOR (UNITS_VECTOR | UNIT_VLUT)
 235
 236 struct mir_op_props {
 237         const char *name;
 238         unsigned props;
 239 };
 240
 241 /* This file is common, so don't define the tables themselves. #include
 242  * midgard_op.h if you need that, or edit midgard_ops.c directly */
 243
 244 /* Duplicate bits to convert a 4-bit writemask to duplicated 8-bit format,
 245  * which is used for 32-bit vector units */
 246
 247 static inline unsigned
 248 expand_writemask_32(unsigned mask)
 249 {
 250         unsigned o = 0;
 251
 252         for (int i = 0; i < 4; ++i)
 253                 if (mask & (1 << i))
 254                         o |= (3 << (2 * i));
 255
 256         return o;
 257 }
 258
 259 /* Coerce structs to integer */
 260
 261 static inline unsigned
 262 vector_alu_srco_unsigned(midgard_vector_alu_src src)
 263 {
 264         unsigned u;
 265         memcpy(&u, &src, sizeof(src));
 266         return u;
 267 }
 268
 269 static inline midgard_vector_alu_src
 270 vector_alu_from_unsigned(unsigned u)
 271 {
 272         midgard_vector_alu_src s;
 273         memcpy(&s, &u, sizeof(s));
 274         return s;
 275 }
 276
 277 /* Composes two swizzles */
 278 static inline unsigned
 279 pan_compose_swizzle(unsigned left, unsigned right)
 280 {
 281         unsigned out = 0;
 282
 283         for (unsigned c = 0; c < 4; ++c) {
 284                 unsigned s = (left >> (2*c)) & 0x3;
 285                 unsigned q = (right >> (2*s)) & 0x3;
 286
 287                 out |= (q << (2*c));
 288         }
 289
 290         return out;
 291 }
 292
 293 /* Applies a swizzle to an ALU source */
 294
 295 static inline unsigned
 296 vector_alu_apply_swizzle(unsigned src, unsigned swizzle)
 297 {
 298         midgard_vector_alu_src s =
 299                 vector_alu_from_unsigned(src);
 300
 301         s.swizzle = pan_compose_swizzle(s.swizzle, swizzle);
 302
 303         return vector_alu_srco_unsigned(s);
 304 }
 305
 306 /* Checks for an xyzw.. swizzle, given a mask */
 307
 308 static inline bool
 309 mir_is_simple_swizzle(unsigned swizzle, unsigned mask)
 310 {
 311         for (unsigned i = 0; i < 16; ++i) {
 312                 if (!(mask & (1 << i))) continue;
 313
 314                 if (((swizzle >> (2 * i)) & 0x3) != i)
 315                         return false;
 316         }
 317
 318         return true;
 319 }
 320
 321 #endif