src/panfrost/midgard/helpers.h

   1 /* Copyright (c) 2018-2019 Alyssa Rosenzweig (alyssa@rosenzweig.io)
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a copy
   4  * of this software and associated documentation files (the "Software"), to deal
   5  * in the Software without restriction, including without limitation the rights
   6  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   7  * copies of the Software, and to permit persons to whom the Software is
   8  * furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice shall be included in
  11  * all copies or substantial portions of the Software.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  16  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  18  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  19  * THE SOFTWARE.
  20  */
  21
  22 #ifndef __MDG_HELPERS_H
  23 #define __MDG_HELPERS_H
  24
  25 #include "util/macros.h"
  26 #include <string.h>
  27
  28 #define OP_IS_LOAD_VARY_F(op) (\
  29                 op == midgard_op_ld_vary_16 || \
  30                 op == midgard_op_ld_vary_32 \
  31         )
  32
  33 #define OP_IS_STORE_VARY(op) (\
  34                 op == midgard_op_st_vary_16 || \
  35                 op == midgard_op_st_vary_32 || \
  36                 op == midgard_op_st_vary_32u || \
  37                 op == midgard_op_st_vary_32i \
  38         )
  39
  40 #define OP_IS_STORE_R26(op) (\
  41                 OP_IS_STORE_VARY(op) || \
  42                 op == midgard_op_st_char || \
  43                 op == midgard_op_st_char2 || \
  44                 op == midgard_op_st_char4 || \
  45                 op == midgard_op_st_short4 || \
  46                 op == midgard_op_st_int4 \
  47         )
  48
  49 #define OP_IS_STORE(op) (\
  50                 OP_IS_STORE_VARY(op) || \
  51                 op == midgard_op_st_cubemap_coords \
  52         )
  53
  54 #define OP_IS_PROJECTION(op) ( \
  55                 op == midgard_op_ldst_perspective_division_z || \
  56                 op == midgard_op_ldst_perspective_division_w \
  57         )
  58
  59 #define OP_IS_R27_ONLY(op) ( \
  60                 OP_IS_PROJECTION(op) || \
  61                 op == midgard_op_st_cubemap_coords \
  62         )
  63
  64 #define OP_IS_MOVE(op) ( \
  65                 op == midgard_alu_op_fmov || \
  66                 op == midgard_alu_op_imov \
  67         )
  68
  69 #define OP_IS_UBO_READ(op) ( \
  70                 op == midgard_op_ld_uniform_32  || \
  71                 op == midgard_op_ld_uniform_16  || \
  72                 op == midgard_op_ld_uniform_32i \
  73         )
  74
  75 #define OP_IS_CSEL(op) ( \
  76                 op == midgard_alu_op_icsel || \
  77                 op == midgard_alu_op_icsel_v || \
  78                 op == midgard_alu_op_fcsel_v || \
  79                 op == midgard_alu_op_fcsel \
  80         )
  81
  82 /* ALU control words are single bit fields with a lot of space */
  83
  84 #define ALU_ENAB_VEC_MUL  (1 << 17)
  85 #define ALU_ENAB_SCAL_ADD  (1 << 19)
  86 #define ALU_ENAB_VEC_ADD  (1 << 21)
  87 #define ALU_ENAB_SCAL_MUL  (1 << 23)
  88 #define ALU_ENAB_VEC_LUT  (1 << 25)
  89 #define ALU_ENAB_BR_COMPACT (1 << 26)
  90 #define ALU_ENAB_BRANCH   (1 << 27)
  91
  92 /* Other opcode properties that don't conflict with the ALU_ENABs, non-ISA */
  93
  94 /* Denotes an opcode that takes a vector input with a fixed-number of
  95  * channels, but outputs to only a single output channel, like dot products.
  96  * For these, to determine the effective mask, this quirk can be set. We have
  97  * an intentional off-by-one (a la MALI_POSITIVE), since 0-channel makes no
  98  * sense but we need to fit 4 channels in 2-bits. Similarly, 1-channel doesn't
  99  * make sense (since then why are we quirked?), so that corresponds to "no
 100  * count set" */
 101
 102 #define OP_CHANNEL_COUNT(c) ((c - 1) << 0)
 103 #define GET_CHANNEL_COUNT(c) ((c & (0x3 << 0)) ? ((c & (0x3 << 0)) + 1) : 0)
 104
 105 /* For instructions that take a single argument, normally the first argument
 106  * slot is used for the argument and the second slot is a dummy #0 constant.
 107  * However, there are exceptions: instructions like fmov store their argument
 108  * in the _second_ slot and store a dummy r24 in the first slot, designated by
 109  * QUIRK_FLIPPED_R24 */
 110
 111 #define QUIRK_FLIPPED_R24 (1 << 2)
 112
 113 /* Is the op commutative? */
 114 #define OP_COMMUTES (1 << 3)
 115
 116 /* Does the op convert types between int- and float- space (i2f/f2u/etc) */
 117 #define OP_TYPE_CONVERT (1 << 4)
 118
 119 /* Vector-independant shorthands for the above; these numbers are arbitrary and
 120  * not from the ISA. Convert to the above with unit_enum_to_midgard */
 121
 122 #define UNIT_MUL 0
 123 #define UNIT_ADD 1
 124 #define UNIT_LUT 2
 125
 126 /* 4-bit type tags */
 127
 128 #define TAG_TEXTURE_4_VTX 0x2
 129 #define TAG_TEXTURE_4 0x3
 130 #define TAG_LOAD_STORE_4 0x5
 131 #define TAG_ALU_4 0x8
 132 #define TAG_ALU_8 0x9
 133 #define TAG_ALU_12 0xA
 134 #define TAG_ALU_16 0xB
 135
 136 static inline int
 137 quadword_size(int tag)
 138 {
 139         switch (tag) {
 140         case TAG_ALU_4:
 141         case TAG_LOAD_STORE_4:
 142         case TAG_TEXTURE_4:
 143         case TAG_TEXTURE_4_VTX:
 144                 return 1;
 145         case TAG_ALU_8:
 146                 return 2;
 147         case TAG_ALU_12:
 148                 return 3;
 149         case TAG_ALU_16:
 150                 return 4;
 151         default:
 152                 unreachable("Unknown tag");
 153         }
 154 }
 155
 156 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 ||  \
 157                      tag == TAG_ALU_12 || tag == TAG_ALU_16)
 158
 159 /* Special register aliases */
 160
 161 #define MAX_WORK_REGISTERS 16
 162
 163 /* Uniforms are begin at (REGISTER_UNIFORMS - uniform_count) */
 164 #define REGISTER_UNIFORMS 24
 165
 166 #define REGISTER_UNUSED 24
 167 #define REGISTER_CONSTANT 26
 168 #define REGISTER_VARYING_BASE 26
 169 #define REGISTER_OFFSET 27
 170 #define REGISTER_TEXTURE_BASE 28
 171 #define REGISTER_SELECT 31
 172
 173 /* SSA helper aliases to mimic the registers. UNUSED_0 encoded as an inline
 174  * constant. UNUSED_1 encoded as REGISTER_UNUSED */
 175
 176 #define SSA_UNUSED_0 0
 177 #define SSA_UNUSED_1 -2
 178
 179 #define SSA_FIXED_SHIFT 24
 180 #define SSA_FIXED_REGISTER(reg) ((1 + reg) << SSA_FIXED_SHIFT)
 181 #define SSA_REG_FROM_FIXED(reg) ((reg >> SSA_FIXED_SHIFT) - 1)
 182 #define SSA_FIXED_MINIMUM SSA_FIXED_REGISTER(0)
 183
 184 /* Swizzle support */
 185
 186 #define SWIZZLE(A, B, C, D) ((D << 6) | (C << 4) | (B << 2) | (A << 0))
 187 #define SWIZZLE_FROM_ARRAY(r) SWIZZLE(r[0], r[1], r[2], r[3])
 188 #define COMPONENT_X 0x0
 189 #define COMPONENT_Y 0x1
 190 #define COMPONENT_Z 0x2
 191 #define COMPONENT_W 0x3
 192
 193 #define SWIZZLE_XXXX SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X)
 194 #define SWIZZLE_XYXX SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_X)
 195 #define SWIZZLE_XYZX SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_X)
 196 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
 197 #define SWIZZLE_XYXZ SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_Z)
 198 #define SWIZZLE_XYZZ SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_Z)
 199 #define SWIZZLE_WWWW SWIZZLE(COMPONENT_W, COMPONENT_W, COMPONENT_W, COMPONENT_W)
 200
 201 static inline unsigned
 202 swizzle_of(unsigned comp)
 203 {
 204         switch (comp) {
 205         case 1:
 206                 return SWIZZLE_XXXX;
 207         case 2:
 208                 return SWIZZLE_XYXX;
 209         case 3:
 210                 return SWIZZLE_XYZX;
 211         case 4:
 212                 return SWIZZLE_XYZW;
 213         default:
 214                 unreachable("Invalid component count");
 215         }
 216 }
 217
 218 static inline unsigned
 219 mask_of(unsigned nr_comp)
 220 {
 221         return (1 << nr_comp) - 1;
 222 }
 223
 224
 225 /* See ISA notes */
 226
 227 #define LDST_NOP (3)
 228
 229 /* There are five ALU units: VMUL, VADD, SMUL, SADD, LUT. A given opcode is
 230  * implemented on some subset of these units (or occassionally all of them).
 231  * This table encodes a bit mask of valid units for each opcode, so the
 232  * scheduler can figure where to plonk the instruction. */
 233
 234 /* Shorthands for each unit */
 235 #define UNIT_VMUL ALU_ENAB_VEC_MUL
 236 #define UNIT_SADD ALU_ENAB_SCAL_ADD
 237 #define UNIT_VADD ALU_ENAB_VEC_ADD
 238 #define UNIT_SMUL ALU_ENAB_SCAL_MUL
 239 #define UNIT_VLUT ALU_ENAB_VEC_LUT
 240
 241 /* Shorthands for usual combinations of units */
 242
 243 #define UNITS_MUL (UNIT_VMUL | UNIT_SMUL)
 244 #define UNITS_ADD (UNIT_VADD | UNIT_SADD)
 245 #define UNITS_MOST (UNITS_MUL | UNITS_ADD)
 246 #define UNITS_ALL (UNITS_MOST | UNIT_VLUT)
 247 #define UNITS_SCALAR (UNIT_SADD | UNIT_SMUL)
 248 #define UNITS_VECTOR (UNIT_VMUL | UNIT_VADD)
 249 #define UNITS_ANY_VECTOR (UNITS_VECTOR | UNIT_VLUT)
 250
 251 struct mir_op_props {
 252         const char *name;
 253         unsigned props;
 254 };
 255
 256 /* This file is common, so don't define the tables themselves. #include
 257  * midgard_op.h if you need that, or edit midgard_ops.c directly */
 258
 259 /* Duplicate bits to convert a 4-bit writemask to duplicated 8-bit format,
 260  * which is used for 32-bit vector units */
 261
 262 static inline unsigned
 263 expand_writemask_32(unsigned mask)
 264 {
 265         unsigned o = 0;
 266
 267         for (int i = 0; i < 4; ++i)
 268                 if (mask & (1 << i))
 269                         o |= (3 << (2 * i));
 270
 271         return o;
 272 }
 273
 274 /* Coerce structs to integer */
 275
 276 static inline unsigned
 277 vector_alu_srco_unsigned(midgard_vector_alu_src src)
 278 {
 279         unsigned u;
 280         memcpy(&u, &src, sizeof(src));
 281         return u;
 282 }
 283
 284 static inline midgard_vector_alu_src
 285 vector_alu_from_unsigned(unsigned u)
 286 {
 287         midgard_vector_alu_src s;
 288         memcpy(&s, &u, sizeof(s));
 289         return s;
 290 }
 291
 292 /* Composes two swizzles */
 293 static inline unsigned
 294 pan_compose_swizzle(unsigned left, unsigned right)
 295 {
 296         unsigned out = 0;
 297
 298         for (unsigned c = 0; c < 4; ++c) {
 299                 unsigned s = (left >> (2*c)) & 0x3;
 300                 unsigned q = (right >> (2*s)) & 0x3;
 301
 302                 out |= (q << (2*c));
 303         }
 304
 305         return out;
 306 }
 307
 308 /* Applies a swizzle to an ALU source */
 309
 310 static inline unsigned
 311 vector_alu_apply_swizzle(unsigned src, unsigned swizzle)
 312 {
 313         midgard_vector_alu_src s =
 314                 vector_alu_from_unsigned(src);
 315
 316         s.swizzle = pan_compose_swizzle(s.swizzle, swizzle);
 317
 318         return vector_alu_srco_unsigned(s);
 319 }
 320
 321 /* Checks for an xyzw.. swizzle, given a mask */
 322
 323 static inline bool
 324 mir_is_simple_swizzle(unsigned swizzle, unsigned mask)
 325 {
 326         for (unsigned i = 0; i < 16; ++i) {
 327                 if (!(mask & (1 << i))) continue;
 328
 329                 if (((swizzle >> (2 * i)) & 0x3) != i)
 330                         return false;
 331         }
 332
 333         return true;
 334 }
 335
 336 #endif