src/panfrost/midgard/helpers.h

   1 /* Copyright (c) 2018-2019 Alyssa Rosenzweig (alyssa@rosenzweig.io)
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a copy
   4  * of this software and associated documentation files (the "Software"), to deal
   5  * in the Software without restriction, including without limitation the rights
   6  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   7  * copies of the Software, and to permit persons to whom the Software is
   8  * furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice shall be included in
  11  * all copies or substantial portions of the Software.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  16  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  18  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  19  * THE SOFTWARE.
  20  */
  21
  22 #ifndef __MDG_HELPERS_H
  23 #define __MDG_HELPERS_H
  24
  25 #include "util/macros.h"
  26 #include <string.h>
  27
  28 #define OP_IS_LOAD_VARY_F(op) (\
  29                 op == midgard_op_ld_vary_16 || \
  30                 op == midgard_op_ld_vary_32 \
  31         )
  32
  33 #define OP_IS_STORE_VARY(op) (\
  34                 op == midgard_op_st_vary_16 || \
  35                 op == midgard_op_st_vary_32 || \
  36                 op == midgard_op_st_vary_32u || \
  37                 op == midgard_op_st_vary_32i \
  38         )
  39
  40 #define OP_IS_PROJECTION(op) ( \
  41                 op == midgard_op_ldst_perspective_division_z || \
  42                 op == midgard_op_ldst_perspective_division_w \
  43         )
  44
  45 #define OP_IS_VEC4_ONLY(op) ( \
  46                 OP_IS_PROJECTION(op) || \
  47                 op == midgard_op_ld_cubemap_coords \
  48         )
  49
  50 #define OP_IS_MOVE(op) ( \
  51                 op == midgard_alu_op_fmov || \
  52                 op == midgard_alu_op_imov \
  53         )
  54
  55 #define OP_IS_UBO_READ(op) ( \
  56                 op == midgard_op_ld_ubo_char  || \
  57                 op == midgard_op_ld_ubo_char2  || \
  58                 op == midgard_op_ld_ubo_char4  || \
  59                 op == midgard_op_ld_ubo_short4  || \
  60                 op == midgard_op_ld_ubo_int4 \
  61         )
  62
  63 #define OP_IS_CSEL_V(op) ( \
  64                 op == midgard_alu_op_icsel_v || \
  65                 op == midgard_alu_op_fcsel_v \
  66         )
  67
  68 #define OP_IS_CSEL(op) ( \
  69                 OP_IS_CSEL_V(op) || \
  70                 op == midgard_alu_op_icsel || \
  71                 op == midgard_alu_op_fcsel \
  72         )
  73
  74 #define OP_IS_DERIVATIVE(op) ( \
  75                 op == TEXTURE_OP_DFDX || \
  76                 op == TEXTURE_OP_DFDY \
  77         )
  78
  79 /* ALU control words are single bit fields with a lot of space */
  80
  81 #define ALU_ENAB_VEC_MUL  (1 << 17)
  82 #define ALU_ENAB_SCAL_ADD  (1 << 19)
  83 #define ALU_ENAB_VEC_ADD  (1 << 21)
  84 #define ALU_ENAB_SCAL_MUL  (1 << 23)
  85 #define ALU_ENAB_VEC_LUT  (1 << 25)
  86 #define ALU_ENAB_BR_COMPACT (1 << 26)
  87 #define ALU_ENAB_BRANCH   (1 << 27)
  88
  89 /* Other opcode properties that don't conflict with the ALU_ENABs, non-ISA */
  90
  91 /* Denotes an opcode that takes a vector input with a fixed-number of
  92  * channels, but outputs to only a single output channel, like dot products.
  93  * For these, to determine the effective mask, this quirk can be set. We have
  94  * an intentional off-by-one (a la MALI_POSITIVE), since 0-channel makes no
  95  * sense but we need to fit 4 channels in 2-bits. Similarly, 1-channel doesn't
  96  * make sense (since then why are we quirked?), so that corresponds to "no
  97  * count set" */
  98
  99 #define OP_CHANNEL_COUNT(c) ((c - 1) << 0)
 100 #define GET_CHANNEL_COUNT(c) ((c & (0x3 << 0)) ? ((c & (0x3 << 0)) + 1) : 0)
 101
 102 /* For instructions that take a single argument, normally the first argument
 103  * slot is used for the argument and the second slot is a dummy #0 constant.
 104  * However, there are exceptions: instructions like fmov store their argument
 105  * in the _second_ slot and store a dummy r24 in the first slot, designated by
 106  * QUIRK_FLIPPED_R24 */
 107
 108 #define QUIRK_FLIPPED_R24 (1 << 2)
 109
 110 /* Is the op commutative? */
 111 #define OP_COMMUTES (1 << 3)
 112
 113 /* Does the op convert types between int- and float- space (i2f/f2u/etc) */
 114 #define OP_TYPE_CONVERT (1 << 4)
 115
 116 /* Vector-independant shorthands for the above; these numbers are arbitrary and
 117  * not from the ISA. Convert to the above with unit_enum_to_midgard */
 118
 119 #define UNIT_MUL 0
 120 #define UNIT_ADD 1
 121 #define UNIT_LUT 2
 122
 123 /* 4-bit type tags */
 124
 125 #define TAG_TEXTURE_4_VTX 0x2
 126 #define TAG_TEXTURE_4 0x3
 127 #define TAG_LOAD_STORE_4 0x5
 128 #define TAG_ALU_4 0x8
 129 #define TAG_ALU_8 0x9
 130 #define TAG_ALU_12 0xA
 131 #define TAG_ALU_16 0xB
 132
 133 static inline int
 134 quadword_size(int tag)
 135 {
 136         switch (tag) {
 137         case TAG_ALU_4:
 138         case TAG_LOAD_STORE_4:
 139         case TAG_TEXTURE_4:
 140         case TAG_TEXTURE_4_VTX:
 141                 return 1;
 142         case TAG_ALU_8:
 143                 return 2;
 144         case TAG_ALU_12:
 145                 return 3;
 146         case TAG_ALU_16:
 147                 return 4;
 148         default:
 149                 unreachable("Unknown tag");
 150         }
 151 }
 152
 153 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 ||  \
 154                      tag == TAG_ALU_12 || tag == TAG_ALU_16)
 155
 156 /* Special register aliases */
 157
 158 #define MAX_WORK_REGISTERS 16
 159
 160 /* Uniforms are begin at (REGISTER_UNIFORMS - uniform_count) */
 161 #define REGISTER_UNIFORMS 24
 162
 163 #define REGISTER_UNUSED 24
 164 #define REGISTER_CONSTANT 26
 165 #define REGISTER_LDST_BASE 26
 166 #define REGISTER_TEXTURE_BASE 28
 167 #define REGISTER_SELECT 31
 168
 169 /* SSA helper aliases to mimic the registers. */
 170
 171 #define SSA_UNUSED ~0
 172 #define SSA_FIXED_SHIFT 24
 173 #define SSA_FIXED_REGISTER(reg) (((1 + (reg)) << SSA_FIXED_SHIFT) | 1)
 174 #define SSA_REG_FROM_FIXED(reg) ((((reg) & ~1) >> SSA_FIXED_SHIFT) - 1)
 175 #define SSA_FIXED_MINIMUM SSA_FIXED_REGISTER(0)
 176
 177 /* Swizzle support */
 178
 179 #define SWIZZLE(A, B, C, D) (((D) << 6) | ((C) << 4) | ((B) << 2) | ((A) << 0))
 180 #define SWIZZLE_FROM_ARRAY(r) SWIZZLE(r[0], r[1], r[2], r[3])
 181 #define COMPONENT_X 0x0
 182 #define COMPONENT_Y 0x1
 183 #define COMPONENT_Z 0x2
 184 #define COMPONENT_W 0x3
 185
 186 #define SWIZZLE_XXXX SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X)
 187 #define SWIZZLE_XYXX SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_X)
 188 #define SWIZZLE_XYZX SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_X)
 189 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
 190 #define SWIZZLE_XYXZ SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_Z)
 191 #define SWIZZLE_XYZZ SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_Z)
 192 #define SWIZZLE_XXXY SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_Y)
 193 #define SWIZZLE_ZZZW SWIZZLE(COMPONENT_Z, COMPONENT_Z, COMPONENT_Z, COMPONENT_W)
 194 #define SWIZZLE_ZWWW SWIZZLE(COMPONENT_Z, COMPONENT_W, COMPONENT_W, COMPONENT_W)
 195 #define SWIZZLE_WWWW SWIZZLE(COMPONENT_W, COMPONENT_W, COMPONENT_W, COMPONENT_W)
 196
 197 static inline unsigned
 198 swizzle_of(unsigned comp)
 199 {
 200         switch (comp) {
 201         case 1:
 202                 return SWIZZLE_XXXX;
 203         case 2:
 204                 return SWIZZLE_XYXX;
 205         case 3:
 206                 return SWIZZLE_XYZX;
 207         case 4:
 208                 return SWIZZLE_XYZW;
 209         default:
 210                 unreachable("Invalid component count");
 211         }
 212 }
 213
 214 static inline unsigned
 215 mask_of(unsigned nr_comp)
 216 {
 217         return (1 << nr_comp) - 1;
 218 }
 219
 220
 221 /* See ISA notes */
 222
 223 #define LDST_NOP (3)
 224
 225 /* There are five ALU units: VMUL, VADD, SMUL, SADD, LUT. A given opcode is
 226  * implemented on some subset of these units (or occassionally all of them).
 227  * This table encodes a bit mask of valid units for each opcode, so the
 228  * scheduler can figure where to plonk the instruction. */
 229
 230 /* Shorthands for each unit */
 231 #define UNIT_VMUL ALU_ENAB_VEC_MUL
 232 #define UNIT_SADD ALU_ENAB_SCAL_ADD
 233 #define UNIT_VADD ALU_ENAB_VEC_ADD
 234 #define UNIT_SMUL ALU_ENAB_SCAL_MUL
 235 #define UNIT_VLUT ALU_ENAB_VEC_LUT
 236
 237 /* Shorthands for usual combinations of units */
 238
 239 #define UNITS_MUL (UNIT_VMUL | UNIT_SMUL)
 240 #define UNITS_ADD (UNIT_VADD | UNIT_SADD)
 241 #define UNITS_MOST (UNITS_MUL | UNITS_ADD)
 242 #define UNITS_ALL (UNITS_MOST | UNIT_VLUT)
 243 #define UNITS_SCALAR (UNIT_SADD | UNIT_SMUL)
 244 #define UNITS_VECTOR (UNIT_VMUL | UNIT_VADD)
 245 #define UNITS_ANY_VECTOR (UNITS_VECTOR | UNIT_VLUT)
 246
 247 struct mir_op_props {
 248         const char *name;
 249         unsigned props;
 250 };
 251
 252 /* For load/store */
 253
 254 struct mir_ldst_op_props {
 255         const char *name;
 256         unsigned props;
 257 };
 258
 259 /* Lower 2-bits are a midgard_reg_mode */
 260 #define GET_LDST_SIZE(c) (c & 3)
 261
 262 /* Store (so the primary register is a source, not a destination */
 263 #define LDST_STORE (1 << 2)
 264
 265 /* Mask has special meaning and should not be manipulated directly */
 266 #define LDST_SPECIAL_MASK (1 << 3)
 267
 268 /* Non-store operation has side effects and should not be eliminated even if
 269  * its mask is 0 */
 270 #define LDST_SIDE_FX (1 << 4)
 271
 272 /* This file is common, so don't define the tables themselves. #include
 273  * midgard_op.h if you need that, or edit midgard_ops.c directly */
 274
 275 /* Duplicate bits to convert a 4-bit writemask to duplicated 8-bit format,
 276  * which is used for 32-bit vector units */
 277
 278 static inline unsigned
 279 expand_writemask_32(unsigned mask)
 280 {
 281         unsigned o = 0;
 282
 283         for (int i = 0; i < 4; ++i)
 284                 if (mask & (1 << i))
 285                         o |= (3 << (2 * i));
 286
 287         return o;
 288 }
 289
 290 /* Coerce structs to integer */
 291
 292 static inline unsigned
 293 vector_alu_srco_unsigned(midgard_vector_alu_src src)
 294 {
 295         unsigned u;
 296         memcpy(&u, &src, sizeof(src));
 297         return u;
 298 }
 299
 300 static inline midgard_vector_alu_src
 301 vector_alu_from_unsigned(unsigned u)
 302 {
 303         midgard_vector_alu_src s;
 304         memcpy(&s, &u, sizeof(s));
 305         return s;
 306 }
 307
 308 /* Composes two swizzles */
 309 static inline unsigned
 310 pan_compose_swizzle(unsigned left, unsigned right)
 311 {
 312         unsigned out = 0;
 313
 314         for (unsigned c = 0; c < 4; ++c) {
 315                 unsigned s = (left >> (2*c)) & 0x3;
 316                 unsigned q = (right >> (2*s)) & 0x3;
 317
 318                 out |= (q << (2*c));
 319         }
 320
 321         return out;
 322 }
 323
 324 /* Applies a swizzle to an ALU source */
 325
 326 static inline unsigned
 327 vector_alu_apply_swizzle(unsigned src, unsigned swizzle)
 328 {
 329         midgard_vector_alu_src s =
 330                 vector_alu_from_unsigned(src);
 331
 332         s.swizzle = pan_compose_swizzle(s.swizzle, swizzle);
 333
 334         return vector_alu_srco_unsigned(s);
 335 }
 336
 337 /* Checks for an xyzw.. swizzle, given a mask */
 338
 339 static inline bool
 340 mir_is_simple_swizzle(unsigned swizzle, unsigned mask)
 341 {
 342         for (unsigned i = 0; i < 16; ++i) {
 343                 if (!(mask & (1 << i))) continue;
 344
 345                 if (((swizzle >> (2 * i)) & 0x3) != i)
 346                         return false;
 347         }
 348
 349         return true;
 350 }
 351
 352 /* Packs a load/store argument */
 353
 354 static inline uint8_t
 355 midgard_ldst_reg(unsigned reg, unsigned component)
 356 {
 357         assert((reg == REGISTER_LDST_BASE) || (reg == REGISTER_LDST_BASE + 1));
 358
 359         midgard_ldst_register_select sel = {
 360                 .component = component,
 361                 .select = reg - 26
 362         };
 363
 364         uint8_t packed;
 365         memcpy(&packed, &sel, sizeof(packed));
 366
 367         return packed;
 368 }
 369
 370 /* Unpacks a load/store argument */
 371
 372 static inline midgard_ldst_register_select
 373 midgard_ldst_select(uint8_t u)
 374 {
 375         midgard_ldst_register_select sel;
 376         memcpy(&sel, &u, sizeof(u));
 377         return sel;
 378 }
 379
 380 static inline uint8_t
 381 midgard_ldst_pack(midgard_ldst_register_select sel)
 382 {
 383         uint8_t packed;
 384         memcpy(&packed, &sel, sizeof(packed));
 385         return packed;
 386 }
 387
 388 /* Gets a swizzle like yyyy and returns y */
 389
 390 static inline unsigned
 391 swizzle_to_component(unsigned swizzle)
 392 {
 393         unsigned c = swizzle & 3;
 394         assert(((swizzle >> 2) & 3) == c);
 395         assert(((swizzle >> 4) & 3) == c);
 396         assert(((swizzle >> 6) & 3) == c);
 397         return  c;
 398 }
 399
 400
 401 static inline unsigned
 402 component_to_swizzle(unsigned c, unsigned count)
 403 {
 404         switch (count) {
 405         case 1:
 406                 return SWIZZLE(c, c, c, c);
 407         case 2:
 408                 return SWIZZLE(c, c + 1, c + 1, c + 1);
 409         case 3:
 410                 return SWIZZLE(c, c + 1, c + 2, c + 2);
 411         case 4:
 412                 return SWIZZLE(c, c + 1, c + 2, c + 3);
 413         default:
 414                 unreachable("Invalid component count");
 415         }
 416 }
 417
 418 #endif