1 /* Copyright (c) 2018-2019 Alyssa Rosenzweig (alyssa@rosenzweig.io)
3 * Permission is hereby granted, free of charge, to any person obtaining a copy
4 * of this software and associated documentation files (the "Software"), to deal
5 * in the Software without restriction, including without limitation the rights
6 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
7 * copies of the Software, and to permit persons to whom the Software is
8 * furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice shall be included in
11 * all copies or substantial portions of the Software.
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
16 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
18 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 #ifndef __MDG_HELPERS_H
23 #define __MDG_HELPERS_H
25 #include "util/macros.h"
29 #define OP_IS_LOAD_VARY_F(op) (\
30 op == midgard_op_ld_vary_16 || \
31 op == midgard_op_ld_vary_32 \
34 #define OP_IS_PROJECTION(op) ( \
35 op == midgard_op_ldst_perspective_division_z || \
36 op == midgard_op_ldst_perspective_division_w \
39 #define OP_IS_VEC4_ONLY(op) ( \
40 OP_IS_PROJECTION(op) || \
41 op == midgard_op_ld_cubemap_coords \
44 #define OP_IS_MOVE(op) ( \
45 op == midgard_alu_op_fmov || \
46 op == midgard_alu_op_imov \
49 #define OP_IS_UBO_READ(op) ( \
50 op == midgard_op_ld_ubo_char || \
51 op == midgard_op_ld_ubo_char2 || \
52 op == midgard_op_ld_ubo_char4 || \
53 op == midgard_op_ld_ubo_short4 || \
54 op == midgard_op_ld_ubo_int4 \
57 #define OP_IS_CSEL_V(op) ( \
58 op == midgard_alu_op_icsel_v || \
59 op == midgard_alu_op_fcsel_v \
62 #define OP_IS_CSEL(op) ( \
64 op == midgard_alu_op_icsel || \
65 op == midgard_alu_op_fcsel \
68 #define OP_IS_UNSIGNED_CMP(op) ( \
69 op == midgard_alu_op_ult || \
70 op == midgard_alu_op_ule \
73 #define OP_IS_INTEGER_CMP(op) ( \
74 op == midgard_alu_op_ieq || \
75 op == midgard_alu_op_ine || \
76 op == midgard_alu_op_ilt || \
77 op == midgard_alu_op_ile || \
78 OP_IS_UNSIGNED_CMP(op) \
81 /* ALU control words are single bit fields with a lot of space */
83 #define ALU_ENAB_VEC_MUL (1 << 17)
84 #define ALU_ENAB_SCAL_ADD (1 << 19)
85 #define ALU_ENAB_VEC_ADD (1 << 21)
86 #define ALU_ENAB_SCAL_MUL (1 << 23)
87 #define ALU_ENAB_VEC_LUT (1 << 25)
88 #define ALU_ENAB_BR_COMPACT (1 << 26)
89 #define ALU_ENAB_BRANCH (1 << 27)
91 /* Other opcode properties that don't conflict with the ALU_ENABs, non-ISA */
93 /* Denotes an opcode that takes a vector input with a fixed-number of
94 * channels, but outputs to only a single output channel, like dot products.
95 * For these, to determine the effective mask, this quirk can be set. We have
96 * an intentional off-by-one (a la MALI_POSITIVE), since 0-channel makes no
97 * sense but we need to fit 4 channels in 2-bits. Similarly, 1-channel doesn't
98 * make sense (since then why are we quirked?), so that corresponds to "no
101 #define OP_CHANNEL_COUNT(c) ((c - 1) << 0)
102 #define GET_CHANNEL_COUNT(c) ((c & (0x3 << 0)) ? ((c & (0x3 << 0)) + 1) : 0)
104 /* For instructions that take a single argument, normally the first argument
105 * slot is used for the argument and the second slot is a dummy #0 constant.
106 * However, there are exceptions: instructions like fmov store their argument
107 * in the _second_ slot and store a dummy r24 in the first slot, designated by
108 * QUIRK_FLIPPED_R24 */
110 #define QUIRK_FLIPPED_R24 (1 << 2)
112 /* Is the op commutative? */
113 #define OP_COMMUTES (1 << 3)
115 /* Does the op convert types between int- and float- space (i2f/f2u/etc) */
116 #define OP_TYPE_CONVERT (1 << 4)
118 /* Is this opcode the first in a f2x (rte, rtz, rtn, rtp) sequence? If so,
119 * takes a roundmode argument in the IR. This has the semantic of rounding the
120 * source (it's all fused in), which is why it doesn't necessarily make sense
121 * for i2f (though folding there might be necessary for OpenCL reasons). Comes
122 * up in format conversion, i.e. f2u_rte */
123 #define MIDGARD_ROUNDS (1 << 5)
125 /* Vector-independant shorthands for the above; these numbers are arbitrary and
126 * not from the ISA. Convert to the above with unit_enum_to_midgard */
132 #define IS_ALU(tag) (tag >= TAG_ALU_4)
134 /* Special register aliases */
136 #define MAX_WORK_REGISTERS 16
138 /* Uniforms are begin at (REGISTER_UNIFORMS - uniform_count) */
139 #define REGISTER_UNIFORMS 24
141 /* r24 and r25 are special registers that only exist during the pipeline,
142 * by using them when we don't care about the register we skip a roundtrip
143 * to the register file. */
144 #define REGISTER_UNUSED 24
145 #define REGISTER_CONSTANT 26
146 #define REGISTER_LDST_BASE 26
147 #define REGISTER_TEXTURE_BASE 28
148 #define REGISTER_SELECT 31
150 /* SSA helper aliases to mimic the registers. */
152 #define SSA_FIXED_SHIFT 24
153 #define SSA_FIXED_REGISTER(reg) (((1 + (reg)) << SSA_FIXED_SHIFT) | 1)
154 #define SSA_REG_FROM_FIXED(reg) ((((reg) & ~1) >> SSA_FIXED_SHIFT) - 1)
155 #define SSA_FIXED_MINIMUM SSA_FIXED_REGISTER(0)
157 #define COMPONENT_X 0x0
158 #define COMPONENT_Y 0x1
159 #define COMPONENT_Z 0x2
160 #define COMPONENT_W 0x3
162 #define SWIZZLE_IDENTITY { \
163 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, \
164 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, \
165 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, \
166 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 } \
169 #define SWIZZLE_IDENTITY_4 { \
170 { 0, 1, 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
171 { 0, 1, 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
172 { 0, 1, 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
173 { 0, 1, 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
176 static inline unsigned
177 mask_of(unsigned nr_comp
)
179 return (1 << nr_comp
) - 1;
186 /* There are five ALU units: VMUL, VADD, SMUL, SADD, LUT. A given opcode is
187 * implemented on some subset of these units (or occassionally all of them).
188 * This table encodes a bit mask of valid units for each opcode, so the
189 * scheduler can figure where to plonk the instruction. */
191 /* Shorthands for each unit */
192 #define UNIT_VMUL ALU_ENAB_VEC_MUL
193 #define UNIT_SADD ALU_ENAB_SCAL_ADD
194 #define UNIT_VADD ALU_ENAB_VEC_ADD
195 #define UNIT_SMUL ALU_ENAB_SCAL_MUL
196 #define UNIT_VLUT ALU_ENAB_VEC_LUT
198 /* Shorthands for usual combinations of units */
200 #define UNITS_MUL (UNIT_VMUL | UNIT_SMUL)
201 #define UNITS_ADD (UNIT_VADD | UNIT_SADD)
202 #define UNITS_MOST (UNITS_MUL | UNITS_ADD)
203 #define UNITS_ALL (UNITS_MOST | UNIT_VLUT)
204 #define UNITS_SCALAR (UNIT_SADD | UNIT_SMUL)
205 #define UNITS_VECTOR (UNIT_VMUL | UNIT_VADD)
206 #define UNITS_ANY_VECTOR (UNITS_VECTOR | UNIT_VLUT)
208 struct mir_op_props
{
215 struct mir_ldst_op_props
{
220 struct mir_tag_props
{
225 /* Lower 2-bits are a midgard_reg_mode */
226 #define GET_LDST_SIZE(c) (c & 3)
228 /* Store (so the primary register is a source, not a destination */
229 #define LDST_STORE (1 << 2)
231 /* Mask has special meaning and should not be manipulated directly */
232 #define LDST_SPECIAL_MASK (1 << 3)
234 /* Non-store operation has side effects and should not be eliminated even if
236 #define LDST_SIDE_FX (1 << 4)
238 /* Computes an address according to indirects/zext/shift/etc */
239 #define LDST_ADDRESS (1 << 5)
241 /* This file is common, so don't define the tables themselves. #include
242 * midgard_op.h if you need that, or edit midgard_ops.c directly */
244 /* Duplicate bits to convert a per-component to duplicated 8-bit format,
245 * which is used for vector units */
247 static inline unsigned
248 expand_writemask(unsigned mask
, unsigned log2_channels
)
251 unsigned factor
= 8 >> log2_channels
;
252 unsigned expanded
= (1 << factor
) - 1;
254 for (unsigned i
= 0; i
< (1 << log2_channels
); ++i
)
256 o
|= (expanded
<< (factor
* i
));
261 /* Coerce structs to integer */
263 static inline unsigned
264 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
267 memcpy(&u
, &src
, sizeof(src
));
271 static inline midgard_vector_alu_src
272 vector_alu_from_unsigned(unsigned u
)
274 midgard_vector_alu_src s
;
275 memcpy(&s
, &u
, sizeof(s
));
280 mir_compose_swizzle(unsigned *left
, unsigned *right
, unsigned *final_out
)
284 for (unsigned c
= 0; c
< 16; ++c
)
285 out
[c
] = right
[left
[c
]];
287 memcpy(final_out
, out
, sizeof(out
));
290 /* Checks for an xyzw.. swizzle, given a mask */
293 mir_is_simple_swizzle(unsigned *swizzle
, unsigned mask
)
295 for (unsigned i
= 0; i
< 16; ++i
) {
296 if (!(mask
& (1 << i
))) continue;
305 /* Packs a load/store argument */
307 static inline uint8_t
308 midgard_ldst_reg(unsigned reg
, unsigned component
, unsigned size
)
310 assert((reg
== REGISTER_LDST_BASE
) || (reg
== REGISTER_LDST_BASE
+ 1));
311 assert(size
== 16 || size
== 32 || size
== 64);
313 /* Shift so everything is in terms of 32-bit units */
315 assert(component
< 2);
317 } else if (size
== 16) {
318 assert((component
& 1) == 0);
322 midgard_ldst_register_select sel
= {
323 .component
= component
,
328 memcpy(&packed
, &sel
, sizeof(packed
));
334 midgard_is_branch_unit(unsigned unit
)
336 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
339 /* Packs ALU mod argument */
340 struct midgard_instruction
;
341 unsigned mir_pack_mod(struct midgard_instruction
*ins
, unsigned i
, bool scalar
);
344 mir_print_constant_component(FILE *fp
, const midgard_constants
*consts
,
345 unsigned c
, midgard_reg_mode reg_mode
, bool half
,
346 unsigned mod
, midgard_alu_op op
);