src/panfrost/midgard/midgard.h

   1 /* Author(s):
   2  *   Connor Abbott
   3  *   Alyssa Rosenzweig
   4  *
   5  * Copyright (c) 2013 Connor Abbott (connor@abbott.cx)
   6  * Copyright (c) 2018 Alyssa Rosenzweig (alyssa@rosenzweig.io)
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  21  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26
  27 #ifndef __midgard_h__
  28 #define __midgard_h__
  29
  30 #include <stdint.h>
  31 #include <stdbool.h>
  32 #include "panfrost-job.h"
  33
  34 #define MIDGARD_DBG_MSGS                0x0001
  35 #define MIDGARD_DBG_SHADERS             0x0002
  36 #define MIDGARD_DBG_SHADERDB            0x0004
  37
  38 extern int midgard_debug;
  39
  40 typedef enum {
  41         midgard_word_type_alu,
  42         midgard_word_type_load_store,
  43         midgard_word_type_texture,
  44         midgard_word_type_unknown
  45 } midgard_word_type;
  46
  47 typedef enum {
  48         midgard_alu_vmul,
  49         midgard_alu_sadd,
  50         midgard_alu_smul,
  51         midgard_alu_vadd,
  52         midgard_alu_lut
  53 } midgard_alu;
  54
  55 /*
  56  * ALU words
  57  */
  58
  59 typedef enum {
  60         midgard_alu_op_fadd       = 0x10,
  61         midgard_alu_op_fmul       = 0x14,
  62
  63         midgard_alu_op_fmin       = 0x28,
  64         midgard_alu_op_fmax       = 0x2C,
  65
  66         midgard_alu_op_fmov       = 0x30, /* fmov_rte */
  67         midgard_alu_op_fmov_rtz   = 0x31,
  68         midgard_alu_op_fmov_rtn   = 0x32,
  69         midgard_alu_op_fmov_rtp   = 0x33,
  70         midgard_alu_op_froundeven = 0x34,
  71         midgard_alu_op_ftrunc     = 0x35,
  72         midgard_alu_op_ffloor     = 0x36,
  73         midgard_alu_op_fceil      = 0x37,
  74         midgard_alu_op_ffma       = 0x38,
  75         midgard_alu_op_fdot3      = 0x3C,
  76         midgard_alu_op_fdot3r     = 0x3D,
  77         midgard_alu_op_fdot4      = 0x3E,
  78         midgard_alu_op_freduce    = 0x3F,
  79
  80         midgard_alu_op_iadd       = 0x40,
  81         midgard_alu_op_ishladd    = 0x41, /* a + (b<<1) */
  82         midgard_alu_op_isub       = 0x46,
  83         midgard_alu_op_iaddsat    = 0x48,
  84         midgard_alu_op_uaddsat    = 0x49,
  85         midgard_alu_op_isubsat    = 0x4E,
  86         midgard_alu_op_usubsat    = 0x4F,
  87
  88         midgard_alu_op_imul       = 0x58,
  89
  90         midgard_alu_op_imin       = 0x60,
  91         midgard_alu_op_umin       = 0x61,
  92         midgard_alu_op_imax       = 0x62,
  93         midgard_alu_op_umax       = 0x63,
  94         midgard_alu_op_ihadd      = 0x64,
  95         midgard_alu_op_uhadd      = 0x65,
  96         midgard_alu_op_irhadd     = 0x66,
  97         midgard_alu_op_urhadd     = 0x67,
  98         midgard_alu_op_iasr       = 0x68,
  99         midgard_alu_op_ilsr       = 0x69,
 100         midgard_alu_op_ishl       = 0x6E,
 101
 102         midgard_alu_op_iand       = 0x70,
 103         midgard_alu_op_ior        = 0x71,
 104         midgard_alu_op_inand      = 0x72, /* ~(a & b), for inot let a = b */
 105         midgard_alu_op_inor       = 0x73, /* ~(a | b) */
 106         midgard_alu_op_iandnot    = 0x74, /* (a & ~b), used for not/b2f */
 107         midgard_alu_op_iornot     = 0x75, /* (a | ~b) */
 108         midgard_alu_op_ixor       = 0x76,
 109         midgard_alu_op_inxor      = 0x77, /* ~(a & b) */
 110         midgard_alu_op_iclz       = 0x78, /* Number of zeroes on left */
 111         midgard_alu_op_ibitcount8 = 0x7A, /* Counts bits in 8-bit increments */
 112         midgard_alu_op_imov       = 0x7B,
 113         midgard_alu_op_iabsdiff   = 0x7C,
 114         midgard_alu_op_uabsdiff   = 0x7D,
 115         midgard_alu_op_ichoose    = 0x7E, /* vector, component number - dupe for shuffle() */
 116
 117         midgard_alu_op_feq        = 0x80,
 118         midgard_alu_op_fne        = 0x81,
 119         midgard_alu_op_flt        = 0x82,
 120         midgard_alu_op_fle        = 0x83,
 121         midgard_alu_op_fball_eq   = 0x88,
 122         midgard_alu_op_fball_neq  = 0x89,
 123         midgard_alu_op_fball_lt   = 0x8A, /* all(lessThan(.., ..)) */
 124         midgard_alu_op_fball_lte  = 0x8B, /* all(lessThanEqual(.., ..)) */
 125
 126         midgard_alu_op_fbany_eq   = 0x90,
 127         midgard_alu_op_fbany_neq  = 0x91,
 128         midgard_alu_op_fbany_lt   = 0x92, /* any(lessThan(.., ..)) */
 129         midgard_alu_op_fbany_lte  = 0x93, /* any(lessThanEqual(.., ..)) */
 130
 131         midgard_alu_op_f2i_rte    = 0x98,
 132         midgard_alu_op_f2i_rtz    = 0x99,
 133         midgard_alu_op_f2i_rtn    = 0x9A,
 134         midgard_alu_op_f2i_rtp    = 0x9B,
 135         midgard_alu_op_f2u_rte    = 0x9C,
 136         midgard_alu_op_f2u_rtz    = 0x9D,
 137         midgard_alu_op_f2u_rtn    = 0x9E,
 138         midgard_alu_op_f2u_rtp    = 0x9F,
 139
 140         midgard_alu_op_ieq        = 0xA0,
 141         midgard_alu_op_ine        = 0xA1,
 142         midgard_alu_op_ult        = 0xA2,
 143         midgard_alu_op_ule        = 0xA3,
 144         midgard_alu_op_ilt        = 0xA4,
 145         midgard_alu_op_ile        = 0xA5,
 146         midgard_alu_op_iball_eq   = 0xA8,
 147         midgard_alu_op_iball_neq  = 0xA9,
 148         midgard_alu_op_uball_lt   = 0xAA,
 149         midgard_alu_op_uball_lte  = 0xAB,
 150         midgard_alu_op_iball_lt   = 0xAC,
 151         midgard_alu_op_iball_lte  = 0xAD,
 152
 153         midgard_alu_op_ibany_eq   = 0xB0,
 154         midgard_alu_op_ibany_neq  = 0xB1,
 155         midgard_alu_op_ubany_lt   = 0xB2,
 156         midgard_alu_op_ubany_lte  = 0xB3,
 157         midgard_alu_op_ibany_lt   = 0xB4, /* any(lessThan(.., ..)) */
 158         midgard_alu_op_ibany_lte  = 0xB5, /* any(lessThanEqual(.., ..)) */
 159         midgard_alu_op_i2f_rte    = 0xB8,
 160         midgard_alu_op_i2f_rtz    = 0xB9,
 161         midgard_alu_op_i2f_rtn    = 0xBA,
 162         midgard_alu_op_i2f_rtp    = 0xBB,
 163         midgard_alu_op_u2f_rte    = 0xBC,
 164         midgard_alu_op_u2f_rtz    = 0xBD,
 165         midgard_alu_op_u2f_rtn    = 0xBE,
 166         midgard_alu_op_u2f_rtp    = 0xBF,
 167
 168         midgard_alu_op_icsel_v    = 0xC0, /* condition code r31 */
 169         midgard_alu_op_icsel      = 0xC1, /* condition code r31.w */
 170         midgard_alu_op_fcsel_v    = 0xC4,
 171         midgard_alu_op_fcsel      = 0xC5,
 172         midgard_alu_op_fround     = 0xC6,
 173
 174         midgard_alu_op_fatan_pt2  = 0xE8,
 175         midgard_alu_op_fpow_pt1   = 0xEC,
 176         midgard_alu_op_fpown_pt1  = 0xED,
 177         midgard_alu_op_fpowr_pt1  = 0xEE,
 178
 179         midgard_alu_op_frcp       = 0xF0,
 180         midgard_alu_op_frsqrt     = 0xF2,
 181         midgard_alu_op_fsqrt      = 0xF3,
 182         midgard_alu_op_fexp2      = 0xF4,
 183         midgard_alu_op_flog2      = 0xF5,
 184         midgard_alu_op_fsin       = 0xF6,
 185         midgard_alu_op_fcos       = 0xF7,
 186         midgard_alu_op_fatan2_pt1 = 0xF9,
 187 } midgard_alu_op;
 188
 189 typedef enum {
 190         midgard_outmod_none = 0,
 191         midgard_outmod_pos  = 1,
 192         /* 0x2 unknown */
 193         midgard_outmod_sat  = 3
 194 } midgard_outmod_float;
 195
 196 typedef enum {
 197         midgard_outmod_int_saturate = 0,
 198         midgard_outmod_uint_saturate = 1,
 199         midgard_outmod_int_wrap = 2,
 200         midgard_outmod_int_high = 3, /* Overflowed portion */
 201 } midgard_outmod_int;
 202
 203 typedef enum {
 204         midgard_reg_mode_8 = 0,
 205         midgard_reg_mode_16 = 1,
 206         midgard_reg_mode_32 = 2,
 207         midgard_reg_mode_64 = 3
 208 } midgard_reg_mode;
 209
 210 typedef enum {
 211         midgard_dest_override_lower = 0,
 212         midgard_dest_override_upper = 1,
 213         midgard_dest_override_none = 2
 214 } midgard_dest_override;
 215
 216 typedef enum {
 217         midgard_int_sign_extend = 0,
 218         midgard_int_zero_extend = 1,
 219         midgard_int_normal = 2,
 220         midgard_int_shift = 3
 221 } midgard_int_mod;
 222
 223 #define MIDGARD_FLOAT_MOD_ABS (1 << 0)
 224 #define MIDGARD_FLOAT_MOD_NEG (1 << 1)
 225
 226 typedef struct
 227 __attribute__((__packed__))
 228 {
 229         /* Either midgard_int_mod or from midgard_float_mod_*, depending on the
 230          * type of op */
 231         unsigned mod : 2;
 232
 233         /* replicate lower half if dest = half, or low/high half selection if
 234          * dest = full
 235          */
 236         bool rep_low     : 1;
 237         bool rep_high    : 1; /* unused if dest = full */
 238         bool half        : 1; /* only matters if dest = full */
 239         unsigned swizzle : 8;
 240 }
 241 midgard_vector_alu_src;
 242
 243 typedef struct
 244 __attribute__((__packed__))
 245 {
 246         midgard_alu_op op               :  8;
 247         midgard_reg_mode reg_mode   :  2;
 248         unsigned src1 : 13;
 249         unsigned src2 : 13;
 250         midgard_dest_override dest_override : 2;
 251         unsigned outmod               : 2;
 252         unsigned mask                           : 8;
 253 }
 254 midgard_vector_alu;
 255
 256 typedef struct
 257 __attribute__((__packed__))
 258 {
 259         bool abs           : 1;
 260         bool negate        : 1;
 261         bool full          : 1; /* 0 = half, 1 = full */
 262         unsigned component : 3;
 263 }
 264 midgard_scalar_alu_src;
 265
 266 typedef struct
 267 __attribute__((__packed__))
 268 {
 269         midgard_alu_op op         :  8;
 270         unsigned src1             :  6;
 271         unsigned src2             : 11;
 272         unsigned unknown          :  1;
 273         unsigned outmod :  2;
 274         bool output_full          :  1;
 275         unsigned output_component :  3;
 276 }
 277 midgard_scalar_alu;
 278
 279 typedef struct
 280 __attribute__((__packed__))
 281 {
 282         unsigned src1_reg : 5;
 283         unsigned src2_reg : 5;
 284         unsigned out_reg  : 5;
 285         bool src2_imm     : 1;
 286 }
 287 midgard_reg_info;
 288
 289 /* In addition to conditional branches and jumps (unconditional branches),
 290  * Midgard implements a bit of fixed function functionality used in fragment
 291  * shaders via specially crafted branches. These have special branch opcodes,
 292  * which perform a fixed-function operation and/or use the results of a
 293  * fixed-function operation as the branch condition.  */
 294
 295 typedef enum {
 296         /* Regular branches */
 297         midgard_jmp_writeout_op_branch_uncond = 1,
 298         midgard_jmp_writeout_op_branch_cond = 2,
 299
 300         /* In a fragment shader, execute a discard_if instruction, with the
 301          * corresponding condition code. Terminates the shader, so generally
 302          * set the branch target to out of the shader */
 303         midgard_jmp_writeout_op_discard = 4,
 304
 305         /* Branch if the tilebuffer is not yet ready. At the beginning of a
 306          * fragment shader that reads from the tile buffer, for instance via
 307          * ARM_shader_framebuffer_fetch or EXT_pixel_local_storage, this branch
 308          * operation should be used as a loop. An instruction like
 309          * "br.tilebuffer.always -1" does the trick, corresponding to
 310          * "while(!is_tilebuffer_ready) */
 311         midgard_jmp_writeout_op_tilebuffer_pending = 6,
 312
 313         /* In a fragment shader, try to write out the value pushed to r0 to the
 314          * tilebuffer, subject to unknown state in r1.z and r1.w. If this
 315          * succeeds, the shader terminates. If it fails, it branches to the
 316          * specified branch target. Generally, this should be used in a loop to
 317          * itself, acting as "do { write(r0); } while(!write_successful);" */
 318         midgard_jmp_writeout_op_writeout = 7,
 319 } midgard_jmp_writeout_op;
 320
 321 typedef enum {
 322         midgard_condition_write0 = 0,
 323
 324         /* These condition codes denote a conditional branch on FALSE and on
 325          * TRUE respectively */
 326         midgard_condition_false = 1,
 327         midgard_condition_true = 2,
 328
 329         /* This condition code always branches. For a pure branch, the
 330          * unconditional branch coding should be used instead, but for
 331          * fixed-function branch opcodes, this is still useful */
 332         midgard_condition_always = 3,
 333 } midgard_condition;
 334
 335 typedef struct
 336 __attribute__((__packed__))
 337 {
 338         midgard_jmp_writeout_op op : 3; /* == branch_uncond */
 339         unsigned dest_tag : 4; /* tag of branch destination */
 340         unsigned unknown : 2;
 341         int offset : 7;
 342 }
 343 midgard_branch_uncond;
 344
 345 typedef struct
 346 __attribute__((__packed__))
 347 {
 348         midgard_jmp_writeout_op op : 3; /* == branch_cond */
 349         unsigned dest_tag : 4; /* tag of branch destination */
 350         int offset : 7;
 351         midgard_condition cond : 2;
 352 }
 353 midgard_branch_cond;
 354
 355 typedef struct
 356 __attribute__((__packed__))
 357 {
 358         midgard_jmp_writeout_op op : 3; /* == branch_cond */
 359         unsigned dest_tag : 4; /* tag of branch destination */
 360         unsigned unknown : 2;
 361         signed offset : 23;
 362
 363         /* Extended branches permit inputting up to 4 conditions loaded into
 364          * r31 (two in r31.w and two in r31.x). In the most general case, we
 365          * specify a function f(A, B, C, D) mapping 4 1-bit conditions to a
 366          * single 1-bit branch criteria. Note that the domain of f has 2^(2^4)
 367          * elements, each mapping to 1-bit of output, so we can trivially
 368          * construct a Godel numbering of f as a (2^4)=16-bit integer. This
 369          * 16-bit integer serves as a lookup table to compute f, subject to
 370          * some swaps for ordering.
 371          *
 372          * Interesting, the standard 2-bit condition codes are also a LUT with
 373          * the same format (2^1-bit), but it's usually easier to use enums. */
 374
 375         unsigned cond : 16;
 376 }
 377 midgard_branch_extended;
 378
 379 typedef struct
 380 __attribute__((__packed__))
 381 {
 382         midgard_jmp_writeout_op op : 3; /* == writeout */
 383         unsigned unknown : 13;
 384 }
 385 midgard_writeout;
 386
 387 /*
 388  * Load/store words
 389  */
 390
 391 typedef enum {
 392         midgard_op_ld_st_noop   = 0x03,
 393
 394         /* Unclear why this is on the L/S unit, but moves fp32 cube map
 395          * coordinates in r27 to its cube map texture coordinate destination
 396          * (e.g r29). */
 397
 398         midgard_op_ld_cubemap_coords = 0x0E,
 399
 400         /* Loads a global/local/group ID, depending on arguments */
 401         midgard_op_ld_compute_id = 0x10,
 402
 403         /* The L/S unit can do perspective division a clock faster than the ALU
 404          * if you're lucky. Put the vec4 in r27, and call with 0x24 as the
 405          * unknown state; the output will be <x/w, y/w, z/w, 1>. Replace w with
 406          * z for the z version */
 407         midgard_op_ldst_perspective_division_z = 0x12,
 408         midgard_op_ldst_perspective_division_w = 0x13,
 409
 410         /* val in r27.y, address embedded, outputs result to argument. Invert val for sub. Let val = +-1 for inc/dec. */
 411         midgard_op_atomic_add = 0x40,
 412         midgard_op_atomic_add64 = 0x41,
 413
 414         midgard_op_atomic_and = 0x44,
 415         midgard_op_atomic_and64 = 0x45,
 416         midgard_op_atomic_or = 0x48,
 417         midgard_op_atomic_or64 = 0x49,
 418         midgard_op_atomic_xor = 0x4C,
 419         midgard_op_atomic_xor64 = 0x4D,
 420
 421         midgard_op_atomic_imin = 0x50,
 422         midgard_op_atomic_imin64 = 0x51,
 423         midgard_op_atomic_umin = 0x54,
 424         midgard_op_atomic_umin64 = 0x55,
 425         midgard_op_atomic_imax = 0x58,
 426         midgard_op_atomic_imax64 = 0x59,
 427         midgard_op_atomic_umax = 0x5C,
 428         midgard_op_atomic_umax64 = 0x5D,
 429
 430         midgard_op_atomic_xchg = 0x60,
 431         midgard_op_atomic_xchg64 = 0x61,
 432
 433         /* Used for compute shader's __global arguments, __local variables (or
 434          * for register spilling) */
 435
 436         midgard_op_ld_char = 0x81,
 437         midgard_op_ld_char2 = 0x84,
 438         midgard_op_ld_short = 0x85,
 439         midgard_op_ld_char4 = 0x88, /* short2, int, float */
 440         midgard_op_ld_short4 = 0x8C, /* int2, float2, long */
 441         midgard_op_ld_int4 = 0x90, /* float4, long2 */
 442
 443         midgard_op_ld_attr_32 = 0x94,
 444         midgard_op_ld_attr_16 = 0x95,
 445         midgard_op_ld_attr_32u = 0x96,
 446         midgard_op_ld_attr_32i = 0x97,
 447         midgard_op_ld_vary_32 = 0x98,
 448         midgard_op_ld_vary_16 = 0x99,
 449         midgard_op_ld_vary_32u = 0x9A,
 450         midgard_op_ld_vary_32i = 0x9B,
 451
 452         /* Old version of midgard_op_ld_color_buffer_u8_as_fp16, for T720 */
 453         midgard_op_ld_color_buffer_u8_as_fp16_old = 0x9D,
 454
 455         /* The distinction between these ops is the alignment requirement /
 456          * accompanying shift. Thus, the offset to ld_ubo_int4 is in 16-byte
 457          * units and can load 128-bit. The offset to ld_ubo_short4 is in 8-byte
 458          * units; ld_ubo_char4 in 4-byte units. ld_ubo_char/ld_ubo_char2 are
 459          * purely theoretical (never seen in the wild) since int8/int16/fp16
 460          * UBOs don't really exist. The ops are still listed to maintain
 461          * symmetry with generic I/O ops. */
 462
 463         midgard_op_ld_ubo_char   = 0xA0, /* theoretical */
 464         midgard_op_ld_ubo_char2  = 0xA4, /* theoretical */
 465         midgard_op_ld_ubo_char4  = 0xA8,
 466         midgard_op_ld_ubo_short4 = 0xAC,
 467         midgard_op_ld_ubo_int4   = 0xB0,
 468
 469         /* New-style blending ops. Works on T760/T860 */
 470         midgard_op_ld_color_buffer_u8_as_fp16 = 0xB9,
 471         midgard_op_ld_color_buffer_8 = 0xBA,
 472
 473         midgard_op_st_char = 0xC0,
 474         midgard_op_st_char2 = 0xC4, /* short */
 475         midgard_op_st_char4 = 0xC8, /* short2, int, float */
 476         midgard_op_st_short4 = 0xCC, /* int2, float2, long */
 477         midgard_op_st_int4 = 0xD0, /* float4, long2 */
 478
 479         midgard_op_st_vary_32 = 0xD4,
 480         midgard_op_st_vary_16 = 0xD5,
 481         midgard_op_st_vary_32u = 0xD6,
 482         midgard_op_st_vary_32i = 0xD7,
 483
 484         /* Value to st in r27, location r26.w as short2 */
 485         midgard_op_st_image_f = 0xD8,
 486         midgard_op_st_image_ui = 0xDA,
 487         midgard_op_st_image_i = 0xDB,
 488 } midgard_load_store_op;
 489
 490 typedef enum {
 491         midgard_interp_centroid = 1,
 492         midgard_interp_default = 2
 493 } midgard_interpolation;
 494
 495 typedef enum {
 496         midgard_varying_mod_none = 0,
 497
 498         /* Other values unknown */
 499
 500         /* Take the would-be result and divide all components by its z/w
 501          * (perspective division baked in with the load)  */
 502         midgard_varying_mod_perspective_z = 2,
 503         midgard_varying_mod_perspective_w = 3,
 504 } midgard_varying_modifier;
 505
 506 typedef struct
 507 __attribute__((__packed__))
 508 {
 509         unsigned zero0 : 1; /* Always zero */
 510
 511         midgard_varying_modifier modifier : 2;
 512
 513         unsigned zero1: 1; /* Always zero */
 514
 515         /* Varying qualifiers, zero if not a varying */
 516         unsigned flat    : 1;
 517         unsigned is_varying : 1; /* Always one for varying, but maybe something else? */
 518         midgard_interpolation interpolation : 2;
 519
 520         unsigned zero2 : 2; /* Always zero */
 521 }
 522 midgard_varying_parameter;
 523
 524 /* 8-bit register/etc selector for load/store ops */
 525 typedef struct
 526 __attribute__((__packed__))
 527 {
 528         /* Indexes into the register */
 529         unsigned component : 2;
 530
 531         /* Register select between r26/r27 */
 532         unsigned select : 1;
 533
 534         unsigned unknown : 2;
 535
 536         /* Like any good Arm instruction set, load/store arguments can be
 537          * implicitly left-shifted... but only the second argument. Zero for no
 538          * shifting, up to <<7 possible though. This is useful for indexing.
 539          *
 540          * For the first argument, it's unknown what these bits mean */
 541         unsigned shift : 3;
 542 }
 543 midgard_ldst_register_select;
 544
 545 typedef struct
 546 __attribute__((__packed__))
 547 {
 548         midgard_load_store_op op : 8;
 549         unsigned reg     : 5;
 550         unsigned mask    : 4;
 551         unsigned swizzle : 8;
 552
 553         /* Load/store ops can take two additional registers as arguments, but
 554          * these are limited to load/store registers with only a few supported
 555          * mask/swizzle combinations. The tradeoff is these are much more
 556          * compact, requiring 8-bits each rather than 17-bits for a full
 557          * reg/mask/swizzle. Usually (?) encoded as
 558          * midgard_ldst_register_select. */
 559         unsigned arg_1   : 8;
 560         unsigned arg_2   : 8;
 561
 562         unsigned varying_parameters : 10;
 563
 564         unsigned address : 9;
 565 }
 566 midgard_load_store_word;
 567
 568 typedef struct
 569 __attribute__((__packed__))
 570 {
 571         unsigned type      : 4;
 572         unsigned next_type : 4;
 573         uint64_t word1     : 60;
 574         uint64_t word2     : 60;
 575 }
 576 midgard_load_store;
 577
 578 /* 8-bit register selector used in texture ops to select a bias/LOD/gradient
 579  * register, shoved into the `bias` field */
 580
 581 typedef struct
 582 __attribute__((__packed__))
 583 {
 584         /* 32-bit register, clear for half-register */
 585         unsigned full : 1;
 586
 587         /* Register select between r28/r29 */
 588         unsigned select : 1;
 589
 590         /* For a half-register, selects the upper half */
 591         unsigned upper : 1;
 592
 593         /* Indexes into the register */
 594         unsigned component : 2;
 595
 596         /* Padding to make this 8-bit */
 597         unsigned zero : 3;
 598 }
 599 midgard_tex_register_select;
 600
 601 /* Texture pipeline results are in r28-r29 */
 602 #define REG_TEX_BASE 28
 603
 604 /* Texture opcodes... maybe? */
 605 #define TEXTURE_OP_NORMAL 0x11          /* texture */
 606 #define TEXTURE_OP_LOD 0x12             /* textureLod */
 607 #define TEXTURE_OP_TEXEL_FETCH 0x14     /* texelFetch */
 608
 609 /* Computes horizontal and vertical derivatives respectively. Use with a float
 610  * sampler and a "2D" texture.  Leave texture/sampler IDs as zero; they ought
 611  * to be ignored. Only works for fp32 on 64-bit at a time, so derivatives of a
 612  * vec4 require 2 texture ops.  For some reason, the blob computes both X and Y
 613  * derivatives at the same time and just throws out whichever is unused; it's
 614  * not known if this is a quirk of the hardware or just of the blob. */
 615
 616 #define TEXTURE_OP_DFDX 0x0D
 617 #define TEXTURE_OP_DFDY 0x1D
 618
 619 enum mali_sampler_type {
 620         MALI_SAMPLER_UNK        = 0x0,
 621         MALI_SAMPLER_FLOAT      = 0x1, /* sampler */
 622         MALI_SAMPLER_UNSIGNED   = 0x2, /* usampler */
 623         MALI_SAMPLER_SIGNED     = 0x3, /* isampler */
 624 };
 625
 626 typedef struct
 627 __attribute__((__packed__))
 628 {
 629         unsigned type      : 4;
 630         unsigned next_type : 4;
 631
 632         unsigned op  : 6;
 633         unsigned shadow    : 1;
 634         unsigned is_gather  : 1;
 635
 636         /* A little obscure, but last is set for the last texture operation in
 637          * a shader. cont appears to just be last's opposite (?). Yeah, I know,
 638          * kind of funky.. BiOpen thinks it could do with memory hinting, or
 639          * tile locking? */
 640
 641         unsigned cont  : 1;
 642         unsigned last  : 1;
 643
 644         enum mali_texture_type format : 2;
 645
 646         /* Are sampler_handle/texture_handler respectively set by registers? If
 647          * true, the lower 8-bits of the respective field is a register word.
 648          * If false, they are an immediate */
 649
 650         unsigned sampler_register : 1;
 651         unsigned texture_register : 1;
 652
 653         /* Is a register used to specify the
 654          * LOD/bias/offset? If set, use the `bias` field as
 655          * a register index. If clear, use the `bias` field
 656          * as an immediate. */
 657         unsigned lod_register : 1;
 658
 659         /* Is a register used to specify an offset? If set, use the
 660          * offset_reg_* fields to encode this, duplicated for each of the
 661          * components. If clear, there is implcitly always an immediate offst
 662          * specificed in offset_imm_* */
 663         unsigned offset_register : 1;
 664
 665         unsigned in_reg_full  : 1;
 666         unsigned in_reg_select : 1;
 667         unsigned in_reg_upper  : 1;
 668         unsigned in_reg_swizzle : 8;
 669
 670         unsigned unknown8  : 2;
 671
 672         unsigned out_full  : 1;
 673
 674         enum mali_sampler_type sampler_type : 2;
 675
 676         unsigned out_reg_select : 1;
 677         unsigned out_upper : 1;
 678
 679         unsigned mask : 4;
 680
 681         /* Intriguingly, textures can take an outmod just like textures. Int
 682          * outmods are not supported as far as I can tell, so this is only
 683          * meaningful for float samplers */
 684         midgard_outmod_float outmod  : 2;
 685
 686         unsigned swizzle  : 8;
 687         unsigned unknown4  : 8;
 688
 689         unsigned unknownA  : 4;
 690
 691         /* In immediate mode, each offset field is an immediate range [0, 7].
 692          *
 693          * In register mode, offset_x becomes a register full / select / upper
 694          * triplet and a vec3 swizzle is splattered across offset_y/offset_z in
 695          * a genuinely bizarre way.
 696          *
 697          * For texel fetches in immediate mode, the range is the full [-8, 7],
 698          * but for normal texturing the top bit must be zero and a register
 699          * used instead. It's not clear where this limitation is from. */
 700
 701         signed offset_x : 4;
 702         signed offset_y : 4;
 703         signed offset_z : 4;
 704
 705         /* In immediate bias mode, for a normal texture op, this is
 706          * texture bias, computed as int(2^8 * frac(biasf)), with
 707          * bias_int = floor(bias). For a textureLod, it's that, but
 708          * s/bias/lod. For a texel fetch, this is the LOD as-is.
 709          *
 710          * In register mode, this is a midgard_tex_register_select
 711          * structure and bias_int is zero */
 712
 713         unsigned bias : 8;
 714         signed bias_int  : 8;
 715
 716         /* If sampler/texture_register is set, the bottom 8-bits are
 717          * midgard_tex_register_select and the top 8-bits are zero. If they are
 718          * clear, they are immediate texture indices */
 719
 720         unsigned sampler_handle : 16;
 721         unsigned texture_handle : 16;
 722 }
 723 midgard_texture_word;
 724
 725 #endif