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panfrost: add atomic ops infrastructure
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51 #include "panfrost-quirks.h"
52 #include "panfrost/util/pan_lower_framebuffer.h"
53
54 #include "disassemble.h"
55
56 static const struct debug_named_value debug_options[] = {
57 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
58 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
59 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
60 DEBUG_NAMED_VALUE_END
61 };
62
63 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
64
65 unsigned SHADER_DB_COUNT = 0;
66
67 int midgard_debug = 0;
68
69 #define DBG(fmt, ...) \
70 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
71 fprintf(stderr, "%s:%d: "fmt, \
72 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
73 static midgard_block *
74 create_empty_block(compiler_context *ctx)
75 {
76 midgard_block *blk = rzalloc(ctx, midgard_block);
77
78 blk->base.predecessors = _mesa_set_create(blk,
79 _mesa_hash_pointer,
80 _mesa_key_pointer_equal);
81
82 blk->base.name = ctx->block_source_count++;
83
84 return blk;
85 }
86
87 static void
88 schedule_barrier(compiler_context *ctx)
89 {
90 midgard_block *temp = ctx->after_block;
91 ctx->after_block = create_empty_block(ctx);
92 ctx->block_count++;
93 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
94 list_inithead(&ctx->after_block->base.instructions);
95 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
96 ctx->current_block = ctx->after_block;
97 ctx->after_block = temp;
98 }
99
100 /* Helpers to generate midgard_instruction's using macro magic, since every
101 * driver seems to do it that way */
102
103 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
104
105 #define M_LOAD_STORE(name, store, T) \
106 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
107 midgard_instruction i = { \
108 .type = TAG_LOAD_STORE_4, \
109 .mask = 0xF, \
110 .dest = ~0, \
111 .src = { ~0, ~0, ~0, ~0 }, \
112 .swizzle = SWIZZLE_IDENTITY_4, \
113 .op = midgard_op_##name, \
114 .load_store = { \
115 .address = address \
116 } \
117 }; \
118 \
119 if (store) { \
120 i.src[0] = ssa; \
121 i.src_types[0] = T; \
122 i.dest_type = T; \
123 } else { \
124 i.dest = ssa; \
125 i.dest_type = T; \
126 } \
127 return i; \
128 }
129
130 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
131 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
132
133 M_LOAD(ld_attr_32, nir_type_uint32);
134 M_LOAD(ld_vary_32, nir_type_uint32);
135 M_LOAD(ld_ubo_int4, nir_type_uint32);
136 M_LOAD(ld_int4, nir_type_uint32);
137 M_STORE(st_int4, nir_type_uint32);
138 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
139 M_LOAD(ld_color_buffer_as_fp16, nir_type_float16);
140 M_LOAD(ld_color_buffer_as_fp32, nir_type_float32);
141 M_STORE(st_vary_32, nir_type_uint32);
142 M_LOAD(ld_cubemap_coords, nir_type_uint32);
143 M_LOAD(ld_compute_id, nir_type_uint32);
144
145 static midgard_instruction
146 v_branch(bool conditional, bool invert)
147 {
148 midgard_instruction ins = {
149 .type = TAG_ALU_4,
150 .unit = ALU_ENAB_BRANCH,
151 .compact_branch = true,
152 .branch = {
153 .conditional = conditional,
154 .invert_conditional = invert
155 },
156 .dest = ~0,
157 .src = { ~0, ~0, ~0, ~0 },
158 };
159
160 return ins;
161 }
162
163 static void
164 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
165 {
166 ins->has_constants = true;
167 memcpy(&ins->constants, constants, 16);
168 }
169
170 static int
171 glsl_type_size(const struct glsl_type *type, bool bindless)
172 {
173 return glsl_count_attribute_slots(type, false);
174 }
175
176 /* Lower fdot2 to a vector multiplication followed by channel addition */
177 static void
178 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
179 {
180 if (alu->op != nir_op_fdot2)
181 return;
182
183 b->cursor = nir_before_instr(&alu->instr);
184
185 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
186 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
187
188 nir_ssa_def *product = nir_fmul(b, src0, src1);
189
190 nir_ssa_def *sum = nir_fadd(b,
191 nir_channel(b, product, 0),
192 nir_channel(b, product, 1));
193
194 /* Replace the fdot2 with this sum */
195 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
196 }
197
198 static bool
199 midgard_nir_lower_fdot2(nir_shader *shader)
200 {
201 bool progress = false;
202
203 nir_foreach_function(function, shader) {
204 if (!function->impl) continue;
205
206 nir_builder _b;
207 nir_builder *b = &_b;
208 nir_builder_init(b, function->impl);
209
210 nir_foreach_block(block, function->impl) {
211 nir_foreach_instr_safe(instr, block) {
212 if (instr->type != nir_instr_type_alu) continue;
213
214 nir_alu_instr *alu = nir_instr_as_alu(instr);
215 midgard_nir_lower_fdot2_body(b, alu);
216
217 progress |= true;
218 }
219 }
220
221 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
222
223 }
224
225 return progress;
226 }
227
228 static const nir_variable *
229 search_var(nir_shader *nir, nir_variable_mode mode, unsigned driver_loc)
230 {
231 nir_foreach_variable_with_modes(var, nir, mode) {
232 if (var->data.driver_location == driver_loc)
233 return var;
234 }
235
236 return NULL;
237 }
238
239 /* Midgard can write all of color, depth and stencil in a single writeout
240 * operation, so we merge depth/stencil stores with color stores.
241 * If there are no color stores, we add a write to the "depth RT".
242 */
243 static bool
244 midgard_nir_lower_zs_store(nir_shader *nir)
245 {
246 if (nir->info.stage != MESA_SHADER_FRAGMENT)
247 return false;
248
249 nir_variable *z_var = NULL, *s_var = NULL;
250
251 nir_foreach_shader_out_variable(var, nir) {
252 if (var->data.location == FRAG_RESULT_DEPTH)
253 z_var = var;
254 else if (var->data.location == FRAG_RESULT_STENCIL)
255 s_var = var;
256 }
257
258 if (!z_var && !s_var)
259 return false;
260
261 bool progress = false;
262
263 nir_foreach_function(function, nir) {
264 if (!function->impl) continue;
265
266 nir_intrinsic_instr *z_store = NULL, *s_store = NULL;
267
268 nir_foreach_block(block, function->impl) {
269 nir_foreach_instr_safe(instr, block) {
270 if (instr->type != nir_instr_type_intrinsic)
271 continue;
272
273 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
274 if (intr->intrinsic != nir_intrinsic_store_output)
275 continue;
276
277 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
278 assert(!z_store);
279 z_store = intr;
280 }
281
282 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
283 assert(!s_store);
284 s_store = intr;
285 }
286 }
287 }
288
289 if (!z_store && !s_store) continue;
290
291 bool replaced = false;
292
293 nir_foreach_block(block, function->impl) {
294 nir_foreach_instr_safe(instr, block) {
295 if (instr->type != nir_instr_type_intrinsic)
296 continue;
297
298 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
299 if (intr->intrinsic != nir_intrinsic_store_output)
300 continue;
301
302 const nir_variable *var = search_var(nir, nir_var_shader_out, nir_intrinsic_base(intr));
303 assert(var);
304
305 if (var->data.location != FRAG_RESULT_COLOR &&
306 var->data.location < FRAG_RESULT_DATA0)
307 continue;
308
309 if (var->data.index)
310 continue;
311
312 assert(nir_src_is_const(intr->src[1]) && "no indirect outputs");
313
314 nir_builder b;
315 nir_builder_init(&b, function->impl);
316
317 assert(!z_store || z_store->instr.block == instr->block);
318 assert(!s_store || s_store->instr.block == instr->block);
319 b.cursor = nir_after_block_before_jump(instr->block);
320
321 nir_intrinsic_instr *combined_store;
322 combined_store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_combined_output_pan);
323
324 combined_store->num_components = intr->src[0].ssa->num_components;
325
326 nir_intrinsic_set_base(combined_store, nir_intrinsic_base(intr));
327
328 unsigned writeout = PAN_WRITEOUT_C;
329 if (z_store)
330 writeout |= PAN_WRITEOUT_Z;
331 if (s_store)
332 writeout |= PAN_WRITEOUT_S;
333
334 nir_intrinsic_set_component(combined_store, writeout);
335
336 struct nir_ssa_def *zero = nir_imm_int(&b, 0);
337
338 struct nir_ssa_def *src[4] = {
339 intr->src[0].ssa,
340 intr->src[1].ssa,
341 z_store ? z_store->src[0].ssa : zero,
342 s_store ? s_store->src[0].ssa : zero,
343 };
344
345 for (int i = 0; i < 4; ++i)
346 combined_store->src[i] = nir_src_for_ssa(src[i]);
347
348 nir_builder_instr_insert(&b, &combined_store->instr);
349
350 nir_instr_remove(instr);
351
352 replaced = true;
353 }
354 }
355
356 /* Insert a store to the depth RT (0xff) if needed */
357 if (!replaced) {
358 nir_builder b;
359 nir_builder_init(&b, function->impl);
360
361 nir_block *block = NULL;
362 if (z_store && s_store)
363 assert(z_store->instr.block == s_store->instr.block);
364
365 if (z_store)
366 block = z_store->instr.block;
367 else
368 block = s_store->instr.block;
369
370 b.cursor = nir_after_block_before_jump(block);
371
372 nir_intrinsic_instr *combined_store;
373 combined_store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_combined_output_pan);
374
375 combined_store->num_components = 4;
376
377 unsigned base;
378 if (z_store)
379 base = nir_intrinsic_base(z_store);
380 else
381 base = nir_intrinsic_base(s_store);
382 nir_intrinsic_set_base(combined_store, base);
383
384 unsigned writeout = 0;
385 if (z_store)
386 writeout |= PAN_WRITEOUT_Z;
387 if (s_store)
388 writeout |= PAN_WRITEOUT_S;
389
390 nir_intrinsic_set_component(combined_store, writeout);
391
392 struct nir_ssa_def *zero = nir_imm_int(&b, 0);
393
394 struct nir_ssa_def *src[4] = {
395 nir_imm_vec4(&b, 0, 0, 0, 0),
396 zero,
397 z_store ? z_store->src[0].ssa : zero,
398 s_store ? s_store->src[0].ssa : zero,
399 };
400
401 for (int i = 0; i < 4; ++i)
402 combined_store->src[i] = nir_src_for_ssa(src[i]);
403
404 nir_builder_instr_insert(&b, &combined_store->instr);
405 }
406
407 if (z_store)
408 nir_instr_remove(&z_store->instr);
409
410 if (s_store)
411 nir_instr_remove(&s_store->instr);
412
413 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
414 progress = true;
415 }
416
417 return progress;
418 }
419
420 /* Real writeout stores, which break execution, need to be moved to after
421 * dual-source stores, which are just standard register writes. */
422 static bool
423 midgard_nir_reorder_writeout(nir_shader *nir)
424 {
425 bool progress = false;
426
427 nir_foreach_function(function, nir) {
428 if (!function->impl) continue;
429
430 nir_foreach_block(block, function->impl) {
431 nir_instr *last_writeout = NULL;
432
433 nir_foreach_instr_reverse_safe(instr, block) {
434 if (instr->type != nir_instr_type_intrinsic)
435 continue;
436
437 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
438 if (intr->intrinsic != nir_intrinsic_store_output)
439 continue;
440
441 const nir_variable *var = search_var(nir, nir_var_shader_out, nir_intrinsic_base(intr));
442
443 if (var->data.index) {
444 if (!last_writeout)
445 last_writeout = instr;
446 continue;
447 }
448
449 if (!last_writeout)
450 continue;
451
452 /* This is a real store, so move it to after dual-source stores */
453 exec_node_remove(&instr->node);
454 exec_node_insert_after(&last_writeout->node, &instr->node);
455
456 progress = true;
457 }
458 }
459 }
460
461 return progress;
462 }
463
464 static bool
465 mdg_is_64(const nir_instr *instr, const void *_unused)
466 {
467 const nir_alu_instr *alu = nir_instr_as_alu(instr);
468
469 if (nir_dest_bit_size(alu->dest.dest) == 64)
470 return true;
471
472 switch (alu->op) {
473 case nir_op_umul_high:
474 case nir_op_imul_high:
475 return true;
476 default:
477 return false;
478 }
479 }
480
481 /* Flushes undefined values to zero */
482
483 static void
484 optimise_nir(nir_shader *nir, unsigned quirks, bool is_blend)
485 {
486 bool progress;
487 unsigned lower_flrp =
488 (nir->options->lower_flrp16 ? 16 : 0) |
489 (nir->options->lower_flrp32 ? 32 : 0) |
490 (nir->options->lower_flrp64 ? 64 : 0);
491
492 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
493 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
494
495 nir_lower_tex_options lower_tex_options = {
496 .lower_txs_lod = true,
497 .lower_txp = ~0,
498 .lower_tex_without_implicit_lod =
499 (quirks & MIDGARD_EXPLICIT_LOD),
500 .lower_tg4_broadcom_swizzle = true,
501
502 /* TODO: we have native gradient.. */
503 .lower_txd = true,
504 };
505
506 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
507
508 /* Must lower fdot2 after tex is lowered */
509 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
510
511 /* T720 is broken. */
512
513 if (quirks & MIDGARD_BROKEN_LOD)
514 NIR_PASS_V(nir, midgard_nir_lod_errata);
515
516 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_early);
517
518 do {
519 progress = false;
520
521 NIR_PASS(progress, nir, nir_lower_var_copies);
522 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
523
524 NIR_PASS(progress, nir, nir_copy_prop);
525 NIR_PASS(progress, nir, nir_opt_remove_phis);
526 NIR_PASS(progress, nir, nir_opt_dce);
527 NIR_PASS(progress, nir, nir_opt_dead_cf);
528 NIR_PASS(progress, nir, nir_opt_cse);
529 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
530 NIR_PASS(progress, nir, nir_opt_algebraic);
531 NIR_PASS(progress, nir, nir_opt_constant_folding);
532
533 if (lower_flrp != 0) {
534 bool lower_flrp_progress = false;
535 NIR_PASS(lower_flrp_progress,
536 nir,
537 nir_lower_flrp,
538 lower_flrp,
539 false /* always_precise */,
540 nir->options->lower_ffma);
541 if (lower_flrp_progress) {
542 NIR_PASS(progress, nir,
543 nir_opt_constant_folding);
544 progress = true;
545 }
546
547 /* Nothing should rematerialize any flrps, so we only
548 * need to do this lowering once.
549 */
550 lower_flrp = 0;
551 }
552
553 NIR_PASS(progress, nir, nir_opt_undef);
554 NIR_PASS(progress, nir, nir_undef_to_zero);
555
556 NIR_PASS(progress, nir, nir_opt_loop_unroll,
557 nir_var_shader_in |
558 nir_var_shader_out |
559 nir_var_function_temp);
560
561 NIR_PASS(progress, nir, nir_opt_vectorize);
562 } while (progress);
563
564 NIR_PASS_V(nir, nir_lower_alu_to_scalar, mdg_is_64, NULL);
565
566 /* Run after opts so it can hit more */
567 if (!is_blend)
568 NIR_PASS(progress, nir, nir_fuse_io_16);
569
570 /* Must be run at the end to prevent creation of fsin/fcos ops */
571 NIR_PASS(progress, nir, midgard_nir_scale_trig);
572
573 do {
574 progress = false;
575
576 NIR_PASS(progress, nir, nir_opt_dce);
577 NIR_PASS(progress, nir, nir_opt_algebraic);
578 NIR_PASS(progress, nir, nir_opt_constant_folding);
579 NIR_PASS(progress, nir, nir_copy_prop);
580 } while (progress);
581
582 NIR_PASS(progress, nir, nir_opt_algebraic_late);
583 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
584
585 /* We implement booleans as 32-bit 0/~0 */
586 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
587
588 /* Now that booleans are lowered, we can run out late opts */
589 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
590 NIR_PASS(progress, nir, midgard_nir_cancel_inot);
591
592 NIR_PASS(progress, nir, nir_copy_prop);
593 NIR_PASS(progress, nir, nir_opt_dce);
594
595 /* Take us out of SSA */
596 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
597 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
598
599 /* We are a vector architecture; write combine where possible */
600 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
601 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
602
603 NIR_PASS(progress, nir, nir_opt_dce);
604 }
605
606 /* Do not actually emit a load; instead, cache the constant for inlining */
607
608 static void
609 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
610 {
611 nir_ssa_def def = instr->def;
612
613 midgard_constants *consts = rzalloc(NULL, midgard_constants);
614
615 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
616
617 #define RAW_CONST_COPY(bits) \
618 nir_const_value_to_array(consts->u##bits, instr->value, \
619 instr->def.num_components, u##bits)
620
621 switch (instr->def.bit_size) {
622 case 64:
623 RAW_CONST_COPY(64);
624 break;
625 case 32:
626 RAW_CONST_COPY(32);
627 break;
628 case 16:
629 RAW_CONST_COPY(16);
630 break;
631 case 8:
632 RAW_CONST_COPY(8);
633 break;
634 default:
635 unreachable("Invalid bit_size for load_const instruction\n");
636 }
637
638 /* Shifted for SSA, +1 for off-by-one */
639 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
640 }
641
642 /* Normally constants are embedded implicitly, but for I/O and such we have to
643 * explicitly emit a move with the constant source */
644
645 static void
646 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
647 {
648 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
649
650 if (constant_value) {
651 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
652 attach_constants(ctx, &ins, constant_value, node + 1);
653 emit_mir_instruction(ctx, ins);
654 }
655 }
656
657 static bool
658 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
659 {
660 unsigned comp = src->swizzle[0];
661
662 for (unsigned c = 1; c < nr_components; ++c) {
663 if (src->swizzle[c] != comp)
664 return true;
665 }
666
667 return false;
668 }
669
670 #define ATOMIC_CASE_IMPL(ctx, instr, nir, op, is_shared) \
671 case nir_intrinsic_##nir: \
672 emit_atomic(ctx, instr, is_shared, midgard_op_##op); \
673 break;
674
675 #define ATOMIC_CASE(ctx, instr, nir, op) \
676 ATOMIC_CASE_IMPL(ctx, instr, shared_atomic_##nir, atomic_##op, true); \
677 ATOMIC_CASE_IMPL(ctx, instr, global_atomic_##nir, atomic_##op, false);
678
679 #define ALU_CASE(nir, _op) \
680 case nir_op_##nir: \
681 op = midgard_alu_op_##_op; \
682 assert(src_bitsize == dst_bitsize); \
683 break;
684
685 #define ALU_CASE_RTZ(nir, _op) \
686 case nir_op_##nir: \
687 op = midgard_alu_op_##_op; \
688 roundmode = MIDGARD_RTZ; \
689 break;
690
691 #define ALU_CHECK_CMP(sext) \
692 assert(src_bitsize == 16 || src_bitsize == 32); \
693 assert(dst_bitsize == 16 || dst_bitsize == 32); \
694
695 #define ALU_CASE_BCAST(nir, _op, count) \
696 case nir_op_##nir: \
697 op = midgard_alu_op_##_op; \
698 broadcast_swizzle = count; \
699 ALU_CHECK_CMP(true); \
700 break;
701
702 #define ALU_CASE_CMP(nir, _op, sext) \
703 case nir_op_##nir: \
704 op = midgard_alu_op_##_op; \
705 ALU_CHECK_CMP(sext); \
706 break;
707
708 /* Compare mir_lower_invert */
709 static bool
710 nir_accepts_inot(nir_op op, unsigned src)
711 {
712 switch (op) {
713 case nir_op_ior:
714 case nir_op_iand: /* TODO: b2f16 */
715 case nir_op_ixor:
716 return true;
717 case nir_op_b32csel:
718 /* Only the condition */
719 return (src == 0);
720 default:
721 return false;
722 }
723 }
724
725 static bool
726 mir_accept_dest_mod(compiler_context *ctx, nir_dest **dest, nir_op op)
727 {
728 if (pan_has_dest_mod(dest, op)) {
729 assert((*dest)->is_ssa);
730 BITSET_SET(ctx->already_emitted, (*dest)->ssa.index);
731 return true;
732 }
733
734 return false;
735 }
736
737 /* Look for floating point mods. We have the mods fsat, fsat_signed,
738 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
739 *
740 * fsat_signed(fpos(x)) = fsat(x)
741 * fsat_signed(fsat(x)) = fsat(x)
742 * fpos(fsat_signed(x)) = fsat(x)
743 * fpos(fsat(x)) = fsat(x)
744 * fsat(fsat_signed(x)) = fsat(x)
745 * fsat(fpos(x)) = fsat(x)
746 *
747 * So by cases any composition of output modifiers is equivalent to
748 * fsat alone.
749 */
750 static unsigned
751 mir_determine_float_outmod(compiler_context *ctx, nir_dest **dest, unsigned prior_outmod)
752 {
753 bool fpos = mir_accept_dest_mod(ctx, dest, nir_op_fclamp_pos);
754 bool fsat = mir_accept_dest_mod(ctx, dest, nir_op_fsat);
755 bool ssat = mir_accept_dest_mod(ctx, dest, nir_op_fsat_signed);
756 bool prior = (prior_outmod != midgard_outmod_none);
757 int count = (int) prior + (int) fpos + (int) ssat + (int) fsat;
758
759 return ((count > 1) || fsat) ? midgard_outmod_sat :
760 fpos ? midgard_outmod_pos :
761 ssat ? midgard_outmod_sat_signed :
762 prior_outmod;
763 }
764
765 static void
766 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool *not, enum midgard_roundmode *roundmode, bool is_int, unsigned bcast_count)
767 {
768 nir_alu_src src = instr->src[i];
769
770 if (!is_int) {
771 if (pan_has_source_mod(&src, nir_op_fneg))
772 *neg = !(*neg);
773
774 if (pan_has_source_mod(&src, nir_op_fabs))
775 *abs = true;
776 }
777
778 if (nir_accepts_inot(instr->op, i) && pan_has_source_mod(&src, nir_op_inot))
779 *not = true;
780
781 if (roundmode) {
782 if (pan_has_source_mod(&src, nir_op_fround_even))
783 *roundmode = MIDGARD_RTE;
784
785 if (pan_has_source_mod(&src, nir_op_ftrunc))
786 *roundmode = MIDGARD_RTZ;
787
788 if (pan_has_source_mod(&src, nir_op_ffloor))
789 *roundmode = MIDGARD_RTN;
790
791 if (pan_has_source_mod(&src, nir_op_fceil))
792 *roundmode = MIDGARD_RTP;
793 }
794
795 unsigned bits = nir_src_bit_size(src.src);
796
797 ins->src[to] = nir_src_index(NULL, &src.src);
798 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
799
800 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
801 ins->swizzle[to][c] = src.swizzle[
802 (!bcast_count || c < bcast_count) ? c :
803 (bcast_count - 1)];
804 }
805 }
806
807 /* Midgard features both fcsel and icsel, depending on whether you want int or
808 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
809 * we should emit an int or float csel depending on what modifiers could be
810 * placed. In the absense of modifiers, this is probably arbitrary. */
811
812 static bool
813 mir_is_bcsel_float(nir_alu_instr *instr)
814 {
815 nir_op intmods[] = {
816 nir_op_i2i8, nir_op_i2i16,
817 nir_op_i2i32, nir_op_i2i64
818 };
819
820 nir_op floatmods[] = {
821 nir_op_fabs, nir_op_fneg,
822 nir_op_f2f16, nir_op_f2f32,
823 nir_op_f2f64
824 };
825
826 nir_op floatdestmods[] = {
827 nir_op_fsat, nir_op_fsat_signed, nir_op_fclamp_pos,
828 nir_op_f2f16, nir_op_f2f32
829 };
830
831 signed score = 0;
832
833 for (unsigned i = 1; i < 3; ++i) {
834 nir_alu_src s = instr->src[i];
835 for (unsigned q = 0; q < ARRAY_SIZE(intmods); ++q) {
836 if (pan_has_source_mod(&s, intmods[q]))
837 score--;
838 }
839 }
840
841 for (unsigned i = 1; i < 3; ++i) {
842 nir_alu_src s = instr->src[i];
843 for (unsigned q = 0; q < ARRAY_SIZE(floatmods); ++q) {
844 if (pan_has_source_mod(&s, floatmods[q]))
845 score++;
846 }
847 }
848
849 for (unsigned q = 0; q < ARRAY_SIZE(floatdestmods); ++q) {
850 nir_dest *dest = &instr->dest.dest;
851 if (pan_has_dest_mod(&dest, floatdestmods[q]))
852 score++;
853 }
854
855 return (score > 0);
856 }
857
858 static void
859 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
860 {
861 nir_dest *dest = &instr->dest.dest;
862
863 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index))
864 return;
865
866 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
867 * is handled elsewhere */
868
869 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
870 midgard_emit_derivatives(ctx, instr);
871 return;
872 }
873
874 bool is_ssa = dest->is_ssa;
875
876 unsigned nr_components = nir_dest_num_components(*dest);
877 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
878 unsigned op = 0;
879
880 /* Number of components valid to check for the instruction (the rest
881 * will be forced to the last), or 0 to use as-is. Relevant as
882 * ball-type instructions have a channel count in NIR but are all vec4
883 * in Midgard */
884
885 unsigned broadcast_swizzle = 0;
886
887 /* Should we swap arguments? */
888 bool flip_src12 = false;
889
890 ASSERTED unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
891 ASSERTED unsigned dst_bitsize = nir_dest_bit_size(*dest);
892
893 enum midgard_roundmode roundmode = MIDGARD_RTE;
894
895 switch (instr->op) {
896 ALU_CASE(fadd, fadd);
897 ALU_CASE(fmul, fmul);
898 ALU_CASE(fmin, fmin);
899 ALU_CASE(fmax, fmax);
900 ALU_CASE(imin, imin);
901 ALU_CASE(imax, imax);
902 ALU_CASE(umin, umin);
903 ALU_CASE(umax, umax);
904 ALU_CASE(ffloor, ffloor);
905 ALU_CASE(fround_even, froundeven);
906 ALU_CASE(ftrunc, ftrunc);
907 ALU_CASE(fceil, fceil);
908 ALU_CASE(fdot3, fdot3);
909 ALU_CASE(fdot4, fdot4);
910 ALU_CASE(iadd, iadd);
911 ALU_CASE(isub, isub);
912 ALU_CASE(imul, imul);
913 ALU_CASE(imul_high, imul);
914 ALU_CASE(umul_high, imul);
915
916 /* Zero shoved as second-arg */
917 ALU_CASE(iabs, iabsdiff);
918
919 ALU_CASE(mov, imov);
920
921 ALU_CASE_CMP(feq32, feq, false);
922 ALU_CASE_CMP(fneu32, fne, false);
923 ALU_CASE_CMP(flt32, flt, false);
924 ALU_CASE_CMP(ieq32, ieq, true);
925 ALU_CASE_CMP(ine32, ine, true);
926 ALU_CASE_CMP(ilt32, ilt, true);
927 ALU_CASE_CMP(ult32, ult, false);
928
929 /* We don't have a native b2f32 instruction. Instead, like many
930 * GPUs, we exploit booleans as 0/~0 for false/true, and
931 * correspondingly AND
932 * by 1.0 to do the type conversion. For the moment, prime us
933 * to emit:
934 *
935 * iand [whatever], #0
936 *
937 * At the end of emit_alu (as MIR), we'll fix-up the constant
938 */
939
940 ALU_CASE_CMP(b2f32, iand, true);
941 ALU_CASE_CMP(b2f16, iand, true);
942 ALU_CASE_CMP(b2i32, iand, true);
943
944 /* Likewise, we don't have a dedicated f2b32 instruction, but
945 * we can do a "not equal to 0.0" test. */
946
947 ALU_CASE_CMP(f2b32, fne, false);
948 ALU_CASE_CMP(i2b32, ine, true);
949
950 ALU_CASE(frcp, frcp);
951 ALU_CASE(frsq, frsqrt);
952 ALU_CASE(fsqrt, fsqrt);
953 ALU_CASE(fexp2, fexp2);
954 ALU_CASE(flog2, flog2);
955
956 ALU_CASE_RTZ(f2i64, f2i_rte);
957 ALU_CASE_RTZ(f2u64, f2u_rte);
958 ALU_CASE_RTZ(i2f64, i2f_rte);
959 ALU_CASE_RTZ(u2f64, u2f_rte);
960
961 ALU_CASE_RTZ(f2i32, f2i_rte);
962 ALU_CASE_RTZ(f2u32, f2u_rte);
963 ALU_CASE_RTZ(i2f32, i2f_rte);
964 ALU_CASE_RTZ(u2f32, u2f_rte);
965
966 ALU_CASE_RTZ(f2i8, f2i_rte);
967 ALU_CASE_RTZ(f2u8, f2u_rte);
968
969 ALU_CASE_RTZ(f2i16, f2i_rte);
970 ALU_CASE_RTZ(f2u16, f2u_rte);
971 ALU_CASE_RTZ(i2f16, i2f_rte);
972 ALU_CASE_RTZ(u2f16, u2f_rte);
973
974 ALU_CASE(fsin, fsin);
975 ALU_CASE(fcos, fcos);
976
977 /* We'll get 0 in the second arg, so:
978 * ~a = ~(a | 0) = nor(a, 0) */
979 ALU_CASE(inot, inor);
980 ALU_CASE(iand, iand);
981 ALU_CASE(ior, ior);
982 ALU_CASE(ixor, ixor);
983 ALU_CASE(ishl, ishl);
984 ALU_CASE(ishr, iasr);
985 ALU_CASE(ushr, ilsr);
986
987 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
988 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
989 ALU_CASE_CMP(b32all_fequal4, fball_eq, true);
990
991 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
992 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
993 ALU_CASE_CMP(b32any_fnequal4, fbany_neq, true);
994
995 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
996 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
997 ALU_CASE_CMP(b32all_iequal4, iball_eq, true);
998
999 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
1000 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
1001 ALU_CASE_CMP(b32any_inequal4, ibany_neq, true);
1002
1003 /* Source mods will be shoved in later */
1004 ALU_CASE(fabs, fmov);
1005 ALU_CASE(fneg, fmov);
1006 ALU_CASE(fsat, fmov);
1007 ALU_CASE(fsat_signed, fmov);
1008 ALU_CASE(fclamp_pos, fmov);
1009
1010 /* For size conversion, we use a move. Ideally though we would squash
1011 * these ops together; maybe that has to happen after in NIR as part of
1012 * propagation...? An earlier algebraic pass ensured we step down by
1013 * only / exactly one size. If stepping down, we use a dest override to
1014 * reduce the size; if stepping up, we use a larger-sized move with a
1015 * half source and a sign/zero-extension modifier */
1016
1017 case nir_op_i2i8:
1018 case nir_op_i2i16:
1019 case nir_op_i2i32:
1020 case nir_op_i2i64:
1021 case nir_op_u2u8:
1022 case nir_op_u2u16:
1023 case nir_op_u2u32:
1024 case nir_op_u2u64:
1025 case nir_op_f2f16:
1026 case nir_op_f2f32:
1027 case nir_op_f2f64: {
1028 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
1029 instr->op == nir_op_f2f64)
1030 op = midgard_alu_op_fmov;
1031 else
1032 op = midgard_alu_op_imov;
1033
1034 break;
1035 }
1036
1037 /* For greater-or-equal, we lower to less-or-equal and flip the
1038 * arguments */
1039
1040 case nir_op_fge:
1041 case nir_op_fge32:
1042 case nir_op_ige32:
1043 case nir_op_uge32: {
1044 op =
1045 instr->op == nir_op_fge ? midgard_alu_op_fle :
1046 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
1047 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
1048 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
1049 0;
1050
1051 flip_src12 = true;
1052 ALU_CHECK_CMP(false);
1053 break;
1054 }
1055
1056 case nir_op_b32csel: {
1057 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
1058 bool is_float = mir_is_bcsel_float(instr);
1059 op = is_float ?
1060 (mixed ? midgard_alu_op_fcsel_v : midgard_alu_op_fcsel) :
1061 (mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel);
1062
1063 break;
1064 }
1065
1066 case nir_op_unpack_32_2x16:
1067 case nir_op_unpack_32_4x8:
1068 case nir_op_pack_32_2x16:
1069 case nir_op_pack_32_4x8: {
1070 op = midgard_alu_op_imov;
1071 break;
1072 }
1073
1074 default:
1075 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
1076 assert(0);
1077 return;
1078 }
1079
1080 /* Promote imov to fmov if it might help inline a constant */
1081 if (op == midgard_alu_op_imov && nir_src_is_const(instr->src[0].src)
1082 && nir_src_bit_size(instr->src[0].src) == 32
1083 && nir_is_same_comp_swizzle(instr->src[0].swizzle,
1084 nir_src_num_components(instr->src[0].src))) {
1085 op = midgard_alu_op_fmov;
1086 }
1087
1088 /* Midgard can perform certain modifiers on output of an ALU op */
1089
1090 unsigned outmod = 0;
1091 bool is_int = midgard_is_integer_op(op);
1092
1093 if (instr->op == nir_op_umul_high || instr->op == nir_op_imul_high) {
1094 outmod = midgard_outmod_int_high;
1095 } else if (midgard_is_integer_out_op(op)) {
1096 outmod = midgard_outmod_int_wrap;
1097 } else if (instr->op == nir_op_fsat) {
1098 outmod = midgard_outmod_sat;
1099 } else if (instr->op == nir_op_fsat_signed) {
1100 outmod = midgard_outmod_sat_signed;
1101 } else if (instr->op == nir_op_fclamp_pos) {
1102 outmod = midgard_outmod_pos;
1103 }
1104
1105 /* Fetch unit, quirks, etc information */
1106 unsigned opcode_props = alu_opcode_props[op].props;
1107 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
1108
1109 if (!midgard_is_integer_out_op(op)) {
1110 outmod = mir_determine_float_outmod(ctx, &dest, outmod);
1111 }
1112
1113 midgard_instruction ins = {
1114 .type = TAG_ALU_4,
1115 .dest = nir_dest_index(dest),
1116 .dest_type = nir_op_infos[instr->op].output_type
1117 | nir_dest_bit_size(*dest),
1118 .roundmode = roundmode,
1119 };
1120
1121 enum midgard_roundmode *roundptr = (opcode_props & MIDGARD_ROUNDS) ?
1122 &ins.roundmode : NULL;
1123
1124 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
1125 ins.src[i] = ~0;
1126
1127 if (quirk_flipped_r24) {
1128 ins.src[0] = ~0;
1129 mir_copy_src(&ins, instr, 0, 1, &ins.src_abs[1], &ins.src_neg[1], &ins.src_invert[1], roundptr, is_int, broadcast_swizzle);
1130 } else {
1131 for (unsigned i = 0; i < nr_inputs; ++i) {
1132 unsigned to = i;
1133
1134 if (instr->op == nir_op_b32csel) {
1135 /* The condition is the first argument; move
1136 * the other arguments up one to be a binary
1137 * instruction for Midgard with the condition
1138 * last */
1139
1140 if (i == 0)
1141 to = 2;
1142 else if (flip_src12)
1143 to = 2 - i;
1144 else
1145 to = i - 1;
1146 } else if (flip_src12) {
1147 to = 1 - to;
1148 }
1149
1150 mir_copy_src(&ins, instr, i, to, &ins.src_abs[to], &ins.src_neg[to], &ins.src_invert[to], roundptr, is_int, broadcast_swizzle);
1151
1152 /* (!c) ? a : b = c ? b : a */
1153 if (instr->op == nir_op_b32csel && ins.src_invert[2]) {
1154 ins.src_invert[2] = false;
1155 flip_src12 ^= true;
1156 }
1157 }
1158 }
1159
1160 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
1161 /* Lowered to move */
1162 if (instr->op == nir_op_fneg)
1163 ins.src_neg[1] ^= true;
1164
1165 if (instr->op == nir_op_fabs)
1166 ins.src_abs[1] = true;
1167 }
1168
1169 ins.mask = mask_of(nr_components);
1170
1171 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1172 * components that don't exist. Note modifier => SSA => !reg => no
1173 * writemask, so we don't have to worry about writemasks here.*/
1174
1175 if (!is_ssa)
1176 ins.mask &= instr->dest.write_mask;
1177
1178 ins.op = op;
1179 ins.outmod = outmod;
1180
1181 /* Late fixup for emulated instructions */
1182
1183 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1184 /* Presently, our second argument is an inline #0 constant.
1185 * Switch over to an embedded 1.0 constant (that can't fit
1186 * inline, since we're 32-bit, not 16-bit like the inline
1187 * constants) */
1188
1189 ins.has_inline_constant = false;
1190 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1191 ins.src_types[1] = nir_type_float32;
1192 ins.has_constants = true;
1193
1194 if (instr->op == nir_op_b2f32)
1195 ins.constants.f32[0] = 1.0f;
1196 else
1197 ins.constants.i32[0] = 1;
1198
1199 for (unsigned c = 0; c < 16; ++c)
1200 ins.swizzle[1][c] = 0;
1201 } else if (instr->op == nir_op_b2f16) {
1202 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1203 ins.src_types[1] = nir_type_float16;
1204 ins.has_constants = true;
1205 ins.constants.i16[0] = _mesa_float_to_half(1.0);
1206
1207 for (unsigned c = 0; c < 16; ++c)
1208 ins.swizzle[1][c] = 0;
1209 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1210 /* Lots of instructions need a 0 plonked in */
1211 ins.has_inline_constant = false;
1212 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1213 ins.src_types[1] = ins.src_types[0];
1214 ins.has_constants = true;
1215 ins.constants.u32[0] = 0;
1216
1217 for (unsigned c = 0; c < 16; ++c)
1218 ins.swizzle[1][c] = 0;
1219 } else if (instr->op == nir_op_pack_32_2x16) {
1220 ins.dest_type = nir_type_uint16;
1221 ins.mask = mask_of(nr_components * 2);
1222 ins.is_pack = true;
1223 } else if (instr->op == nir_op_pack_32_4x8) {
1224 ins.dest_type = nir_type_uint8;
1225 ins.mask = mask_of(nr_components * 4);
1226 ins.is_pack = true;
1227 } else if (instr->op == nir_op_unpack_32_2x16) {
1228 ins.dest_type = nir_type_uint32;
1229 ins.mask = mask_of(nr_components >> 1);
1230 ins.is_pack = true;
1231 } else if (instr->op == nir_op_unpack_32_4x8) {
1232 ins.dest_type = nir_type_uint32;
1233 ins.mask = mask_of(nr_components >> 2);
1234 ins.is_pack = true;
1235 }
1236
1237 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1238 /* To avoid duplicating the lookup tables (probably), true LUT
1239 * instructions can only operate as if they were scalars. Lower
1240 * them here by changing the component. */
1241
1242 unsigned orig_mask = ins.mask;
1243
1244 unsigned swizzle_back[MIR_VEC_COMPONENTS];
1245 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
1246
1247 midgard_instruction ins_split[MIR_VEC_COMPONENTS];
1248 unsigned ins_count = 0;
1249
1250 for (int i = 0; i < nr_components; ++i) {
1251 /* Mask the associated component, dropping the
1252 * instruction if needed */
1253
1254 ins.mask = 1 << i;
1255 ins.mask &= orig_mask;
1256
1257 for (unsigned j = 0; j < ins_count; ++j) {
1258 if (swizzle_back[i] == ins_split[j].swizzle[0][0]) {
1259 ins_split[j].mask |= ins.mask;
1260 ins.mask = 0;
1261 break;
1262 }
1263 }
1264
1265 if (!ins.mask)
1266 continue;
1267
1268 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1269 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1270
1271 ins_split[ins_count] = ins;
1272
1273 ++ins_count;
1274 }
1275
1276 for (unsigned i = 0; i < ins_count; ++i) {
1277 emit_mir_instruction(ctx, ins_split[i]);
1278 }
1279 } else {
1280 emit_mir_instruction(ctx, ins);
1281 }
1282 }
1283
1284 #undef ALU_CASE
1285
1286 static void
1287 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1288 {
1289 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1290 unsigned nir_mask = 0;
1291 unsigned dsize = 0;
1292
1293 if (is_read) {
1294 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1295 dsize = nir_dest_bit_size(intr->dest);
1296 } else {
1297 nir_mask = nir_intrinsic_write_mask(intr);
1298 dsize = 32;
1299 }
1300
1301 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1302 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1303 ins->dest_type = nir_type_uint | dsize;
1304 mir_set_bytemask(ins, bytemask);
1305 }
1306
1307 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1308 * optimized) versions of UBO #0 */
1309
1310 static midgard_instruction *
1311 emit_ubo_read(
1312 compiler_context *ctx,
1313 nir_instr *instr,
1314 unsigned dest,
1315 unsigned offset,
1316 nir_src *indirect_offset,
1317 unsigned indirect_shift,
1318 unsigned index)
1319 {
1320 /* TODO: half-floats */
1321
1322 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1323 ins.constants.u32[0] = offset;
1324
1325 if (instr->type == nir_instr_type_intrinsic)
1326 mir_set_intr_mask(instr, &ins, true);
1327
1328 if (indirect_offset) {
1329 ins.src[2] = nir_src_index(ctx, indirect_offset);
1330 ins.src_types[2] = nir_type_uint32;
1331 ins.load_store.arg_2 = (indirect_shift << 5);
1332
1333 /* X component for the whole swizzle to prevent register
1334 * pressure from ballooning from the extra components */
1335 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[2]); ++i)
1336 ins.swizzle[2][i] = 0;
1337 } else {
1338 ins.load_store.arg_2 = 0x1E;
1339 }
1340
1341 ins.load_store.arg_1 = index;
1342
1343 return emit_mir_instruction(ctx, ins);
1344 }
1345
1346 /* Globals are like UBOs if you squint. And shared memory is like globals if
1347 * you squint even harder */
1348
1349 static void
1350 emit_global(
1351 compiler_context *ctx,
1352 nir_instr *instr,
1353 bool is_read,
1354 unsigned srcdest,
1355 nir_src *offset,
1356 bool is_shared)
1357 {
1358 /* TODO: types */
1359
1360 midgard_instruction ins;
1361
1362 if (is_read)
1363 ins = m_ld_int4(srcdest, 0);
1364 else
1365 ins = m_st_int4(srcdest, 0);
1366
1367 mir_set_offset(ctx, &ins, offset, is_shared);
1368 mir_set_intr_mask(instr, &ins, is_read);
1369
1370 /* Set a valid swizzle for masked out components */
1371 assert(ins.mask);
1372 unsigned first_component = __builtin_ffs(ins.mask) - 1;
1373
1374 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i) {
1375 if (!(ins.mask & (1 << i)))
1376 ins.swizzle[0][i] = first_component;
1377 }
1378
1379 emit_mir_instruction(ctx, ins);
1380 }
1381
1382 /* If is_shared is off, the only other possible value are globals, since
1383 * SSBO's are being lowered to globals through a NIR pass. */
1384 static void
1385 emit_atomic(
1386 compiler_context *ctx,
1387 nir_intrinsic_instr *instr,
1388 bool is_shared,
1389 midgard_load_store_op op)
1390 {
1391 unsigned bitsize = nir_src_bit_size(instr->src[1]);
1392 nir_alu_type type =
1393 (op == midgard_op_atomic_imin || op == midgard_op_atomic_imax) ?
1394 nir_type_int : nir_type_uint;
1395
1396 unsigned dest = nir_dest_index(&instr->dest);
1397 unsigned val = nir_src_index(ctx, &instr->src[1]);
1398 emit_explicit_constant(ctx, val, val);
1399
1400 midgard_instruction ins = {
1401 .type = TAG_LOAD_STORE_4,
1402 .mask = 0xF,
1403 .dest = dest,
1404 .src = { ~0, ~0, ~0, val },
1405 .src_types = { 0, 0, 0, type | bitsize },
1406 .op = op
1407 };
1408
1409 nir_src *src_offset = nir_get_io_offset_src(instr);
1410
1411 /* cmpxchg takes an extra value in arg_2, so we don't use it for the offset */
1412 if (op == midgard_op_atomic_cmpxchg) {
1413 unsigned addr = nir_src_index(ctx, src_offset);
1414
1415 ins.src[1] = addr;
1416 ins.src_types[1] = nir_type_uint | nir_src_bit_size(*src_offset);
1417
1418 unsigned xchg_val = nir_src_index(ctx, &instr->src[2]);
1419 emit_explicit_constant(ctx, xchg_val, xchg_val);
1420
1421 ins.src[2] = val;
1422 ins.src_types[2] = type | bitsize;
1423 ins.src[3] = xchg_val;
1424
1425 if (is_shared)
1426 ins.load_store.arg_1 |= 0x6E;
1427 } else {
1428 mir_set_offset(ctx, &ins, src_offset, is_shared);
1429 }
1430
1431 mir_set_intr_mask(&instr->instr, &ins, true);
1432
1433 emit_mir_instruction(ctx, ins);
1434 }
1435
1436 static void
1437 emit_varying_read(
1438 compiler_context *ctx,
1439 unsigned dest, unsigned offset,
1440 unsigned nr_comp, unsigned component,
1441 nir_src *indirect_offset, nir_alu_type type, bool flat)
1442 {
1443 /* XXX: Half-floats? */
1444 /* TODO: swizzle, mask */
1445
1446 midgard_instruction ins = m_ld_vary_32(dest, offset);
1447 ins.mask = mask_of(nr_comp);
1448 ins.dest_type = type;
1449
1450 if (type == nir_type_float16) {
1451 /* Ensure we are aligned so we can pack it later */
1452 ins.mask = mask_of(ALIGN_POT(nr_comp, 2));
1453 }
1454
1455 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1456 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1457
1458 midgard_varying_parameter p = {
1459 .is_varying = 1,
1460 .interpolation = midgard_interp_default,
1461 .flat = flat,
1462 };
1463
1464 unsigned u;
1465 memcpy(&u, &p, sizeof(p));
1466 ins.load_store.varying_parameters = u;
1467
1468 if (indirect_offset) {
1469 ins.src[2] = nir_src_index(ctx, indirect_offset);
1470 ins.src_types[2] = nir_type_uint32;
1471 } else
1472 ins.load_store.arg_2 = 0x1E;
1473
1474 ins.load_store.arg_1 = 0x9E;
1475
1476 /* Use the type appropriate load */
1477 switch (type) {
1478 case nir_type_uint32:
1479 case nir_type_bool32:
1480 ins.op = midgard_op_ld_vary_32u;
1481 break;
1482 case nir_type_int32:
1483 ins.op = midgard_op_ld_vary_32i;
1484 break;
1485 case nir_type_float32:
1486 ins.op = midgard_op_ld_vary_32;
1487 break;
1488 case nir_type_float16:
1489 ins.op = midgard_op_ld_vary_16;
1490 break;
1491 default:
1492 unreachable("Attempted to load unknown type");
1493 break;
1494 }
1495
1496 emit_mir_instruction(ctx, ins);
1497 }
1498
1499 static void
1500 emit_attr_read(
1501 compiler_context *ctx,
1502 unsigned dest, unsigned offset,
1503 unsigned nr_comp, nir_alu_type t)
1504 {
1505 midgard_instruction ins = m_ld_attr_32(dest, offset);
1506 ins.load_store.arg_1 = 0x1E;
1507 ins.load_store.arg_2 = 0x1E;
1508 ins.mask = mask_of(nr_comp);
1509
1510 /* Use the type appropriate load */
1511 switch (t) {
1512 case nir_type_uint:
1513 case nir_type_bool:
1514 ins.op = midgard_op_ld_attr_32u;
1515 break;
1516 case nir_type_int:
1517 ins.op = midgard_op_ld_attr_32i;
1518 break;
1519 case nir_type_float:
1520 ins.op = midgard_op_ld_attr_32;
1521 break;
1522 default:
1523 unreachable("Attempted to load unknown type");
1524 break;
1525 }
1526
1527 emit_mir_instruction(ctx, ins);
1528 }
1529
1530 static void
1531 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1532 unsigned nr_components, unsigned offset)
1533 {
1534 nir_dest nir_dest;
1535
1536 /* Figure out which uniform this is */
1537 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1538 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1539
1540 unsigned dest = nir_dest_index(&nir_dest);
1541
1542 /* Sysvals are prefix uniforms */
1543 unsigned uniform = ((uintptr_t) val) - 1;
1544
1545 /* Emit the read itself -- this is never indirect */
1546 midgard_instruction *ins =
1547 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1548
1549 ins->mask = mask_of(nr_components);
1550 }
1551
1552 static unsigned
1553 compute_builtin_arg(nir_op op)
1554 {
1555 switch (op) {
1556 case nir_intrinsic_load_work_group_id:
1557 return 0x14;
1558 case nir_intrinsic_load_local_invocation_id:
1559 return 0x10;
1560 default:
1561 unreachable("Invalid compute paramater loaded");
1562 }
1563 }
1564
1565 static void
1566 emit_fragment_store(compiler_context *ctx, unsigned src, unsigned src_z, unsigned src_s, enum midgard_rt_id rt)
1567 {
1568 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1569
1570 midgard_instruction *br = ctx->writeout_branch[rt];
1571
1572 assert(!br);
1573
1574 emit_explicit_constant(ctx, src, src);
1575
1576 struct midgard_instruction ins =
1577 v_branch(false, false);
1578
1579 bool depth_only = (rt == MIDGARD_ZS_RT);
1580
1581 ins.writeout = depth_only ? 0 : PAN_WRITEOUT_C;
1582
1583 /* Add dependencies */
1584 ins.src[0] = src;
1585 ins.src_types[0] = nir_type_uint32;
1586 ins.constants.u32[0] = depth_only ? 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1587 for (int i = 0; i < 4; ++i)
1588 ins.swizzle[0][i] = i;
1589
1590 if (~src_z) {
1591 emit_explicit_constant(ctx, src_z, src_z);
1592 ins.src[2] = src_z;
1593 ins.src_types[2] = nir_type_uint32;
1594 ins.writeout |= PAN_WRITEOUT_Z;
1595 }
1596 if (~src_s) {
1597 emit_explicit_constant(ctx, src_s, src_s);
1598 ins.src[3] = src_s;
1599 ins.src_types[3] = nir_type_uint32;
1600 ins.writeout |= PAN_WRITEOUT_S;
1601 }
1602
1603 /* Emit the branch */
1604 br = emit_mir_instruction(ctx, ins);
1605 schedule_barrier(ctx);
1606 ctx->writeout_branch[rt] = br;
1607
1608 /* Push our current location = current block count - 1 = where we'll
1609 * jump to. Maybe a bit too clever for my own good */
1610
1611 br->branch.target_block = ctx->block_count - 1;
1612 }
1613
1614 static void
1615 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1616 {
1617 unsigned reg = nir_dest_index(&instr->dest);
1618 midgard_instruction ins = m_ld_compute_id(reg, 0);
1619 ins.mask = mask_of(3);
1620 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1621 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1622 emit_mir_instruction(ctx, ins);
1623 }
1624
1625 static unsigned
1626 vertex_builtin_arg(nir_op op)
1627 {
1628 switch (op) {
1629 case nir_intrinsic_load_vertex_id:
1630 return PAN_VERTEX_ID;
1631 case nir_intrinsic_load_instance_id:
1632 return PAN_INSTANCE_ID;
1633 default:
1634 unreachable("Invalid vertex builtin");
1635 }
1636 }
1637
1638 static void
1639 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1640 {
1641 unsigned reg = nir_dest_index(&instr->dest);
1642 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1643 }
1644
1645 static void
1646 emit_special(compiler_context *ctx, nir_intrinsic_instr *instr, unsigned idx)
1647 {
1648 unsigned reg = nir_dest_index(&instr->dest);
1649
1650 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1651 ld.op = midgard_op_ld_color_buffer_32u_old;
1652 ld.load_store.address = idx;
1653 ld.load_store.arg_2 = 0x1E;
1654
1655 for (int i = 0; i < 4; ++i)
1656 ld.swizzle[0][i] = COMPONENT_X;
1657
1658 emit_mir_instruction(ctx, ld);
1659 }
1660
1661 static void
1662 emit_control_barrier(compiler_context *ctx)
1663 {
1664 midgard_instruction ins = {
1665 .type = TAG_TEXTURE_4,
1666 .dest = ~0,
1667 .src = { ~0, ~0, ~0, ~0 },
1668 .op = TEXTURE_OP_BARRIER,
1669 };
1670
1671 emit_mir_instruction(ctx, ins);
1672 }
1673
1674 static unsigned
1675 mir_get_branch_cond(nir_src *src, bool *invert)
1676 {
1677 /* Wrap it. No swizzle since it's a scalar */
1678
1679 nir_alu_src alu = {
1680 .src = *src
1681 };
1682
1683 *invert = pan_has_source_mod(&alu, nir_op_inot);
1684 return nir_src_index(NULL, &alu.src);
1685 }
1686
1687 static uint8_t
1688 output_load_rt_addr(compiler_context *ctx, nir_intrinsic_instr *instr)
1689 {
1690 if (ctx->is_blend)
1691 return ctx->blend_rt;
1692
1693 const nir_variable *var;
1694 var = search_var(ctx->nir, nir_var_shader_out, nir_intrinsic_base(instr));
1695 assert(var);
1696
1697 unsigned loc = var->data.location;
1698
1699 if (loc == FRAG_RESULT_COLOR)
1700 loc = FRAG_RESULT_DATA0;
1701
1702 if (loc >= FRAG_RESULT_DATA0)
1703 return loc - FRAG_RESULT_DATA0;
1704
1705 if (loc == FRAG_RESULT_DEPTH)
1706 return 0x1F;
1707 if (loc == FRAG_RESULT_STENCIL)
1708 return 0x1E;
1709
1710 unreachable("Invalid RT to load from");
1711 }
1712
1713 static void
1714 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1715 {
1716 unsigned offset = 0, reg;
1717
1718 switch (instr->intrinsic) {
1719 case nir_intrinsic_discard_if:
1720 case nir_intrinsic_discard: {
1721 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1722 struct midgard_instruction discard = v_branch(conditional, false);
1723 discard.branch.target_type = TARGET_DISCARD;
1724
1725 if (conditional) {
1726 discard.src[0] = mir_get_branch_cond(&instr->src[0],
1727 &discard.branch.invert_conditional);
1728 discard.src_types[0] = nir_type_uint32;
1729 }
1730
1731 emit_mir_instruction(ctx, discard);
1732 schedule_barrier(ctx);
1733
1734 break;
1735 }
1736
1737 case nir_intrinsic_load_uniform:
1738 case nir_intrinsic_load_ubo:
1739 case nir_intrinsic_load_global:
1740 case nir_intrinsic_load_shared:
1741 case nir_intrinsic_load_input:
1742 case nir_intrinsic_load_interpolated_input: {
1743 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1744 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1745 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1746 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1747 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1748 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1749
1750 /* Get the base type of the intrinsic */
1751 /* TODO: Infer type? Does it matter? */
1752 nir_alu_type t =
1753 (is_ubo || is_global || is_shared) ? nir_type_uint :
1754 (is_interp) ? nir_type_float :
1755 nir_intrinsic_type(instr);
1756
1757 t = nir_alu_type_get_base_type(t);
1758
1759 if (!(is_ubo || is_global)) {
1760 offset = nir_intrinsic_base(instr);
1761 }
1762
1763 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1764
1765 nir_src *src_offset = nir_get_io_offset_src(instr);
1766
1767 bool direct = nir_src_is_const(*src_offset);
1768 nir_src *indirect_offset = direct ? NULL : src_offset;
1769
1770 if (direct)
1771 offset += nir_src_as_uint(*src_offset);
1772
1773 /* We may need to apply a fractional offset */
1774 int component = (is_flat || is_interp) ?
1775 nir_intrinsic_component(instr) : 0;
1776 reg = nir_dest_index(&instr->dest);
1777
1778 if (is_uniform && !ctx->is_blend) {
1779 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1780 } else if (is_ubo) {
1781 nir_src index = instr->src[0];
1782
1783 /* TODO: Is indirect block number possible? */
1784 assert(nir_src_is_const(index));
1785
1786 uint32_t uindex = nir_src_as_uint(index) + 1;
1787 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1788 } else if (is_global || is_shared) {
1789 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1790 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1791 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t | nir_dest_bit_size(instr->dest), is_flat);
1792 } else if (ctx->is_blend) {
1793 /* ctx->blend_input will be precoloured to r0/r2, where
1794 * the input is preloaded */
1795
1796 unsigned *input = offset ? &ctx->blend_src1 : &ctx->blend_input;
1797
1798 if (*input == ~0)
1799 *input = reg;
1800 else
1801 emit_mir_instruction(ctx, v_mov(*input, reg));
1802 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1803 emit_attr_read(ctx, reg, offset, nr_comp, t);
1804 } else {
1805 DBG("Unknown load\n");
1806 assert(0);
1807 }
1808
1809 break;
1810 }
1811
1812 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1813 case nir_intrinsic_load_barycentric_pixel:
1814 case nir_intrinsic_load_barycentric_centroid:
1815 break;
1816
1817 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1818
1819 case nir_intrinsic_load_raw_output_pan: {
1820 reg = nir_dest_index(&instr->dest);
1821
1822 /* T720 and below use different blend opcodes with slightly
1823 * different semantics than T760 and up */
1824
1825 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1826
1827 ld.load_store.arg_2 = output_load_rt_addr(ctx, instr);
1828
1829 if (nir_src_is_const(instr->src[0])) {
1830 ld.load_store.arg_1 = nir_src_as_uint(instr->src[0]);
1831 } else {
1832 ld.load_store.varying_parameters = 2;
1833 ld.src[1] = nir_src_index(ctx, &instr->src[0]);
1834 ld.src_types[1] = nir_type_int32;
1835 }
1836
1837 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1838 ld.op = midgard_op_ld_color_buffer_32u_old;
1839 ld.load_store.address = 16;
1840 ld.load_store.arg_2 = 0x1E;
1841 }
1842
1843 emit_mir_instruction(ctx, ld);
1844 break;
1845 }
1846
1847 case nir_intrinsic_load_output: {
1848 reg = nir_dest_index(&instr->dest);
1849
1850 unsigned bits = nir_dest_bit_size(instr->dest);
1851
1852 midgard_instruction ld;
1853 if (bits == 16)
1854 ld = m_ld_color_buffer_as_fp16(reg, 0);
1855 else
1856 ld = m_ld_color_buffer_as_fp32(reg, 0);
1857
1858 ld.load_store.arg_2 = output_load_rt_addr(ctx, instr);
1859
1860 for (unsigned c = 4; c < 16; ++c)
1861 ld.swizzle[0][c] = 0;
1862
1863 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1864 if (bits == 16)
1865 ld.op = midgard_op_ld_color_buffer_as_fp16_old;
1866 else
1867 ld.op = midgard_op_ld_color_buffer_as_fp32_old;
1868 ld.load_store.address = 1;
1869 ld.load_store.arg_2 = 0x1E;
1870 }
1871
1872 emit_mir_instruction(ctx, ld);
1873 break;
1874 }
1875
1876 case nir_intrinsic_load_blend_const_color_rgba: {
1877 assert(ctx->is_blend);
1878 reg = nir_dest_index(&instr->dest);
1879
1880 /* Blend constants are embedded directly in the shader and
1881 * patched in, so we use some magic routing */
1882
1883 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1884 ins.has_constants = true;
1885 ins.has_blend_constant = true;
1886 emit_mir_instruction(ctx, ins);
1887 break;
1888 }
1889
1890 case nir_intrinsic_store_output:
1891 case nir_intrinsic_store_combined_output_pan:
1892 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1893
1894 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1895
1896 reg = nir_src_index(ctx, &instr->src[0]);
1897
1898 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1899 bool combined = instr->intrinsic ==
1900 nir_intrinsic_store_combined_output_pan;
1901
1902 const nir_variable *var;
1903 var = search_var(ctx->nir, nir_var_shader_out,
1904 nir_intrinsic_base(instr));
1905 assert(var);
1906
1907 /* Dual-source blend writeout is done by leaving the
1908 * value in r2 for the blend shader to use. */
1909 if (var->data.index) {
1910 if (instr->src[0].is_ssa) {
1911 emit_explicit_constant(ctx, reg, reg);
1912
1913 unsigned out = make_compiler_temp(ctx);
1914
1915 midgard_instruction ins = v_mov(reg, out);
1916 emit_mir_instruction(ctx, ins);
1917
1918 ctx->blend_src1 = out;
1919 } else {
1920 ctx->blend_src1 = reg;
1921 }
1922
1923 break;
1924 }
1925
1926 enum midgard_rt_id rt;
1927 if (var->data.location == FRAG_RESULT_COLOR)
1928 rt = MIDGARD_COLOR_RT0;
1929 else if (var->data.location >= FRAG_RESULT_DATA0)
1930 rt = MIDGARD_COLOR_RT0 + var->data.location -
1931 FRAG_RESULT_DATA0;
1932 else if (combined)
1933 rt = MIDGARD_ZS_RT;
1934 else
1935 unreachable("bad rt");
1936
1937 unsigned reg_z = ~0, reg_s = ~0;
1938 if (combined) {
1939 unsigned writeout = nir_intrinsic_component(instr);
1940 if (writeout & PAN_WRITEOUT_Z)
1941 reg_z = nir_src_index(ctx, &instr->src[2]);
1942 if (writeout & PAN_WRITEOUT_S)
1943 reg_s = nir_src_index(ctx, &instr->src[3]);
1944 }
1945
1946 emit_fragment_store(ctx, reg, reg_z, reg_s, rt);
1947 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1948 assert(instr->intrinsic == nir_intrinsic_store_output);
1949
1950 /* We should have been vectorized, though we don't
1951 * currently check that st_vary is emitted only once
1952 * per slot (this is relevant, since there's not a mask
1953 * parameter available on the store [set to 0 by the
1954 * blob]). We do respect the component by adjusting the
1955 * swizzle. If this is a constant source, we'll need to
1956 * emit that explicitly. */
1957
1958 emit_explicit_constant(ctx, reg, reg);
1959
1960 unsigned dst_component = nir_intrinsic_component(instr);
1961 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1962
1963 midgard_instruction st = m_st_vary_32(reg, offset);
1964 st.load_store.arg_1 = 0x9E;
1965 st.load_store.arg_2 = 0x1E;
1966
1967 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1968 case nir_type_uint:
1969 case nir_type_bool:
1970 st.op = midgard_op_st_vary_32u;
1971 break;
1972 case nir_type_int:
1973 st.op = midgard_op_st_vary_32i;
1974 break;
1975 case nir_type_float:
1976 st.op = midgard_op_st_vary_32;
1977 break;
1978 default:
1979 unreachable("Attempted to store unknown type");
1980 break;
1981 }
1982
1983 /* nir_intrinsic_component(store_intr) encodes the
1984 * destination component start. Source component offset
1985 * adjustment is taken care of in
1986 * install_registers_instr(), when offset_swizzle() is
1987 * called.
1988 */
1989 unsigned src_component = COMPONENT_X;
1990
1991 assert(nr_comp > 0);
1992 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1993 st.swizzle[0][i] = src_component;
1994 if (i >= dst_component && i < dst_component + nr_comp - 1)
1995 src_component++;
1996 }
1997
1998 emit_mir_instruction(ctx, st);
1999 } else {
2000 DBG("Unknown store\n");
2001 assert(0);
2002 }
2003
2004 break;
2005
2006 /* Special case of store_output for lowered blend shaders */
2007 case nir_intrinsic_store_raw_output_pan:
2008 assert (ctx->stage == MESA_SHADER_FRAGMENT);
2009 reg = nir_src_index(ctx, &instr->src[0]);
2010 emit_fragment_store(ctx, reg, ~0, ~0, ctx->blend_rt);
2011 break;
2012
2013 case nir_intrinsic_store_global:
2014 case nir_intrinsic_store_shared:
2015 reg = nir_src_index(ctx, &instr->src[0]);
2016 emit_explicit_constant(ctx, reg, reg);
2017
2018 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
2019 break;
2020
2021 case nir_intrinsic_load_ssbo_address:
2022 emit_sysval_read(ctx, &instr->instr, 1, 0);
2023 break;
2024
2025 case nir_intrinsic_get_buffer_size:
2026 emit_sysval_read(ctx, &instr->instr, 1, 8);
2027 break;
2028
2029 case nir_intrinsic_load_viewport_scale:
2030 case nir_intrinsic_load_viewport_offset:
2031 case nir_intrinsic_load_num_work_groups:
2032 case nir_intrinsic_load_sampler_lod_parameters_pan:
2033 emit_sysval_read(ctx, &instr->instr, 3, 0);
2034 break;
2035
2036 case nir_intrinsic_load_work_group_id:
2037 case nir_intrinsic_load_local_invocation_id:
2038 emit_compute_builtin(ctx, instr);
2039 break;
2040
2041 case nir_intrinsic_load_vertex_id:
2042 case nir_intrinsic_load_instance_id:
2043 emit_vertex_builtin(ctx, instr);
2044 break;
2045
2046 case nir_intrinsic_load_sample_mask_in:
2047 emit_special(ctx, instr, 96);
2048 break;
2049
2050 case nir_intrinsic_load_sample_id:
2051 emit_special(ctx, instr, 97);
2052 break;
2053
2054 case nir_intrinsic_memory_barrier_buffer:
2055 case nir_intrinsic_memory_barrier_shared:
2056 break;
2057
2058 case nir_intrinsic_control_barrier:
2059 schedule_barrier(ctx);
2060 emit_control_barrier(ctx);
2061 schedule_barrier(ctx);
2062 break;
2063
2064 default:
2065 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
2066 assert(0);
2067 break;
2068 }
2069 }
2070
2071 /* Returns dimension with 0 special casing cubemaps */
2072 static unsigned
2073 midgard_tex_format(enum glsl_sampler_dim dim)
2074 {
2075 switch (dim) {
2076 case GLSL_SAMPLER_DIM_1D:
2077 case GLSL_SAMPLER_DIM_BUF:
2078 return 1;
2079
2080 case GLSL_SAMPLER_DIM_2D:
2081 case GLSL_SAMPLER_DIM_MS:
2082 case GLSL_SAMPLER_DIM_EXTERNAL:
2083 case GLSL_SAMPLER_DIM_RECT:
2084 return 2;
2085
2086 case GLSL_SAMPLER_DIM_3D:
2087 return 3;
2088
2089 case GLSL_SAMPLER_DIM_CUBE:
2090 return 0;
2091
2092 default:
2093 DBG("Unknown sampler dim type\n");
2094 assert(0);
2095 return 0;
2096 }
2097 }
2098
2099 /* Tries to attach an explicit LOD or bias as a constant. Returns whether this
2100 * was successful */
2101
2102 static bool
2103 pan_attach_constant_bias(
2104 compiler_context *ctx,
2105 nir_src lod,
2106 midgard_texture_word *word)
2107 {
2108 /* To attach as constant, it has to *be* constant */
2109
2110 if (!nir_src_is_const(lod))
2111 return false;
2112
2113 float f = nir_src_as_float(lod);
2114
2115 /* Break into fixed-point */
2116 signed lod_int = f;
2117 float lod_frac = f - lod_int;
2118
2119 /* Carry over negative fractions */
2120 if (lod_frac < 0.0) {
2121 lod_int--;
2122 lod_frac += 1.0;
2123 }
2124
2125 /* Encode */
2126 word->bias = float_to_ubyte(lod_frac);
2127 word->bias_int = lod_int;
2128
2129 return true;
2130 }
2131
2132 static enum mali_texture_mode
2133 mdg_texture_mode(nir_tex_instr *instr)
2134 {
2135 if (instr->op == nir_texop_tg4 && instr->is_shadow)
2136 return TEXTURE_GATHER_SHADOW;
2137 else if (instr->op == nir_texop_tg4)
2138 return TEXTURE_GATHER_X + instr->component;
2139 else if (instr->is_shadow)
2140 return TEXTURE_SHADOW;
2141 else
2142 return TEXTURE_NORMAL;
2143 }
2144
2145 static void
2146 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
2147 unsigned midgard_texop)
2148 {
2149 /* TODO */
2150 //assert (!instr->sampler);
2151
2152 nir_dest *dest = &instr->dest;
2153
2154 int texture_index = instr->texture_index;
2155 int sampler_index = texture_index;
2156
2157 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
2158 nir_alu_type dest_type = dest_base | nir_dest_bit_size(*dest);
2159
2160 /* texture instructions support float outmods */
2161 unsigned outmod = midgard_outmod_none;
2162 if (dest_base == nir_type_float) {
2163 outmod = mir_determine_float_outmod(ctx, &dest, 0);
2164 }
2165
2166 midgard_instruction ins = {
2167 .type = TAG_TEXTURE_4,
2168 .mask = 0xF,
2169 .dest = nir_dest_index(dest),
2170 .src = { ~0, ~0, ~0, ~0 },
2171 .dest_type = dest_type,
2172 .swizzle = SWIZZLE_IDENTITY_4,
2173 .outmod = outmod,
2174 .op = midgard_texop,
2175 .texture = {
2176 .format = midgard_tex_format(instr->sampler_dim),
2177 .texture_handle = texture_index,
2178 .sampler_handle = sampler_index,
2179 .mode = mdg_texture_mode(instr)
2180 }
2181 };
2182
2183 if (instr->is_shadow && !instr->is_new_style_shadow && instr->op != nir_texop_tg4)
2184 for (int i = 0; i < 4; ++i)
2185 ins.swizzle[0][i] = COMPONENT_X;
2186
2187 /* We may need a temporary for the coordinate */
2188
2189 bool needs_temp_coord =
2190 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
2191 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
2192 (instr->is_shadow);
2193
2194 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
2195
2196 for (unsigned i = 0; i < instr->num_srcs; ++i) {
2197 int index = nir_src_index(ctx, &instr->src[i].src);
2198 unsigned nr_components = nir_src_num_components(instr->src[i].src);
2199 unsigned sz = nir_src_bit_size(instr->src[i].src);
2200 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
2201
2202 switch (instr->src[i].src_type) {
2203 case nir_tex_src_coord: {
2204 emit_explicit_constant(ctx, index, index);
2205
2206 unsigned coord_mask = mask_of(instr->coord_components);
2207
2208 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
2209
2210 if (flip_zw)
2211 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
2212
2213 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2214 /* texelFetch is undefined on samplerCube */
2215 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
2216
2217 /* For cubemaps, we use a special ld/st op to
2218 * select the face and copy the xy into the
2219 * texture register */
2220
2221 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
2222 ld.src[1] = index;
2223 ld.src_types[1] = T;
2224 ld.mask = 0x3; /* xy */
2225 ld.load_store.arg_1 = 0x20;
2226 ld.swizzle[1][3] = COMPONENT_X;
2227 emit_mir_instruction(ctx, ld);
2228
2229 /* xyzw -> xyxx */
2230 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
2231 ins.swizzle[1][3] = COMPONENT_X;
2232 } else if (needs_temp_coord) {
2233 /* mov coord_temp, coords */
2234 midgard_instruction mov = v_mov(index, coords);
2235 mov.mask = coord_mask;
2236
2237 if (flip_zw)
2238 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
2239
2240 emit_mir_instruction(ctx, mov);
2241 } else {
2242 coords = index;
2243 }
2244
2245 ins.src[1] = coords;
2246 ins.src_types[1] = T;
2247
2248 /* Texelfetch coordinates uses all four elements
2249 * (xyz/index) regardless of texture dimensionality,
2250 * which means it's necessary to zero the unused
2251 * components to keep everything happy */
2252
2253 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
2254 /* mov index.zw, #0, or generalized */
2255 midgard_instruction mov =
2256 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
2257 mov.has_constants = true;
2258 mov.mask = coord_mask ^ 0xF;
2259 emit_mir_instruction(ctx, mov);
2260 }
2261
2262 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
2263 /* Array component in w but NIR wants it in z,
2264 * but if we have a temp coord we already fixed
2265 * that up */
2266
2267 if (nr_components == 3) {
2268 ins.swizzle[1][2] = COMPONENT_Z;
2269 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
2270 } else if (nr_components == 2) {
2271 ins.swizzle[1][2] =
2272 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
2273 ins.swizzle[1][3] = COMPONENT_X;
2274 } else
2275 unreachable("Invalid texture 2D components");
2276 }
2277
2278 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
2279 /* We zeroed */
2280 ins.swizzle[1][2] = COMPONENT_Z;
2281 ins.swizzle[1][3] = COMPONENT_W;
2282 }
2283
2284 break;
2285 }
2286
2287 case nir_tex_src_bias:
2288 case nir_tex_src_lod: {
2289 /* Try as a constant if we can */
2290
2291 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
2292 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
2293 break;
2294
2295 ins.texture.lod_register = true;
2296 ins.src[2] = index;
2297 ins.src_types[2] = T;
2298
2299 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2300 ins.swizzle[2][c] = COMPONENT_X;
2301
2302 emit_explicit_constant(ctx, index, index);
2303
2304 break;
2305 };
2306
2307 case nir_tex_src_offset: {
2308 ins.texture.offset_register = true;
2309 ins.src[3] = index;
2310 ins.src_types[3] = T;
2311
2312 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2313 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
2314
2315 emit_explicit_constant(ctx, index, index);
2316 break;
2317 };
2318
2319 case nir_tex_src_comparator:
2320 case nir_tex_src_ms_index: {
2321 unsigned comp = COMPONENT_Z;
2322
2323 /* mov coord_temp.foo, coords */
2324 midgard_instruction mov = v_mov(index, coords);
2325 mov.mask = 1 << comp;
2326
2327 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
2328 mov.swizzle[1][i] = COMPONENT_X;
2329
2330 emit_mir_instruction(ctx, mov);
2331 break;
2332 }
2333
2334 default: {
2335 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
2336 assert(0);
2337 }
2338 }
2339 }
2340
2341 emit_mir_instruction(ctx, ins);
2342 }
2343
2344 static void
2345 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
2346 {
2347 switch (instr->op) {
2348 case nir_texop_tex:
2349 case nir_texop_txb:
2350 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
2351 break;
2352 case nir_texop_txl:
2353 case nir_texop_tg4:
2354 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
2355 break;
2356 case nir_texop_txf:
2357 case nir_texop_txf_ms:
2358 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
2359 break;
2360 case nir_texop_txs:
2361 emit_sysval_read(ctx, &instr->instr, 4, 0);
2362 break;
2363 default: {
2364 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
2365 assert(0);
2366 }
2367 }
2368 }
2369
2370 static void
2371 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
2372 {
2373 switch (instr->type) {
2374 case nir_jump_break: {
2375 /* Emit a branch out of the loop */
2376 struct midgard_instruction br = v_branch(false, false);
2377 br.branch.target_type = TARGET_BREAK;
2378 br.branch.target_break = ctx->current_loop_depth;
2379 emit_mir_instruction(ctx, br);
2380 break;
2381 }
2382
2383 default:
2384 DBG("Unknown jump type %d\n", instr->type);
2385 break;
2386 }
2387 }
2388
2389 static void
2390 emit_instr(compiler_context *ctx, struct nir_instr *instr)
2391 {
2392 switch (instr->type) {
2393 case nir_instr_type_load_const:
2394 emit_load_const(ctx, nir_instr_as_load_const(instr));
2395 break;
2396
2397 case nir_instr_type_intrinsic:
2398 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2399 break;
2400
2401 case nir_instr_type_alu:
2402 emit_alu(ctx, nir_instr_as_alu(instr));
2403 break;
2404
2405 case nir_instr_type_tex:
2406 emit_tex(ctx, nir_instr_as_tex(instr));
2407 break;
2408
2409 case nir_instr_type_jump:
2410 emit_jump(ctx, nir_instr_as_jump(instr));
2411 break;
2412
2413 case nir_instr_type_ssa_undef:
2414 /* Spurious */
2415 break;
2416
2417 default:
2418 DBG("Unhandled instruction type\n");
2419 break;
2420 }
2421 }
2422
2423
2424 /* ALU instructions can inline or embed constants, which decreases register
2425 * pressure and saves space. */
2426
2427 #define CONDITIONAL_ATTACH(idx) { \
2428 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2429 \
2430 if (entry) { \
2431 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2432 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2433 } \
2434 }
2435
2436 static void
2437 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2438 {
2439 mir_foreach_instr_in_block(block, alu) {
2440 /* Other instructions cannot inline constants */
2441 if (alu->type != TAG_ALU_4) continue;
2442 if (alu->compact_branch) continue;
2443
2444 /* If there is already a constant here, we can do nothing */
2445 if (alu->has_constants) continue;
2446
2447 CONDITIONAL_ATTACH(0);
2448
2449 if (!alu->has_constants) {
2450 CONDITIONAL_ATTACH(1)
2451 } else if (!alu->inline_constant) {
2452 /* Corner case: _two_ vec4 constants, for instance with a
2453 * csel. For this case, we can only use a constant
2454 * register for one, we'll have to emit a move for the
2455 * other. */
2456
2457 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2458 unsigned scratch = make_compiler_temp(ctx);
2459
2460 if (entry) {
2461 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2462 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2463
2464 /* Set the source */
2465 alu->src[1] = scratch;
2466
2467 /* Inject us -before- the last instruction which set r31 */
2468 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2469 }
2470 }
2471 }
2472 }
2473
2474 unsigned
2475 max_bitsize_for_alu(midgard_instruction *ins)
2476 {
2477 unsigned max_bitsize = 0;
2478 for (int i = 0; i < MIR_SRC_COUNT; i++) {
2479 if (ins->src[i] == ~0) continue;
2480 unsigned src_bitsize = nir_alu_type_get_type_size(ins->src_types[i]);
2481 max_bitsize = MAX2(src_bitsize, max_bitsize);
2482 }
2483 unsigned dst_bitsize = nir_alu_type_get_type_size(ins->dest_type);
2484 max_bitsize = MAX2(dst_bitsize, max_bitsize);
2485
2486 /* We don't have fp16 LUTs, so we'll want to emit code like:
2487 *
2488 * vlut.fsinr hr0, hr0
2489 *
2490 * where both input and output are 16-bit but the operation is carried
2491 * out in 32-bit
2492 */
2493
2494 switch (ins->op) {
2495 case midgard_alu_op_fsqrt:
2496 case midgard_alu_op_frcp:
2497 case midgard_alu_op_frsqrt:
2498 case midgard_alu_op_fsin:
2499 case midgard_alu_op_fcos:
2500 case midgard_alu_op_fexp2:
2501 case midgard_alu_op_flog2:
2502 max_bitsize = MAX2(max_bitsize, 32);
2503 break;
2504
2505 default:
2506 break;
2507 }
2508
2509 /* High implies computing at a higher bitsize, e.g umul_high of 32-bit
2510 * requires computing at 64-bit */
2511 if (midgard_is_integer_out_op(ins->op) && ins->outmod == midgard_outmod_int_high) {
2512 max_bitsize *= 2;
2513 assert(max_bitsize <= 64);
2514 }
2515
2516 return max_bitsize;
2517 }
2518
2519 midgard_reg_mode
2520 reg_mode_for_bitsize(unsigned bitsize)
2521 {
2522 switch (bitsize) {
2523 /* use 16 pipe for 8 since we don't support vec16 yet */
2524 case 8:
2525 case 16:
2526 return midgard_reg_mode_16;
2527 case 32:
2528 return midgard_reg_mode_32;
2529 case 64:
2530 return midgard_reg_mode_64;
2531 default:
2532 unreachable("invalid bit size");
2533 }
2534 }
2535
2536 /* Midgard supports two types of constants, embedded constants (128-bit) and
2537 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2538 * constants can be demoted to inline constants, for space savings and
2539 * sometimes a performance boost */
2540
2541 static void
2542 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2543 {
2544 mir_foreach_instr_in_block(block, ins) {
2545 if (!ins->has_constants) continue;
2546 if (ins->has_inline_constant) continue;
2547
2548 /* Blend constants must not be inlined by definition */
2549 if (ins->has_blend_constant) continue;
2550
2551 unsigned max_bitsize = max_bitsize_for_alu(ins);
2552
2553 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2554 bool is_16 = max_bitsize == 16;
2555 bool is_32 = max_bitsize == 32;
2556
2557 if (!(is_16 || is_32))
2558 continue;
2559
2560 /* src1 cannot be an inline constant due to encoding
2561 * restrictions. So, if possible we try to flip the arguments
2562 * in that case */
2563
2564 int op = ins->op;
2565
2566 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2567 alu_opcode_props[op].props & OP_COMMUTES) {
2568 mir_flip(ins);
2569 }
2570
2571 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2572 /* Component is from the swizzle. Take a nonzero component */
2573 assert(ins->mask);
2574 unsigned first_comp = ffs(ins->mask) - 1;
2575 unsigned component = ins->swizzle[1][first_comp];
2576
2577 /* Scale constant appropriately, if we can legally */
2578 int16_t scaled_constant = 0;
2579
2580 if (is_16) {
2581 scaled_constant = ins->constants.u16[component];
2582 } else if (midgard_is_integer_op(op)) {
2583 scaled_constant = ins->constants.u32[component];
2584
2585 /* Constant overflow after resize */
2586 if (scaled_constant != ins->constants.u32[component])
2587 continue;
2588 } else {
2589 float original = ins->constants.f32[component];
2590 scaled_constant = _mesa_float_to_half(original);
2591
2592 /* Check for loss of precision. If this is
2593 * mediump, we don't care, but for a highp
2594 * shader, we need to pay attention. NIR
2595 * doesn't yet tell us which mode we're in!
2596 * Practically this prevents most constants
2597 * from being inlined, sadly. */
2598
2599 float fp32 = _mesa_half_to_float(scaled_constant);
2600
2601 if (fp32 != original)
2602 continue;
2603 }
2604
2605 /* Should've been const folded */
2606 if (ins->src_abs[1] || ins->src_neg[1])
2607 continue;
2608
2609 /* Make sure that the constant is not itself a vector
2610 * by checking if all accessed values are the same. */
2611
2612 const midgard_constants *cons = &ins->constants;
2613 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2614
2615 bool is_vector = false;
2616 unsigned mask = effective_writemask(ins->op, ins->mask);
2617
2618 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2619 /* We only care if this component is actually used */
2620 if (!(mask & (1 << c)))
2621 continue;
2622
2623 uint32_t test = is_16 ?
2624 cons->u16[ins->swizzle[1][c]] :
2625 cons->u32[ins->swizzle[1][c]];
2626
2627 if (test != value) {
2628 is_vector = true;
2629 break;
2630 }
2631 }
2632
2633 if (is_vector)
2634 continue;
2635
2636 /* Get rid of the embedded constant */
2637 ins->has_constants = false;
2638 ins->src[1] = ~0;
2639 ins->has_inline_constant = true;
2640 ins->inline_constant = scaled_constant;
2641 }
2642 }
2643 }
2644
2645 /* Dead code elimination for branches at the end of a block - only one branch
2646 * per block is legal semantically */
2647
2648 static void
2649 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2650 {
2651 bool branched = false;
2652
2653 mir_foreach_instr_in_block_safe(block, ins) {
2654 if (!midgard_is_branch_unit(ins->unit)) continue;
2655
2656 if (branched)
2657 mir_remove_instruction(ins);
2658
2659 branched = true;
2660 }
2661 }
2662
2663 /* We want to force the invert on AND/OR to the second slot to legalize into
2664 * iandnot/iornot. The relevant patterns are for AND (and OR respectively)
2665 *
2666 * ~a & #b = ~a & ~(#~b)
2667 * ~a & b = b & ~a
2668 */
2669
2670 static void
2671 midgard_legalize_invert(compiler_context *ctx, midgard_block *block)
2672 {
2673 mir_foreach_instr_in_block(block, ins) {
2674 if (ins->type != TAG_ALU_4) continue;
2675
2676 if (ins->op != midgard_alu_op_iand &&
2677 ins->op != midgard_alu_op_ior) continue;
2678
2679 if (ins->src_invert[1] || !ins->src_invert[0]) continue;
2680
2681 if (ins->has_inline_constant) {
2682 /* ~(#~a) = ~(~#a) = a, so valid, and forces both
2683 * inverts on */
2684 ins->inline_constant = ~ins->inline_constant;
2685 ins->src_invert[1] = true;
2686 } else {
2687 /* Flip to the right invert order. Note
2688 * has_inline_constant false by assumption on the
2689 * branch, so flipping makes sense. */
2690 mir_flip(ins);
2691 }
2692 }
2693 }
2694
2695 static unsigned
2696 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2697 {
2698 /* Loop to ourselves */
2699 midgard_instruction *br = ctx->writeout_branch[rt];
2700 struct midgard_instruction ins = v_branch(false, false);
2701 ins.writeout = br->writeout;
2702 ins.branch.target_block = ctx->block_count - 1;
2703 ins.constants.u32[0] = br->constants.u32[0];
2704 memcpy(&ins.src_types, &br->src_types, sizeof(ins.src_types));
2705 emit_mir_instruction(ctx, ins);
2706
2707 ctx->current_block->epilogue = true;
2708 schedule_barrier(ctx);
2709 return ins.branch.target_block;
2710 }
2711
2712 static midgard_block *
2713 emit_block_init(compiler_context *ctx)
2714 {
2715 midgard_block *this_block = ctx->after_block;
2716 ctx->after_block = NULL;
2717
2718 if (!this_block)
2719 this_block = create_empty_block(ctx);
2720
2721 list_addtail(&this_block->base.link, &ctx->blocks);
2722
2723 this_block->scheduled = false;
2724 ++ctx->block_count;
2725
2726 /* Set up current block */
2727 list_inithead(&this_block->base.instructions);
2728 ctx->current_block = this_block;
2729
2730 return this_block;
2731 }
2732
2733 static midgard_block *
2734 emit_block(compiler_context *ctx, nir_block *block)
2735 {
2736 midgard_block *this_block = emit_block_init(ctx);
2737
2738 nir_foreach_instr(instr, block) {
2739 emit_instr(ctx, instr);
2740 ++ctx->instruction_count;
2741 }
2742
2743 return this_block;
2744 }
2745
2746 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2747
2748 static void
2749 emit_if(struct compiler_context *ctx, nir_if *nif)
2750 {
2751 midgard_block *before_block = ctx->current_block;
2752
2753 /* Speculatively emit the branch, but we can't fill it in until later */
2754 bool inv = false;
2755 EMIT(branch, true, true);
2756 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2757 then_branch->src[0] = mir_get_branch_cond(&nif->condition, &inv);
2758 then_branch->src_types[0] = nir_type_uint32;
2759 then_branch->branch.invert_conditional = !inv;
2760
2761 /* Emit the two subblocks. */
2762 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2763 midgard_block *end_then_block = ctx->current_block;
2764
2765 /* Emit a jump from the end of the then block to the end of the else */
2766 EMIT(branch, false, false);
2767 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2768
2769 /* Emit second block, and check if it's empty */
2770
2771 int else_idx = ctx->block_count;
2772 int count_in = ctx->instruction_count;
2773 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2774 midgard_block *end_else_block = ctx->current_block;
2775 int after_else_idx = ctx->block_count;
2776
2777 /* Now that we have the subblocks emitted, fix up the branches */
2778
2779 assert(then_block);
2780 assert(else_block);
2781
2782 if (ctx->instruction_count == count_in) {
2783 /* The else block is empty, so don't emit an exit jump */
2784 mir_remove_instruction(then_exit);
2785 then_branch->branch.target_block = after_else_idx;
2786 } else {
2787 then_branch->branch.target_block = else_idx;
2788 then_exit->branch.target_block = after_else_idx;
2789 }
2790
2791 /* Wire up the successors */
2792
2793 ctx->after_block = create_empty_block(ctx);
2794
2795 pan_block_add_successor(&before_block->base, &then_block->base);
2796 pan_block_add_successor(&before_block->base, &else_block->base);
2797
2798 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2799 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2800 }
2801
2802 static void
2803 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2804 {
2805 /* Remember where we are */
2806 midgard_block *start_block = ctx->current_block;
2807
2808 /* Allocate a loop number, growing the current inner loop depth */
2809 int loop_idx = ++ctx->current_loop_depth;
2810
2811 /* Get index from before the body so we can loop back later */
2812 int start_idx = ctx->block_count;
2813
2814 /* Emit the body itself */
2815 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2816
2817 /* Branch back to loop back */
2818 struct midgard_instruction br_back = v_branch(false, false);
2819 br_back.branch.target_block = start_idx;
2820 emit_mir_instruction(ctx, br_back);
2821
2822 /* Mark down that branch in the graph. */
2823 pan_block_add_successor(&start_block->base, &loop_block->base);
2824 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2825
2826 /* Find the index of the block about to follow us (note: we don't add
2827 * one; blocks are 0-indexed so we get a fencepost problem) */
2828 int break_block_idx = ctx->block_count;
2829
2830 /* Fix up the break statements we emitted to point to the right place,
2831 * now that we can allocate a block number for them */
2832 ctx->after_block = create_empty_block(ctx);
2833
2834 mir_foreach_block_from(ctx, start_block, _block) {
2835 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2836 if (ins->type != TAG_ALU_4) continue;
2837 if (!ins->compact_branch) continue;
2838
2839 /* We found a branch -- check the type to see if we need to do anything */
2840 if (ins->branch.target_type != TARGET_BREAK) continue;
2841
2842 /* It's a break! Check if it's our break */
2843 if (ins->branch.target_break != loop_idx) continue;
2844
2845 /* Okay, cool, we're breaking out of this loop.
2846 * Rewrite from a break to a goto */
2847
2848 ins->branch.target_type = TARGET_GOTO;
2849 ins->branch.target_block = break_block_idx;
2850
2851 pan_block_add_successor(_block, &ctx->after_block->base);
2852 }
2853 }
2854
2855 /* Now that we've finished emitting the loop, free up the depth again
2856 * so we play nice with recursion amid nested loops */
2857 --ctx->current_loop_depth;
2858
2859 /* Dump loop stats */
2860 ++ctx->loop_count;
2861 }
2862
2863 static midgard_block *
2864 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2865 {
2866 midgard_block *start_block = NULL;
2867
2868 foreach_list_typed(nir_cf_node, node, node, list) {
2869 switch (node->type) {
2870 case nir_cf_node_block: {
2871 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2872
2873 if (!start_block)
2874 start_block = block;
2875
2876 break;
2877 }
2878
2879 case nir_cf_node_if:
2880 emit_if(ctx, nir_cf_node_as_if(node));
2881 break;
2882
2883 case nir_cf_node_loop:
2884 emit_loop(ctx, nir_cf_node_as_loop(node));
2885 break;
2886
2887 case nir_cf_node_function:
2888 assert(0);
2889 break;
2890 }
2891 }
2892
2893 return start_block;
2894 }
2895
2896 /* Due to lookahead, we need to report the first tag executed in the command
2897 * stream and in branch targets. An initial block might be empty, so iterate
2898 * until we find one that 'works' */
2899
2900 unsigned
2901 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2902 {
2903 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2904
2905 mir_foreach_block_from(ctx, initial_block, _v) {
2906 midgard_block *v = (midgard_block *) _v;
2907 if (v->quadword_count) {
2908 midgard_bundle *initial_bundle =
2909 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2910
2911 return initial_bundle->tag;
2912 }
2913 }
2914
2915 /* Default to a tag 1 which will break from the shader, in case we jump
2916 * to the exit block (i.e. `return` in a compute shader) */
2917
2918 return 1;
2919 }
2920
2921 /* For each fragment writeout instruction, generate a writeout loop to
2922 * associate with it */
2923
2924 static void
2925 mir_add_writeout_loops(compiler_context *ctx)
2926 {
2927 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2928 midgard_instruction *br = ctx->writeout_branch[rt];
2929 if (!br) continue;
2930
2931 unsigned popped = br->branch.target_block;
2932 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2933 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2934 br->branch.target_type = TARGET_GOTO;
2935
2936 /* If we have more RTs, we'll need to restore back after our
2937 * loop terminates */
2938
2939 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2940 midgard_instruction uncond = v_branch(false, false);
2941 uncond.branch.target_block = popped;
2942 uncond.branch.target_type = TARGET_GOTO;
2943 emit_mir_instruction(ctx, uncond);
2944 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2945 schedule_barrier(ctx);
2946 } else {
2947 /* We're last, so we can terminate here */
2948 br->last_writeout = true;
2949 }
2950 }
2951 }
2952
2953 int
2954 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb, bool silent)
2955 {
2956 struct util_dynarray *compiled = &program->compiled;
2957
2958 midgard_debug = debug_get_option_midgard_debug();
2959
2960 /* TODO: Bound against what? */
2961 compiler_context *ctx = rzalloc(NULL, compiler_context);
2962
2963 ctx->nir = nir;
2964 ctx->stage = nir->info.stage;
2965 ctx->is_blend = is_blend;
2966 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2967 ctx->blend_input = ~0;
2968 ctx->blend_src1 = ~0;
2969 ctx->quirks = midgard_get_quirks(gpu_id);
2970
2971 /* Start off with a safe cutoff, allowing usage of all 16 work
2972 * registers. Later, we'll promote uniform reads to uniform registers
2973 * if we determine it is beneficial to do so */
2974 ctx->uniform_cutoff = 8;
2975
2976 /* Initialize at a global (not block) level hash tables */
2977
2978 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2979
2980 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2981 * (so we don't accidentally duplicate the epilogue since mesa/st has
2982 * messed with our I/O quite a bit already) */
2983
2984 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2985
2986 if (ctx->stage == MESA_SHADER_VERTEX) {
2987 NIR_PASS_V(nir, nir_lower_viewport_transform);
2988 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2989 }
2990
2991 NIR_PASS_V(nir, nir_lower_var_copies);
2992 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2993 NIR_PASS_V(nir, nir_split_var_copies);
2994 NIR_PASS_V(nir, nir_lower_var_copies);
2995 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2996 NIR_PASS_V(nir, nir_lower_var_copies);
2997 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2998
2999 unsigned pan_quirks = panfrost_get_quirks(gpu_id);
3000 NIR_PASS_V(nir, pan_lower_framebuffer,
3001 program->rt_formats, is_blend, pan_quirks);
3002
3003 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
3004 glsl_type_size, 0);
3005 NIR_PASS_V(nir, nir_lower_ssbo);
3006 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
3007
3008 /* Optimisation passes */
3009
3010 optimise_nir(nir, ctx->quirks, is_blend);
3011
3012 NIR_PASS_V(nir, midgard_nir_reorder_writeout);
3013
3014 if ((midgard_debug & MIDGARD_DBG_SHADERS) && !silent) {
3015 nir_print_shader(nir, stdout);
3016 }
3017
3018 /* Assign sysvals and counts, now that we're sure
3019 * (post-optimisation) */
3020
3021 panfrost_nir_assign_sysvals(&ctx->sysvals, ctx, nir);
3022 program->sysval_count = ctx->sysvals.sysval_count;
3023 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
3024
3025 nir_foreach_function(func, nir) {
3026 if (!func->impl)
3027 continue;
3028
3029 list_inithead(&ctx->blocks);
3030 ctx->block_count = 0;
3031 ctx->func = func;
3032 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
3033
3034 if (nir->info.outputs_read && !is_blend) {
3035 emit_block_init(ctx);
3036
3037 struct midgard_instruction wait = v_branch(false, false);
3038 wait.branch.target_type = TARGET_TILEBUF_WAIT;
3039
3040 emit_mir_instruction(ctx, wait);
3041
3042 ++ctx->instruction_count;
3043 }
3044
3045 emit_cf_list(ctx, &func->impl->body);
3046 free(ctx->already_emitted);
3047 break; /* TODO: Multi-function shaders */
3048 }
3049
3050 util_dynarray_init(compiled, NULL);
3051
3052 /* Per-block lowering before opts */
3053
3054 mir_foreach_block(ctx, _block) {
3055 midgard_block *block = (midgard_block *) _block;
3056 inline_alu_constants(ctx, block);
3057 embedded_to_inline_constant(ctx, block);
3058 }
3059 /* MIR-level optimizations */
3060
3061 bool progress = false;
3062
3063 do {
3064 progress = false;
3065 progress |= midgard_opt_dead_code_eliminate(ctx);
3066
3067 mir_foreach_block(ctx, _block) {
3068 midgard_block *block = (midgard_block *) _block;
3069 progress |= midgard_opt_copy_prop(ctx, block);
3070 progress |= midgard_opt_combine_projection(ctx, block);
3071 progress |= midgard_opt_varying_projection(ctx, block);
3072 }
3073 } while (progress);
3074
3075 mir_foreach_block(ctx, _block) {
3076 midgard_block *block = (midgard_block *) _block;
3077 midgard_lower_derivatives(ctx, block);
3078 midgard_legalize_invert(ctx, block);
3079 midgard_cull_dead_branch(ctx, block);
3080 }
3081
3082 if (ctx->stage == MESA_SHADER_FRAGMENT)
3083 mir_add_writeout_loops(ctx);
3084
3085 /* Analyze now that the code is known but before scheduling creates
3086 * pipeline registers which are harder to track */
3087 mir_analyze_helper_terminate(ctx);
3088 mir_analyze_helper_requirements(ctx);
3089
3090 /* Schedule! */
3091 midgard_schedule_program(ctx);
3092 mir_ra(ctx);
3093
3094 /* Emit flat binary from the instruction arrays. Iterate each block in
3095 * sequence. Save instruction boundaries such that lookahead tags can
3096 * be assigned easily */
3097
3098 /* Cache _all_ bundles in source order for lookahead across failed branches */
3099
3100 int bundle_count = 0;
3101 mir_foreach_block(ctx, _block) {
3102 midgard_block *block = (midgard_block *) _block;
3103 bundle_count += block->bundles.size / sizeof(midgard_bundle);
3104 }
3105 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
3106 int bundle_idx = 0;
3107 mir_foreach_block(ctx, _block) {
3108 midgard_block *block = (midgard_block *) _block;
3109 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
3110 source_order_bundles[bundle_idx++] = bundle;
3111 }
3112 }
3113
3114 int current_bundle = 0;
3115
3116 /* Midgard prefetches instruction types, so during emission we
3117 * need to lookahead. Unless this is the last instruction, in
3118 * which we return 1. */
3119
3120 mir_foreach_block(ctx, _block) {
3121 midgard_block *block = (midgard_block *) _block;
3122 mir_foreach_bundle_in_block(block, bundle) {
3123 int lookahead = 1;
3124
3125 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
3126 lookahead = source_order_bundles[current_bundle + 1]->tag;
3127
3128 emit_binary_bundle(ctx, block, bundle, compiled, lookahead);
3129 ++current_bundle;
3130 }
3131
3132 /* TODO: Free deeper */
3133 //util_dynarray_fini(&block->instructions);
3134 }
3135
3136 free(source_order_bundles);
3137
3138 /* Report the very first tag executed */
3139 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
3140
3141 /* Deal with off-by-one related to the fencepost problem */
3142 program->work_register_count = ctx->work_registers + 1;
3143 program->uniform_cutoff = ctx->uniform_cutoff;
3144
3145 program->blend_patch_offset = ctx->blend_constant_offset;
3146 program->tls_size = ctx->tls_size;
3147
3148 if ((midgard_debug & MIDGARD_DBG_SHADERS) && !silent)
3149 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
3150
3151 if ((midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) && !silent) {
3152 unsigned nr_bundles = 0, nr_ins = 0;
3153
3154 /* Count instructions and bundles */
3155
3156 mir_foreach_block(ctx, _block) {
3157 midgard_block *block = (midgard_block *) _block;
3158 nr_bundles += util_dynarray_num_elements(
3159 &block->bundles, midgard_bundle);
3160
3161 mir_foreach_bundle_in_block(block, bun)
3162 nr_ins += bun->instruction_count;
3163 }
3164
3165 /* Calculate thread count. There are certain cutoffs by
3166 * register count for thread count */
3167
3168 unsigned nr_registers = program->work_register_count;
3169
3170 unsigned nr_threads =
3171 (nr_registers <= 4) ? 4 :
3172 (nr_registers <= 8) ? 2 :
3173 1;
3174
3175 /* Dump stats */
3176
3177 fprintf(stderr, "shader%d - %s shader: "
3178 "%u inst, %u bundles, %u quadwords, "
3179 "%u registers, %u threads, %u loops, "
3180 "%u:%u spills:fills\n",
3181 SHADER_DB_COUNT++,
3182 ctx->is_blend ? "PAN_SHADER_BLEND" :
3183 gl_shader_stage_name(ctx->stage),
3184 nr_ins, nr_bundles, ctx->quadword_count,
3185 nr_registers, nr_threads,
3186 ctx->loop_count,
3187 ctx->spills, ctx->fills);
3188 }
3189
3190 ralloc_free(ctx);
3191
3192 return 0;
3193 }