2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
51 #include "midgard_quirks.h"
53 #include "disassemble.h"
55 static const struct debug_named_value debug_options
[] = {
56 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
57 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
58 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
62 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
64 unsigned SHADER_DB_COUNT
= 0;
66 int midgard_debug
= 0;
68 #define DBG(fmt, ...) \
69 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
70 fprintf(stderr, "%s:%d: "fmt, \
71 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
72 static midgard_block
*
73 create_empty_block(compiler_context
*ctx
)
75 midgard_block
*blk
= rzalloc(ctx
, midgard_block
);
77 blk
->base
.predecessors
= _mesa_set_create(blk
,
79 _mesa_key_pointer_equal
);
81 blk
->base
.name
= ctx
->block_source_count
++;
87 schedule_barrier(compiler_context
*ctx
)
89 midgard_block
*temp
= ctx
->after_block
;
90 ctx
->after_block
= create_empty_block(ctx
);
92 list_addtail(&ctx
->after_block
->base
.link
, &ctx
->blocks
);
93 list_inithead(&ctx
->after_block
->base
.instructions
);
94 pan_block_add_successor(&ctx
->current_block
->base
, &ctx
->after_block
->base
);
95 ctx
->current_block
= ctx
->after_block
;
96 ctx
->after_block
= temp
;
99 /* Helpers to generate midgard_instruction's using macro magic, since every
100 * driver seems to do it that way */
102 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
104 #define M_LOAD_STORE(name, store) \
105 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
106 midgard_instruction i = { \
107 .type = TAG_LOAD_STORE_4, \
110 .src = { ~0, ~0, ~0, ~0 }, \
111 .swizzle = SWIZZLE_IDENTITY_4, \
113 .op = midgard_op_##name, \
126 #define M_LOAD(name) M_LOAD_STORE(name, false)
127 #define M_STORE(name) M_LOAD_STORE(name, true)
129 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
130 * the corresponding Midgard source */
132 static midgard_vector_alu_src
133 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
, unsigned broadcast_count
,
134 bool half
, bool sext
)
136 /* Figure out how many components there are so we can adjust.
137 * Specifically we want to broadcast the last channel so things like
141 if (broadcast_count
&& src
) {
142 uint8_t last_component
= src
->swizzle
[broadcast_count
- 1];
144 for (unsigned c
= broadcast_count
; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
145 src
->swizzle
[c
] = last_component
;
149 midgard_vector_alu_src alu_src
= {
156 alu_src
.mod
= midgard_int_normal
;
158 /* Sign/zero-extend if needed */
162 midgard_int_sign_extend
163 : midgard_int_zero_extend
;
166 /* These should have been lowered away */
168 assert(!(src
->abs
|| src
->negate
));
171 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
177 /* load/store instructions have both 32-bit and 16-bit variants, depending on
178 * whether we are using vectors composed of highp or mediump. At the moment, we
179 * don't support half-floats -- this requires changes in other parts of the
180 * compiler -- therefore the 16-bit versions are commented out. */
182 //M_LOAD(ld_attr_16);
184 //M_LOAD(ld_vary_16);
189 M_LOAD(ld_color_buffer_32u
);
190 //M_STORE(st_vary_16);
192 M_LOAD(ld_cubemap_coords
);
193 M_LOAD(ld_compute_id
);
195 static midgard_instruction
196 v_branch(bool conditional
, bool invert
)
198 midgard_instruction ins
= {
200 .unit
= ALU_ENAB_BRANCH
,
201 .compact_branch
= true,
203 .conditional
= conditional
,
204 .invert_conditional
= invert
207 .src
= { ~0, ~0, ~0, ~0 },
213 static midgard_branch_extended
214 midgard_create_branch_extended( midgard_condition cond
,
215 midgard_jmp_writeout_op op
,
217 signed quadword_offset
)
219 /* The condition code is actually a LUT describing a function to
220 * combine multiple condition codes. However, we only support a single
221 * condition code at the moment, so we just duplicate over a bunch of
224 uint16_t duplicated_cond
=
234 midgard_branch_extended branch
= {
236 .dest_tag
= dest_tag
,
237 .offset
= quadword_offset
,
238 .cond
= duplicated_cond
245 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
247 ins
->has_constants
= true;
248 memcpy(&ins
->constants
, constants
, 16);
252 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
254 return glsl_count_attribute_slots(type
, false);
257 /* Lower fdot2 to a vector multiplication followed by channel addition */
259 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
261 if (alu
->op
!= nir_op_fdot2
)
264 b
->cursor
= nir_before_instr(&alu
->instr
);
266 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
267 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
269 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
271 nir_ssa_def
*sum
= nir_fadd(b
,
272 nir_channel(b
, product
, 0),
273 nir_channel(b
, product
, 1));
275 /* Replace the fdot2 with this sum */
276 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
280 midgard_nir_lower_fdot2(nir_shader
*shader
)
282 bool progress
= false;
284 nir_foreach_function(function
, shader
) {
285 if (!function
->impl
) continue;
288 nir_builder
*b
= &_b
;
289 nir_builder_init(b
, function
->impl
);
291 nir_foreach_block(block
, function
->impl
) {
292 nir_foreach_instr_safe(instr
, block
) {
293 if (instr
->type
!= nir_instr_type_alu
) continue;
295 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
296 midgard_nir_lower_fdot2_body(b
, alu
);
302 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
309 /* Midgard can't write depth and stencil separately. It has to happen in a
310 * single store operation containing both. Let's add a panfrost specific
311 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
315 midgard_nir_lower_zs_store(nir_shader
*nir
)
317 if (nir
->info
.stage
!= MESA_SHADER_FRAGMENT
)
320 nir_variable
*z_var
= NULL
, *s_var
= NULL
;
322 nir_foreach_variable(var
, &nir
->outputs
) {
323 if (var
->data
.location
== FRAG_RESULT_DEPTH
)
325 else if (var
->data
.location
== FRAG_RESULT_STENCIL
)
329 if (!z_var
&& !s_var
)
332 bool progress
= false;
334 nir_foreach_function(function
, nir
) {
335 if (!function
->impl
) continue;
337 nir_intrinsic_instr
*z_store
= NULL
, *s_store
= NULL
, *last_store
= NULL
;
339 nir_foreach_block(block
, function
->impl
) {
340 nir_foreach_instr_safe(instr
, block
) {
341 if (instr
->type
!= nir_instr_type_intrinsic
)
344 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
345 if (intr
->intrinsic
!= nir_intrinsic_store_output
)
348 if (z_var
&& nir_intrinsic_base(intr
) == z_var
->data
.driver_location
) {
354 if (s_var
&& nir_intrinsic_base(intr
) == s_var
->data
.driver_location
) {
362 if (!z_store
&& !s_store
) continue;
365 nir_builder_init(&b
, function
->impl
);
367 b
.cursor
= nir_before_instr(&last_store
->instr
);
369 nir_ssa_def
*zs_store_src
;
371 if (z_store
&& s_store
) {
372 nir_ssa_def
*srcs
[2] = {
373 nir_ssa_for_src(&b
, z_store
->src
[0], 1),
374 nir_ssa_for_src(&b
, s_store
->src
[0], 1),
377 zs_store_src
= nir_vec(&b
, srcs
, 2);
379 zs_store_src
= nir_ssa_for_src(&b
, last_store
->src
[0], 1);
382 nir_intrinsic_instr
*zs_store
;
384 zs_store
= nir_intrinsic_instr_create(b
.shader
,
385 nir_intrinsic_store_zs_output_pan
);
386 zs_store
->src
[0] = nir_src_for_ssa(zs_store_src
);
387 zs_store
->num_components
= z_store
&& s_store
? 2 : 1;
388 nir_intrinsic_set_component(zs_store
, z_store
? 0 : 1);
390 /* Replace the Z and S store by a ZS store */
391 nir_builder_instr_insert(&b
, &zs_store
->instr
);
394 nir_instr_remove(&z_store
->instr
);
397 nir_instr_remove(&s_store
->instr
);
399 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
406 /* Flushes undefined values to zero */
409 optimise_nir(nir_shader
*nir
, unsigned quirks
)
412 unsigned lower_flrp
=
413 (nir
->options
->lower_flrp16
? 16 : 0) |
414 (nir
->options
->lower_flrp32
? 32 : 0) |
415 (nir
->options
->lower_flrp64
? 64 : 0);
417 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
418 NIR_PASS(progress
, nir
, nir_lower_idiv
, nir_lower_idiv_fast
);
420 nir_lower_tex_options lower_tex_options
= {
421 .lower_txs_lod
= true,
423 .lower_tex_without_implicit_lod
=
424 (quirks
& MIDGARD_EXPLICIT_LOD
),
426 /* TODO: we have native gradient.. */
430 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
432 /* Must lower fdot2 after tex is lowered */
433 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
435 /* T720 is broken. */
437 if (quirks
& MIDGARD_BROKEN_LOD
)
438 NIR_PASS_V(nir
, midgard_nir_lod_errata
);
443 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
444 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
446 NIR_PASS(progress
, nir
, nir_copy_prop
);
447 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
448 NIR_PASS(progress
, nir
, nir_opt_dce
);
449 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
450 NIR_PASS(progress
, nir
, nir_opt_cse
);
451 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
452 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
453 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
455 if (lower_flrp
!= 0) {
456 bool lower_flrp_progress
= false;
457 NIR_PASS(lower_flrp_progress
,
461 false /* always_precise */,
462 nir
->options
->lower_ffma
);
463 if (lower_flrp_progress
) {
464 NIR_PASS(progress
, nir
,
465 nir_opt_constant_folding
);
469 /* Nothing should rematerialize any flrps, so we only
470 * need to do this lowering once.
475 NIR_PASS(progress
, nir
, nir_opt_undef
);
476 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
478 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
481 nir_var_function_temp
);
483 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
486 /* Must be run at the end to prevent creation of fsin/fcos ops */
487 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
492 NIR_PASS(progress
, nir
, nir_opt_dce
);
493 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
494 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
495 NIR_PASS(progress
, nir
, nir_copy_prop
);
498 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
500 /* We implement booleans as 32-bit 0/~0 */
501 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
503 /* Now that booleans are lowered, we can run out late opts */
504 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
506 /* Lower mods for float ops only. Integer ops don't support modifiers
507 * (saturate doesn't make sense on integers, neg/abs require dedicated
510 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
511 NIR_PASS(progress
, nir
, nir_copy_prop
);
512 NIR_PASS(progress
, nir
, nir_opt_dce
);
514 /* Take us out of SSA */
515 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
516 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
518 /* We are a vector architecture; write combine where possible */
519 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
520 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
522 NIR_PASS(progress
, nir
, nir_opt_dce
);
525 /* Do not actually emit a load; instead, cache the constant for inlining */
528 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
530 nir_ssa_def def
= instr
->def
;
532 midgard_constants
*consts
= rzalloc(NULL
, midgard_constants
);
534 assert(instr
->def
.num_components
* instr
->def
.bit_size
<= sizeof(*consts
) * 8);
536 #define RAW_CONST_COPY(bits) \
537 nir_const_value_to_array(consts->u##bits, instr->value, \
538 instr->def.num_components, u##bits)
540 switch (instr
->def
.bit_size
) {
554 unreachable("Invalid bit_size for load_const instruction\n");
557 /* Shifted for SSA, +1 for off-by-one */
558 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (def
.index
<< 1) + 1, consts
);
561 /* Normally constants are embedded implicitly, but for I/O and such we have to
562 * explicitly emit a move with the constant source */
565 emit_explicit_constant(compiler_context
*ctx
, unsigned node
, unsigned to
)
567 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, node
+ 1);
569 if (constant_value
) {
570 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), to
);
571 attach_constants(ctx
, &ins
, constant_value
, node
+ 1);
572 emit_mir_instruction(ctx
, ins
);
577 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
579 unsigned comp
= src
->swizzle
[0];
581 for (unsigned c
= 1; c
< nr_components
; ++c
) {
582 if (src
->swizzle
[c
] != comp
)
589 #define ALU_CASE(nir, _op) \
591 op = midgard_alu_op_##_op; \
592 assert(src_bitsize == dst_bitsize); \
595 #define ALU_CASE_BCAST(nir, _op, count) \
597 op = midgard_alu_op_##_op; \
598 broadcast_swizzle = count; \
599 assert(src_bitsize == dst_bitsize); \
602 nir_is_fzero_constant(nir_src src
)
604 if (!nir_src_is_const(src
))
607 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
608 if (nir_src_comp_as_float(src
, c
) != 0.0)
615 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
616 * special treatment override this anyway. */
618 static midgard_reg_mode
619 reg_mode_for_nir(nir_alu_instr
*instr
)
621 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
623 switch (src_bitsize
) {
625 return midgard_reg_mode_8
;
627 return midgard_reg_mode_16
;
629 return midgard_reg_mode_32
;
631 return midgard_reg_mode_64
;
633 unreachable("Invalid bit size");
638 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
640 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
641 * is handled elsewhere */
643 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddy
) {
644 midgard_emit_derivatives(ctx
, instr
);
648 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
650 unsigned dest
= nir_dest_index(&instr
->dest
.dest
);
651 unsigned nr_components
= nir_dest_num_components(instr
->dest
.dest
);
652 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
654 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
655 * supported. A few do not and are commented for now. Also, there are a
656 * number of NIR ops which Midgard does not support and need to be
657 * lowered, also TODO. This switch block emits the opcode and calling
658 * convention of the Midgard instruction; actual packing is done in
663 /* Number of components valid to check for the instruction (the rest
664 * will be forced to the last), or 0 to use as-is. Relevant as
665 * ball-type instructions have a channel count in NIR but are all vec4
668 unsigned broadcast_swizzle
= 0;
670 /* What register mode should we operate in? */
671 midgard_reg_mode reg_mode
=
672 reg_mode_for_nir(instr
);
674 /* Do we need a destination override? Used for inline
677 midgard_dest_override dest_override
=
678 midgard_dest_override_none
;
680 /* Should we use a smaller respective source and sign-extend? */
682 bool half_1
= false, sext_1
= false;
683 bool half_2
= false, sext_2
= false;
685 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
686 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
689 ALU_CASE(fadd
, fadd
);
690 ALU_CASE(fmul
, fmul
);
691 ALU_CASE(fmin
, fmin
);
692 ALU_CASE(fmax
, fmax
);
693 ALU_CASE(imin
, imin
);
694 ALU_CASE(imax
, imax
);
695 ALU_CASE(umin
, umin
);
696 ALU_CASE(umax
, umax
);
697 ALU_CASE(ffloor
, ffloor
);
698 ALU_CASE(fround_even
, froundeven
);
699 ALU_CASE(ftrunc
, ftrunc
);
700 ALU_CASE(fceil
, fceil
);
701 ALU_CASE(fdot3
, fdot3
);
702 ALU_CASE(fdot4
, fdot4
);
703 ALU_CASE(iadd
, iadd
);
704 ALU_CASE(isub
, isub
);
705 ALU_CASE(imul
, imul
);
707 /* Zero shoved as second-arg */
708 ALU_CASE(iabs
, iabsdiff
);
712 ALU_CASE(feq32
, feq
);
713 ALU_CASE(fne32
, fne
);
714 ALU_CASE(flt32
, flt
);
715 ALU_CASE(ieq32
, ieq
);
716 ALU_CASE(ine32
, ine
);
717 ALU_CASE(ilt32
, ilt
);
718 ALU_CASE(ult32
, ult
);
720 /* We don't have a native b2f32 instruction. Instead, like many
721 * GPUs, we exploit booleans as 0/~0 for false/true, and
722 * correspondingly AND
723 * by 1.0 to do the type conversion. For the moment, prime us
726 * iand [whatever], #0
728 * At the end of emit_alu (as MIR), we'll fix-up the constant
731 ALU_CASE(b2f32
, iand
);
732 ALU_CASE(b2i32
, iand
);
734 /* Likewise, we don't have a dedicated f2b32 instruction, but
735 * we can do a "not equal to 0.0" test. */
737 ALU_CASE(f2b32
, fne
);
738 ALU_CASE(i2b32
, ine
);
740 ALU_CASE(frcp
, frcp
);
741 ALU_CASE(frsq
, frsqrt
);
742 ALU_CASE(fsqrt
, fsqrt
);
743 ALU_CASE(fexp2
, fexp2
);
744 ALU_CASE(flog2
, flog2
);
746 ALU_CASE(f2i64
, f2i_rtz
);
747 ALU_CASE(f2u64
, f2u_rtz
);
748 ALU_CASE(i2f64
, i2f_rtz
);
749 ALU_CASE(u2f64
, u2f_rtz
);
751 ALU_CASE(f2i32
, f2i_rtz
);
752 ALU_CASE(f2u32
, f2u_rtz
);
753 ALU_CASE(i2f32
, i2f_rtz
);
754 ALU_CASE(u2f32
, u2f_rtz
);
756 ALU_CASE(f2i16
, f2i_rtz
);
757 ALU_CASE(f2u16
, f2u_rtz
);
758 ALU_CASE(i2f16
, i2f_rtz
);
759 ALU_CASE(u2f16
, u2f_rtz
);
761 ALU_CASE(fsin
, fsin
);
762 ALU_CASE(fcos
, fcos
);
764 /* We'll set invert */
765 ALU_CASE(inot
, imov
);
766 ALU_CASE(iand
, iand
);
768 ALU_CASE(ixor
, ixor
);
769 ALU_CASE(ishl
, ishl
);
770 ALU_CASE(ishr
, iasr
);
771 ALU_CASE(ushr
, ilsr
);
773 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
774 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
775 ALU_CASE(b32all_fequal4
, fball_eq
);
777 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
778 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
779 ALU_CASE(b32any_fnequal4
, fbany_neq
);
781 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
782 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
783 ALU_CASE(b32all_iequal4
, iball_eq
);
785 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
786 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
787 ALU_CASE(b32any_inequal4
, ibany_neq
);
789 /* Source mods will be shoved in later */
790 ALU_CASE(fabs
, fmov
);
791 ALU_CASE(fneg
, fmov
);
792 ALU_CASE(fsat
, fmov
);
794 /* For size conversion, we use a move. Ideally though we would squash
795 * these ops together; maybe that has to happen after in NIR as part of
796 * propagation...? An earlier algebraic pass ensured we step down by
797 * only / exactly one size. If stepping down, we use a dest override to
798 * reduce the size; if stepping up, we use a larger-sized move with a
799 * half source and a sign/zero-extension modifier */
805 /* If we end up upscale, we'll need a sign-extend on the
806 * operand (the second argument) */
817 if (instr
->op
== nir_op_f2f16
|| instr
->op
== nir_op_f2f32
||
818 instr
->op
== nir_op_f2f64
)
819 op
= midgard_alu_op_fmov
;
821 op
= midgard_alu_op_imov
;
823 if (dst_bitsize
== (src_bitsize
* 2)) {
827 /* Use a greater register mode */
829 } else if (src_bitsize
== (dst_bitsize
* 2)) {
830 /* Converting down */
831 dest_override
= midgard_dest_override_lower
;
837 /* For greater-or-equal, we lower to less-or-equal and flip the
845 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
846 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
847 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
848 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
851 /* Swap via temporary */
852 nir_alu_src temp
= instr
->src
[1];
853 instr
->src
[1] = instr
->src
[0];
854 instr
->src
[0] = temp
;
859 case nir_op_b32csel
: {
860 /* Midgard features both fcsel and icsel, depending on
861 * the type of the arguments/output. However, as long
862 * as we're careful we can _always_ use icsel and
863 * _never_ need fcsel, since the latter does additional
864 * floating-point-specific processing whereas the
865 * former just moves bits on the wire. It's not obvious
866 * why these are separate opcodes, save for the ability
867 * to do things like sat/pos/abs/neg for free */
869 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
870 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
872 /* The condition is the first argument; move the other
873 * arguments up one to be a binary instruction for
874 * Midgard with the condition last */
876 nir_alu_src temp
= instr
->src
[2];
878 instr
->src
[2] = instr
->src
[0];
879 instr
->src
[0] = instr
->src
[1];
880 instr
->src
[1] = temp
;
886 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
891 /* Midgard can perform certain modifiers on output of an ALU op */
894 if (midgard_is_integer_out_op(op
)) {
895 outmod
= midgard_outmod_int_wrap
;
897 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
898 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
901 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
903 if (instr
->op
== nir_op_fmax
) {
904 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
905 op
= midgard_alu_op_fmov
;
907 outmod
= midgard_outmod_pos
;
908 instr
->src
[0] = instr
->src
[1];
909 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
910 op
= midgard_alu_op_fmov
;
912 outmod
= midgard_outmod_pos
;
916 /* Fetch unit, quirks, etc information */
917 unsigned opcode_props
= alu_opcode_props
[op
].props
;
918 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
920 /* src0 will always exist afaik, but src1 will not for 1-argument
921 * instructions. The latter can only be fetched if the instruction
922 * needs it, or else we may segfault. */
924 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
925 unsigned src1
= nr_inputs
>= 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : ~0;
926 unsigned src2
= nr_inputs
== 3 ? nir_alu_src_index(ctx
, &instr
->src
[2]) : ~0;
927 assert(nr_inputs
<= 3);
929 /* Rather than use the instruction generation helpers, we do it
930 * ourselves here to avoid the mess */
932 midgard_instruction ins
= {
935 quirk_flipped_r24
? ~0 : src0
,
936 quirk_flipped_r24
? src0
: src1
,
943 nir_alu_src
*nirmods
[3] = { NULL
};
945 if (nr_inputs
>= 2) {
946 nirmods
[0] = &instr
->src
[0];
947 nirmods
[1] = &instr
->src
[1];
948 } else if (nr_inputs
== 1) {
949 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
955 nirmods
[2] = &instr
->src
[2];
957 /* These were lowered to a move, so apply the corresponding mod */
959 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
960 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
962 if (instr
->op
== nir_op_fneg
)
963 s
->negate
= !s
->negate
;
965 if (instr
->op
== nir_op_fabs
)
969 bool is_int
= midgard_is_integer_op(op
);
971 ins
.mask
= mask_of(nr_components
);
973 midgard_vector_alu alu
= {
975 .reg_mode
= reg_mode
,
976 .dest_override
= dest_override
,
979 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, sext_1
)),
980 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
, broadcast_swizzle
, half_2
, sext_2
)),
983 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
986 ins
.mask
&= instr
->dest
.write_mask
;
988 for (unsigned m
= 0; m
< 3; ++m
) {
992 for (unsigned c
= 0; c
< NIR_MAX_VEC_COMPONENTS
; ++c
)
993 ins
.swizzle
[m
][c
] = nirmods
[m
]->swizzle
[c
];
995 /* Replicate. TODO: remove when vec16 lands */
996 for (unsigned c
= NIR_MAX_VEC_COMPONENTS
; c
< MIR_VEC_COMPONENTS
; ++c
)
997 ins
.swizzle
[m
][c
] = nirmods
[m
]->swizzle
[NIR_MAX_VEC_COMPONENTS
- 1];
1000 if (nr_inputs
== 3) {
1001 /* Conditions can't have mods */
1002 assert(!nirmods
[2]->abs
);
1003 assert(!nirmods
[2]->negate
);
1008 /* Late fixup for emulated instructions */
1010 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1011 /* Presently, our second argument is an inline #0 constant.
1012 * Switch over to an embedded 1.0 constant (that can't fit
1013 * inline, since we're 32-bit, not 16-bit like the inline
1016 ins
.has_inline_constant
= false;
1017 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1018 ins
.has_constants
= true;
1020 if (instr
->op
== nir_op_b2f32
)
1021 ins
.constants
.f32
[0] = 1.0f
;
1023 ins
.constants
.i32
[0] = 1;
1025 for (unsigned c
= 0; c
< 16; ++c
)
1026 ins
.swizzle
[1][c
] = 0;
1027 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1028 /* Lots of instructions need a 0 plonked in */
1029 ins
.has_inline_constant
= false;
1030 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1031 ins
.has_constants
= true;
1032 ins
.constants
.u32
[0] = 0;
1034 for (unsigned c
= 0; c
< 16; ++c
)
1035 ins
.swizzle
[1][c
] = 0;
1036 } else if (instr
->op
== nir_op_inot
) {
1040 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1041 /* To avoid duplicating the lookup tables (probably), true LUT
1042 * instructions can only operate as if they were scalars. Lower
1043 * them here by changing the component. */
1045 unsigned orig_mask
= ins
.mask
;
1047 for (int i
= 0; i
< nr_components
; ++i
) {
1048 /* Mask the associated component, dropping the
1049 * instruction if needed */
1052 ins
.mask
&= orig_mask
;
1057 for (unsigned j
= 0; j
< MIR_VEC_COMPONENTS
; ++j
)
1058 ins
.swizzle
[0][j
] = nirmods
[0]->swizzle
[i
]; /* Pull from the correct component */
1060 emit_mir_instruction(ctx
, ins
);
1063 emit_mir_instruction(ctx
, ins
);
1070 mir_set_intr_mask(nir_instr
*instr
, midgard_instruction
*ins
, bool is_read
)
1072 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
1073 unsigned nir_mask
= 0;
1077 nir_mask
= mask_of(nir_intrinsic_dest_components(intr
));
1078 dsize
= nir_dest_bit_size(intr
->dest
);
1080 nir_mask
= nir_intrinsic_write_mask(intr
);
1084 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1085 unsigned bytemask
= pan_to_bytemask(dsize
, nir_mask
);
1086 mir_set_bytemask(ins
, bytemask
);
1089 ins
->load_64
= true;
1092 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1093 * optimized) versions of UBO #0 */
1095 static midgard_instruction
*
1097 compiler_context
*ctx
,
1101 nir_src
*indirect_offset
,
1102 unsigned indirect_shift
,
1105 /* TODO: half-floats */
1107 midgard_instruction ins
= m_ld_ubo_int4(dest
, 0);
1108 ins
.constants
.u32
[0] = offset
;
1110 if (instr
->type
== nir_instr_type_intrinsic
)
1111 mir_set_intr_mask(instr
, &ins
, true);
1113 if (indirect_offset
) {
1114 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1115 ins
.load_store
.arg_2
= (indirect_shift
<< 5);
1117 ins
.load_store
.arg_2
= 0x1E;
1120 ins
.load_store
.arg_1
= index
;
1122 return emit_mir_instruction(ctx
, ins
);
1125 /* Globals are like UBOs if you squint. And shared memory is like globals if
1126 * you squint even harder */
1130 compiler_context
*ctx
,
1139 midgard_instruction ins
;
1142 ins
= m_ld_int4(srcdest
, 0);
1144 ins
= m_st_int4(srcdest
, 0);
1146 mir_set_offset(ctx
, &ins
, offset
, is_shared
);
1147 mir_set_intr_mask(instr
, &ins
, is_read
);
1149 emit_mir_instruction(ctx
, ins
);
1154 compiler_context
*ctx
,
1155 unsigned dest
, unsigned offset
,
1156 unsigned nr_comp
, unsigned component
,
1157 nir_src
*indirect_offset
, nir_alu_type type
, bool flat
)
1159 /* XXX: Half-floats? */
1160 /* TODO: swizzle, mask */
1162 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1163 ins
.mask
= mask_of(nr_comp
);
1165 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
.swizzle
[0]); ++i
)
1166 ins
.swizzle
[0][i
] = MIN2(i
+ component
, COMPONENT_W
);
1168 midgard_varying_parameter p
= {
1170 .interpolation
= midgard_interp_default
,
1175 memcpy(&u
, &p
, sizeof(p
));
1176 ins
.load_store
.varying_parameters
= u
;
1178 if (indirect_offset
)
1179 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1181 ins
.load_store
.arg_2
= 0x1E;
1183 ins
.load_store
.arg_1
= 0x9E;
1185 /* Use the type appropriate load */
1189 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1192 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1194 case nir_type_float
:
1195 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1198 unreachable("Attempted to load unknown type");
1202 emit_mir_instruction(ctx
, ins
);
1207 compiler_context
*ctx
,
1208 unsigned dest
, unsigned offset
,
1209 unsigned nr_comp
, nir_alu_type t
)
1211 midgard_instruction ins
= m_ld_attr_32(dest
, offset
);
1212 ins
.load_store
.arg_1
= 0x1E;
1213 ins
.load_store
.arg_2
= 0x1E;
1214 ins
.mask
= mask_of(nr_comp
);
1216 /* Use the type appropriate load */
1220 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1223 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1225 case nir_type_float
:
1226 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1229 unreachable("Attempted to load unknown type");
1233 emit_mir_instruction(ctx
, ins
);
1237 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
,
1238 unsigned nr_components
, unsigned offset
)
1242 /* Figure out which uniform this is */
1243 int sysval
= panfrost_sysval_for_instr(instr
, &nir_dest
);
1244 void *val
= _mesa_hash_table_u64_search(ctx
->sysvals
.sysval_to_id
, sysval
);
1246 unsigned dest
= nir_dest_index(&nir_dest
);
1248 /* Sysvals are prefix uniforms */
1249 unsigned uniform
= ((uintptr_t) val
) - 1;
1251 /* Emit the read itself -- this is never indirect */
1252 midgard_instruction
*ins
=
1253 emit_ubo_read(ctx
, instr
, dest
, (uniform
* 16) + offset
, NULL
, 0, 0);
1255 ins
->mask
= mask_of(nr_components
);
1259 compute_builtin_arg(nir_op op
)
1262 case nir_intrinsic_load_work_group_id
:
1264 case nir_intrinsic_load_local_invocation_id
:
1267 unreachable("Invalid compute paramater loaded");
1272 emit_fragment_store(compiler_context
*ctx
, unsigned src
, enum midgard_rt_id rt
)
1274 assert(rt
< ARRAY_SIZE(ctx
->writeout_branch
));
1276 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
1280 emit_explicit_constant(ctx
, src
, src
);
1282 struct midgard_instruction ins
=
1283 v_branch(false, false);
1285 ins
.writeout
= true;
1287 /* Add dependencies */
1289 ins
.constants
.u32
[0] = rt
== MIDGARD_ZS_RT
?
1290 0xFF : (rt
- MIDGARD_COLOR_RT0
) * 0x100;
1292 /* Emit the branch */
1293 br
= emit_mir_instruction(ctx
, ins
);
1294 schedule_barrier(ctx
);
1295 ctx
->writeout_branch
[rt
] = br
;
1297 /* Push our current location = current block count - 1 = where we'll
1298 * jump to. Maybe a bit too clever for my own good */
1300 br
->branch
.target_block
= ctx
->block_count
- 1;
1304 emit_compute_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1306 unsigned reg
= nir_dest_index(&instr
->dest
);
1307 midgard_instruction ins
= m_ld_compute_id(reg
, 0);
1308 ins
.mask
= mask_of(3);
1309 ins
.swizzle
[0][3] = COMPONENT_X
; /* xyzx */
1310 ins
.load_store
.arg_1
= compute_builtin_arg(instr
->intrinsic
);
1311 emit_mir_instruction(ctx
, ins
);
1315 vertex_builtin_arg(nir_op op
)
1318 case nir_intrinsic_load_vertex_id
:
1319 return PAN_VERTEX_ID
;
1320 case nir_intrinsic_load_instance_id
:
1321 return PAN_INSTANCE_ID
;
1323 unreachable("Invalid vertex builtin");
1328 emit_vertex_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1330 unsigned reg
= nir_dest_index(&instr
->dest
);
1331 emit_attr_read(ctx
, reg
, vertex_builtin_arg(instr
->intrinsic
), 1, nir_type_int
);
1335 emit_control_barrier(compiler_context
*ctx
)
1337 midgard_instruction ins
= {
1338 .type
= TAG_TEXTURE_4
,
1339 .src
= { ~0, ~0, ~0, ~0 },
1341 .op
= TEXTURE_OP_BARRIER
,
1343 /* TODO: optimize */
1344 .barrier_buffer
= 1,
1349 emit_mir_instruction(ctx
, ins
);
1352 static const nir_variable
*
1353 search_var(struct exec_list
*vars
, unsigned driver_loc
)
1355 nir_foreach_variable(var
, vars
) {
1356 if (var
->data
.driver_location
== driver_loc
)
1364 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1366 unsigned offset
= 0, reg
;
1368 switch (instr
->intrinsic
) {
1369 case nir_intrinsic_discard_if
:
1370 case nir_intrinsic_discard
: {
1371 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1372 struct midgard_instruction discard
= v_branch(conditional
, false);
1373 discard
.branch
.target_type
= TARGET_DISCARD
;
1376 discard
.src
[0] = nir_src_index(ctx
, &instr
->src
[0]);
1378 emit_mir_instruction(ctx
, discard
);
1379 schedule_barrier(ctx
);
1384 case nir_intrinsic_load_uniform
:
1385 case nir_intrinsic_load_ubo
:
1386 case nir_intrinsic_load_global
:
1387 case nir_intrinsic_load_shared
:
1388 case nir_intrinsic_load_input
:
1389 case nir_intrinsic_load_interpolated_input
: {
1390 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1391 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1392 bool is_global
= instr
->intrinsic
== nir_intrinsic_load_global
;
1393 bool is_shared
= instr
->intrinsic
== nir_intrinsic_load_shared
;
1394 bool is_flat
= instr
->intrinsic
== nir_intrinsic_load_input
;
1395 bool is_interp
= instr
->intrinsic
== nir_intrinsic_load_interpolated_input
;
1397 /* Get the base type of the intrinsic */
1398 /* TODO: Infer type? Does it matter? */
1400 (is_ubo
|| is_global
|| is_shared
) ? nir_type_uint
:
1401 (is_interp
) ? nir_type_float
:
1402 nir_intrinsic_type(instr
);
1404 t
= nir_alu_type_get_base_type(t
);
1406 if (!(is_ubo
|| is_global
)) {
1407 offset
= nir_intrinsic_base(instr
);
1410 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1412 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1414 bool direct
= nir_src_is_const(*src_offset
);
1415 nir_src
*indirect_offset
= direct
? NULL
: src_offset
;
1418 offset
+= nir_src_as_uint(*src_offset
);
1420 /* We may need to apply a fractional offset */
1421 int component
= (is_flat
|| is_interp
) ?
1422 nir_intrinsic_component(instr
) : 0;
1423 reg
= nir_dest_index(&instr
->dest
);
1425 if (is_uniform
&& !ctx
->is_blend
) {
1426 emit_ubo_read(ctx
, &instr
->instr
, reg
, (ctx
->sysvals
.sysval_count
+ offset
) * 16, indirect_offset
, 4, 0);
1427 } else if (is_ubo
) {
1428 nir_src index
= instr
->src
[0];
1430 /* TODO: Is indirect block number possible? */
1431 assert(nir_src_is_const(index
));
1433 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1434 emit_ubo_read(ctx
, &instr
->instr
, reg
, offset
, indirect_offset
, 0, uindex
);
1435 } else if (is_global
|| is_shared
) {
1436 emit_global(ctx
, &instr
->instr
, true, reg
, src_offset
, is_shared
);
1437 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1438 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, indirect_offset
, t
, is_flat
);
1439 } else if (ctx
->is_blend
) {
1440 /* For blend shaders, load the input color, which is
1441 * preloaded to r0 */
1443 midgard_instruction move
= v_mov(SSA_FIXED_REGISTER(0), reg
);
1444 emit_mir_instruction(ctx
, move
);
1445 schedule_barrier(ctx
);
1446 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1447 emit_attr_read(ctx
, reg
, offset
, nr_comp
, t
);
1449 DBG("Unknown load\n");
1456 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1457 case nir_intrinsic_load_barycentric_pixel
:
1458 case nir_intrinsic_load_barycentric_centroid
:
1461 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1463 case nir_intrinsic_load_raw_output_pan
:
1464 case nir_intrinsic_load_output_u8_as_fp16_pan
:
1465 reg
= nir_dest_index(&instr
->dest
);
1466 assert(ctx
->is_blend
);
1468 /* T720 and below use different blend opcodes with slightly
1469 * different semantics than T760 and up */
1471 midgard_instruction ld
= m_ld_color_buffer_32u(reg
, 0);
1472 bool old_blend
= ctx
->quirks
& MIDGARD_OLD_BLEND
;
1474 if (instr
->intrinsic
== nir_intrinsic_load_output_u8_as_fp16_pan
) {
1475 ld
.load_store
.op
= old_blend
?
1476 midgard_op_ld_color_buffer_u8_as_fp16_old
:
1477 midgard_op_ld_color_buffer_u8_as_fp16
;
1480 ld
.load_store
.address
= 1;
1481 ld
.load_store
.arg_2
= 0x1E;
1484 for (unsigned c
= 2; c
< 16; ++c
)
1485 ld
.swizzle
[0][c
] = 0;
1488 emit_mir_instruction(ctx
, ld
);
1491 case nir_intrinsic_load_blend_const_color_rgba
: {
1492 assert(ctx
->is_blend
);
1493 reg
= nir_dest_index(&instr
->dest
);
1495 /* Blend constants are embedded directly in the shader and
1496 * patched in, so we use some magic routing */
1498 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), reg
);
1499 ins
.has_constants
= true;
1500 ins
.has_blend_constant
= true;
1501 emit_mir_instruction(ctx
, ins
);
1505 case nir_intrinsic_store_zs_output_pan
: {
1506 assert(ctx
->stage
== MESA_SHADER_FRAGMENT
);
1507 emit_fragment_store(ctx
, nir_src_index(ctx
, &instr
->src
[0]),
1510 midgard_instruction
*br
= ctx
->writeout_branch
[MIDGARD_ZS_RT
];
1512 if (!nir_intrinsic_component(instr
))
1513 br
->writeout_depth
= true;
1514 if (nir_intrinsic_component(instr
) ||
1515 instr
->num_components
)
1516 br
->writeout_stencil
= true;
1517 assert(br
->writeout_depth
| br
->writeout_stencil
);
1521 case nir_intrinsic_store_output
:
1522 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1524 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1526 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1528 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1529 const nir_variable
*var
;
1530 enum midgard_rt_id rt
;
1532 var
= search_var(&ctx
->nir
->outputs
,
1533 nir_intrinsic_base(instr
));
1535 if (var
->data
.location
== FRAG_RESULT_COLOR
)
1536 rt
= MIDGARD_COLOR_RT0
;
1537 else if (var
->data
.location
>= FRAG_RESULT_DATA0
)
1538 rt
= MIDGARD_COLOR_RT0
+ var
->data
.location
-
1543 emit_fragment_store(ctx
, reg
, rt
);
1544 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1545 /* We should have been vectorized, though we don't
1546 * currently check that st_vary is emitted only once
1547 * per slot (this is relevant, since there's not a mask
1548 * parameter available on the store [set to 0 by the
1549 * blob]). We do respect the component by adjusting the
1550 * swizzle. If this is a constant source, we'll need to
1551 * emit that explicitly. */
1553 emit_explicit_constant(ctx
, reg
, reg
);
1555 unsigned dst_component
= nir_intrinsic_component(instr
);
1556 unsigned nr_comp
= nir_src_num_components(instr
->src
[0]);
1558 midgard_instruction st
= m_st_vary_32(reg
, offset
);
1559 st
.load_store
.arg_1
= 0x9E;
1560 st
.load_store
.arg_2
= 0x1E;
1562 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr
))) {
1565 st
.load_store
.op
= midgard_op_st_vary_32u
;
1568 st
.load_store
.op
= midgard_op_st_vary_32i
;
1570 case nir_type_float
:
1571 st
.load_store
.op
= midgard_op_st_vary_32
;
1574 unreachable("Attempted to store unknown type");
1578 /* nir_intrinsic_component(store_intr) encodes the
1579 * destination component start. Source component offset
1580 * adjustment is taken care of in
1581 * install_registers_instr(), when offset_swizzle() is
1584 unsigned src_component
= COMPONENT_X
;
1586 assert(nr_comp
> 0);
1587 for (unsigned i
= 0; i
< ARRAY_SIZE(st
.swizzle
); ++i
) {
1588 st
.swizzle
[0][i
] = src_component
;
1589 if (i
>= dst_component
&& i
< dst_component
+ nr_comp
- 1)
1593 emit_mir_instruction(ctx
, st
);
1595 DBG("Unknown store\n");
1601 /* Special case of store_output for lowered blend shaders */
1602 case nir_intrinsic_store_raw_output_pan
:
1603 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1604 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1606 if (ctx
->quirks
& MIDGARD_OLD_BLEND
) {
1607 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1608 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1611 * imov r0.xyzw, r0.xxxx
1614 unsigned expanded
= make_compiler_temp(ctx
);
1616 midgard_instruction splatter
= v_mov(reg
, expanded
);
1618 for (unsigned c
= 0; c
< 16; ++c
)
1619 splatter
.swizzle
[1][c
] = 0;
1621 emit_mir_instruction(ctx
, splatter
);
1622 emit_fragment_store(ctx
, expanded
, ctx
->blend_rt
);
1624 emit_fragment_store(ctx
, reg
, ctx
->blend_rt
);
1628 case nir_intrinsic_store_global
:
1629 case nir_intrinsic_store_shared
:
1630 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1631 emit_explicit_constant(ctx
, reg
, reg
);
1633 emit_global(ctx
, &instr
->instr
, false, reg
, &instr
->src
[1], instr
->intrinsic
== nir_intrinsic_store_shared
);
1636 case nir_intrinsic_load_ssbo_address
:
1637 emit_sysval_read(ctx
, &instr
->instr
, 1, 0);
1640 case nir_intrinsic_get_buffer_size
:
1641 emit_sysval_read(ctx
, &instr
->instr
, 1, 8);
1644 case nir_intrinsic_load_viewport_scale
:
1645 case nir_intrinsic_load_viewport_offset
:
1646 case nir_intrinsic_load_num_work_groups
:
1647 case nir_intrinsic_load_sampler_lod_parameters_pan
:
1648 emit_sysval_read(ctx
, &instr
->instr
, 3, 0);
1651 case nir_intrinsic_load_work_group_id
:
1652 case nir_intrinsic_load_local_invocation_id
:
1653 emit_compute_builtin(ctx
, instr
);
1656 case nir_intrinsic_load_vertex_id
:
1657 case nir_intrinsic_load_instance_id
:
1658 emit_vertex_builtin(ctx
, instr
);
1661 case nir_intrinsic_memory_barrier_buffer
:
1662 case nir_intrinsic_memory_barrier_shared
:
1665 case nir_intrinsic_control_barrier
:
1666 schedule_barrier(ctx
);
1667 emit_control_barrier(ctx
);
1668 schedule_barrier(ctx
);
1672 fprintf(stderr
, "Unhandled intrinsic %s\n", nir_intrinsic_infos
[instr
->intrinsic
].name
);
1679 midgard_tex_format(enum glsl_sampler_dim dim
)
1682 case GLSL_SAMPLER_DIM_1D
:
1683 case GLSL_SAMPLER_DIM_BUF
:
1686 case GLSL_SAMPLER_DIM_2D
:
1687 case GLSL_SAMPLER_DIM_EXTERNAL
:
1688 case GLSL_SAMPLER_DIM_RECT
:
1691 case GLSL_SAMPLER_DIM_3D
:
1694 case GLSL_SAMPLER_DIM_CUBE
:
1695 return MALI_TEX_CUBE
;
1698 DBG("Unknown sampler dim type\n");
1704 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1708 pan_attach_constant_bias(
1709 compiler_context
*ctx
,
1711 midgard_texture_word
*word
)
1713 /* To attach as constant, it has to *be* constant */
1715 if (!nir_src_is_const(lod
))
1718 float f
= nir_src_as_float(lod
);
1720 /* Break into fixed-point */
1722 float lod_frac
= f
- lod_int
;
1724 /* Carry over negative fractions */
1725 if (lod_frac
< 0.0) {
1731 word
->bias
= float_to_ubyte(lod_frac
);
1732 word
->bias_int
= lod_int
;
1737 static enum mali_sampler_type
1738 midgard_sampler_type(nir_alu_type t
) {
1739 switch (nir_alu_type_get_base_type(t
))
1741 case nir_type_float
:
1742 return MALI_SAMPLER_FLOAT
;
1744 return MALI_SAMPLER_SIGNED
;
1746 return MALI_SAMPLER_UNSIGNED
;
1748 unreachable("Unknown sampler type");
1753 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1754 unsigned midgard_texop
)
1757 //assert (!instr->sampler);
1759 int texture_index
= instr
->texture_index
;
1760 int sampler_index
= texture_index
;
1762 /* No helper to build texture words -- we do it all here */
1763 midgard_instruction ins
= {
1764 .type
= TAG_TEXTURE_4
,
1766 .dest
= nir_dest_index(&instr
->dest
),
1767 .src
= { ~0, ~0, ~0, ~0 },
1768 .swizzle
= SWIZZLE_IDENTITY_4
,
1770 .op
= midgard_texop
,
1771 .format
= midgard_tex_format(instr
->sampler_dim
),
1772 .texture_handle
= texture_index
,
1773 .sampler_handle
= sampler_index
,
1779 .sampler_type
= midgard_sampler_type(instr
->dest_type
),
1780 .shadow
= instr
->is_shadow
,
1784 /* We may need a temporary for the coordinate */
1786 bool needs_temp_coord
=
1787 (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) ||
1788 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) ||
1791 unsigned coords
= needs_temp_coord
? make_compiler_temp_reg(ctx
) : 0;
1793 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1794 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1795 unsigned nr_components
= nir_src_num_components(instr
->src
[i
].src
);
1797 switch (instr
->src
[i
].src_type
) {
1798 case nir_tex_src_coord
: {
1799 emit_explicit_constant(ctx
, index
, index
);
1801 unsigned coord_mask
= mask_of(instr
->coord_components
);
1803 bool flip_zw
= (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) && (coord_mask
& (1 << COMPONENT_Z
));
1806 coord_mask
^= ((1 << COMPONENT_Z
) | (1 << COMPONENT_W
));
1808 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1809 /* texelFetch is undefined on samplerCube */
1810 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
1812 /* For cubemaps, we use a special ld/st op to
1813 * select the face and copy the xy into the
1814 * texture register */
1816 midgard_instruction ld
= m_ld_cubemap_coords(coords
, 0);
1818 ld
.mask
= 0x3; /* xy */
1819 ld
.load_store
.arg_1
= 0x20;
1820 ld
.swizzle
[1][3] = COMPONENT_X
;
1821 emit_mir_instruction(ctx
, ld
);
1824 ins
.swizzle
[1][2] = instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
1825 ins
.swizzle
[1][3] = COMPONENT_X
;
1826 } else if (needs_temp_coord
) {
1827 /* mov coord_temp, coords */
1828 midgard_instruction mov
= v_mov(index
, coords
);
1829 mov
.mask
= coord_mask
;
1832 mov
.swizzle
[1][COMPONENT_W
] = COMPONENT_Z
;
1834 emit_mir_instruction(ctx
, mov
);
1839 ins
.src
[1] = coords
;
1841 /* Texelfetch coordinates uses all four elements
1842 * (xyz/index) regardless of texture dimensionality,
1843 * which means it's necessary to zero the unused
1844 * components to keep everything happy */
1846 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1847 /* mov index.zw, #0, or generalized */
1848 midgard_instruction mov
=
1849 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), coords
);
1850 mov
.has_constants
= true;
1851 mov
.mask
= coord_mask
^ 0xF;
1852 emit_mir_instruction(ctx
, mov
);
1855 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) {
1856 /* Array component in w but NIR wants it in z,
1857 * but if we have a temp coord we already fixed
1860 if (nr_components
== 3) {
1861 ins
.swizzle
[1][2] = COMPONENT_Z
;
1862 ins
.swizzle
[1][3] = needs_temp_coord
? COMPONENT_W
: COMPONENT_Z
;
1863 } else if (nr_components
== 2) {
1865 instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
1866 ins
.swizzle
[1][3] = COMPONENT_X
;
1868 unreachable("Invalid texture 2D components");
1871 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1873 ins
.swizzle
[1][2] = COMPONENT_Z
;
1874 ins
.swizzle
[1][3] = COMPONENT_W
;
1880 case nir_tex_src_bias
:
1881 case nir_tex_src_lod
: {
1882 /* Try as a constant if we can */
1884 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
1885 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
1888 ins
.texture
.lod_register
= true;
1891 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
1892 ins
.swizzle
[2][c
] = COMPONENT_X
;
1894 emit_explicit_constant(ctx
, index
, index
);
1899 case nir_tex_src_offset
: {
1900 ins
.texture
.offset_register
= true;
1903 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
1904 ins
.swizzle
[3][c
] = (c
> COMPONENT_Z
) ? 0 : c
;
1906 emit_explicit_constant(ctx
, index
, index
);
1910 case nir_tex_src_comparator
: {
1911 unsigned comp
= COMPONENT_Z
;
1913 /* mov coord_temp.foo, coords */
1914 midgard_instruction mov
= v_mov(index
, coords
);
1915 mov
.mask
= 1 << comp
;
1917 for (unsigned i
= 0; i
< MIR_VEC_COMPONENTS
; ++i
)
1918 mov
.swizzle
[1][i
] = COMPONENT_X
;
1920 emit_mir_instruction(ctx
, mov
);
1925 fprintf(stderr
, "Unknown texture source type: %d\n", instr
->src
[i
].src_type
);
1931 emit_mir_instruction(ctx
, ins
);
1933 /* Used for .cont and .last hinting */
1934 ctx
->texture_op_count
++;
1938 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1940 switch (instr
->op
) {
1943 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
1946 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
1949 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
1952 emit_sysval_read(ctx
, &instr
->instr
, 4, 0);
1955 fprintf(stderr
, "Unhandled texture op: %d\n", instr
->op
);
1962 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1964 switch (instr
->type
) {
1965 case nir_jump_break
: {
1966 /* Emit a branch out of the loop */
1967 struct midgard_instruction br
= v_branch(false, false);
1968 br
.branch
.target_type
= TARGET_BREAK
;
1969 br
.branch
.target_break
= ctx
->current_loop_depth
;
1970 emit_mir_instruction(ctx
, br
);
1975 DBG("Unknown jump type %d\n", instr
->type
);
1981 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1983 switch (instr
->type
) {
1984 case nir_instr_type_load_const
:
1985 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1988 case nir_instr_type_intrinsic
:
1989 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1992 case nir_instr_type_alu
:
1993 emit_alu(ctx
, nir_instr_as_alu(instr
));
1996 case nir_instr_type_tex
:
1997 emit_tex(ctx
, nir_instr_as_tex(instr
));
2000 case nir_instr_type_jump
:
2001 emit_jump(ctx
, nir_instr_as_jump(instr
));
2004 case nir_instr_type_ssa_undef
:
2009 DBG("Unhandled instruction type\n");
2015 /* ALU instructions can inline or embed constants, which decreases register
2016 * pressure and saves space. */
2018 #define CONDITIONAL_ATTACH(idx) { \
2019 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2022 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2023 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2028 inline_alu_constants(compiler_context
*ctx
, midgard_block
*block
)
2030 mir_foreach_instr_in_block(block
, alu
) {
2031 /* Other instructions cannot inline constants */
2032 if (alu
->type
!= TAG_ALU_4
) continue;
2033 if (alu
->compact_branch
) continue;
2035 /* If there is already a constant here, we can do nothing */
2036 if (alu
->has_constants
) continue;
2038 CONDITIONAL_ATTACH(0);
2040 if (!alu
->has_constants
) {
2041 CONDITIONAL_ATTACH(1)
2042 } else if (!alu
->inline_constant
) {
2043 /* Corner case: _two_ vec4 constants, for instance with a
2044 * csel. For this case, we can only use a constant
2045 * register for one, we'll have to emit a move for the
2046 * other. Note, if both arguments are constants, then
2047 * necessarily neither argument depends on the value of
2048 * any particular register. As the destination register
2049 * will be wiped, that means we can spill the constant
2050 * to the destination register.
2053 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->src
[1] + 1);
2054 unsigned scratch
= alu
->dest
;
2057 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), scratch
);
2058 attach_constants(ctx
, &ins
, entry
, alu
->src
[1] + 1);
2060 /* Set the source */
2061 alu
->src
[1] = scratch
;
2063 /* Inject us -before- the last instruction which set r31 */
2064 mir_insert_instruction_before(ctx
, mir_prev_op(alu
), ins
);
2070 /* Being a little silly with the names, but returns the op that is the bitwise
2071 * inverse of the op with the argument switched. I.e. (f and g are
2074 * f(a, b) = ~g(b, a)
2076 * Corollary: if g is the contrapositve of f, f is the contrapositive of g:
2078 * f(a, b) = ~g(b, a)
2079 * ~f(a, b) = g(b, a)
2080 * ~f(a, b) = ~h(a, b) where h is the contrapositive of g
2083 * Thus we define this function in pairs.
2086 static inline midgard_alu_op
2087 mir_contrapositive(midgard_alu_op op
)
2090 case midgard_alu_op_flt
:
2091 return midgard_alu_op_fle
;
2092 case midgard_alu_op_fle
:
2093 return midgard_alu_op_flt
;
2095 case midgard_alu_op_ilt
:
2096 return midgard_alu_op_ile
;
2097 case midgard_alu_op_ile
:
2098 return midgard_alu_op_ilt
;
2101 unreachable("No known contrapositive");
2105 /* Midgard supports two types of constants, embedded constants (128-bit) and
2106 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2107 * constants can be demoted to inline constants, for space savings and
2108 * sometimes a performance boost */
2111 embedded_to_inline_constant(compiler_context
*ctx
, midgard_block
*block
)
2113 mir_foreach_instr_in_block(block
, ins
) {
2114 if (!ins
->has_constants
) continue;
2115 if (ins
->has_inline_constant
) continue;
2117 /* Blend constants must not be inlined by definition */
2118 if (ins
->has_blend_constant
) continue;
2120 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2121 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
2122 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
2124 if (!(is_16
|| is_32
))
2127 /* src1 cannot be an inline constant due to encoding
2128 * restrictions. So, if possible we try to flip the arguments
2131 int op
= ins
->alu
.op
;
2133 if (ins
->src
[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2134 bool flip
= alu_opcode_props
[op
].props
& OP_COMMUTES
;
2137 /* Conditionals can be inverted */
2138 case midgard_alu_op_flt
:
2139 case midgard_alu_op_ilt
:
2140 case midgard_alu_op_fle
:
2141 case midgard_alu_op_ile
:
2142 ins
->alu
.op
= mir_contrapositive(ins
->alu
.op
);
2147 case midgard_alu_op_fcsel
:
2148 case midgard_alu_op_icsel
:
2149 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
2158 if (ins
->src
[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2159 /* Extract the source information */
2161 midgard_vector_alu_src
*src
;
2162 int q
= ins
->alu
.src2
;
2163 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2166 /* Component is from the swizzle. Take a nonzero component */
2168 unsigned first_comp
= ffs(ins
->mask
) - 1;
2169 unsigned component
= ins
->swizzle
[1][first_comp
];
2171 /* Scale constant appropriately, if we can legally */
2172 uint16_t scaled_constant
= 0;
2175 scaled_constant
= ins
->constants
.u16
[component
];
2176 } else if (midgard_is_integer_op(op
)) {
2177 scaled_constant
= ins
->constants
.u32
[component
];
2179 /* Constant overflow after resize */
2180 if (scaled_constant
!= ins
->constants
.u32
[component
])
2183 float original
= ins
->constants
.f32
[component
];
2184 scaled_constant
= _mesa_float_to_half(original
);
2186 /* Check for loss of precision. If this is
2187 * mediump, we don't care, but for a highp
2188 * shader, we need to pay attention. NIR
2189 * doesn't yet tell us which mode we're in!
2190 * Practically this prevents most constants
2191 * from being inlined, sadly. */
2193 float fp32
= _mesa_half_to_float(scaled_constant
);
2195 if (fp32
!= original
)
2199 /* We don't know how to handle these with a constant */
2201 if (mir_nontrivial_source2_mod_simple(ins
) || src
->rep_low
|| src
->rep_high
) {
2202 DBG("Bailing inline constant...\n");
2206 /* Make sure that the constant is not itself a vector
2207 * by checking if all accessed values are the same. */
2209 const midgard_constants
*cons
= &ins
->constants
;
2210 uint32_t value
= is_16
? cons
->u16
[component
] : cons
->u32
[component
];
2212 bool is_vector
= false;
2213 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
2215 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
) {
2216 /* We only care if this component is actually used */
2217 if (!(mask
& (1 << c
)))
2220 uint32_t test
= is_16
?
2221 cons
->u16
[ins
->swizzle
[1][c
]] :
2222 cons
->u32
[ins
->swizzle
[1][c
]];
2224 if (test
!= value
) {
2233 /* Get rid of the embedded constant */
2234 ins
->has_constants
= false;
2236 ins
->has_inline_constant
= true;
2237 ins
->inline_constant
= scaled_constant
;
2242 /* Dead code elimination for branches at the end of a block - only one branch
2243 * per block is legal semantically */
2246 midgard_opt_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
2248 bool branched
= false;
2250 mir_foreach_instr_in_block_safe(block
, ins
) {
2251 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2254 mir_remove_instruction(ins
);
2260 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2261 * the move can be propagated away entirely */
2264 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
2267 if (comp
== midgard_outmod_none
)
2270 if (*outmod
== midgard_outmod_none
) {
2275 /* TODO: Compose rules */
2280 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
2282 bool progress
= false;
2284 mir_foreach_instr_in_block_safe(block
, ins
) {
2285 if (ins
->type
!= TAG_ALU_4
) continue;
2286 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2287 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
2289 /* TODO: Registers? */
2290 unsigned src
= ins
->src
[1];
2291 if (src
& IS_REG
) continue;
2293 /* There might be a source modifier, too */
2294 if (mir_nontrivial_source2_mod(ins
)) continue;
2296 /* Backpropagate the modifier */
2297 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2298 if (v
->type
!= TAG_ALU_4
) continue;
2299 if (v
->dest
!= src
) continue;
2301 /* Can we even take a float outmod? */
2302 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
2304 midgard_outmod_float temp
= v
->alu
.outmod
;
2305 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
2307 /* Throw in the towel.. */
2308 if (!progress
) break;
2310 /* Otherwise, transfer the modifier */
2311 v
->alu
.outmod
= temp
;
2312 ins
->alu
.outmod
= midgard_outmod_none
;
2322 emit_fragment_epilogue(compiler_context
*ctx
, unsigned rt
)
2324 /* Loop to ourselves */
2325 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
2326 struct midgard_instruction ins
= v_branch(false, false);
2327 ins
.writeout
= true;
2328 ins
.writeout_depth
= br
->writeout_depth
;
2329 ins
.writeout_stencil
= br
->writeout_stencil
;
2330 ins
.branch
.target_block
= ctx
->block_count
- 1;
2331 ins
.constants
.u32
[0] = br
->constants
.u32
[0];
2332 emit_mir_instruction(ctx
, ins
);
2334 ctx
->current_block
->epilogue
= true;
2335 schedule_barrier(ctx
);
2336 return ins
.branch
.target_block
;
2339 static midgard_block
*
2340 emit_block(compiler_context
*ctx
, nir_block
*block
)
2342 midgard_block
*this_block
= ctx
->after_block
;
2343 ctx
->after_block
= NULL
;
2346 this_block
= create_empty_block(ctx
);
2348 list_addtail(&this_block
->base
.link
, &ctx
->blocks
);
2350 this_block
->scheduled
= false;
2353 /* Set up current block */
2354 list_inithead(&this_block
->base
.instructions
);
2355 ctx
->current_block
= this_block
;
2357 nir_foreach_instr(instr
, block
) {
2358 emit_instr(ctx
, instr
);
2359 ++ctx
->instruction_count
;
2365 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2368 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2370 midgard_block
*before_block
= ctx
->current_block
;
2372 /* Speculatively emit the branch, but we can't fill it in until later */
2373 EMIT(branch
, true, true);
2374 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2375 then_branch
->src
[0] = nir_src_index(ctx
, &nif
->condition
);
2377 /* Emit the two subblocks. */
2378 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2379 midgard_block
*end_then_block
= ctx
->current_block
;
2381 /* Emit a jump from the end of the then block to the end of the else */
2382 EMIT(branch
, false, false);
2383 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2385 /* Emit second block, and check if it's empty */
2387 int else_idx
= ctx
->block_count
;
2388 int count_in
= ctx
->instruction_count
;
2389 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2390 midgard_block
*end_else_block
= ctx
->current_block
;
2391 int after_else_idx
= ctx
->block_count
;
2393 /* Now that we have the subblocks emitted, fix up the branches */
2398 if (ctx
->instruction_count
== count_in
) {
2399 /* The else block is empty, so don't emit an exit jump */
2400 mir_remove_instruction(then_exit
);
2401 then_branch
->branch
.target_block
= after_else_idx
;
2403 then_branch
->branch
.target_block
= else_idx
;
2404 then_exit
->branch
.target_block
= after_else_idx
;
2407 /* Wire up the successors */
2409 ctx
->after_block
= create_empty_block(ctx
);
2411 pan_block_add_successor(&before_block
->base
, &then_block
->base
);
2412 pan_block_add_successor(&before_block
->base
, &else_block
->base
);
2414 pan_block_add_successor(&end_then_block
->base
, &ctx
->after_block
->base
);
2415 pan_block_add_successor(&end_else_block
->base
, &ctx
->after_block
->base
);
2419 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2421 /* Remember where we are */
2422 midgard_block
*start_block
= ctx
->current_block
;
2424 /* Allocate a loop number, growing the current inner loop depth */
2425 int loop_idx
= ++ctx
->current_loop_depth
;
2427 /* Get index from before the body so we can loop back later */
2428 int start_idx
= ctx
->block_count
;
2430 /* Emit the body itself */
2431 midgard_block
*loop_block
= emit_cf_list(ctx
, &nloop
->body
);
2433 /* Branch back to loop back */
2434 struct midgard_instruction br_back
= v_branch(false, false);
2435 br_back
.branch
.target_block
= start_idx
;
2436 emit_mir_instruction(ctx
, br_back
);
2438 /* Mark down that branch in the graph. */
2439 pan_block_add_successor(&start_block
->base
, &loop_block
->base
);
2440 pan_block_add_successor(&ctx
->current_block
->base
, &loop_block
->base
);
2442 /* Find the index of the block about to follow us (note: we don't add
2443 * one; blocks are 0-indexed so we get a fencepost problem) */
2444 int break_block_idx
= ctx
->block_count
;
2446 /* Fix up the break statements we emitted to point to the right place,
2447 * now that we can allocate a block number for them */
2448 ctx
->after_block
= create_empty_block(ctx
);
2450 mir_foreach_block_from(ctx
, start_block
, _block
) {
2451 mir_foreach_instr_in_block(((midgard_block
*) _block
), ins
) {
2452 if (ins
->type
!= TAG_ALU_4
) continue;
2453 if (!ins
->compact_branch
) continue;
2455 /* We found a branch -- check the type to see if we need to do anything */
2456 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2458 /* It's a break! Check if it's our break */
2459 if (ins
->branch
.target_break
!= loop_idx
) continue;
2461 /* Okay, cool, we're breaking out of this loop.
2462 * Rewrite from a break to a goto */
2464 ins
->branch
.target_type
= TARGET_GOTO
;
2465 ins
->branch
.target_block
= break_block_idx
;
2467 pan_block_add_successor(_block
, &ctx
->after_block
->base
);
2471 /* Now that we've finished emitting the loop, free up the depth again
2472 * so we play nice with recursion amid nested loops */
2473 --ctx
->current_loop_depth
;
2475 /* Dump loop stats */
2479 static midgard_block
*
2480 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2482 midgard_block
*start_block
= NULL
;
2484 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2485 switch (node
->type
) {
2486 case nir_cf_node_block
: {
2487 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2490 start_block
= block
;
2495 case nir_cf_node_if
:
2496 emit_if(ctx
, nir_cf_node_as_if(node
));
2499 case nir_cf_node_loop
:
2500 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2503 case nir_cf_node_function
:
2512 /* Due to lookahead, we need to report the first tag executed in the command
2513 * stream and in branch targets. An initial block might be empty, so iterate
2514 * until we find one that 'works' */
2517 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2519 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2521 mir_foreach_block_from(ctx
, initial_block
, _v
) {
2522 midgard_block
*v
= (midgard_block
*) _v
;
2523 if (v
->quadword_count
) {
2524 midgard_bundle
*initial_bundle
=
2525 util_dynarray_element(&v
->bundles
, midgard_bundle
, 0);
2527 return initial_bundle
->tag
;
2531 /* Default to a tag 1 which will break from the shader, in case we jump
2532 * to the exit block (i.e. `return` in a compute shader) */
2538 pan_format_from_nir_base(nir_alu_type base
)
2542 return MALI_FORMAT_SINT
;
2545 return MALI_FORMAT_UINT
;
2546 case nir_type_float
:
2547 return MALI_CHANNEL_FLOAT
;
2549 unreachable("Invalid base");
2554 pan_format_from_nir_size(nir_alu_type base
, unsigned size
)
2556 if (base
== nir_type_float
) {
2558 case 16: return MALI_FORMAT_SINT
;
2559 case 32: return MALI_FORMAT_UNORM
;
2561 unreachable("Invalid float size for format");
2566 case 8: return MALI_CHANNEL_8
;
2567 case 16: return MALI_CHANNEL_16
;
2568 case 32: return MALI_CHANNEL_32
;
2570 unreachable("Invalid int size for format");
2575 static enum mali_format
2576 pan_format_from_glsl(const struct glsl_type
*type
)
2578 enum glsl_base_type glsl_base
= glsl_get_base_type(glsl_without_array(type
));
2579 nir_alu_type t
= nir_get_nir_type_for_glsl_base_type(glsl_base
);
2581 unsigned base
= nir_alu_type_get_base_type(t
);
2582 unsigned size
= nir_alu_type_get_type_size(t
);
2584 return pan_format_from_nir_base(base
) |
2585 pan_format_from_nir_size(base
, size
) |
2586 MALI_NR_CHANNELS(4);
2589 /* For each fragment writeout instruction, generate a writeout loop to
2590 * associate with it */
2593 mir_add_writeout_loops(compiler_context
*ctx
)
2595 for (unsigned rt
= 0; rt
< ARRAY_SIZE(ctx
->writeout_branch
); ++rt
) {
2596 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
2599 unsigned popped
= br
->branch
.target_block
;
2600 pan_block_add_successor(&(mir_get_block(ctx
, popped
- 1)->base
), &ctx
->current_block
->base
);
2601 br
->branch
.target_block
= emit_fragment_epilogue(ctx
, rt
);
2603 /* If we have more RTs, we'll need to restore back after our
2604 * loop terminates */
2606 if ((rt
+ 1) < ARRAY_SIZE(ctx
->writeout_branch
) && ctx
->writeout_branch
[rt
+ 1]) {
2607 midgard_instruction uncond
= v_branch(false, false);
2608 uncond
.branch
.target_block
= popped
;
2609 emit_mir_instruction(ctx
, uncond
);
2610 pan_block_add_successor(&ctx
->current_block
->base
, &(mir_get_block(ctx
, popped
)->base
));
2611 schedule_barrier(ctx
);
2613 /* We're last, so we can terminate here */
2614 br
->last_writeout
= true;
2620 midgard_compile_shader_nir(nir_shader
*nir
, panfrost_program
*program
, bool is_blend
, unsigned blend_rt
, unsigned gpu_id
, bool shaderdb
)
2622 struct util_dynarray
*compiled
= &program
->compiled
;
2624 midgard_debug
= debug_get_option_midgard_debug();
2626 /* TODO: Bound against what? */
2627 compiler_context
*ctx
= rzalloc(NULL
, compiler_context
);
2630 ctx
->stage
= nir
->info
.stage
;
2631 ctx
->is_blend
= is_blend
;
2632 ctx
->alpha_ref
= program
->alpha_ref
;
2633 ctx
->blend_rt
= MIDGARD_COLOR_RT0
+ blend_rt
;
2634 ctx
->quirks
= midgard_get_quirks(gpu_id
);
2636 /* Start off with a safe cutoff, allowing usage of all 16 work
2637 * registers. Later, we'll promote uniform reads to uniform registers
2638 * if we determine it is beneficial to do so */
2639 ctx
->uniform_cutoff
= 8;
2641 /* Initialize at a global (not block) level hash tables */
2643 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2644 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2646 /* Record the varying mapping for the command stream's bookkeeping */
2648 struct exec_list
*varyings
=
2649 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2651 unsigned max_varying
= 0;
2652 nir_foreach_variable(var
, varyings
) {
2653 unsigned loc
= var
->data
.driver_location
;
2654 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2656 for (int c
= 0; c
< sz
; ++c
) {
2657 program
->varyings
[loc
+ c
] = var
->data
.location
+ c
;
2658 program
->varying_type
[loc
+ c
] = pan_format_from_glsl(var
->type
);
2659 max_varying
= MAX2(max_varying
, loc
+ c
);
2663 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2664 * (so we don't accidentally duplicate the epilogue since mesa/st has
2665 * messed with our I/O quite a bit already) */
2667 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2669 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2670 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2671 NIR_PASS_V(nir
, nir_lower_point_size
, 1.0, 1024.0);
2674 NIR_PASS_V(nir
, nir_lower_var_copies
);
2675 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2676 NIR_PASS_V(nir
, nir_split_var_copies
);
2677 NIR_PASS_V(nir
, nir_lower_var_copies
);
2678 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2679 NIR_PASS_V(nir
, nir_lower_var_copies
);
2680 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2682 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2683 NIR_PASS_V(nir
, nir_lower_ssbo
);
2684 NIR_PASS_V(nir
, midgard_nir_lower_zs_store
);
2686 /* Optimisation passes */
2688 optimise_nir(nir
, ctx
->quirks
);
2690 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2691 nir_print_shader(nir
, stdout
);
2694 /* Assign sysvals and counts, now that we're sure
2695 * (post-optimisation) */
2697 panfrost_nir_assign_sysvals(&ctx
->sysvals
, nir
);
2699 program
->uniform_count
= nir
->num_uniforms
;
2700 program
->sysval_count
= ctx
->sysvals
.sysval_count
;
2701 memcpy(program
->sysvals
, ctx
->sysvals
.sysvals
, sizeof(ctx
->sysvals
.sysvals
[0]) * ctx
->sysvals
.sysval_count
);
2703 nir_foreach_function(func
, nir
) {
2707 list_inithead(&ctx
->blocks
);
2708 ctx
->block_count
= 0;
2711 emit_cf_list(ctx
, &func
->impl
->body
);
2712 break; /* TODO: Multi-function shaders */
2715 util_dynarray_init(compiled
, NULL
);
2717 /* Per-block lowering before opts */
2719 mir_foreach_block(ctx
, _block
) {
2720 midgard_block
*block
= (midgard_block
*) _block
;
2721 inline_alu_constants(ctx
, block
);
2722 midgard_opt_promote_fmov(ctx
, block
);
2723 embedded_to_inline_constant(ctx
, block
);
2725 /* MIR-level optimizations */
2727 bool progress
= false;
2732 mir_foreach_block(ctx
, _block
) {
2733 midgard_block
*block
= (midgard_block
*) _block
;
2734 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2735 progress
|= midgard_opt_copy_prop(ctx
, block
);
2736 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2737 progress
|= midgard_opt_combine_projection(ctx
, block
);
2738 progress
|= midgard_opt_varying_projection(ctx
, block
);
2739 progress
|= midgard_opt_not_propagate(ctx
, block
);
2740 progress
|= midgard_opt_fuse_src_invert(ctx
, block
);
2741 progress
|= midgard_opt_fuse_dest_invert(ctx
, block
);
2742 progress
|= midgard_opt_csel_invert(ctx
, block
);
2743 progress
|= midgard_opt_drop_cmp_invert(ctx
, block
);
2744 progress
|= midgard_opt_invert_branch(ctx
, block
);
2748 mir_foreach_block(ctx
, _block
) {
2749 midgard_block
*block
= (midgard_block
*) _block
;
2750 midgard_lower_invert(ctx
, block
);
2751 midgard_lower_derivatives(ctx
, block
);
2754 /* Nested control-flow can result in dead branches at the end of the
2755 * block. This messes with our analysis and is just dead code, so cull
2757 mir_foreach_block(ctx
, _block
) {
2758 midgard_block
*block
= (midgard_block
*) _block
;
2759 midgard_opt_cull_dead_branch(ctx
, block
);
2762 /* Ensure we were lowered */
2763 mir_foreach_instr_global(ctx
, ins
) {
2764 assert(!ins
->invert
);
2767 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
2768 mir_add_writeout_loops(ctx
);
2771 midgard_schedule_program(ctx
);
2774 /* Now that all the bundles are scheduled and we can calculate block
2775 * sizes, emit actual branch instructions rather than placeholders */
2777 int br_block_idx
= 0;
2779 mir_foreach_block(ctx
, _block
) {
2780 midgard_block
*block
= (midgard_block
*) _block
;
2781 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2782 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2783 midgard_instruction
*ins
= bundle
->instructions
[c
];
2785 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2787 /* Parse some basic branch info */
2788 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2789 bool is_conditional
= ins
->branch
.conditional
;
2790 bool is_inverted
= ins
->branch
.invert_conditional
;
2791 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2792 bool is_writeout
= ins
->writeout
;
2794 /* Determine the block we're jumping to */
2795 int target_number
= ins
->branch
.target_block
;
2797 /* Report the destination tag */
2798 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2800 /* Count up the number of quadwords we're
2801 * jumping over = number of quadwords until
2802 * (br_block_idx, target_number) */
2804 int quadword_offset
= 0;
2808 } else if (target_number
> br_block_idx
) {
2811 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2812 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2815 quadword_offset
+= blk
->quadword_count
;
2818 /* Jump backwards */
2820 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2821 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2824 quadword_offset
-= blk
->quadword_count
;
2828 /* Unconditional extended branches (far jumps)
2829 * have issues, so we always use a conditional
2830 * branch, setting the condition to always for
2831 * unconditional. For compact unconditional
2832 * branches, cond isn't used so it doesn't
2833 * matter what we pick. */
2835 midgard_condition cond
=
2836 !is_conditional
? midgard_condition_always
:
2837 is_inverted
? midgard_condition_false
:
2838 midgard_condition_true
;
2840 midgard_jmp_writeout_op op
=
2841 is_discard
? midgard_jmp_writeout_op_discard
:
2842 is_writeout
? midgard_jmp_writeout_op_writeout
:
2843 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2844 midgard_jmp_writeout_op_branch_cond
;
2847 midgard_branch_extended branch
=
2848 midgard_create_branch_extended(
2853 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2854 } else if (is_conditional
|| is_discard
) {
2855 midgard_branch_cond branch
= {
2857 .dest_tag
= dest_tag
,
2858 .offset
= quadword_offset
,
2862 assert(branch
.offset
== quadword_offset
);
2864 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2866 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2868 midgard_branch_uncond branch
= {
2870 .dest_tag
= dest_tag
,
2871 .offset
= quadword_offset
,
2875 assert(branch
.offset
== quadword_offset
);
2877 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2885 /* Emit flat binary from the instruction arrays. Iterate each block in
2886 * sequence. Save instruction boundaries such that lookahead tags can
2887 * be assigned easily */
2889 /* Cache _all_ bundles in source order for lookahead across failed branches */
2891 int bundle_count
= 0;
2892 mir_foreach_block(ctx
, _block
) {
2893 midgard_block
*block
= (midgard_block
*) _block
;
2894 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2896 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2898 mir_foreach_block(ctx
, _block
) {
2899 midgard_block
*block
= (midgard_block
*) _block
;
2900 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2901 source_order_bundles
[bundle_idx
++] = bundle
;
2905 int current_bundle
= 0;
2907 /* Midgard prefetches instruction types, so during emission we
2908 * need to lookahead. Unless this is the last instruction, in
2909 * which we return 1. */
2911 mir_foreach_block(ctx
, _block
) {
2912 midgard_block
*block
= (midgard_block
*) _block
;
2913 mir_foreach_bundle_in_block(block
, bundle
) {
2916 if (!bundle
->last_writeout
&& (current_bundle
+ 1 < bundle_count
))
2917 lookahead
= source_order_bundles
[current_bundle
+ 1]->tag
;
2919 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2923 /* TODO: Free deeper */
2924 //util_dynarray_fini(&block->instructions);
2927 free(source_order_bundles
);
2929 /* Report the very first tag executed */
2930 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2932 /* Deal with off-by-one related to the fencepost problem */
2933 program
->work_register_count
= ctx
->work_registers
+ 1;
2934 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2936 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2937 program
->tls_size
= ctx
->tls_size
;
2939 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2940 disassemble_midgard(stdout
, program
->compiled
.data
, program
->compiled
.size
, gpu_id
, ctx
->stage
);
2942 if (midgard_debug
& MIDGARD_DBG_SHADERDB
|| shaderdb
) {
2943 unsigned nr_bundles
= 0, nr_ins
= 0;
2945 /* Count instructions and bundles */
2947 mir_foreach_block(ctx
, _block
) {
2948 midgard_block
*block
= (midgard_block
*) _block
;
2949 nr_bundles
+= util_dynarray_num_elements(
2950 &block
->bundles
, midgard_bundle
);
2952 mir_foreach_bundle_in_block(block
, bun
)
2953 nr_ins
+= bun
->instruction_count
;
2956 /* Calculate thread count. There are certain cutoffs by
2957 * register count for thread count */
2959 unsigned nr_registers
= program
->work_register_count
;
2961 unsigned nr_threads
=
2962 (nr_registers
<= 4) ? 4 :
2963 (nr_registers
<= 8) ? 2 :
2968 fprintf(stderr
, "shader%d - %s shader: "
2969 "%u inst, %u bundles, %u quadwords, "
2970 "%u registers, %u threads, %u loops, "
2971 "%u:%u spills:fills\n",
2973 gl_shader_stage_name(ctx
->stage
),
2974 nr_ins
, nr_bundles
, ctx
->quadword_count
,
2975 nr_registers
, nr_threads
,
2977 ctx
->spills
, ctx
->fills
);