2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
50 #include "midgard_quirks.h"
51 #include "panfrost-quirks.h"
52 #include "panfrost/util/pan_lower_framebuffer.h"
54 #include "disassemble.h"
56 static const struct debug_named_value debug_options
[] = {
57 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
58 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
59 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
63 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
65 unsigned SHADER_DB_COUNT
= 0;
67 int midgard_debug
= 0;
69 #define DBG(fmt, ...) \
70 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
71 fprintf(stderr, "%s:%d: "fmt, \
72 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
73 static midgard_block
*
74 create_empty_block(compiler_context
*ctx
)
76 midgard_block
*blk
= rzalloc(ctx
, midgard_block
);
78 blk
->base
.predecessors
= _mesa_set_create(blk
,
80 _mesa_key_pointer_equal
);
82 blk
->base
.name
= ctx
->block_source_count
++;
88 schedule_barrier(compiler_context
*ctx
)
90 midgard_block
*temp
= ctx
->after_block
;
91 ctx
->after_block
= create_empty_block(ctx
);
93 list_addtail(&ctx
->after_block
->base
.link
, &ctx
->blocks
);
94 list_inithead(&ctx
->after_block
->base
.instructions
);
95 pan_block_add_successor(&ctx
->current_block
->base
, &ctx
->after_block
->base
);
96 ctx
->current_block
= ctx
->after_block
;
97 ctx
->after_block
= temp
;
100 /* Helpers to generate midgard_instruction's using macro magic, since every
101 * driver seems to do it that way */
103 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
105 #define M_LOAD_STORE(name, store, T) \
106 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
107 midgard_instruction i = { \
108 .type = TAG_LOAD_STORE_4, \
111 .src = { ~0, ~0, ~0, ~0 }, \
112 .swizzle = SWIZZLE_IDENTITY_4, \
113 .op = midgard_op_##name, \
121 i.src_types[0] = T; \
130 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
131 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
133 M_LOAD(ld_attr_32
, nir_type_uint32
);
134 M_LOAD(ld_vary_32
, nir_type_uint32
);
135 M_LOAD(ld_ubo_int4
, nir_type_uint32
);
136 M_LOAD(ld_int4
, nir_type_uint32
);
137 M_STORE(st_int4
, nir_type_uint32
);
138 M_LOAD(ld_color_buffer_32u
, nir_type_uint32
);
139 M_LOAD(ld_color_buffer_as_fp16
, nir_type_float16
);
140 M_LOAD(ld_color_buffer_as_fp32
, nir_type_float32
);
141 M_STORE(st_vary_32
, nir_type_uint32
);
142 M_LOAD(ld_cubemap_coords
, nir_type_uint32
);
143 M_LOAD(ld_compute_id
, nir_type_uint32
);
145 static midgard_instruction
146 v_branch(bool conditional
, bool invert
)
148 midgard_instruction ins
= {
150 .unit
= ALU_ENAB_BRANCH
,
151 .compact_branch
= true,
153 .conditional
= conditional
,
154 .invert_conditional
= invert
157 .src
= { ~0, ~0, ~0, ~0 },
164 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
166 ins
->has_constants
= true;
167 memcpy(&ins
->constants
, constants
, 16);
171 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
173 return glsl_count_attribute_slots(type
, false);
176 /* Lower fdot2 to a vector multiplication followed by channel addition */
178 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
180 if (alu
->op
!= nir_op_fdot2
)
183 b
->cursor
= nir_before_instr(&alu
->instr
);
185 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
186 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
188 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
190 nir_ssa_def
*sum
= nir_fadd(b
,
191 nir_channel(b
, product
, 0),
192 nir_channel(b
, product
, 1));
194 /* Replace the fdot2 with this sum */
195 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
199 midgard_nir_lower_fdot2(nir_shader
*shader
)
201 bool progress
= false;
203 nir_foreach_function(function
, shader
) {
204 if (!function
->impl
) continue;
207 nir_builder
*b
= &_b
;
208 nir_builder_init(b
, function
->impl
);
210 nir_foreach_block(block
, function
->impl
) {
211 nir_foreach_instr_safe(instr
, block
) {
212 if (instr
->type
!= nir_instr_type_alu
) continue;
214 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
215 midgard_nir_lower_fdot2_body(b
, alu
);
221 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
228 static const nir_variable
*
229 search_var(nir_shader
*nir
, nir_variable_mode mode
, unsigned driver_loc
)
231 nir_foreach_variable_with_modes(var
, nir
, mode
) {
232 if (var
->data
.driver_location
== driver_loc
)
239 /* Midgard can write all of color, depth and stencil in a single writeout
240 * operation, so we merge depth/stencil stores with color stores.
241 * If there are no color stores, we add a write to the "depth RT".
244 midgard_nir_lower_zs_store(nir_shader
*nir
)
246 if (nir
->info
.stage
!= MESA_SHADER_FRAGMENT
)
249 nir_variable
*z_var
= NULL
, *s_var
= NULL
;
251 nir_foreach_shader_out_variable(var
, nir
) {
252 if (var
->data
.location
== FRAG_RESULT_DEPTH
)
254 else if (var
->data
.location
== FRAG_RESULT_STENCIL
)
258 if (!z_var
&& !s_var
)
261 bool progress
= false;
263 nir_foreach_function(function
, nir
) {
264 if (!function
->impl
) continue;
266 nir_intrinsic_instr
*z_store
= NULL
, *s_store
= NULL
;
268 nir_foreach_block(block
, function
->impl
) {
269 nir_foreach_instr_safe(instr
, block
) {
270 if (instr
->type
!= nir_instr_type_intrinsic
)
273 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
274 if (intr
->intrinsic
!= nir_intrinsic_store_output
)
277 if (z_var
&& nir_intrinsic_base(intr
) == z_var
->data
.driver_location
) {
282 if (s_var
&& nir_intrinsic_base(intr
) == s_var
->data
.driver_location
) {
289 if (!z_store
&& !s_store
) continue;
291 bool replaced
= false;
293 nir_foreach_block(block
, function
->impl
) {
294 nir_foreach_instr_safe(instr
, block
) {
295 if (instr
->type
!= nir_instr_type_intrinsic
)
298 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
299 if (intr
->intrinsic
!= nir_intrinsic_store_output
)
302 const nir_variable
*var
= search_var(nir
, nir_var_shader_out
, nir_intrinsic_base(intr
));
305 if (var
->data
.location
!= FRAG_RESULT_COLOR
&&
306 var
->data
.location
< FRAG_RESULT_DATA0
)
312 assert(nir_src_is_const(intr
->src
[1]) && "no indirect outputs");
315 nir_builder_init(&b
, function
->impl
);
317 assert(!z_store
|| z_store
->instr
.block
== instr
->block
);
318 assert(!s_store
|| s_store
->instr
.block
== instr
->block
);
319 b
.cursor
= nir_after_block_before_jump(instr
->block
);
321 nir_intrinsic_instr
*combined_store
;
322 combined_store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_combined_output_pan
);
324 combined_store
->num_components
= intr
->src
[0].ssa
->num_components
;
326 nir_intrinsic_set_base(combined_store
, nir_intrinsic_base(intr
));
328 unsigned writeout
= PAN_WRITEOUT_C
;
330 writeout
|= PAN_WRITEOUT_Z
;
332 writeout
|= PAN_WRITEOUT_S
;
334 nir_intrinsic_set_component(combined_store
, writeout
);
336 struct nir_ssa_def
*zero
= nir_imm_int(&b
, 0);
338 struct nir_ssa_def
*src
[4] = {
341 z_store
? z_store
->src
[0].ssa
: zero
,
342 s_store
? s_store
->src
[0].ssa
: zero
,
345 for (int i
= 0; i
< 4; ++i
)
346 combined_store
->src
[i
] = nir_src_for_ssa(src
[i
]);
348 nir_builder_instr_insert(&b
, &combined_store
->instr
);
350 nir_instr_remove(instr
);
356 /* Insert a store to the depth RT (0xff) if needed */
359 nir_builder_init(&b
, function
->impl
);
361 nir_block
*block
= NULL
;
362 if (z_store
&& s_store
)
363 assert(z_store
->instr
.block
== s_store
->instr
.block
);
366 block
= z_store
->instr
.block
;
368 block
= s_store
->instr
.block
;
370 b
.cursor
= nir_after_block_before_jump(block
);
372 nir_intrinsic_instr
*combined_store
;
373 combined_store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_combined_output_pan
);
375 combined_store
->num_components
= 4;
379 base
= nir_intrinsic_base(z_store
);
381 base
= nir_intrinsic_base(s_store
);
382 nir_intrinsic_set_base(combined_store
, base
);
384 unsigned writeout
= 0;
386 writeout
|= PAN_WRITEOUT_Z
;
388 writeout
|= PAN_WRITEOUT_S
;
390 nir_intrinsic_set_component(combined_store
, writeout
);
392 struct nir_ssa_def
*zero
= nir_imm_int(&b
, 0);
394 struct nir_ssa_def
*src
[4] = {
395 nir_imm_vec4(&b
, 0, 0, 0, 0),
397 z_store
? z_store
->src
[0].ssa
: zero
,
398 s_store
? s_store
->src
[0].ssa
: zero
,
401 for (int i
= 0; i
< 4; ++i
)
402 combined_store
->src
[i
] = nir_src_for_ssa(src
[i
]);
404 nir_builder_instr_insert(&b
, &combined_store
->instr
);
408 nir_instr_remove(&z_store
->instr
);
411 nir_instr_remove(&s_store
->instr
);
413 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
420 /* Real writeout stores, which break execution, need to be moved to after
421 * dual-source stores, which are just standard register writes. */
423 midgard_nir_reorder_writeout(nir_shader
*nir
)
425 bool progress
= false;
427 nir_foreach_function(function
, nir
) {
428 if (!function
->impl
) continue;
430 nir_foreach_block(block
, function
->impl
) {
431 nir_instr
*last_writeout
= NULL
;
433 nir_foreach_instr_reverse_safe(instr
, block
) {
434 if (instr
->type
!= nir_instr_type_intrinsic
)
437 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
438 if (intr
->intrinsic
!= nir_intrinsic_store_output
)
441 const nir_variable
*var
= search_var(nir
, nir_var_shader_out
, nir_intrinsic_base(intr
));
443 if (var
->data
.index
) {
445 last_writeout
= instr
;
452 /* This is a real store, so move it to after dual-source stores */
453 exec_node_remove(&instr
->node
);
454 exec_node_insert_after(&last_writeout
->node
, &instr
->node
);
465 mdg_is_64(const nir_instr
*instr
, const void *_unused
)
467 const nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
469 if (nir_dest_bit_size(alu
->dest
.dest
) == 64)
473 case nir_op_umul_high
:
474 case nir_op_imul_high
:
481 /* Flushes undefined values to zero */
484 optimise_nir(nir_shader
*nir
, unsigned quirks
, bool is_blend
)
487 unsigned lower_flrp
=
488 (nir
->options
->lower_flrp16
? 16 : 0) |
489 (nir
->options
->lower_flrp32
? 32 : 0) |
490 (nir
->options
->lower_flrp64
? 64 : 0);
492 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
493 NIR_PASS(progress
, nir
, nir_lower_idiv
, nir_lower_idiv_fast
);
495 nir_lower_tex_options lower_tex_options
= {
496 .lower_txs_lod
= true,
498 .lower_tex_without_implicit_lod
=
499 (quirks
& MIDGARD_EXPLICIT_LOD
),
500 .lower_tg4_broadcom_swizzle
= true,
502 /* TODO: we have native gradient.. */
506 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
508 /* Must lower fdot2 after tex is lowered */
509 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
511 /* T720 is broken. */
513 if (quirks
& MIDGARD_BROKEN_LOD
)
514 NIR_PASS_V(nir
, midgard_nir_lod_errata
);
516 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_early
);
521 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
522 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
524 NIR_PASS(progress
, nir
, nir_copy_prop
);
525 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
526 NIR_PASS(progress
, nir
, nir_opt_dce
);
527 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
528 NIR_PASS(progress
, nir
, nir_opt_cse
);
529 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
530 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
531 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
533 if (lower_flrp
!= 0) {
534 bool lower_flrp_progress
= false;
535 NIR_PASS(lower_flrp_progress
,
539 false /* always_precise */,
540 nir
->options
->lower_ffma
);
541 if (lower_flrp_progress
) {
542 NIR_PASS(progress
, nir
,
543 nir_opt_constant_folding
);
547 /* Nothing should rematerialize any flrps, so we only
548 * need to do this lowering once.
553 NIR_PASS(progress
, nir
, nir_opt_undef
);
554 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
556 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
559 nir_var_function_temp
);
561 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
564 NIR_PASS_V(nir
, nir_lower_alu_to_scalar
, mdg_is_64
, NULL
);
566 /* Run after opts so it can hit more */
568 NIR_PASS(progress
, nir
, nir_fuse_io_16
);
570 /* Must be run at the end to prevent creation of fsin/fcos ops */
571 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
576 NIR_PASS(progress
, nir
, nir_opt_dce
);
577 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
578 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
579 NIR_PASS(progress
, nir
, nir_copy_prop
);
582 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
583 NIR_PASS(progress
, nir
, nir_opt_algebraic_distribute_src_mods
);
585 /* We implement booleans as 32-bit 0/~0 */
586 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
588 /* Now that booleans are lowered, we can run out late opts */
589 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
590 NIR_PASS(progress
, nir
, midgard_nir_cancel_inot
);
592 NIR_PASS(progress
, nir
, nir_copy_prop
);
593 NIR_PASS(progress
, nir
, nir_opt_dce
);
595 /* Take us out of SSA */
596 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
597 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
599 /* We are a vector architecture; write combine where possible */
600 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
601 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
603 NIR_PASS(progress
, nir
, nir_opt_dce
);
606 /* Do not actually emit a load; instead, cache the constant for inlining */
609 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
611 nir_ssa_def def
= instr
->def
;
613 midgard_constants
*consts
= rzalloc(NULL
, midgard_constants
);
615 assert(instr
->def
.num_components
* instr
->def
.bit_size
<= sizeof(*consts
) * 8);
617 #define RAW_CONST_COPY(bits) \
618 nir_const_value_to_array(consts->u##bits, instr->value, \
619 instr->def.num_components, u##bits)
621 switch (instr
->def
.bit_size
) {
635 unreachable("Invalid bit_size for load_const instruction\n");
638 /* Shifted for SSA, +1 for off-by-one */
639 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (def
.index
<< 1) + 1, consts
);
642 /* Normally constants are embedded implicitly, but for I/O and such we have to
643 * explicitly emit a move with the constant source */
646 emit_explicit_constant(compiler_context
*ctx
, unsigned node
, unsigned to
)
648 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, node
+ 1);
650 if (constant_value
) {
651 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), to
);
652 attach_constants(ctx
, &ins
, constant_value
, node
+ 1);
653 emit_mir_instruction(ctx
, ins
);
658 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
660 unsigned comp
= src
->swizzle
[0];
662 for (unsigned c
= 1; c
< nr_components
; ++c
) {
663 if (src
->swizzle
[c
] != comp
)
670 #define ATOMIC_CASE_IMPL(ctx, instr, nir, op, is_shared) \
671 case nir_intrinsic_##nir: \
672 emit_atomic(ctx, instr, is_shared, midgard_op_##op); \
675 #define ATOMIC_CASE(ctx, instr, nir, op) \
676 ATOMIC_CASE_IMPL(ctx, instr, shared_atomic_##nir, atomic_##op, true); \
677 ATOMIC_CASE_IMPL(ctx, instr, global_atomic_##nir, atomic_##op, false);
679 #define ALU_CASE(nir, _op) \
681 op = midgard_alu_op_##_op; \
682 assert(src_bitsize == dst_bitsize); \
685 #define ALU_CASE_RTZ(nir, _op) \
687 op = midgard_alu_op_##_op; \
688 roundmode = MIDGARD_RTZ; \
691 #define ALU_CHECK_CMP(sext) \
692 assert(src_bitsize == 16 || src_bitsize == 32); \
693 assert(dst_bitsize == 16 || dst_bitsize == 32); \
695 #define ALU_CASE_BCAST(nir, _op, count) \
697 op = midgard_alu_op_##_op; \
698 broadcast_swizzle = count; \
699 ALU_CHECK_CMP(true); \
702 #define ALU_CASE_CMP(nir, _op, sext) \
704 op = midgard_alu_op_##_op; \
705 ALU_CHECK_CMP(sext); \
708 /* Compare mir_lower_invert */
710 nir_accepts_inot(nir_op op
, unsigned src
)
714 case nir_op_iand
: /* TODO: b2f16 */
718 /* Only the condition */
726 mir_accept_dest_mod(compiler_context
*ctx
, nir_dest
**dest
, nir_op op
)
728 if (pan_has_dest_mod(dest
, op
)) {
729 assert((*dest
)->is_ssa
);
730 BITSET_SET(ctx
->already_emitted
, (*dest
)->ssa
.index
);
737 /* Look for floating point mods. We have the mods fsat, fsat_signed,
738 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
740 * fsat_signed(fpos(x)) = fsat(x)
741 * fsat_signed(fsat(x)) = fsat(x)
742 * fpos(fsat_signed(x)) = fsat(x)
743 * fpos(fsat(x)) = fsat(x)
744 * fsat(fsat_signed(x)) = fsat(x)
745 * fsat(fpos(x)) = fsat(x)
747 * So by cases any composition of output modifiers is equivalent to
751 mir_determine_float_outmod(compiler_context
*ctx
, nir_dest
**dest
, unsigned prior_outmod
)
753 bool fpos
= mir_accept_dest_mod(ctx
, dest
, nir_op_fclamp_pos
);
754 bool fsat
= mir_accept_dest_mod(ctx
, dest
, nir_op_fsat
);
755 bool ssat
= mir_accept_dest_mod(ctx
, dest
, nir_op_fsat_signed
);
756 bool prior
= (prior_outmod
!= midgard_outmod_none
);
757 int count
= (int) prior
+ (int) fpos
+ (int) ssat
+ (int) fsat
;
759 return ((count
> 1) || fsat
) ? midgard_outmod_sat
:
760 fpos
? midgard_outmod_pos
:
761 ssat
? midgard_outmod_sat_signed
:
766 mir_copy_src(midgard_instruction
*ins
, nir_alu_instr
*instr
, unsigned i
, unsigned to
, bool *abs
, bool *neg
, bool *not, enum midgard_roundmode
*roundmode
, bool is_int
, unsigned bcast_count
)
768 nir_alu_src src
= instr
->src
[i
];
771 if (pan_has_source_mod(&src
, nir_op_fneg
))
774 if (pan_has_source_mod(&src
, nir_op_fabs
))
778 if (nir_accepts_inot(instr
->op
, i
) && pan_has_source_mod(&src
, nir_op_inot
))
782 if (pan_has_source_mod(&src
, nir_op_fround_even
))
783 *roundmode
= MIDGARD_RTE
;
785 if (pan_has_source_mod(&src
, nir_op_ftrunc
))
786 *roundmode
= MIDGARD_RTZ
;
788 if (pan_has_source_mod(&src
, nir_op_ffloor
))
789 *roundmode
= MIDGARD_RTN
;
791 if (pan_has_source_mod(&src
, nir_op_fceil
))
792 *roundmode
= MIDGARD_RTP
;
795 unsigned bits
= nir_src_bit_size(src
.src
);
797 ins
->src
[to
] = nir_src_index(NULL
, &src
.src
);
798 ins
->src_types
[to
] = nir_op_infos
[instr
->op
].input_types
[i
] | bits
;
800 for (unsigned c
= 0; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
801 ins
->swizzle
[to
][c
] = src
.swizzle
[
802 (!bcast_count
|| c
< bcast_count
) ? c
:
807 /* Midgard features both fcsel and icsel, depending on whether you want int or
808 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
809 * we should emit an int or float csel depending on what modifiers could be
810 * placed. In the absense of modifiers, this is probably arbitrary. */
813 mir_is_bcsel_float(nir_alu_instr
*instr
)
816 nir_op_i2i8
, nir_op_i2i16
,
817 nir_op_i2i32
, nir_op_i2i64
820 nir_op floatmods
[] = {
821 nir_op_fabs
, nir_op_fneg
,
822 nir_op_f2f16
, nir_op_f2f32
,
826 nir_op floatdestmods
[] = {
827 nir_op_fsat
, nir_op_fsat_signed
, nir_op_fclamp_pos
,
828 nir_op_f2f16
, nir_op_f2f32
833 for (unsigned i
= 1; i
< 3; ++i
) {
834 nir_alu_src s
= instr
->src
[i
];
835 for (unsigned q
= 0; q
< ARRAY_SIZE(intmods
); ++q
) {
836 if (pan_has_source_mod(&s
, intmods
[q
]))
841 for (unsigned i
= 1; i
< 3; ++i
) {
842 nir_alu_src s
= instr
->src
[i
];
843 for (unsigned q
= 0; q
< ARRAY_SIZE(floatmods
); ++q
) {
844 if (pan_has_source_mod(&s
, floatmods
[q
]))
849 for (unsigned q
= 0; q
< ARRAY_SIZE(floatdestmods
); ++q
) {
850 nir_dest
*dest
= &instr
->dest
.dest
;
851 if (pan_has_dest_mod(&dest
, floatdestmods
[q
]))
859 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
861 nir_dest
*dest
= &instr
->dest
.dest
;
863 if (dest
->is_ssa
&& BITSET_TEST(ctx
->already_emitted
, dest
->ssa
.index
))
866 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
867 * is handled elsewhere */
869 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddy
) {
870 midgard_emit_derivatives(ctx
, instr
);
874 bool is_ssa
= dest
->is_ssa
;
876 unsigned nr_components
= nir_dest_num_components(*dest
);
877 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
880 /* Number of components valid to check for the instruction (the rest
881 * will be forced to the last), or 0 to use as-is. Relevant as
882 * ball-type instructions have a channel count in NIR but are all vec4
885 unsigned broadcast_swizzle
= 0;
887 /* Should we swap arguments? */
888 bool flip_src12
= false;
890 ASSERTED
unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
891 ASSERTED
unsigned dst_bitsize
= nir_dest_bit_size(*dest
);
893 enum midgard_roundmode roundmode
= MIDGARD_RTE
;
896 ALU_CASE(fadd
, fadd
);
897 ALU_CASE(fmul
, fmul
);
898 ALU_CASE(fmin
, fmin
);
899 ALU_CASE(fmax
, fmax
);
900 ALU_CASE(imin
, imin
);
901 ALU_CASE(imax
, imax
);
902 ALU_CASE(umin
, umin
);
903 ALU_CASE(umax
, umax
);
904 ALU_CASE(ffloor
, ffloor
);
905 ALU_CASE(fround_even
, froundeven
);
906 ALU_CASE(ftrunc
, ftrunc
);
907 ALU_CASE(fceil
, fceil
);
908 ALU_CASE(fdot3
, fdot3
);
909 ALU_CASE(fdot4
, fdot4
);
910 ALU_CASE(iadd
, iadd
);
911 ALU_CASE(isub
, isub
);
912 ALU_CASE(imul
, imul
);
913 ALU_CASE(imul_high
, imul
);
914 ALU_CASE(umul_high
, imul
);
916 /* Zero shoved as second-arg */
917 ALU_CASE(iabs
, iabsdiff
);
921 ALU_CASE_CMP(feq32
, feq
, false);
922 ALU_CASE_CMP(fneu32
, fne
, false);
923 ALU_CASE_CMP(flt32
, flt
, false);
924 ALU_CASE_CMP(ieq32
, ieq
, true);
925 ALU_CASE_CMP(ine32
, ine
, true);
926 ALU_CASE_CMP(ilt32
, ilt
, true);
927 ALU_CASE_CMP(ult32
, ult
, false);
929 /* We don't have a native b2f32 instruction. Instead, like many
930 * GPUs, we exploit booleans as 0/~0 for false/true, and
931 * correspondingly AND
932 * by 1.0 to do the type conversion. For the moment, prime us
935 * iand [whatever], #0
937 * At the end of emit_alu (as MIR), we'll fix-up the constant
940 ALU_CASE_CMP(b2f32
, iand
, true);
941 ALU_CASE_CMP(b2f16
, iand
, true);
942 ALU_CASE_CMP(b2i32
, iand
, true);
944 /* Likewise, we don't have a dedicated f2b32 instruction, but
945 * we can do a "not equal to 0.0" test. */
947 ALU_CASE_CMP(f2b32
, fne
, false);
948 ALU_CASE_CMP(i2b32
, ine
, true);
950 ALU_CASE(frcp
, frcp
);
951 ALU_CASE(frsq
, frsqrt
);
952 ALU_CASE(fsqrt
, fsqrt
);
953 ALU_CASE(fexp2
, fexp2
);
954 ALU_CASE(flog2
, flog2
);
956 ALU_CASE_RTZ(f2i64
, f2i_rte
);
957 ALU_CASE_RTZ(f2u64
, f2u_rte
);
958 ALU_CASE_RTZ(i2f64
, i2f_rte
);
959 ALU_CASE_RTZ(u2f64
, u2f_rte
);
961 ALU_CASE_RTZ(f2i32
, f2i_rte
);
962 ALU_CASE_RTZ(f2u32
, f2u_rte
);
963 ALU_CASE_RTZ(i2f32
, i2f_rte
);
964 ALU_CASE_RTZ(u2f32
, u2f_rte
);
966 ALU_CASE_RTZ(f2i8
, f2i_rte
);
967 ALU_CASE_RTZ(f2u8
, f2u_rte
);
969 ALU_CASE_RTZ(f2i16
, f2i_rte
);
970 ALU_CASE_RTZ(f2u16
, f2u_rte
);
971 ALU_CASE_RTZ(i2f16
, i2f_rte
);
972 ALU_CASE_RTZ(u2f16
, u2f_rte
);
974 ALU_CASE(fsin
, fsin
);
975 ALU_CASE(fcos
, fcos
);
977 /* We'll get 0 in the second arg, so:
978 * ~a = ~(a | 0) = nor(a, 0) */
979 ALU_CASE(inot
, inor
);
980 ALU_CASE(iand
, iand
);
982 ALU_CASE(ixor
, ixor
);
983 ALU_CASE(ishl
, ishl
);
984 ALU_CASE(ishr
, iasr
);
985 ALU_CASE(ushr
, ilsr
);
987 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
988 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
989 ALU_CASE_CMP(b32all_fequal4
, fball_eq
, true);
991 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
992 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
993 ALU_CASE_CMP(b32any_fnequal4
, fbany_neq
, true);
995 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
996 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
997 ALU_CASE_CMP(b32all_iequal4
, iball_eq
, true);
999 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
1000 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
1001 ALU_CASE_CMP(b32any_inequal4
, ibany_neq
, true);
1003 /* Source mods will be shoved in later */
1004 ALU_CASE(fabs
, fmov
);
1005 ALU_CASE(fneg
, fmov
);
1006 ALU_CASE(fsat
, fmov
);
1007 ALU_CASE(fsat_signed
, fmov
);
1008 ALU_CASE(fclamp_pos
, fmov
);
1010 /* For size conversion, we use a move. Ideally though we would squash
1011 * these ops together; maybe that has to happen after in NIR as part of
1012 * propagation...? An earlier algebraic pass ensured we step down by
1013 * only / exactly one size. If stepping down, we use a dest override to
1014 * reduce the size; if stepping up, we use a larger-sized move with a
1015 * half source and a sign/zero-extension modifier */
1027 case nir_op_f2f64
: {
1028 if (instr
->op
== nir_op_f2f16
|| instr
->op
== nir_op_f2f32
||
1029 instr
->op
== nir_op_f2f64
)
1030 op
= midgard_alu_op_fmov
;
1032 op
= midgard_alu_op_imov
;
1037 /* For greater-or-equal, we lower to less-or-equal and flip the
1043 case nir_op_uge32
: {
1045 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
1046 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
1047 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
1048 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
1052 ALU_CHECK_CMP(false);
1056 case nir_op_b32csel
: {
1057 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
1058 bool is_float
= mir_is_bcsel_float(instr
);
1060 (mixed
? midgard_alu_op_fcsel_v
: midgard_alu_op_fcsel
) :
1061 (mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
);
1066 case nir_op_unpack_32_2x16
:
1067 case nir_op_unpack_32_4x8
:
1068 case nir_op_pack_32_2x16
:
1069 case nir_op_pack_32_4x8
: {
1070 op
= midgard_alu_op_imov
;
1075 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1080 /* Promote imov to fmov if it might help inline a constant */
1081 if (op
== midgard_alu_op_imov
&& nir_src_is_const(instr
->src
[0].src
)
1082 && nir_src_bit_size(instr
->src
[0].src
) == 32
1083 && nir_is_same_comp_swizzle(instr
->src
[0].swizzle
,
1084 nir_src_num_components(instr
->src
[0].src
))) {
1085 op
= midgard_alu_op_fmov
;
1088 /* Midgard can perform certain modifiers on output of an ALU op */
1090 unsigned outmod
= 0;
1091 bool is_int
= midgard_is_integer_op(op
);
1093 if (instr
->op
== nir_op_umul_high
|| instr
->op
== nir_op_imul_high
) {
1094 outmod
= midgard_outmod_int_high
;
1095 } else if (midgard_is_integer_out_op(op
)) {
1096 outmod
= midgard_outmod_int_wrap
;
1097 } else if (instr
->op
== nir_op_fsat
) {
1098 outmod
= midgard_outmod_sat
;
1099 } else if (instr
->op
== nir_op_fsat_signed
) {
1100 outmod
= midgard_outmod_sat_signed
;
1101 } else if (instr
->op
== nir_op_fclamp_pos
) {
1102 outmod
= midgard_outmod_pos
;
1105 /* Fetch unit, quirks, etc information */
1106 unsigned opcode_props
= alu_opcode_props
[op
].props
;
1107 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1109 if (!midgard_is_integer_out_op(op
)) {
1110 outmod
= mir_determine_float_outmod(ctx
, &dest
, outmod
);
1113 midgard_instruction ins
= {
1115 .dest
= nir_dest_index(dest
),
1116 .dest_type
= nir_op_infos
[instr
->op
].output_type
1117 | nir_dest_bit_size(*dest
),
1118 .roundmode
= roundmode
,
1121 enum midgard_roundmode
*roundptr
= (opcode_props
& MIDGARD_ROUNDS
) ?
1122 &ins
.roundmode
: NULL
;
1124 for (unsigned i
= nr_inputs
; i
< ARRAY_SIZE(ins
.src
); ++i
)
1127 if (quirk_flipped_r24
) {
1129 mir_copy_src(&ins
, instr
, 0, 1, &ins
.src_abs
[1], &ins
.src_neg
[1], &ins
.src_invert
[1], roundptr
, is_int
, broadcast_swizzle
);
1131 for (unsigned i
= 0; i
< nr_inputs
; ++i
) {
1134 if (instr
->op
== nir_op_b32csel
) {
1135 /* The condition is the first argument; move
1136 * the other arguments up one to be a binary
1137 * instruction for Midgard with the condition
1142 else if (flip_src12
)
1146 } else if (flip_src12
) {
1150 mir_copy_src(&ins
, instr
, i
, to
, &ins
.src_abs
[to
], &ins
.src_neg
[to
], &ins
.src_invert
[to
], roundptr
, is_int
, broadcast_swizzle
);
1152 /* (!c) ? a : b = c ? b : a */
1153 if (instr
->op
== nir_op_b32csel
&& ins
.src_invert
[2]) {
1154 ins
.src_invert
[2] = false;
1160 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
1161 /* Lowered to move */
1162 if (instr
->op
== nir_op_fneg
)
1163 ins
.src_neg
[1] ^= true;
1165 if (instr
->op
== nir_op_fabs
)
1166 ins
.src_abs
[1] = true;
1169 ins
.mask
= mask_of(nr_components
);
1171 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1172 * components that don't exist. Note modifier => SSA => !reg => no
1173 * writemask, so we don't have to worry about writemasks here.*/
1176 ins
.mask
&= instr
->dest
.write_mask
;
1179 ins
.outmod
= outmod
;
1181 /* Late fixup for emulated instructions */
1183 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1184 /* Presently, our second argument is an inline #0 constant.
1185 * Switch over to an embedded 1.0 constant (that can't fit
1186 * inline, since we're 32-bit, not 16-bit like the inline
1189 ins
.has_inline_constant
= false;
1190 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1191 ins
.src_types
[1] = nir_type_float32
;
1192 ins
.has_constants
= true;
1194 if (instr
->op
== nir_op_b2f32
)
1195 ins
.constants
.f32
[0] = 1.0f
;
1197 ins
.constants
.i32
[0] = 1;
1199 for (unsigned c
= 0; c
< 16; ++c
)
1200 ins
.swizzle
[1][c
] = 0;
1201 } else if (instr
->op
== nir_op_b2f16
) {
1202 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1203 ins
.src_types
[1] = nir_type_float16
;
1204 ins
.has_constants
= true;
1205 ins
.constants
.i16
[0] = _mesa_float_to_half(1.0);
1207 for (unsigned c
= 0; c
< 16; ++c
)
1208 ins
.swizzle
[1][c
] = 0;
1209 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1210 /* Lots of instructions need a 0 plonked in */
1211 ins
.has_inline_constant
= false;
1212 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1213 ins
.src_types
[1] = ins
.src_types
[0];
1214 ins
.has_constants
= true;
1215 ins
.constants
.u32
[0] = 0;
1217 for (unsigned c
= 0; c
< 16; ++c
)
1218 ins
.swizzle
[1][c
] = 0;
1219 } else if (instr
->op
== nir_op_pack_32_2x16
) {
1220 ins
.dest_type
= nir_type_uint16
;
1221 ins
.mask
= mask_of(nr_components
* 2);
1223 } else if (instr
->op
== nir_op_pack_32_4x8
) {
1224 ins
.dest_type
= nir_type_uint8
;
1225 ins
.mask
= mask_of(nr_components
* 4);
1227 } else if (instr
->op
== nir_op_unpack_32_2x16
) {
1228 ins
.dest_type
= nir_type_uint32
;
1229 ins
.mask
= mask_of(nr_components
>> 1);
1231 } else if (instr
->op
== nir_op_unpack_32_4x8
) {
1232 ins
.dest_type
= nir_type_uint32
;
1233 ins
.mask
= mask_of(nr_components
>> 2);
1237 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1238 /* To avoid duplicating the lookup tables (probably), true LUT
1239 * instructions can only operate as if they were scalars. Lower
1240 * them here by changing the component. */
1242 unsigned orig_mask
= ins
.mask
;
1244 unsigned swizzle_back
[MIR_VEC_COMPONENTS
];
1245 memcpy(&swizzle_back
, ins
.swizzle
[0], sizeof(swizzle_back
));
1247 midgard_instruction ins_split
[MIR_VEC_COMPONENTS
];
1248 unsigned ins_count
= 0;
1250 for (int i
= 0; i
< nr_components
; ++i
) {
1251 /* Mask the associated component, dropping the
1252 * instruction if needed */
1255 ins
.mask
&= orig_mask
;
1257 for (unsigned j
= 0; j
< ins_count
; ++j
) {
1258 if (swizzle_back
[i
] == ins_split
[j
].swizzle
[0][0]) {
1259 ins_split
[j
].mask
|= ins
.mask
;
1268 for (unsigned j
= 0; j
< MIR_VEC_COMPONENTS
; ++j
)
1269 ins
.swizzle
[0][j
] = swizzle_back
[i
]; /* Pull from the correct component */
1271 ins_split
[ins_count
] = ins
;
1276 for (unsigned i
= 0; i
< ins_count
; ++i
) {
1277 emit_mir_instruction(ctx
, ins_split
[i
]);
1280 emit_mir_instruction(ctx
, ins
);
1287 mir_set_intr_mask(nir_instr
*instr
, midgard_instruction
*ins
, bool is_read
)
1289 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
1290 unsigned nir_mask
= 0;
1294 nir_mask
= mask_of(nir_intrinsic_dest_components(intr
));
1295 dsize
= nir_dest_bit_size(intr
->dest
);
1297 nir_mask
= nir_intrinsic_write_mask(intr
);
1301 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1302 unsigned bytemask
= pan_to_bytemask(dsize
, nir_mask
);
1303 ins
->dest_type
= nir_type_uint
| dsize
;
1304 mir_set_bytemask(ins
, bytemask
);
1307 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1308 * optimized) versions of UBO #0 */
1310 static midgard_instruction
*
1312 compiler_context
*ctx
,
1316 nir_src
*indirect_offset
,
1317 unsigned indirect_shift
,
1320 /* TODO: half-floats */
1322 midgard_instruction ins
= m_ld_ubo_int4(dest
, 0);
1323 ins
.constants
.u32
[0] = offset
;
1325 if (instr
->type
== nir_instr_type_intrinsic
)
1326 mir_set_intr_mask(instr
, &ins
, true);
1328 if (indirect_offset
) {
1329 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1330 ins
.src_types
[2] = nir_type_uint32
;
1331 ins
.load_store
.arg_2
= (indirect_shift
<< 5);
1333 /* X component for the whole swizzle to prevent register
1334 * pressure from ballooning from the extra components */
1335 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
.swizzle
[2]); ++i
)
1336 ins
.swizzle
[2][i
] = 0;
1338 ins
.load_store
.arg_2
= 0x1E;
1341 ins
.load_store
.arg_1
= index
;
1343 return emit_mir_instruction(ctx
, ins
);
1346 /* Globals are like UBOs if you squint. And shared memory is like globals if
1347 * you squint even harder */
1351 compiler_context
*ctx
,
1360 midgard_instruction ins
;
1363 ins
= m_ld_int4(srcdest
, 0);
1365 ins
= m_st_int4(srcdest
, 0);
1367 mir_set_offset(ctx
, &ins
, offset
, is_shared
);
1368 mir_set_intr_mask(instr
, &ins
, is_read
);
1370 /* Set a valid swizzle for masked out components */
1372 unsigned first_component
= __builtin_ffs(ins
.mask
) - 1;
1374 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
.swizzle
[0]); ++i
) {
1375 if (!(ins
.mask
& (1 << i
)))
1376 ins
.swizzle
[0][i
] = first_component
;
1379 emit_mir_instruction(ctx
, ins
);
1382 /* If is_shared is off, the only other possible value are globals, since
1383 * SSBO's are being lowered to globals through a NIR pass. */
1386 compiler_context
*ctx
,
1387 nir_intrinsic_instr
*instr
,
1389 midgard_load_store_op op
)
1391 unsigned bitsize
= nir_src_bit_size(instr
->src
[1]);
1393 (op
== midgard_op_atomic_imin
|| op
== midgard_op_atomic_imax
) ?
1394 nir_type_int
: nir_type_uint
;
1396 unsigned dest
= nir_dest_index(&instr
->dest
);
1397 unsigned val
= nir_src_index(ctx
, &instr
->src
[1]);
1398 emit_explicit_constant(ctx
, val
, val
);
1400 midgard_instruction ins
= {
1401 .type
= TAG_LOAD_STORE_4
,
1404 .src
= { ~0, ~0, ~0, val
},
1405 .src_types
= { 0, 0, 0, type
| bitsize
},
1409 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1411 /* cmpxchg takes an extra value in arg_2, so we don't use it for the offset */
1412 if (op
== midgard_op_atomic_cmpxchg
) {
1413 unsigned addr
= nir_src_index(ctx
, src_offset
);
1416 ins
.src_types
[1] = nir_type_uint
| nir_src_bit_size(*src_offset
);
1418 unsigned xchg_val
= nir_src_index(ctx
, &instr
->src
[2]);
1419 emit_explicit_constant(ctx
, xchg_val
, xchg_val
);
1422 ins
.src_types
[2] = type
| bitsize
;
1423 ins
.src
[3] = xchg_val
;
1426 ins
.load_store
.arg_1
|= 0x6E;
1428 mir_set_offset(ctx
, &ins
, src_offset
, is_shared
);
1431 mir_set_intr_mask(&instr
->instr
, &ins
, true);
1433 emit_mir_instruction(ctx
, ins
);
1438 compiler_context
*ctx
,
1439 unsigned dest
, unsigned offset
,
1440 unsigned nr_comp
, unsigned component
,
1441 nir_src
*indirect_offset
, nir_alu_type type
, bool flat
)
1443 /* XXX: Half-floats? */
1444 /* TODO: swizzle, mask */
1446 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1447 ins
.mask
= mask_of(nr_comp
);
1448 ins
.dest_type
= type
;
1450 if (type
== nir_type_float16
) {
1451 /* Ensure we are aligned so we can pack it later */
1452 ins
.mask
= mask_of(ALIGN_POT(nr_comp
, 2));
1455 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
.swizzle
[0]); ++i
)
1456 ins
.swizzle
[0][i
] = MIN2(i
+ component
, COMPONENT_W
);
1458 midgard_varying_parameter p
= {
1460 .interpolation
= midgard_interp_default
,
1465 memcpy(&u
, &p
, sizeof(p
));
1466 ins
.load_store
.varying_parameters
= u
;
1468 if (indirect_offset
) {
1469 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1470 ins
.src_types
[2] = nir_type_uint32
;
1472 ins
.load_store
.arg_2
= 0x1E;
1474 ins
.load_store
.arg_1
= 0x9E;
1476 /* Use the type appropriate load */
1478 case nir_type_uint32
:
1479 case nir_type_bool32
:
1480 ins
.op
= midgard_op_ld_vary_32u
;
1482 case nir_type_int32
:
1483 ins
.op
= midgard_op_ld_vary_32i
;
1485 case nir_type_float32
:
1486 ins
.op
= midgard_op_ld_vary_32
;
1488 case nir_type_float16
:
1489 ins
.op
= midgard_op_ld_vary_16
;
1492 unreachable("Attempted to load unknown type");
1496 emit_mir_instruction(ctx
, ins
);
1501 compiler_context
*ctx
,
1502 unsigned dest
, unsigned offset
,
1503 unsigned nr_comp
, nir_alu_type t
)
1505 midgard_instruction ins
= m_ld_attr_32(dest
, offset
);
1506 ins
.load_store
.arg_1
= 0x1E;
1507 ins
.load_store
.arg_2
= 0x1E;
1508 ins
.mask
= mask_of(nr_comp
);
1510 /* Use the type appropriate load */
1514 ins
.op
= midgard_op_ld_attr_32u
;
1517 ins
.op
= midgard_op_ld_attr_32i
;
1519 case nir_type_float
:
1520 ins
.op
= midgard_op_ld_attr_32
;
1523 unreachable("Attempted to load unknown type");
1527 emit_mir_instruction(ctx
, ins
);
1531 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
,
1532 unsigned nr_components
, unsigned offset
)
1536 /* Figure out which uniform this is */
1537 int sysval
= panfrost_sysval_for_instr(instr
, &nir_dest
);
1538 void *val
= _mesa_hash_table_u64_search(ctx
->sysvals
.sysval_to_id
, sysval
);
1540 unsigned dest
= nir_dest_index(&nir_dest
);
1542 /* Sysvals are prefix uniforms */
1543 unsigned uniform
= ((uintptr_t) val
) - 1;
1545 /* Emit the read itself -- this is never indirect */
1546 midgard_instruction
*ins
=
1547 emit_ubo_read(ctx
, instr
, dest
, (uniform
* 16) + offset
, NULL
, 0, 0);
1549 ins
->mask
= mask_of(nr_components
);
1553 compute_builtin_arg(nir_op op
)
1556 case nir_intrinsic_load_work_group_id
:
1558 case nir_intrinsic_load_local_invocation_id
:
1561 unreachable("Invalid compute paramater loaded");
1566 emit_fragment_store(compiler_context
*ctx
, unsigned src
, unsigned src_z
, unsigned src_s
, enum midgard_rt_id rt
)
1568 assert(rt
< ARRAY_SIZE(ctx
->writeout_branch
));
1570 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
1574 emit_explicit_constant(ctx
, src
, src
);
1576 struct midgard_instruction ins
=
1577 v_branch(false, false);
1579 bool depth_only
= (rt
== MIDGARD_ZS_RT
);
1581 ins
.writeout
= depth_only
? 0 : PAN_WRITEOUT_C
;
1583 /* Add dependencies */
1585 ins
.src_types
[0] = nir_type_uint32
;
1586 ins
.constants
.u32
[0] = depth_only
? 0xFF : (rt
- MIDGARD_COLOR_RT0
) * 0x100;
1587 for (int i
= 0; i
< 4; ++i
)
1588 ins
.swizzle
[0][i
] = i
;
1591 emit_explicit_constant(ctx
, src_z
, src_z
);
1593 ins
.src_types
[2] = nir_type_uint32
;
1594 ins
.writeout
|= PAN_WRITEOUT_Z
;
1597 emit_explicit_constant(ctx
, src_s
, src_s
);
1599 ins
.src_types
[3] = nir_type_uint32
;
1600 ins
.writeout
|= PAN_WRITEOUT_S
;
1603 /* Emit the branch */
1604 br
= emit_mir_instruction(ctx
, ins
);
1605 schedule_barrier(ctx
);
1606 ctx
->writeout_branch
[rt
] = br
;
1608 /* Push our current location = current block count - 1 = where we'll
1609 * jump to. Maybe a bit too clever for my own good */
1611 br
->branch
.target_block
= ctx
->block_count
- 1;
1615 emit_compute_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1617 unsigned reg
= nir_dest_index(&instr
->dest
);
1618 midgard_instruction ins
= m_ld_compute_id(reg
, 0);
1619 ins
.mask
= mask_of(3);
1620 ins
.swizzle
[0][3] = COMPONENT_X
; /* xyzx */
1621 ins
.load_store
.arg_1
= compute_builtin_arg(instr
->intrinsic
);
1622 emit_mir_instruction(ctx
, ins
);
1626 vertex_builtin_arg(nir_op op
)
1629 case nir_intrinsic_load_vertex_id
:
1630 return PAN_VERTEX_ID
;
1631 case nir_intrinsic_load_instance_id
:
1632 return PAN_INSTANCE_ID
;
1634 unreachable("Invalid vertex builtin");
1639 emit_vertex_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1641 unsigned reg
= nir_dest_index(&instr
->dest
);
1642 emit_attr_read(ctx
, reg
, vertex_builtin_arg(instr
->intrinsic
), 1, nir_type_int
);
1646 emit_special(compiler_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned idx
)
1648 unsigned reg
= nir_dest_index(&instr
->dest
);
1650 midgard_instruction ld
= m_ld_color_buffer_32u(reg
, 0);
1651 ld
.op
= midgard_op_ld_color_buffer_32u_old
;
1652 ld
.load_store
.address
= idx
;
1653 ld
.load_store
.arg_2
= 0x1E;
1655 for (int i
= 0; i
< 4; ++i
)
1656 ld
.swizzle
[0][i
] = COMPONENT_X
;
1658 emit_mir_instruction(ctx
, ld
);
1662 emit_control_barrier(compiler_context
*ctx
)
1664 midgard_instruction ins
= {
1665 .type
= TAG_TEXTURE_4
,
1667 .src
= { ~0, ~0, ~0, ~0 },
1668 .op
= TEXTURE_OP_BARRIER
,
1671 emit_mir_instruction(ctx
, ins
);
1675 mir_get_branch_cond(nir_src
*src
, bool *invert
)
1677 /* Wrap it. No swizzle since it's a scalar */
1683 *invert
= pan_has_source_mod(&alu
, nir_op_inot
);
1684 return nir_src_index(NULL
, &alu
.src
);
1688 output_load_rt_addr(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1691 return ctx
->blend_rt
;
1693 const nir_variable
*var
;
1694 var
= search_var(ctx
->nir
, nir_var_shader_out
, nir_intrinsic_base(instr
));
1697 unsigned loc
= var
->data
.location
;
1699 if (loc
== FRAG_RESULT_COLOR
)
1700 loc
= FRAG_RESULT_DATA0
;
1702 if (loc
>= FRAG_RESULT_DATA0
)
1703 return loc
- FRAG_RESULT_DATA0
;
1705 if (loc
== FRAG_RESULT_DEPTH
)
1707 if (loc
== FRAG_RESULT_STENCIL
)
1710 unreachable("Invalid RT to load from");
1714 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1716 unsigned offset
= 0, reg
;
1718 switch (instr
->intrinsic
) {
1719 case nir_intrinsic_discard_if
:
1720 case nir_intrinsic_discard
: {
1721 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1722 struct midgard_instruction discard
= v_branch(conditional
, false);
1723 discard
.branch
.target_type
= TARGET_DISCARD
;
1726 discard
.src
[0] = mir_get_branch_cond(&instr
->src
[0],
1727 &discard
.branch
.invert_conditional
);
1728 discard
.src_types
[0] = nir_type_uint32
;
1731 emit_mir_instruction(ctx
, discard
);
1732 schedule_barrier(ctx
);
1737 case nir_intrinsic_load_uniform
:
1738 case nir_intrinsic_load_ubo
:
1739 case nir_intrinsic_load_global
:
1740 case nir_intrinsic_load_shared
:
1741 case nir_intrinsic_load_input
:
1742 case nir_intrinsic_load_interpolated_input
: {
1743 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1744 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1745 bool is_global
= instr
->intrinsic
== nir_intrinsic_load_global
;
1746 bool is_shared
= instr
->intrinsic
== nir_intrinsic_load_shared
;
1747 bool is_flat
= instr
->intrinsic
== nir_intrinsic_load_input
;
1748 bool is_interp
= instr
->intrinsic
== nir_intrinsic_load_interpolated_input
;
1750 /* Get the base type of the intrinsic */
1751 /* TODO: Infer type? Does it matter? */
1753 (is_ubo
|| is_global
|| is_shared
) ? nir_type_uint
:
1754 (is_interp
) ? nir_type_float
:
1755 nir_intrinsic_type(instr
);
1757 t
= nir_alu_type_get_base_type(t
);
1759 if (!(is_ubo
|| is_global
)) {
1760 offset
= nir_intrinsic_base(instr
);
1763 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1765 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1767 bool direct
= nir_src_is_const(*src_offset
);
1768 nir_src
*indirect_offset
= direct
? NULL
: src_offset
;
1771 offset
+= nir_src_as_uint(*src_offset
);
1773 /* We may need to apply a fractional offset */
1774 int component
= (is_flat
|| is_interp
) ?
1775 nir_intrinsic_component(instr
) : 0;
1776 reg
= nir_dest_index(&instr
->dest
);
1778 if (is_uniform
&& !ctx
->is_blend
) {
1779 emit_ubo_read(ctx
, &instr
->instr
, reg
, (ctx
->sysvals
.sysval_count
+ offset
) * 16, indirect_offset
, 4, 0);
1780 } else if (is_ubo
) {
1781 nir_src index
= instr
->src
[0];
1783 /* TODO: Is indirect block number possible? */
1784 assert(nir_src_is_const(index
));
1786 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1787 emit_ubo_read(ctx
, &instr
->instr
, reg
, offset
, indirect_offset
, 0, uindex
);
1788 } else if (is_global
|| is_shared
) {
1789 emit_global(ctx
, &instr
->instr
, true, reg
, src_offset
, is_shared
);
1790 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1791 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, indirect_offset
, t
| nir_dest_bit_size(instr
->dest
), is_flat
);
1792 } else if (ctx
->is_blend
) {
1793 /* ctx->blend_input will be precoloured to r0/r2, where
1794 * the input is preloaded */
1796 unsigned *input
= offset
? &ctx
->blend_src1
: &ctx
->blend_input
;
1801 emit_mir_instruction(ctx
, v_mov(*input
, reg
));
1802 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1803 emit_attr_read(ctx
, reg
, offset
, nr_comp
, t
);
1805 DBG("Unknown load\n");
1812 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1813 case nir_intrinsic_load_barycentric_pixel
:
1814 case nir_intrinsic_load_barycentric_centroid
:
1817 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1819 case nir_intrinsic_load_raw_output_pan
: {
1820 reg
= nir_dest_index(&instr
->dest
);
1822 /* T720 and below use different blend opcodes with slightly
1823 * different semantics than T760 and up */
1825 midgard_instruction ld
= m_ld_color_buffer_32u(reg
, 0);
1827 ld
.load_store
.arg_2
= output_load_rt_addr(ctx
, instr
);
1829 if (nir_src_is_const(instr
->src
[0])) {
1830 ld
.load_store
.arg_1
= nir_src_as_uint(instr
->src
[0]);
1832 ld
.load_store
.varying_parameters
= 2;
1833 ld
.src
[1] = nir_src_index(ctx
, &instr
->src
[0]);
1834 ld
.src_types
[1] = nir_type_int32
;
1837 if (ctx
->quirks
& MIDGARD_OLD_BLEND
) {
1838 ld
.op
= midgard_op_ld_color_buffer_32u_old
;
1839 ld
.load_store
.address
= 16;
1840 ld
.load_store
.arg_2
= 0x1E;
1843 emit_mir_instruction(ctx
, ld
);
1847 case nir_intrinsic_load_output
: {
1848 reg
= nir_dest_index(&instr
->dest
);
1850 unsigned bits
= nir_dest_bit_size(instr
->dest
);
1852 midgard_instruction ld
;
1854 ld
= m_ld_color_buffer_as_fp16(reg
, 0);
1856 ld
= m_ld_color_buffer_as_fp32(reg
, 0);
1858 ld
.load_store
.arg_2
= output_load_rt_addr(ctx
, instr
);
1860 for (unsigned c
= 4; c
< 16; ++c
)
1861 ld
.swizzle
[0][c
] = 0;
1863 if (ctx
->quirks
& MIDGARD_OLD_BLEND
) {
1865 ld
.op
= midgard_op_ld_color_buffer_as_fp16_old
;
1867 ld
.op
= midgard_op_ld_color_buffer_as_fp32_old
;
1868 ld
.load_store
.address
= 1;
1869 ld
.load_store
.arg_2
= 0x1E;
1872 emit_mir_instruction(ctx
, ld
);
1876 case nir_intrinsic_load_blend_const_color_rgba
: {
1877 assert(ctx
->is_blend
);
1878 reg
= nir_dest_index(&instr
->dest
);
1880 /* Blend constants are embedded directly in the shader and
1881 * patched in, so we use some magic routing */
1883 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), reg
);
1884 ins
.has_constants
= true;
1885 ins
.has_blend_constant
= true;
1886 emit_mir_instruction(ctx
, ins
);
1890 case nir_intrinsic_store_output
:
1891 case nir_intrinsic_store_combined_output_pan
:
1892 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1894 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1896 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1898 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1899 bool combined
= instr
->intrinsic
==
1900 nir_intrinsic_store_combined_output_pan
;
1902 const nir_variable
*var
;
1903 var
= search_var(ctx
->nir
, nir_var_shader_out
,
1904 nir_intrinsic_base(instr
));
1907 /* Dual-source blend writeout is done by leaving the
1908 * value in r2 for the blend shader to use. */
1909 if (var
->data
.index
) {
1910 if (instr
->src
[0].is_ssa
) {
1911 emit_explicit_constant(ctx
, reg
, reg
);
1913 unsigned out
= make_compiler_temp(ctx
);
1915 midgard_instruction ins
= v_mov(reg
, out
);
1916 emit_mir_instruction(ctx
, ins
);
1918 ctx
->blend_src1
= out
;
1920 ctx
->blend_src1
= reg
;
1926 enum midgard_rt_id rt
;
1927 if (var
->data
.location
== FRAG_RESULT_COLOR
)
1928 rt
= MIDGARD_COLOR_RT0
;
1929 else if (var
->data
.location
>= FRAG_RESULT_DATA0
)
1930 rt
= MIDGARD_COLOR_RT0
+ var
->data
.location
-
1935 unreachable("bad rt");
1937 unsigned reg_z
= ~0, reg_s
= ~0;
1939 unsigned writeout
= nir_intrinsic_component(instr
);
1940 if (writeout
& PAN_WRITEOUT_Z
)
1941 reg_z
= nir_src_index(ctx
, &instr
->src
[2]);
1942 if (writeout
& PAN_WRITEOUT_S
)
1943 reg_s
= nir_src_index(ctx
, &instr
->src
[3]);
1946 emit_fragment_store(ctx
, reg
, reg_z
, reg_s
, rt
);
1947 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1948 assert(instr
->intrinsic
== nir_intrinsic_store_output
);
1950 /* We should have been vectorized, though we don't
1951 * currently check that st_vary is emitted only once
1952 * per slot (this is relevant, since there's not a mask
1953 * parameter available on the store [set to 0 by the
1954 * blob]). We do respect the component by adjusting the
1955 * swizzle. If this is a constant source, we'll need to
1956 * emit that explicitly. */
1958 emit_explicit_constant(ctx
, reg
, reg
);
1960 unsigned dst_component
= nir_intrinsic_component(instr
);
1961 unsigned nr_comp
= nir_src_num_components(instr
->src
[0]);
1963 midgard_instruction st
= m_st_vary_32(reg
, offset
);
1964 st
.load_store
.arg_1
= 0x9E;
1965 st
.load_store
.arg_2
= 0x1E;
1967 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr
))) {
1970 st
.op
= midgard_op_st_vary_32u
;
1973 st
.op
= midgard_op_st_vary_32i
;
1975 case nir_type_float
:
1976 st
.op
= midgard_op_st_vary_32
;
1979 unreachable("Attempted to store unknown type");
1983 /* nir_intrinsic_component(store_intr) encodes the
1984 * destination component start. Source component offset
1985 * adjustment is taken care of in
1986 * install_registers_instr(), when offset_swizzle() is
1989 unsigned src_component
= COMPONENT_X
;
1991 assert(nr_comp
> 0);
1992 for (unsigned i
= 0; i
< ARRAY_SIZE(st
.swizzle
); ++i
) {
1993 st
.swizzle
[0][i
] = src_component
;
1994 if (i
>= dst_component
&& i
< dst_component
+ nr_comp
- 1)
1998 emit_mir_instruction(ctx
, st
);
2000 DBG("Unknown store\n");
2006 /* Special case of store_output for lowered blend shaders */
2007 case nir_intrinsic_store_raw_output_pan
:
2008 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
2009 reg
= nir_src_index(ctx
, &instr
->src
[0]);
2010 emit_fragment_store(ctx
, reg
, ~0, ~0, ctx
->blend_rt
);
2013 case nir_intrinsic_store_global
:
2014 case nir_intrinsic_store_shared
:
2015 reg
= nir_src_index(ctx
, &instr
->src
[0]);
2016 emit_explicit_constant(ctx
, reg
, reg
);
2018 emit_global(ctx
, &instr
->instr
, false, reg
, &instr
->src
[1], instr
->intrinsic
== nir_intrinsic_store_shared
);
2021 case nir_intrinsic_load_ssbo_address
:
2022 emit_sysval_read(ctx
, &instr
->instr
, 1, 0);
2025 case nir_intrinsic_get_buffer_size
:
2026 emit_sysval_read(ctx
, &instr
->instr
, 1, 8);
2029 case nir_intrinsic_load_viewport_scale
:
2030 case nir_intrinsic_load_viewport_offset
:
2031 case nir_intrinsic_load_num_work_groups
:
2032 case nir_intrinsic_load_sampler_lod_parameters_pan
:
2033 emit_sysval_read(ctx
, &instr
->instr
, 3, 0);
2036 case nir_intrinsic_load_work_group_id
:
2037 case nir_intrinsic_load_local_invocation_id
:
2038 emit_compute_builtin(ctx
, instr
);
2041 case nir_intrinsic_load_vertex_id
:
2042 case nir_intrinsic_load_instance_id
:
2043 emit_vertex_builtin(ctx
, instr
);
2046 case nir_intrinsic_load_sample_mask_in
:
2047 emit_special(ctx
, instr
, 96);
2050 case nir_intrinsic_load_sample_id
:
2051 emit_special(ctx
, instr
, 97);
2054 case nir_intrinsic_memory_barrier_buffer
:
2055 case nir_intrinsic_memory_barrier_shared
:
2058 case nir_intrinsic_control_barrier
:
2059 schedule_barrier(ctx
);
2060 emit_control_barrier(ctx
);
2061 schedule_barrier(ctx
);
2064 ATOMIC_CASE(ctx
, instr
, add
, add
);
2065 ATOMIC_CASE(ctx
, instr
, and, and);
2066 ATOMIC_CASE(ctx
, instr
, comp_swap
, cmpxchg
);
2067 ATOMIC_CASE(ctx
, instr
, exchange
, xchg
);
2068 ATOMIC_CASE(ctx
, instr
, imax
, imax
);
2069 ATOMIC_CASE(ctx
, instr
, imin
, imin
);
2070 ATOMIC_CASE(ctx
, instr
, or, or);
2071 ATOMIC_CASE(ctx
, instr
, umax
, umax
);
2072 ATOMIC_CASE(ctx
, instr
, umin
, umin
);
2073 ATOMIC_CASE(ctx
, instr
, xor, xor);
2076 fprintf(stderr
, "Unhandled intrinsic %s\n", nir_intrinsic_infos
[instr
->intrinsic
].name
);
2082 /* Returns dimension with 0 special casing cubemaps */
2084 midgard_tex_format(enum glsl_sampler_dim dim
)
2087 case GLSL_SAMPLER_DIM_1D
:
2088 case GLSL_SAMPLER_DIM_BUF
:
2091 case GLSL_SAMPLER_DIM_2D
:
2092 case GLSL_SAMPLER_DIM_MS
:
2093 case GLSL_SAMPLER_DIM_EXTERNAL
:
2094 case GLSL_SAMPLER_DIM_RECT
:
2097 case GLSL_SAMPLER_DIM_3D
:
2100 case GLSL_SAMPLER_DIM_CUBE
:
2104 DBG("Unknown sampler dim type\n");
2110 /* Tries to attach an explicit LOD or bias as a constant. Returns whether this
2114 pan_attach_constant_bias(
2115 compiler_context
*ctx
,
2117 midgard_texture_word
*word
)
2119 /* To attach as constant, it has to *be* constant */
2121 if (!nir_src_is_const(lod
))
2124 float f
= nir_src_as_float(lod
);
2126 /* Break into fixed-point */
2128 float lod_frac
= f
- lod_int
;
2130 /* Carry over negative fractions */
2131 if (lod_frac
< 0.0) {
2137 word
->bias
= float_to_ubyte(lod_frac
);
2138 word
->bias_int
= lod_int
;
2143 static enum mali_texture_mode
2144 mdg_texture_mode(nir_tex_instr
*instr
)
2146 if (instr
->op
== nir_texop_tg4
&& instr
->is_shadow
)
2147 return TEXTURE_GATHER_SHADOW
;
2148 else if (instr
->op
== nir_texop_tg4
)
2149 return TEXTURE_GATHER_X
+ instr
->component
;
2150 else if (instr
->is_shadow
)
2151 return TEXTURE_SHADOW
;
2153 return TEXTURE_NORMAL
;
2157 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
2158 unsigned midgard_texop
)
2161 //assert (!instr->sampler);
2163 nir_dest
*dest
= &instr
->dest
;
2165 int texture_index
= instr
->texture_index
;
2166 int sampler_index
= texture_index
;
2168 nir_alu_type dest_base
= nir_alu_type_get_base_type(instr
->dest_type
);
2169 nir_alu_type dest_type
= dest_base
| nir_dest_bit_size(*dest
);
2171 /* texture instructions support float outmods */
2172 unsigned outmod
= midgard_outmod_none
;
2173 if (dest_base
== nir_type_float
) {
2174 outmod
= mir_determine_float_outmod(ctx
, &dest
, 0);
2177 midgard_instruction ins
= {
2178 .type
= TAG_TEXTURE_4
,
2180 .dest
= nir_dest_index(dest
),
2181 .src
= { ~0, ~0, ~0, ~0 },
2182 .dest_type
= dest_type
,
2183 .swizzle
= SWIZZLE_IDENTITY_4
,
2185 .op
= midgard_texop
,
2187 .format
= midgard_tex_format(instr
->sampler_dim
),
2188 .texture_handle
= texture_index
,
2189 .sampler_handle
= sampler_index
,
2190 .mode
= mdg_texture_mode(instr
)
2194 if (instr
->is_shadow
&& !instr
->is_new_style_shadow
&& instr
->op
!= nir_texop_tg4
)
2195 for (int i
= 0; i
< 4; ++i
)
2196 ins
.swizzle
[0][i
] = COMPONENT_X
;
2198 /* We may need a temporary for the coordinate */
2200 bool needs_temp_coord
=
2201 (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) ||
2202 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) ||
2205 unsigned coords
= needs_temp_coord
? make_compiler_temp_reg(ctx
) : 0;
2207 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
2208 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
2209 unsigned nr_components
= nir_src_num_components(instr
->src
[i
].src
);
2210 unsigned sz
= nir_src_bit_size(instr
->src
[i
].src
);
2211 nir_alu_type T
= nir_tex_instr_src_type(instr
, i
) | sz
;
2213 switch (instr
->src
[i
].src_type
) {
2214 case nir_tex_src_coord
: {
2215 emit_explicit_constant(ctx
, index
, index
);
2217 unsigned coord_mask
= mask_of(instr
->coord_components
);
2219 bool flip_zw
= (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) && (coord_mask
& (1 << COMPONENT_Z
));
2222 coord_mask
^= ((1 << COMPONENT_Z
) | (1 << COMPONENT_W
));
2224 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2225 /* texelFetch is undefined on samplerCube */
2226 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
2228 /* For cubemaps, we use a special ld/st op to
2229 * select the face and copy the xy into the
2230 * texture register */
2232 midgard_instruction ld
= m_ld_cubemap_coords(coords
, 0);
2234 ld
.src_types
[1] = T
;
2235 ld
.mask
= 0x3; /* xy */
2236 ld
.load_store
.arg_1
= 0x20;
2237 ld
.swizzle
[1][3] = COMPONENT_X
;
2238 emit_mir_instruction(ctx
, ld
);
2241 ins
.swizzle
[1][2] = instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
2242 ins
.swizzle
[1][3] = COMPONENT_X
;
2243 } else if (needs_temp_coord
) {
2244 /* mov coord_temp, coords */
2245 midgard_instruction mov
= v_mov(index
, coords
);
2246 mov
.mask
= coord_mask
;
2249 mov
.swizzle
[1][COMPONENT_W
] = COMPONENT_Z
;
2251 emit_mir_instruction(ctx
, mov
);
2256 ins
.src
[1] = coords
;
2257 ins
.src_types
[1] = T
;
2259 /* Texelfetch coordinates uses all four elements
2260 * (xyz/index) regardless of texture dimensionality,
2261 * which means it's necessary to zero the unused
2262 * components to keep everything happy */
2264 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
2265 /* mov index.zw, #0, or generalized */
2266 midgard_instruction mov
=
2267 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), coords
);
2268 mov
.has_constants
= true;
2269 mov
.mask
= coord_mask
^ 0xF;
2270 emit_mir_instruction(ctx
, mov
);
2273 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) {
2274 /* Array component in w but NIR wants it in z,
2275 * but if we have a temp coord we already fixed
2278 if (nr_components
== 3) {
2279 ins
.swizzle
[1][2] = COMPONENT_Z
;
2280 ins
.swizzle
[1][3] = needs_temp_coord
? COMPONENT_W
: COMPONENT_Z
;
2281 } else if (nr_components
== 2) {
2283 instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
2284 ins
.swizzle
[1][3] = COMPONENT_X
;
2286 unreachable("Invalid texture 2D components");
2289 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
2291 ins
.swizzle
[1][2] = COMPONENT_Z
;
2292 ins
.swizzle
[1][3] = COMPONENT_W
;
2298 case nir_tex_src_bias
:
2299 case nir_tex_src_lod
: {
2300 /* Try as a constant if we can */
2302 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
2303 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
2306 ins
.texture
.lod_register
= true;
2308 ins
.src_types
[2] = T
;
2310 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
2311 ins
.swizzle
[2][c
] = COMPONENT_X
;
2313 emit_explicit_constant(ctx
, index
, index
);
2318 case nir_tex_src_offset
: {
2319 ins
.texture
.offset_register
= true;
2321 ins
.src_types
[3] = T
;
2323 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
2324 ins
.swizzle
[3][c
] = (c
> COMPONENT_Z
) ? 0 : c
;
2326 emit_explicit_constant(ctx
, index
, index
);
2330 case nir_tex_src_comparator
:
2331 case nir_tex_src_ms_index
: {
2332 unsigned comp
= COMPONENT_Z
;
2334 /* mov coord_temp.foo, coords */
2335 midgard_instruction mov
= v_mov(index
, coords
);
2336 mov
.mask
= 1 << comp
;
2338 for (unsigned i
= 0; i
< MIR_VEC_COMPONENTS
; ++i
)
2339 mov
.swizzle
[1][i
] = COMPONENT_X
;
2341 emit_mir_instruction(ctx
, mov
);
2346 fprintf(stderr
, "Unknown texture source type: %d\n", instr
->src
[i
].src_type
);
2352 emit_mir_instruction(ctx
, ins
);
2356 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
2358 switch (instr
->op
) {
2361 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
2365 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
2368 case nir_texop_txf_ms
:
2369 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
2372 emit_sysval_read(ctx
, &instr
->instr
, 4, 0);
2375 fprintf(stderr
, "Unhandled texture op: %d\n", instr
->op
);
2382 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
2384 switch (instr
->type
) {
2385 case nir_jump_break
: {
2386 /* Emit a branch out of the loop */
2387 struct midgard_instruction br
= v_branch(false, false);
2388 br
.branch
.target_type
= TARGET_BREAK
;
2389 br
.branch
.target_break
= ctx
->current_loop_depth
;
2390 emit_mir_instruction(ctx
, br
);
2395 DBG("Unknown jump type %d\n", instr
->type
);
2401 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
2403 switch (instr
->type
) {
2404 case nir_instr_type_load_const
:
2405 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2408 case nir_instr_type_intrinsic
:
2409 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2412 case nir_instr_type_alu
:
2413 emit_alu(ctx
, nir_instr_as_alu(instr
));
2416 case nir_instr_type_tex
:
2417 emit_tex(ctx
, nir_instr_as_tex(instr
));
2420 case nir_instr_type_jump
:
2421 emit_jump(ctx
, nir_instr_as_jump(instr
));
2424 case nir_instr_type_ssa_undef
:
2429 DBG("Unhandled instruction type\n");
2435 /* ALU instructions can inline or embed constants, which decreases register
2436 * pressure and saves space. */
2438 #define CONDITIONAL_ATTACH(idx) { \
2439 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2442 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2443 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2448 inline_alu_constants(compiler_context
*ctx
, midgard_block
*block
)
2450 mir_foreach_instr_in_block(block
, alu
) {
2451 /* Other instructions cannot inline constants */
2452 if (alu
->type
!= TAG_ALU_4
) continue;
2453 if (alu
->compact_branch
) continue;
2455 /* If there is already a constant here, we can do nothing */
2456 if (alu
->has_constants
) continue;
2458 CONDITIONAL_ATTACH(0);
2460 if (!alu
->has_constants
) {
2461 CONDITIONAL_ATTACH(1)
2462 } else if (!alu
->inline_constant
) {
2463 /* Corner case: _two_ vec4 constants, for instance with a
2464 * csel. For this case, we can only use a constant
2465 * register for one, we'll have to emit a move for the
2468 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->src
[1] + 1);
2469 unsigned scratch
= make_compiler_temp(ctx
);
2472 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), scratch
);
2473 attach_constants(ctx
, &ins
, entry
, alu
->src
[1] + 1);
2475 /* Set the source */
2476 alu
->src
[1] = scratch
;
2478 /* Inject us -before- the last instruction which set r31 */
2479 mir_insert_instruction_before(ctx
, mir_prev_op(alu
), ins
);
2486 max_bitsize_for_alu(midgard_instruction
*ins
)
2488 unsigned max_bitsize
= 0;
2489 for (int i
= 0; i
< MIR_SRC_COUNT
; i
++) {
2490 if (ins
->src
[i
] == ~0) continue;
2491 unsigned src_bitsize
= nir_alu_type_get_type_size(ins
->src_types
[i
]);
2492 max_bitsize
= MAX2(src_bitsize
, max_bitsize
);
2494 unsigned dst_bitsize
= nir_alu_type_get_type_size(ins
->dest_type
);
2495 max_bitsize
= MAX2(dst_bitsize
, max_bitsize
);
2497 /* We don't have fp16 LUTs, so we'll want to emit code like:
2499 * vlut.fsinr hr0, hr0
2501 * where both input and output are 16-bit but the operation is carried
2506 case midgard_alu_op_fsqrt
:
2507 case midgard_alu_op_frcp
:
2508 case midgard_alu_op_frsqrt
:
2509 case midgard_alu_op_fsin
:
2510 case midgard_alu_op_fcos
:
2511 case midgard_alu_op_fexp2
:
2512 case midgard_alu_op_flog2
:
2513 max_bitsize
= MAX2(max_bitsize
, 32);
2520 /* High implies computing at a higher bitsize, e.g umul_high of 32-bit
2521 * requires computing at 64-bit */
2522 if (midgard_is_integer_out_op(ins
->op
) && ins
->outmod
== midgard_outmod_int_high
) {
2524 assert(max_bitsize
<= 64);
2531 reg_mode_for_bitsize(unsigned bitsize
)
2534 /* use 16 pipe for 8 since we don't support vec16 yet */
2537 return midgard_reg_mode_16
;
2539 return midgard_reg_mode_32
;
2541 return midgard_reg_mode_64
;
2543 unreachable("invalid bit size");
2547 /* Midgard supports two types of constants, embedded constants (128-bit) and
2548 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2549 * constants can be demoted to inline constants, for space savings and
2550 * sometimes a performance boost */
2553 embedded_to_inline_constant(compiler_context
*ctx
, midgard_block
*block
)
2555 mir_foreach_instr_in_block(block
, ins
) {
2556 if (!ins
->has_constants
) continue;
2557 if (ins
->has_inline_constant
) continue;
2559 /* Blend constants must not be inlined by definition */
2560 if (ins
->has_blend_constant
) continue;
2562 unsigned max_bitsize
= max_bitsize_for_alu(ins
);
2564 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2565 bool is_16
= max_bitsize
== 16;
2566 bool is_32
= max_bitsize
== 32;
2568 if (!(is_16
|| is_32
))
2571 /* src1 cannot be an inline constant due to encoding
2572 * restrictions. So, if possible we try to flip the arguments
2577 if (ins
->src
[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
) &&
2578 alu_opcode_props
[op
].props
& OP_COMMUTES
) {
2582 if (ins
->src
[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2583 /* Component is from the swizzle. Take a nonzero component */
2585 unsigned first_comp
= ffs(ins
->mask
) - 1;
2586 unsigned component
= ins
->swizzle
[1][first_comp
];
2588 /* Scale constant appropriately, if we can legally */
2589 int16_t scaled_constant
= 0;
2592 scaled_constant
= ins
->constants
.u16
[component
];
2593 } else if (midgard_is_integer_op(op
)) {
2594 scaled_constant
= ins
->constants
.u32
[component
];
2596 /* Constant overflow after resize */
2597 if (scaled_constant
!= ins
->constants
.u32
[component
])
2600 float original
= ins
->constants
.f32
[component
];
2601 scaled_constant
= _mesa_float_to_half(original
);
2603 /* Check for loss of precision. If this is
2604 * mediump, we don't care, but for a highp
2605 * shader, we need to pay attention. NIR
2606 * doesn't yet tell us which mode we're in!
2607 * Practically this prevents most constants
2608 * from being inlined, sadly. */
2610 float fp32
= _mesa_half_to_float(scaled_constant
);
2612 if (fp32
!= original
)
2616 /* Should've been const folded */
2617 if (ins
->src_abs
[1] || ins
->src_neg
[1])
2620 /* Make sure that the constant is not itself a vector
2621 * by checking if all accessed values are the same. */
2623 const midgard_constants
*cons
= &ins
->constants
;
2624 uint32_t value
= is_16
? cons
->u16
[component
] : cons
->u32
[component
];
2626 bool is_vector
= false;
2627 unsigned mask
= effective_writemask(ins
->op
, ins
->mask
);
2629 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
) {
2630 /* We only care if this component is actually used */
2631 if (!(mask
& (1 << c
)))
2634 uint32_t test
= is_16
?
2635 cons
->u16
[ins
->swizzle
[1][c
]] :
2636 cons
->u32
[ins
->swizzle
[1][c
]];
2638 if (test
!= value
) {
2647 /* Get rid of the embedded constant */
2648 ins
->has_constants
= false;
2650 ins
->has_inline_constant
= true;
2651 ins
->inline_constant
= scaled_constant
;
2656 /* Dead code elimination for branches at the end of a block - only one branch
2657 * per block is legal semantically */
2660 midgard_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
2662 bool branched
= false;
2664 mir_foreach_instr_in_block_safe(block
, ins
) {
2665 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2668 mir_remove_instruction(ins
);
2674 /* We want to force the invert on AND/OR to the second slot to legalize into
2675 * iandnot/iornot. The relevant patterns are for AND (and OR respectively)
2677 * ~a & #b = ~a & ~(#~b)
2682 midgard_legalize_invert(compiler_context
*ctx
, midgard_block
*block
)
2684 mir_foreach_instr_in_block(block
, ins
) {
2685 if (ins
->type
!= TAG_ALU_4
) continue;
2687 if (ins
->op
!= midgard_alu_op_iand
&&
2688 ins
->op
!= midgard_alu_op_ior
) continue;
2690 if (ins
->src_invert
[1] || !ins
->src_invert
[0]) continue;
2692 if (ins
->has_inline_constant
) {
2693 /* ~(#~a) = ~(~#a) = a, so valid, and forces both
2695 ins
->inline_constant
= ~ins
->inline_constant
;
2696 ins
->src_invert
[1] = true;
2698 /* Flip to the right invert order. Note
2699 * has_inline_constant false by assumption on the
2700 * branch, so flipping makes sense. */
2707 emit_fragment_epilogue(compiler_context
*ctx
, unsigned rt
)
2709 /* Loop to ourselves */
2710 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
2711 struct midgard_instruction ins
= v_branch(false, false);
2712 ins
.writeout
= br
->writeout
;
2713 ins
.branch
.target_block
= ctx
->block_count
- 1;
2714 ins
.constants
.u32
[0] = br
->constants
.u32
[0];
2715 memcpy(&ins
.src_types
, &br
->src_types
, sizeof(ins
.src_types
));
2716 emit_mir_instruction(ctx
, ins
);
2718 ctx
->current_block
->epilogue
= true;
2719 schedule_barrier(ctx
);
2720 return ins
.branch
.target_block
;
2723 static midgard_block
*
2724 emit_block_init(compiler_context
*ctx
)
2726 midgard_block
*this_block
= ctx
->after_block
;
2727 ctx
->after_block
= NULL
;
2730 this_block
= create_empty_block(ctx
);
2732 list_addtail(&this_block
->base
.link
, &ctx
->blocks
);
2734 this_block
->scheduled
= false;
2737 /* Set up current block */
2738 list_inithead(&this_block
->base
.instructions
);
2739 ctx
->current_block
= this_block
;
2744 static midgard_block
*
2745 emit_block(compiler_context
*ctx
, nir_block
*block
)
2747 midgard_block
*this_block
= emit_block_init(ctx
);
2749 nir_foreach_instr(instr
, block
) {
2750 emit_instr(ctx
, instr
);
2751 ++ctx
->instruction_count
;
2757 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2760 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2762 midgard_block
*before_block
= ctx
->current_block
;
2764 /* Speculatively emit the branch, but we can't fill it in until later */
2766 EMIT(branch
, true, true);
2767 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2768 then_branch
->src
[0] = mir_get_branch_cond(&nif
->condition
, &inv
);
2769 then_branch
->src_types
[0] = nir_type_uint32
;
2770 then_branch
->branch
.invert_conditional
= !inv
;
2772 /* Emit the two subblocks. */
2773 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2774 midgard_block
*end_then_block
= ctx
->current_block
;
2776 /* Emit a jump from the end of the then block to the end of the else */
2777 EMIT(branch
, false, false);
2778 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2780 /* Emit second block, and check if it's empty */
2782 int else_idx
= ctx
->block_count
;
2783 int count_in
= ctx
->instruction_count
;
2784 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2785 midgard_block
*end_else_block
= ctx
->current_block
;
2786 int after_else_idx
= ctx
->block_count
;
2788 /* Now that we have the subblocks emitted, fix up the branches */
2793 if (ctx
->instruction_count
== count_in
) {
2794 /* The else block is empty, so don't emit an exit jump */
2795 mir_remove_instruction(then_exit
);
2796 then_branch
->branch
.target_block
= after_else_idx
;
2798 then_branch
->branch
.target_block
= else_idx
;
2799 then_exit
->branch
.target_block
= after_else_idx
;
2802 /* Wire up the successors */
2804 ctx
->after_block
= create_empty_block(ctx
);
2806 pan_block_add_successor(&before_block
->base
, &then_block
->base
);
2807 pan_block_add_successor(&before_block
->base
, &else_block
->base
);
2809 pan_block_add_successor(&end_then_block
->base
, &ctx
->after_block
->base
);
2810 pan_block_add_successor(&end_else_block
->base
, &ctx
->after_block
->base
);
2814 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2816 /* Remember where we are */
2817 midgard_block
*start_block
= ctx
->current_block
;
2819 /* Allocate a loop number, growing the current inner loop depth */
2820 int loop_idx
= ++ctx
->current_loop_depth
;
2822 /* Get index from before the body so we can loop back later */
2823 int start_idx
= ctx
->block_count
;
2825 /* Emit the body itself */
2826 midgard_block
*loop_block
= emit_cf_list(ctx
, &nloop
->body
);
2828 /* Branch back to loop back */
2829 struct midgard_instruction br_back
= v_branch(false, false);
2830 br_back
.branch
.target_block
= start_idx
;
2831 emit_mir_instruction(ctx
, br_back
);
2833 /* Mark down that branch in the graph. */
2834 pan_block_add_successor(&start_block
->base
, &loop_block
->base
);
2835 pan_block_add_successor(&ctx
->current_block
->base
, &loop_block
->base
);
2837 /* Find the index of the block about to follow us (note: we don't add
2838 * one; blocks are 0-indexed so we get a fencepost problem) */
2839 int break_block_idx
= ctx
->block_count
;
2841 /* Fix up the break statements we emitted to point to the right place,
2842 * now that we can allocate a block number for them */
2843 ctx
->after_block
= create_empty_block(ctx
);
2845 mir_foreach_block_from(ctx
, start_block
, _block
) {
2846 mir_foreach_instr_in_block(((midgard_block
*) _block
), ins
) {
2847 if (ins
->type
!= TAG_ALU_4
) continue;
2848 if (!ins
->compact_branch
) continue;
2850 /* We found a branch -- check the type to see if we need to do anything */
2851 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2853 /* It's a break! Check if it's our break */
2854 if (ins
->branch
.target_break
!= loop_idx
) continue;
2856 /* Okay, cool, we're breaking out of this loop.
2857 * Rewrite from a break to a goto */
2859 ins
->branch
.target_type
= TARGET_GOTO
;
2860 ins
->branch
.target_block
= break_block_idx
;
2862 pan_block_add_successor(_block
, &ctx
->after_block
->base
);
2866 /* Now that we've finished emitting the loop, free up the depth again
2867 * so we play nice with recursion amid nested loops */
2868 --ctx
->current_loop_depth
;
2870 /* Dump loop stats */
2874 static midgard_block
*
2875 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2877 midgard_block
*start_block
= NULL
;
2879 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2880 switch (node
->type
) {
2881 case nir_cf_node_block
: {
2882 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2885 start_block
= block
;
2890 case nir_cf_node_if
:
2891 emit_if(ctx
, nir_cf_node_as_if(node
));
2894 case nir_cf_node_loop
:
2895 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2898 case nir_cf_node_function
:
2907 /* Due to lookahead, we need to report the first tag executed in the command
2908 * stream and in branch targets. An initial block might be empty, so iterate
2909 * until we find one that 'works' */
2912 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2914 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2916 mir_foreach_block_from(ctx
, initial_block
, _v
) {
2917 midgard_block
*v
= (midgard_block
*) _v
;
2918 if (v
->quadword_count
) {
2919 midgard_bundle
*initial_bundle
=
2920 util_dynarray_element(&v
->bundles
, midgard_bundle
, 0);
2922 return initial_bundle
->tag
;
2926 /* Default to a tag 1 which will break from the shader, in case we jump
2927 * to the exit block (i.e. `return` in a compute shader) */
2932 /* For each fragment writeout instruction, generate a writeout loop to
2933 * associate with it */
2936 mir_add_writeout_loops(compiler_context
*ctx
)
2938 for (unsigned rt
= 0; rt
< ARRAY_SIZE(ctx
->writeout_branch
); ++rt
) {
2939 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
2942 unsigned popped
= br
->branch
.target_block
;
2943 pan_block_add_successor(&(mir_get_block(ctx
, popped
- 1)->base
), &ctx
->current_block
->base
);
2944 br
->branch
.target_block
= emit_fragment_epilogue(ctx
, rt
);
2945 br
->branch
.target_type
= TARGET_GOTO
;
2947 /* If we have more RTs, we'll need to restore back after our
2948 * loop terminates */
2950 if ((rt
+ 1) < ARRAY_SIZE(ctx
->writeout_branch
) && ctx
->writeout_branch
[rt
+ 1]) {
2951 midgard_instruction uncond
= v_branch(false, false);
2952 uncond
.branch
.target_block
= popped
;
2953 uncond
.branch
.target_type
= TARGET_GOTO
;
2954 emit_mir_instruction(ctx
, uncond
);
2955 pan_block_add_successor(&ctx
->current_block
->base
, &(mir_get_block(ctx
, popped
)->base
));
2956 schedule_barrier(ctx
);
2958 /* We're last, so we can terminate here */
2959 br
->last_writeout
= true;
2965 midgard_compile_shader_nir(nir_shader
*nir
, panfrost_program
*program
, bool is_blend
, unsigned blend_rt
, unsigned gpu_id
, bool shaderdb
, bool silent
)
2967 struct util_dynarray
*compiled
= &program
->compiled
;
2969 midgard_debug
= debug_get_option_midgard_debug();
2971 /* TODO: Bound against what? */
2972 compiler_context
*ctx
= rzalloc(NULL
, compiler_context
);
2975 ctx
->stage
= nir
->info
.stage
;
2976 ctx
->is_blend
= is_blend
;
2977 ctx
->blend_rt
= MIDGARD_COLOR_RT0
+ blend_rt
;
2978 ctx
->blend_input
= ~0;
2979 ctx
->blend_src1
= ~0;
2980 ctx
->quirks
= midgard_get_quirks(gpu_id
);
2982 /* Start off with a safe cutoff, allowing usage of all 16 work
2983 * registers. Later, we'll promote uniform reads to uniform registers
2984 * if we determine it is beneficial to do so */
2985 ctx
->uniform_cutoff
= 8;
2987 /* Initialize at a global (not block) level hash tables */
2989 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2991 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2992 * (so we don't accidentally duplicate the epilogue since mesa/st has
2993 * messed with our I/O quite a bit already) */
2995 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2997 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2998 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2999 NIR_PASS_V(nir
, nir_lower_point_size
, 1.0, 1024.0);
3002 NIR_PASS_V(nir
, nir_lower_var_copies
);
3003 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3004 NIR_PASS_V(nir
, nir_split_var_copies
);
3005 NIR_PASS_V(nir
, nir_lower_var_copies
);
3006 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3007 NIR_PASS_V(nir
, nir_lower_var_copies
);
3008 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3010 unsigned pan_quirks
= panfrost_get_quirks(gpu_id
);
3011 NIR_PASS_V(nir
, pan_lower_framebuffer
,
3012 program
->rt_formats
, is_blend
, pan_quirks
);
3014 NIR_PASS_V(nir
, nir_lower_io
, nir_var_shader_in
| nir_var_shader_out
,
3016 NIR_PASS_V(nir
, nir_lower_ssbo
);
3017 NIR_PASS_V(nir
, midgard_nir_lower_zs_store
);
3019 /* Optimisation passes */
3021 optimise_nir(nir
, ctx
->quirks
, is_blend
);
3023 NIR_PASS_V(nir
, midgard_nir_reorder_writeout
);
3025 if ((midgard_debug
& MIDGARD_DBG_SHADERS
) && !silent
) {
3026 nir_print_shader(nir
, stdout
);
3029 /* Assign sysvals and counts, now that we're sure
3030 * (post-optimisation) */
3032 panfrost_nir_assign_sysvals(&ctx
->sysvals
, ctx
, nir
);
3033 program
->sysval_count
= ctx
->sysvals
.sysval_count
;
3034 memcpy(program
->sysvals
, ctx
->sysvals
.sysvals
, sizeof(ctx
->sysvals
.sysvals
[0]) * ctx
->sysvals
.sysval_count
);
3036 nir_foreach_function(func
, nir
) {
3040 list_inithead(&ctx
->blocks
);
3041 ctx
->block_count
= 0;
3043 ctx
->already_emitted
= calloc(BITSET_WORDS(func
->impl
->ssa_alloc
), sizeof(BITSET_WORD
));
3045 if (nir
->info
.outputs_read
&& !is_blend
) {
3046 emit_block_init(ctx
);
3048 struct midgard_instruction wait
= v_branch(false, false);
3049 wait
.branch
.target_type
= TARGET_TILEBUF_WAIT
;
3051 emit_mir_instruction(ctx
, wait
);
3053 ++ctx
->instruction_count
;
3056 emit_cf_list(ctx
, &func
->impl
->body
);
3057 free(ctx
->already_emitted
);
3058 break; /* TODO: Multi-function shaders */
3061 util_dynarray_init(compiled
, NULL
);
3063 /* Per-block lowering before opts */
3065 mir_foreach_block(ctx
, _block
) {
3066 midgard_block
*block
= (midgard_block
*) _block
;
3067 inline_alu_constants(ctx
, block
);
3068 embedded_to_inline_constant(ctx
, block
);
3070 /* MIR-level optimizations */
3072 bool progress
= false;
3076 progress
|= midgard_opt_dead_code_eliminate(ctx
);
3078 mir_foreach_block(ctx
, _block
) {
3079 midgard_block
*block
= (midgard_block
*) _block
;
3080 progress
|= midgard_opt_copy_prop(ctx
, block
);
3081 progress
|= midgard_opt_combine_projection(ctx
, block
);
3082 progress
|= midgard_opt_varying_projection(ctx
, block
);
3086 mir_foreach_block(ctx
, _block
) {
3087 midgard_block
*block
= (midgard_block
*) _block
;
3088 midgard_lower_derivatives(ctx
, block
);
3089 midgard_legalize_invert(ctx
, block
);
3090 midgard_cull_dead_branch(ctx
, block
);
3093 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
3094 mir_add_writeout_loops(ctx
);
3096 /* Analyze now that the code is known but before scheduling creates
3097 * pipeline registers which are harder to track */
3098 mir_analyze_helper_terminate(ctx
);
3099 mir_analyze_helper_requirements(ctx
);
3102 midgard_schedule_program(ctx
);
3105 /* Emit flat binary from the instruction arrays. Iterate each block in
3106 * sequence. Save instruction boundaries such that lookahead tags can
3107 * be assigned easily */
3109 /* Cache _all_ bundles in source order for lookahead across failed branches */
3111 int bundle_count
= 0;
3112 mir_foreach_block(ctx
, _block
) {
3113 midgard_block
*block
= (midgard_block
*) _block
;
3114 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3116 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3118 mir_foreach_block(ctx
, _block
) {
3119 midgard_block
*block
= (midgard_block
*) _block
;
3120 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3121 source_order_bundles
[bundle_idx
++] = bundle
;
3125 int current_bundle
= 0;
3127 /* Midgard prefetches instruction types, so during emission we
3128 * need to lookahead. Unless this is the last instruction, in
3129 * which we return 1. */
3131 mir_foreach_block(ctx
, _block
) {
3132 midgard_block
*block
= (midgard_block
*) _block
;
3133 mir_foreach_bundle_in_block(block
, bundle
) {
3136 if (!bundle
->last_writeout
&& (current_bundle
+ 1 < bundle_count
))
3137 lookahead
= source_order_bundles
[current_bundle
+ 1]->tag
;
3139 emit_binary_bundle(ctx
, block
, bundle
, compiled
, lookahead
);
3143 /* TODO: Free deeper */
3144 //util_dynarray_fini(&block->instructions);
3147 free(source_order_bundles
);
3149 /* Report the very first tag executed */
3150 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3152 /* Deal with off-by-one related to the fencepost problem */
3153 program
->work_register_count
= ctx
->work_registers
+ 1;
3154 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3156 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3157 program
->tls_size
= ctx
->tls_size
;
3159 if ((midgard_debug
& MIDGARD_DBG_SHADERS
) && !silent
)
3160 disassemble_midgard(stdout
, program
->compiled
.data
, program
->compiled
.size
, gpu_id
, ctx
->stage
);
3162 if ((midgard_debug
& MIDGARD_DBG_SHADERDB
|| shaderdb
) && !silent
) {
3163 unsigned nr_bundles
= 0, nr_ins
= 0;
3165 /* Count instructions and bundles */
3167 mir_foreach_block(ctx
, _block
) {
3168 midgard_block
*block
= (midgard_block
*) _block
;
3169 nr_bundles
+= util_dynarray_num_elements(
3170 &block
->bundles
, midgard_bundle
);
3172 mir_foreach_bundle_in_block(block
, bun
)
3173 nr_ins
+= bun
->instruction_count
;
3176 /* Calculate thread count. There are certain cutoffs by
3177 * register count for thread count */
3179 unsigned nr_registers
= program
->work_register_count
;
3181 unsigned nr_threads
=
3182 (nr_registers
<= 4) ? 4 :
3183 (nr_registers
<= 8) ? 2 :
3188 fprintf(stderr
, "shader%d - %s shader: "
3189 "%u inst, %u bundles, %u quadwords, "
3190 "%u registers, %u threads, %u loops, "
3191 "%u:%u spills:fills\n",
3193 ctx
->is_blend
? "PAN_SHADER_BLEND" :
3194 gl_shader_stage_name(ctx
->stage
),
3195 nr_ins
, nr_bundles
, ctx
->quadword_count
,
3196 nr_registers
, nr_threads
,
3198 ctx
->spills
, ctx
->fills
);