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pan/mdg: Distinguish blend shaders in internal shader-db
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 i.dest_type = T; \
121 } else { \
122 i.dest = ssa; \
123 i.dest_type = T; \
124 } \
125 return i; \
126 }
127
128 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
129 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
130
131 M_LOAD(ld_attr_32, nir_type_uint32);
132 M_LOAD(ld_vary_32, nir_type_uint32);
133 M_LOAD(ld_ubo_int4, nir_type_uint32);
134 M_LOAD(ld_int4, nir_type_uint32);
135 M_STORE(st_int4, nir_type_uint32);
136 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
137 M_STORE(st_vary_32, nir_type_uint32);
138 M_LOAD(ld_cubemap_coords, nir_type_uint32);
139 M_LOAD(ld_compute_id, nir_type_uint32);
140
141 static midgard_instruction
142 v_branch(bool conditional, bool invert)
143 {
144 midgard_instruction ins = {
145 .type = TAG_ALU_4,
146 .unit = ALU_ENAB_BRANCH,
147 .compact_branch = true,
148 .branch = {
149 .conditional = conditional,
150 .invert_conditional = invert
151 },
152 .dest = ~0,
153 .src = { ~0, ~0, ~0, ~0 },
154 };
155
156 return ins;
157 }
158
159 static midgard_branch_extended
160 midgard_create_branch_extended( midgard_condition cond,
161 midgard_jmp_writeout_op op,
162 unsigned dest_tag,
163 signed quadword_offset)
164 {
165 /* The condition code is actually a LUT describing a function to
166 * combine multiple condition codes. However, we only support a single
167 * condition code at the moment, so we just duplicate over a bunch of
168 * times. */
169
170 uint16_t duplicated_cond =
171 (cond << 14) |
172 (cond << 12) |
173 (cond << 10) |
174 (cond << 8) |
175 (cond << 6) |
176 (cond << 4) |
177 (cond << 2) |
178 (cond << 0);
179
180 midgard_branch_extended branch = {
181 .op = op,
182 .dest_tag = dest_tag,
183 .offset = quadword_offset,
184 .cond = duplicated_cond
185 };
186
187 return branch;
188 }
189
190 static void
191 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
192 {
193 ins->has_constants = true;
194 memcpy(&ins->constants, constants, 16);
195 }
196
197 static int
198 glsl_type_size(const struct glsl_type *type, bool bindless)
199 {
200 return glsl_count_attribute_slots(type, false);
201 }
202
203 /* Lower fdot2 to a vector multiplication followed by channel addition */
204 static void
205 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
206 {
207 if (alu->op != nir_op_fdot2)
208 return;
209
210 b->cursor = nir_before_instr(&alu->instr);
211
212 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
213 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
214
215 nir_ssa_def *product = nir_fmul(b, src0, src1);
216
217 nir_ssa_def *sum = nir_fadd(b,
218 nir_channel(b, product, 0),
219 nir_channel(b, product, 1));
220
221 /* Replace the fdot2 with this sum */
222 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
223 }
224
225 static bool
226 midgard_nir_lower_fdot2(nir_shader *shader)
227 {
228 bool progress = false;
229
230 nir_foreach_function(function, shader) {
231 if (!function->impl) continue;
232
233 nir_builder _b;
234 nir_builder *b = &_b;
235 nir_builder_init(b, function->impl);
236
237 nir_foreach_block(block, function->impl) {
238 nir_foreach_instr_safe(instr, block) {
239 if (instr->type != nir_instr_type_alu) continue;
240
241 nir_alu_instr *alu = nir_instr_as_alu(instr);
242 midgard_nir_lower_fdot2_body(b, alu);
243
244 progress |= true;
245 }
246 }
247
248 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
249
250 }
251
252 return progress;
253 }
254
255 /* Midgard can't write depth and stencil separately. It has to happen in a
256 * single store operation containing both. Let's add a panfrost specific
257 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
258 * one.
259 */
260 static bool
261 midgard_nir_lower_zs_store(nir_shader *nir)
262 {
263 if (nir->info.stage != MESA_SHADER_FRAGMENT)
264 return false;
265
266 nir_variable *z_var = NULL, *s_var = NULL;
267
268 nir_foreach_variable(var, &nir->outputs) {
269 if (var->data.location == FRAG_RESULT_DEPTH)
270 z_var = var;
271 else if (var->data.location == FRAG_RESULT_STENCIL)
272 s_var = var;
273 }
274
275 if (!z_var && !s_var)
276 return false;
277
278 bool progress = false;
279
280 nir_foreach_function(function, nir) {
281 if (!function->impl) continue;
282
283 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
284
285 nir_foreach_block(block, function->impl) {
286 nir_foreach_instr_safe(instr, block) {
287 if (instr->type != nir_instr_type_intrinsic)
288 continue;
289
290 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
291 if (intr->intrinsic != nir_intrinsic_store_output)
292 continue;
293
294 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
295 assert(!z_store);
296 z_store = intr;
297 last_store = intr;
298 }
299
300 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
301 assert(!s_store);
302 s_store = intr;
303 last_store = intr;
304 }
305 }
306 }
307
308 if (!z_store && !s_store) continue;
309
310 nir_builder b;
311 nir_builder_init(&b, function->impl);
312
313 b.cursor = nir_before_instr(&last_store->instr);
314
315 nir_ssa_def *zs_store_src;
316
317 if (z_store && s_store) {
318 nir_ssa_def *srcs[2] = {
319 nir_ssa_for_src(&b, z_store->src[0], 1),
320 nir_ssa_for_src(&b, s_store->src[0], 1),
321 };
322
323 zs_store_src = nir_vec(&b, srcs, 2);
324 } else {
325 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
326 }
327
328 nir_intrinsic_instr *zs_store;
329
330 zs_store = nir_intrinsic_instr_create(b.shader,
331 nir_intrinsic_store_zs_output_pan);
332 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
333 zs_store->num_components = z_store && s_store ? 2 : 1;
334 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
335
336 /* Replace the Z and S store by a ZS store */
337 nir_builder_instr_insert(&b, &zs_store->instr);
338
339 if (z_store)
340 nir_instr_remove(&z_store->instr);
341
342 if (s_store)
343 nir_instr_remove(&s_store->instr);
344
345 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
346 progress = true;
347 }
348
349 return progress;
350 }
351
352 /* Flushes undefined values to zero */
353
354 static void
355 optimise_nir(nir_shader *nir, unsigned quirks, bool is_blend)
356 {
357 bool progress;
358 unsigned lower_flrp =
359 (nir->options->lower_flrp16 ? 16 : 0) |
360 (nir->options->lower_flrp32 ? 32 : 0) |
361 (nir->options->lower_flrp64 ? 64 : 0);
362
363 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
364 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
365
366 nir_lower_tex_options lower_tex_options = {
367 .lower_txs_lod = true,
368 .lower_txp = ~0,
369 .lower_tex_without_implicit_lod =
370 (quirks & MIDGARD_EXPLICIT_LOD),
371
372 /* TODO: we have native gradient.. */
373 .lower_txd = true,
374 };
375
376 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
377
378 /* Must lower fdot2 after tex is lowered */
379 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
380
381 /* T720 is broken. */
382
383 if (quirks & MIDGARD_BROKEN_LOD)
384 NIR_PASS_V(nir, midgard_nir_lod_errata);
385
386 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_early);
387
388 if (!is_blend)
389 NIR_PASS(progress, nir, nir_fuse_io_16);
390
391 do {
392 progress = false;
393
394 NIR_PASS(progress, nir, nir_lower_var_copies);
395 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
396
397 NIR_PASS(progress, nir, nir_copy_prop);
398 NIR_PASS(progress, nir, nir_opt_remove_phis);
399 NIR_PASS(progress, nir, nir_opt_dce);
400 NIR_PASS(progress, nir, nir_opt_dead_cf);
401 NIR_PASS(progress, nir, nir_opt_cse);
402 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
403 NIR_PASS(progress, nir, nir_opt_algebraic);
404 NIR_PASS(progress, nir, nir_opt_constant_folding);
405
406 if (lower_flrp != 0) {
407 bool lower_flrp_progress = false;
408 NIR_PASS(lower_flrp_progress,
409 nir,
410 nir_lower_flrp,
411 lower_flrp,
412 false /* always_precise */,
413 nir->options->lower_ffma);
414 if (lower_flrp_progress) {
415 NIR_PASS(progress, nir,
416 nir_opt_constant_folding);
417 progress = true;
418 }
419
420 /* Nothing should rematerialize any flrps, so we only
421 * need to do this lowering once.
422 */
423 lower_flrp = 0;
424 }
425
426 NIR_PASS(progress, nir, nir_opt_undef);
427 NIR_PASS(progress, nir, nir_undef_to_zero);
428
429 NIR_PASS(progress, nir, nir_opt_loop_unroll,
430 nir_var_shader_in |
431 nir_var_shader_out |
432 nir_var_function_temp);
433
434 NIR_PASS(progress, nir, nir_opt_vectorize);
435 } while (progress);
436
437 /* Must be run at the end to prevent creation of fsin/fcos ops */
438 NIR_PASS(progress, nir, midgard_nir_scale_trig);
439
440 do {
441 progress = false;
442
443 NIR_PASS(progress, nir, nir_opt_dce);
444 NIR_PASS(progress, nir, nir_opt_algebraic);
445 NIR_PASS(progress, nir, nir_opt_constant_folding);
446 NIR_PASS(progress, nir, nir_copy_prop);
447 } while (progress);
448
449 NIR_PASS(progress, nir, nir_opt_algebraic_late);
450 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
451
452 /* We implement booleans as 32-bit 0/~0 */
453 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
454
455 /* Now that booleans are lowered, we can run out late opts */
456 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
457 NIR_PASS(progress, nir, midgard_nir_cancel_inot);
458
459 NIR_PASS(progress, nir, nir_copy_prop);
460 NIR_PASS(progress, nir, nir_opt_dce);
461
462 /* Take us out of SSA */
463 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
464 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
465
466 /* We are a vector architecture; write combine where possible */
467 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
468 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
469
470 NIR_PASS(progress, nir, nir_opt_dce);
471 }
472
473 /* Do not actually emit a load; instead, cache the constant for inlining */
474
475 static void
476 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
477 {
478 nir_ssa_def def = instr->def;
479
480 midgard_constants *consts = rzalloc(NULL, midgard_constants);
481
482 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
483
484 #define RAW_CONST_COPY(bits) \
485 nir_const_value_to_array(consts->u##bits, instr->value, \
486 instr->def.num_components, u##bits)
487
488 switch (instr->def.bit_size) {
489 case 64:
490 RAW_CONST_COPY(64);
491 break;
492 case 32:
493 RAW_CONST_COPY(32);
494 break;
495 case 16:
496 RAW_CONST_COPY(16);
497 break;
498 case 8:
499 RAW_CONST_COPY(8);
500 break;
501 default:
502 unreachable("Invalid bit_size for load_const instruction\n");
503 }
504
505 /* Shifted for SSA, +1 for off-by-one */
506 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
507 }
508
509 /* Normally constants are embedded implicitly, but for I/O and such we have to
510 * explicitly emit a move with the constant source */
511
512 static void
513 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
514 {
515 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
516
517 if (constant_value) {
518 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
519 attach_constants(ctx, &ins, constant_value, node + 1);
520 emit_mir_instruction(ctx, ins);
521 }
522 }
523
524 static bool
525 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
526 {
527 unsigned comp = src->swizzle[0];
528
529 for (unsigned c = 1; c < nr_components; ++c) {
530 if (src->swizzle[c] != comp)
531 return true;
532 }
533
534 return false;
535 }
536
537 #define ALU_CASE(nir, _op) \
538 case nir_op_##nir: \
539 op = midgard_alu_op_##_op; \
540 assert(src_bitsize == dst_bitsize); \
541 break;
542
543 #define ALU_CHECK_CMP(sext) \
544 assert(src_bitsize == 16 || src_bitsize == 32); \
545 assert(dst_bitsize == 16 || dst_bitsize == 32); \
546
547 #define ALU_CASE_BCAST(nir, _op, count) \
548 case nir_op_##nir: \
549 op = midgard_alu_op_##_op; \
550 broadcast_swizzle = count; \
551 ALU_CHECK_CMP(true); \
552 break;
553
554 #define ALU_CASE_CMP(nir, _op, sext) \
555 case nir_op_##nir: \
556 op = midgard_alu_op_##_op; \
557 ALU_CHECK_CMP(sext); \
558 break;
559
560 /* Analyze the sizes of the dest and inputs to determine reg mode. */
561
562 static midgard_reg_mode
563 reg_mode_for_nir(nir_alu_instr *instr)
564 {
565 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
566 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
567 unsigned max_bitsize = MAX2(src_bitsize, dst_bitsize);
568
569 /* We don't have fp16 LUTs, so we'll want to emit code like:
570 *
571 * vlut.fsinr hr0, hr0
572 *
573 * where both input and output are 16-bit but the operation is carried
574 * out in 32-bit
575 */
576
577 switch (instr->op) {
578 case nir_op_fsqrt:
579 case nir_op_frcp:
580 case nir_op_frsq:
581 case nir_op_fsin:
582 case nir_op_fcos:
583 case nir_op_fexp2:
584 case nir_op_flog2:
585 max_bitsize = MAX2(max_bitsize, 32);
586 break;
587
588 /* These get lowered to moves */
589 case nir_op_pack_32_4x8:
590 max_bitsize = 8;
591 break;
592 case nir_op_pack_32_2x16:
593 max_bitsize = 16;
594 break;
595 default:
596 break;
597 }
598
599
600 switch (max_bitsize) {
601 /* Use 16 pipe for 8 since we don't support vec16 yet */
602 case 8:
603 case 16:
604 return midgard_reg_mode_16;
605 case 32:
606 return midgard_reg_mode_32;
607 case 64:
608 return midgard_reg_mode_64;
609 default:
610 unreachable("Invalid bit size");
611 }
612 }
613
614 /* Compare mir_lower_invert */
615 static bool
616 nir_accepts_inot(nir_op op, unsigned src)
617 {
618 switch (op) {
619 case nir_op_ior:
620 case nir_op_iand: /* TODO: b2f16 */
621 case nir_op_ixor:
622 return true;
623 case nir_op_b32csel:
624 /* Only the condition */
625 return (src == 0);
626 default:
627 return false;
628 }
629 }
630
631 static bool
632 mir_accept_dest_mod(compiler_context *ctx, nir_dest **dest, nir_op op)
633 {
634 if (pan_has_dest_mod(dest, op)) {
635 assert((*dest)->is_ssa);
636 BITSET_SET(ctx->already_emitted, (*dest)->ssa.index);
637 return true;
638 }
639
640 return false;
641 }
642
643 static void
644 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool *not, bool is_int, unsigned bcast_count)
645 {
646 nir_alu_src src = instr->src[i];
647
648 if (!is_int) {
649 if (pan_has_source_mod(&src, nir_op_fneg))
650 *neg = !(*neg);
651
652 if (pan_has_source_mod(&src, nir_op_fabs))
653 *abs = true;
654 }
655
656 if (nir_accepts_inot(instr->op, i) && pan_has_source_mod(&src, nir_op_inot))
657 *not = true;
658
659 unsigned bits = nir_src_bit_size(src.src);
660
661 ins->src[to] = nir_src_index(NULL, &src.src);
662 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
663
664 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
665 ins->swizzle[to][c] = src.swizzle[
666 (!bcast_count || c < bcast_count) ? c :
667 (bcast_count - 1)];
668 }
669 }
670
671 /* Midgard features both fcsel and icsel, depending on whether you want int or
672 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
673 * we should emit an int or float csel depending on what modifiers could be
674 * placed. In the absense of modifiers, this is probably arbitrary. */
675
676 static bool
677 mir_is_bcsel_float(nir_alu_instr *instr)
678 {
679 nir_op intmods[] = {
680 nir_op_i2i8, nir_op_i2i16,
681 nir_op_i2i32, nir_op_i2i64
682 };
683
684 nir_op floatmods[] = {
685 nir_op_fabs, nir_op_fneg,
686 nir_op_f2f16, nir_op_f2f32,
687 nir_op_f2f64
688 };
689
690 nir_op floatdestmods[] = {
691 nir_op_fsat, nir_op_fsat_signed, nir_op_fclamp_pos,
692 nir_op_f2f16, nir_op_f2f32
693 };
694
695 signed score = 0;
696
697 for (unsigned i = 1; i < 3; ++i) {
698 nir_alu_src s = instr->src[i];
699 for (unsigned q = 0; q < ARRAY_SIZE(intmods); ++q) {
700 if (pan_has_source_mod(&s, intmods[q]))
701 score--;
702 }
703 }
704
705 for (unsigned i = 1; i < 3; ++i) {
706 nir_alu_src s = instr->src[i];
707 for (unsigned q = 0; q < ARRAY_SIZE(floatmods); ++q) {
708 if (pan_has_source_mod(&s, floatmods[q]))
709 score++;
710 }
711 }
712
713 for (unsigned q = 0; q < ARRAY_SIZE(floatdestmods); ++q) {
714 nir_dest *dest = &instr->dest.dest;
715 if (pan_has_dest_mod(&dest, floatdestmods[q]))
716 score++;
717 }
718
719 return (score > 0);
720 }
721
722 static void
723 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
724 {
725 nir_dest *dest = &instr->dest.dest;
726
727 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index))
728 return;
729
730 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
731 * is handled elsewhere */
732
733 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
734 midgard_emit_derivatives(ctx, instr);
735 return;
736 }
737
738 bool is_ssa = dest->is_ssa;
739
740 unsigned nr_components = nir_dest_num_components(*dest);
741 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
742 unsigned op = 0;
743
744 /* Number of components valid to check for the instruction (the rest
745 * will be forced to the last), or 0 to use as-is. Relevant as
746 * ball-type instructions have a channel count in NIR but are all vec4
747 * in Midgard */
748
749 unsigned broadcast_swizzle = 0;
750
751 /* What register mode should we operate in? */
752 midgard_reg_mode reg_mode =
753 reg_mode_for_nir(instr);
754
755 /* Should we swap arguments? */
756 bool flip_src12 = false;
757
758 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
759 unsigned dst_bitsize = nir_dest_bit_size(*dest);
760
761 switch (instr->op) {
762 ALU_CASE(fadd, fadd);
763 ALU_CASE(fmul, fmul);
764 ALU_CASE(fmin, fmin);
765 ALU_CASE(fmax, fmax);
766 ALU_CASE(imin, imin);
767 ALU_CASE(imax, imax);
768 ALU_CASE(umin, umin);
769 ALU_CASE(umax, umax);
770 ALU_CASE(ffloor, ffloor);
771 ALU_CASE(fround_even, froundeven);
772 ALU_CASE(ftrunc, ftrunc);
773 ALU_CASE(fceil, fceil);
774 ALU_CASE(fdot3, fdot3);
775 ALU_CASE(fdot4, fdot4);
776 ALU_CASE(iadd, iadd);
777 ALU_CASE(isub, isub);
778 ALU_CASE(imul, imul);
779
780 /* Zero shoved as second-arg */
781 ALU_CASE(iabs, iabsdiff);
782
783 ALU_CASE(mov, imov);
784
785 ALU_CASE_CMP(feq32, feq, false);
786 ALU_CASE_CMP(fne32, fne, false);
787 ALU_CASE_CMP(flt32, flt, false);
788 ALU_CASE_CMP(ieq32, ieq, true);
789 ALU_CASE_CMP(ine32, ine, true);
790 ALU_CASE_CMP(ilt32, ilt, true);
791 ALU_CASE_CMP(ult32, ult, false);
792
793 /* We don't have a native b2f32 instruction. Instead, like many
794 * GPUs, we exploit booleans as 0/~0 for false/true, and
795 * correspondingly AND
796 * by 1.0 to do the type conversion. For the moment, prime us
797 * to emit:
798 *
799 * iand [whatever], #0
800 *
801 * At the end of emit_alu (as MIR), we'll fix-up the constant
802 */
803
804 ALU_CASE_CMP(b2f32, iand, true);
805 ALU_CASE_CMP(b2f16, iand, true);
806 ALU_CASE_CMP(b2i32, iand, true);
807
808 /* Likewise, we don't have a dedicated f2b32 instruction, but
809 * we can do a "not equal to 0.0" test. */
810
811 ALU_CASE_CMP(f2b32, fne, false);
812 ALU_CASE_CMP(i2b32, ine, true);
813
814 ALU_CASE(frcp, frcp);
815 ALU_CASE(frsq, frsqrt);
816 ALU_CASE(fsqrt, fsqrt);
817 ALU_CASE(fexp2, fexp2);
818 ALU_CASE(flog2, flog2);
819
820 ALU_CASE(f2i64, f2i_rtz);
821 ALU_CASE(f2u64, f2u_rtz);
822 ALU_CASE(i2f64, i2f_rtz);
823 ALU_CASE(u2f64, u2f_rtz);
824
825 ALU_CASE(f2i32, f2i_rtz);
826 ALU_CASE(f2u32, f2u_rtz);
827 ALU_CASE(i2f32, i2f_rtz);
828 ALU_CASE(u2f32, u2f_rtz);
829
830 ALU_CASE(f2i16, f2i_rtz);
831 ALU_CASE(f2u16, f2u_rtz);
832 ALU_CASE(i2f16, i2f_rtz);
833 ALU_CASE(u2f16, u2f_rtz);
834
835 ALU_CASE(fsin, fsin);
836 ALU_CASE(fcos, fcos);
837
838 /* We'll get 0 in the second arg, so:
839 * ~a = ~(a | 0) = nor(a, 0) */
840 ALU_CASE(inot, inor);
841 ALU_CASE(iand, iand);
842 ALU_CASE(ior, ior);
843 ALU_CASE(ixor, ixor);
844 ALU_CASE(ishl, ishl);
845 ALU_CASE(ishr, iasr);
846 ALU_CASE(ushr, ilsr);
847
848 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
849 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
850 ALU_CASE_CMP(b32all_fequal4, fball_eq, true);
851
852 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
853 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
854 ALU_CASE_CMP(b32any_fnequal4, fbany_neq, true);
855
856 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
857 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
858 ALU_CASE_CMP(b32all_iequal4, iball_eq, true);
859
860 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
861 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
862 ALU_CASE_CMP(b32any_inequal4, ibany_neq, true);
863
864 /* Source mods will be shoved in later */
865 ALU_CASE(fabs, fmov);
866 ALU_CASE(fneg, fmov);
867 ALU_CASE(fsat, fmov);
868 ALU_CASE(fsat_signed, fmov);
869 ALU_CASE(fclamp_pos, fmov);
870
871 /* For size conversion, we use a move. Ideally though we would squash
872 * these ops together; maybe that has to happen after in NIR as part of
873 * propagation...? An earlier algebraic pass ensured we step down by
874 * only / exactly one size. If stepping down, we use a dest override to
875 * reduce the size; if stepping up, we use a larger-sized move with a
876 * half source and a sign/zero-extension modifier */
877
878 case nir_op_i2i8:
879 case nir_op_i2i16:
880 case nir_op_i2i32:
881 case nir_op_i2i64:
882 case nir_op_u2u8:
883 case nir_op_u2u16:
884 case nir_op_u2u32:
885 case nir_op_u2u64:
886 case nir_op_f2f16:
887 case nir_op_f2f32:
888 case nir_op_f2f64: {
889 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
890 instr->op == nir_op_f2f64)
891 op = midgard_alu_op_fmov;
892 else
893 op = midgard_alu_op_imov;
894
895 break;
896 }
897
898 /* For greater-or-equal, we lower to less-or-equal and flip the
899 * arguments */
900
901 case nir_op_fge:
902 case nir_op_fge32:
903 case nir_op_ige32:
904 case nir_op_uge32: {
905 op =
906 instr->op == nir_op_fge ? midgard_alu_op_fle :
907 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
908 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
909 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
910 0;
911
912 flip_src12 = true;
913 ALU_CHECK_CMP(false);
914 break;
915 }
916
917 case nir_op_b32csel: {
918 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
919 bool is_float = mir_is_bcsel_float(instr);
920 op = is_float ?
921 (mixed ? midgard_alu_op_fcsel_v : midgard_alu_op_fcsel) :
922 (mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel);
923
924 break;
925 }
926
927 case nir_op_unpack_32_2x16:
928 case nir_op_unpack_32_4x8:
929 case nir_op_pack_32_2x16:
930 case nir_op_pack_32_4x8: {
931 op = midgard_alu_op_imov;
932 break;
933 }
934
935 default:
936 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
937 assert(0);
938 return;
939 }
940
941 /* Promote imov to fmov if it might help inline a constant */
942 if (op == midgard_alu_op_imov && nir_src_is_const(instr->src[0].src)
943 && nir_src_bit_size(instr->src[0].src) == 32
944 && nir_is_same_comp_swizzle(instr->src[0].swizzle,
945 nir_src_num_components(instr->src[0].src))) {
946 op = midgard_alu_op_fmov;
947 }
948
949 /* Midgard can perform certain modifiers on output of an ALU op */
950
951 unsigned outmod = 0;
952 bool is_int = midgard_is_integer_op(op);
953
954 if (midgard_is_integer_out_op(op)) {
955 outmod = midgard_outmod_int_wrap;
956 } else if (instr->op == nir_op_fsat) {
957 outmod = midgard_outmod_sat;
958 } else if (instr->op == nir_op_fsat_signed) {
959 outmod = midgard_outmod_sat_signed;
960 } else if (instr->op == nir_op_fclamp_pos) {
961 outmod = midgard_outmod_pos;
962 }
963
964 /* Fetch unit, quirks, etc information */
965 unsigned opcode_props = alu_opcode_props[op].props;
966 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
967
968 /* Look for floating point mods. We have the mods fsat, fsat_signed,
969 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
970 *
971 * fsat_signed(fpos(x)) = fsat(x)
972 * fsat_signed(fsat(x)) = fsat(x)
973 * fpos(fsat_signed(x)) = fsat(x)
974 * fpos(fsat(x)) = fsat(x)
975 * fsat(fsat_signed(x)) = fsat(x)
976 * fsat(fpos(x)) = fsat(x)
977 *
978 * So by cases any composition of output modifiers is equivalent to
979 * fsat alone.
980 */
981
982 if (!is_int && !(opcode_props & OP_TYPE_CONVERT)) {
983 bool fpos = mir_accept_dest_mod(ctx, &dest, nir_op_fclamp_pos);
984 bool fsat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat);
985 bool ssat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat_signed);
986 bool prior = (outmod != midgard_outmod_none);
987 int count = (int) prior + (int) fpos + (int) ssat + (int) fsat;
988
989 outmod = ((count > 1) || fsat) ? midgard_outmod_sat :
990 fpos ? midgard_outmod_pos :
991 ssat ? midgard_outmod_sat_signed :
992 outmod;
993 }
994
995 midgard_instruction ins = {
996 .type = TAG_ALU_4,
997 .dest = nir_dest_index(dest),
998 .dest_type = nir_op_infos[instr->op].output_type
999 | nir_dest_bit_size(*dest),
1000 };
1001
1002 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
1003 ins.src[i] = ~0;
1004
1005 if (quirk_flipped_r24) {
1006 ins.src[0] = ~0;
1007 mir_copy_src(&ins, instr, 0, 1, &ins.src_abs[1], &ins.src_neg[1], &ins.src_invert[1], is_int, broadcast_swizzle);
1008 } else {
1009 for (unsigned i = 0; i < nr_inputs; ++i) {
1010 unsigned to = i;
1011
1012 if (instr->op == nir_op_b32csel) {
1013 /* The condition is the first argument; move
1014 * the other arguments up one to be a binary
1015 * instruction for Midgard with the condition
1016 * last */
1017
1018 if (i == 0)
1019 to = 2;
1020 else if (flip_src12)
1021 to = 2 - i;
1022 else
1023 to = i - 1;
1024 } else if (flip_src12) {
1025 to = 1 - to;
1026 }
1027
1028 mir_copy_src(&ins, instr, i, to, &ins.src_abs[to], &ins.src_neg[to], &ins.src_invert[to], is_int, broadcast_swizzle);
1029
1030 /* (!c) ? a : b = c ? b : a */
1031 if (instr->op == nir_op_b32csel && ins.src_invert[2]) {
1032 ins.src_invert[2] = false;
1033 flip_src12 ^= true;
1034 }
1035 }
1036 }
1037
1038 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
1039 /* Lowered to move */
1040 if (instr->op == nir_op_fneg)
1041 ins.src_neg[1] ^= true;
1042
1043 if (instr->op == nir_op_fabs)
1044 ins.src_abs[1] = true;
1045 }
1046
1047 ins.mask = mask_of(nr_components);
1048
1049 midgard_vector_alu alu = {
1050 .op = op,
1051 .reg_mode = reg_mode,
1052 .outmod = outmod,
1053 };
1054
1055 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1056 * components that don't exist. Note modifier => SSA => !reg => no
1057 * writemask, so we don't have to worry about writemasks here.*/
1058
1059 if (!is_ssa)
1060 ins.mask &= instr->dest.write_mask;
1061
1062 ins.alu = alu;
1063
1064 /* Late fixup for emulated instructions */
1065
1066 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1067 /* Presently, our second argument is an inline #0 constant.
1068 * Switch over to an embedded 1.0 constant (that can't fit
1069 * inline, since we're 32-bit, not 16-bit like the inline
1070 * constants) */
1071
1072 ins.has_inline_constant = false;
1073 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1074 ins.src_types[1] = nir_type_float32;
1075 ins.has_constants = true;
1076
1077 if (instr->op == nir_op_b2f32)
1078 ins.constants.f32[0] = 1.0f;
1079 else
1080 ins.constants.i32[0] = 1;
1081
1082 for (unsigned c = 0; c < 16; ++c)
1083 ins.swizzle[1][c] = 0;
1084 } else if (instr->op == nir_op_b2f16) {
1085 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1086 ins.src_types[1] = nir_type_float16;
1087 ins.has_constants = true;
1088 ins.constants.i16[0] = _mesa_float_to_half(1.0);
1089
1090 for (unsigned c = 0; c < 16; ++c)
1091 ins.swizzle[1][c] = 0;
1092 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1093 /* Lots of instructions need a 0 plonked in */
1094 ins.has_inline_constant = false;
1095 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1096 ins.src_types[1] = nir_type_uint32;
1097 ins.has_constants = true;
1098 ins.constants.u32[0] = 0;
1099
1100 for (unsigned c = 0; c < 16; ++c)
1101 ins.swizzle[1][c] = 0;
1102 } else if (instr->op == nir_op_pack_32_2x16) {
1103 ins.dest_type = nir_type_uint16;
1104 ins.mask = mask_of(nr_components * 2);
1105 ins.is_pack = true;
1106 } else if (instr->op == nir_op_pack_32_4x8) {
1107 ins.dest_type = nir_type_uint8;
1108 ins.mask = mask_of(nr_components * 4);
1109 ins.is_pack = true;
1110 } else if (instr->op == nir_op_unpack_32_2x16) {
1111 ins.dest_type = nir_type_uint32;
1112 ins.mask = mask_of(nr_components >> 1);
1113 ins.is_pack = true;
1114 } else if (instr->op == nir_op_unpack_32_4x8) {
1115 ins.dest_type = nir_type_uint32;
1116 ins.mask = mask_of(nr_components >> 2);
1117 ins.is_pack = true;
1118 }
1119
1120 /* Arrange for creation of iandnot/iornot */
1121 if (ins.src_invert[0] && !ins.src_invert[1]) {
1122 mir_flip(&ins);
1123 ins.src_invert[0] = false;
1124 ins.src_invert[1] = true;
1125 }
1126
1127 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1128 /* To avoid duplicating the lookup tables (probably), true LUT
1129 * instructions can only operate as if they were scalars. Lower
1130 * them here by changing the component. */
1131
1132 unsigned orig_mask = ins.mask;
1133
1134 unsigned swizzle_back[MIR_VEC_COMPONENTS];
1135 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
1136
1137 for (int i = 0; i < nr_components; ++i) {
1138 /* Mask the associated component, dropping the
1139 * instruction if needed */
1140
1141 ins.mask = 1 << i;
1142 ins.mask &= orig_mask;
1143
1144 if (!ins.mask)
1145 continue;
1146
1147 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1148 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1149
1150 emit_mir_instruction(ctx, ins);
1151 }
1152 } else {
1153 emit_mir_instruction(ctx, ins);
1154 }
1155 }
1156
1157 #undef ALU_CASE
1158
1159 static void
1160 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1161 {
1162 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1163 unsigned nir_mask = 0;
1164 unsigned dsize = 0;
1165
1166 if (is_read) {
1167 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1168 dsize = nir_dest_bit_size(intr->dest);
1169 } else {
1170 nir_mask = nir_intrinsic_write_mask(intr);
1171 dsize = 32;
1172 }
1173
1174 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1175 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1176 mir_set_bytemask(ins, bytemask);
1177 ins->dest_type = nir_type_uint | dsize;
1178 }
1179
1180 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1181 * optimized) versions of UBO #0 */
1182
1183 static midgard_instruction *
1184 emit_ubo_read(
1185 compiler_context *ctx,
1186 nir_instr *instr,
1187 unsigned dest,
1188 unsigned offset,
1189 nir_src *indirect_offset,
1190 unsigned indirect_shift,
1191 unsigned index)
1192 {
1193 /* TODO: half-floats */
1194
1195 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1196 ins.constants.u32[0] = offset;
1197
1198 if (instr->type == nir_instr_type_intrinsic)
1199 mir_set_intr_mask(instr, &ins, true);
1200
1201 if (indirect_offset) {
1202 ins.src[2] = nir_src_index(ctx, indirect_offset);
1203 ins.src_types[2] = nir_type_uint32;
1204 ins.load_store.arg_2 = (indirect_shift << 5);
1205 } else {
1206 ins.load_store.arg_2 = 0x1E;
1207 }
1208
1209 ins.load_store.arg_1 = index;
1210
1211 return emit_mir_instruction(ctx, ins);
1212 }
1213
1214 /* Globals are like UBOs if you squint. And shared memory is like globals if
1215 * you squint even harder */
1216
1217 static void
1218 emit_global(
1219 compiler_context *ctx,
1220 nir_instr *instr,
1221 bool is_read,
1222 unsigned srcdest,
1223 nir_src *offset,
1224 bool is_shared)
1225 {
1226 /* TODO: types */
1227
1228 midgard_instruction ins;
1229
1230 if (is_read)
1231 ins = m_ld_int4(srcdest, 0);
1232 else
1233 ins = m_st_int4(srcdest, 0);
1234
1235 mir_set_offset(ctx, &ins, offset, is_shared);
1236 mir_set_intr_mask(instr, &ins, is_read);
1237
1238 emit_mir_instruction(ctx, ins);
1239 }
1240
1241 static void
1242 emit_varying_read(
1243 compiler_context *ctx,
1244 unsigned dest, unsigned offset,
1245 unsigned nr_comp, unsigned component,
1246 nir_src *indirect_offset, nir_alu_type type, bool flat)
1247 {
1248 /* XXX: Half-floats? */
1249 /* TODO: swizzle, mask */
1250
1251 midgard_instruction ins = m_ld_vary_32(dest, offset);
1252 ins.mask = mask_of(nr_comp);
1253
1254 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1255 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1256
1257 midgard_varying_parameter p = {
1258 .is_varying = 1,
1259 .interpolation = midgard_interp_default,
1260 .flat = flat,
1261 };
1262
1263 unsigned u;
1264 memcpy(&u, &p, sizeof(p));
1265 ins.load_store.varying_parameters = u;
1266
1267 if (indirect_offset) {
1268 ins.src[2] = nir_src_index(ctx, indirect_offset);
1269 ins.src_types[2] = nir_type_uint32;
1270 } else
1271 ins.load_store.arg_2 = 0x1E;
1272
1273 ins.load_store.arg_1 = 0x9E;
1274
1275 /* Use the type appropriate load */
1276 switch (type) {
1277 case nir_type_uint32:
1278 case nir_type_bool32:
1279 ins.load_store.op = midgard_op_ld_vary_32u;
1280 break;
1281 case nir_type_int32:
1282 ins.load_store.op = midgard_op_ld_vary_32i;
1283 break;
1284 case nir_type_float32:
1285 ins.load_store.op = midgard_op_ld_vary_32;
1286 break;
1287 case nir_type_float16:
1288 ins.load_store.op = midgard_op_ld_vary_16;
1289 break;
1290 default:
1291 unreachable("Attempted to load unknown type");
1292 break;
1293 }
1294
1295 emit_mir_instruction(ctx, ins);
1296 }
1297
1298 static void
1299 emit_attr_read(
1300 compiler_context *ctx,
1301 unsigned dest, unsigned offset,
1302 unsigned nr_comp, nir_alu_type t)
1303 {
1304 midgard_instruction ins = m_ld_attr_32(dest, offset);
1305 ins.load_store.arg_1 = 0x1E;
1306 ins.load_store.arg_2 = 0x1E;
1307 ins.mask = mask_of(nr_comp);
1308
1309 /* Use the type appropriate load */
1310 switch (t) {
1311 case nir_type_uint:
1312 case nir_type_bool:
1313 ins.load_store.op = midgard_op_ld_attr_32u;
1314 break;
1315 case nir_type_int:
1316 ins.load_store.op = midgard_op_ld_attr_32i;
1317 break;
1318 case nir_type_float:
1319 ins.load_store.op = midgard_op_ld_attr_32;
1320 break;
1321 default:
1322 unreachable("Attempted to load unknown type");
1323 break;
1324 }
1325
1326 emit_mir_instruction(ctx, ins);
1327 }
1328
1329 static void
1330 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1331 unsigned nr_components, unsigned offset)
1332 {
1333 nir_dest nir_dest;
1334
1335 /* Figure out which uniform this is */
1336 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1337 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1338
1339 unsigned dest = nir_dest_index(&nir_dest);
1340
1341 /* Sysvals are prefix uniforms */
1342 unsigned uniform = ((uintptr_t) val) - 1;
1343
1344 /* Emit the read itself -- this is never indirect */
1345 midgard_instruction *ins =
1346 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1347
1348 ins->mask = mask_of(nr_components);
1349 }
1350
1351 static unsigned
1352 compute_builtin_arg(nir_op op)
1353 {
1354 switch (op) {
1355 case nir_intrinsic_load_work_group_id:
1356 return 0x14;
1357 case nir_intrinsic_load_local_invocation_id:
1358 return 0x10;
1359 default:
1360 unreachable("Invalid compute paramater loaded");
1361 }
1362 }
1363
1364 static void
1365 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1366 {
1367 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1368
1369 midgard_instruction *br = ctx->writeout_branch[rt];
1370
1371 assert(!br);
1372
1373 emit_explicit_constant(ctx, src, src);
1374
1375 struct midgard_instruction ins =
1376 v_branch(false, false);
1377
1378 ins.writeout = true;
1379
1380 /* Add dependencies */
1381 ins.src[0] = src;
1382 ins.src_types[0] = nir_type_uint32;
1383 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1384 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1385
1386 /* Emit the branch */
1387 br = emit_mir_instruction(ctx, ins);
1388 schedule_barrier(ctx);
1389 ctx->writeout_branch[rt] = br;
1390
1391 /* Push our current location = current block count - 1 = where we'll
1392 * jump to. Maybe a bit too clever for my own good */
1393
1394 br->branch.target_block = ctx->block_count - 1;
1395 }
1396
1397 static void
1398 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1399 {
1400 unsigned reg = nir_dest_index(&instr->dest);
1401 midgard_instruction ins = m_ld_compute_id(reg, 0);
1402 ins.mask = mask_of(3);
1403 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1404 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1405 emit_mir_instruction(ctx, ins);
1406 }
1407
1408 static unsigned
1409 vertex_builtin_arg(nir_op op)
1410 {
1411 switch (op) {
1412 case nir_intrinsic_load_vertex_id:
1413 return PAN_VERTEX_ID;
1414 case nir_intrinsic_load_instance_id:
1415 return PAN_INSTANCE_ID;
1416 default:
1417 unreachable("Invalid vertex builtin");
1418 }
1419 }
1420
1421 static void
1422 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1423 {
1424 unsigned reg = nir_dest_index(&instr->dest);
1425 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1426 }
1427
1428 static void
1429 emit_control_barrier(compiler_context *ctx)
1430 {
1431 midgard_instruction ins = {
1432 .type = TAG_TEXTURE_4,
1433 .dest = ~0,
1434 .src = { ~0, ~0, ~0, ~0 },
1435 .texture = {
1436 .op = TEXTURE_OP_BARRIER,
1437
1438 /* TODO: optimize */
1439 .out_of_order = MIDGARD_BARRIER_BUFFER |
1440 MIDGARD_BARRIER_SHARED ,
1441 }
1442 };
1443
1444 emit_mir_instruction(ctx, ins);
1445 }
1446
1447 static const nir_variable *
1448 search_var(struct exec_list *vars, unsigned driver_loc)
1449 {
1450 nir_foreach_variable(var, vars) {
1451 if (var->data.driver_location == driver_loc)
1452 return var;
1453 }
1454
1455 return NULL;
1456 }
1457
1458 static unsigned
1459 mir_get_branch_cond(nir_src *src, bool *invert)
1460 {
1461 /* Wrap it. No swizzle since it's a scalar */
1462
1463 nir_alu_src alu = {
1464 .src = *src
1465 };
1466
1467 *invert = pan_has_source_mod(&alu, nir_op_inot);
1468 return nir_src_index(NULL, &alu.src);
1469 }
1470
1471 static void
1472 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1473 {
1474 unsigned offset = 0, reg;
1475
1476 switch (instr->intrinsic) {
1477 case nir_intrinsic_discard_if:
1478 case nir_intrinsic_discard: {
1479 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1480 struct midgard_instruction discard = v_branch(conditional, false);
1481 discard.branch.target_type = TARGET_DISCARD;
1482
1483 if (conditional) {
1484 discard.src[0] = mir_get_branch_cond(&instr->src[0],
1485 &discard.branch.invert_conditional);
1486 discard.src_types[0] = nir_type_uint32;
1487 }
1488
1489 emit_mir_instruction(ctx, discard);
1490 schedule_barrier(ctx);
1491
1492 break;
1493 }
1494
1495 case nir_intrinsic_load_uniform:
1496 case nir_intrinsic_load_ubo:
1497 case nir_intrinsic_load_global:
1498 case nir_intrinsic_load_shared:
1499 case nir_intrinsic_load_input:
1500 case nir_intrinsic_load_interpolated_input: {
1501 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1502 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1503 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1504 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1505 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1506 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1507
1508 /* Get the base type of the intrinsic */
1509 /* TODO: Infer type? Does it matter? */
1510 nir_alu_type t =
1511 (is_ubo || is_global || is_shared) ? nir_type_uint :
1512 (is_interp) ? nir_type_float :
1513 nir_intrinsic_type(instr);
1514
1515 t = nir_alu_type_get_base_type(t);
1516
1517 if (!(is_ubo || is_global)) {
1518 offset = nir_intrinsic_base(instr);
1519 }
1520
1521 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1522
1523 nir_src *src_offset = nir_get_io_offset_src(instr);
1524
1525 bool direct = nir_src_is_const(*src_offset);
1526 nir_src *indirect_offset = direct ? NULL : src_offset;
1527
1528 if (direct)
1529 offset += nir_src_as_uint(*src_offset);
1530
1531 /* We may need to apply a fractional offset */
1532 int component = (is_flat || is_interp) ?
1533 nir_intrinsic_component(instr) : 0;
1534 reg = nir_dest_index(&instr->dest);
1535
1536 if (is_uniform && !ctx->is_blend) {
1537 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1538 } else if (is_ubo) {
1539 nir_src index = instr->src[0];
1540
1541 /* TODO: Is indirect block number possible? */
1542 assert(nir_src_is_const(index));
1543
1544 uint32_t uindex = nir_src_as_uint(index) + 1;
1545 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1546 } else if (is_global || is_shared) {
1547 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1548 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1549 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t | nir_dest_bit_size(instr->dest), is_flat);
1550 } else if (ctx->is_blend) {
1551 /* For blend shaders, load the input color, which is
1552 * preloaded to r0 */
1553
1554 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1555 emit_mir_instruction(ctx, move);
1556 schedule_barrier(ctx);
1557 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1558 emit_attr_read(ctx, reg, offset, nr_comp, t);
1559 } else {
1560 DBG("Unknown load\n");
1561 assert(0);
1562 }
1563
1564 break;
1565 }
1566
1567 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1568 case nir_intrinsic_load_barycentric_pixel:
1569 case nir_intrinsic_load_barycentric_centroid:
1570 break;
1571
1572 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1573
1574 case nir_intrinsic_load_raw_output_pan:
1575 case nir_intrinsic_load_output_u8_as_fp16_pan:
1576 reg = nir_dest_index(&instr->dest);
1577 assert(ctx->is_blend);
1578
1579 /* T720 and below use different blend opcodes with slightly
1580 * different semantics than T760 and up */
1581
1582 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1583 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1584
1585 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1586 ld.load_store.op = old_blend ?
1587 midgard_op_ld_color_buffer_as_fp16_old :
1588 midgard_op_ld_color_buffer_as_fp16;
1589
1590 for (unsigned c = 4; c < 16; ++c)
1591 ld.swizzle[0][c] = 0;
1592
1593 ld.dest_type = nir_type_float16;
1594
1595 if (old_blend) {
1596 ld.load_store.address = 1;
1597 ld.load_store.arg_2 = 0x1E;
1598 }
1599 } else if (old_blend) {
1600 ld.load_store.op = midgard_op_ld_color_buffer_32u_old;
1601 ld.load_store.address = 16;
1602 ld.load_store.arg_2 = 0x1E;
1603 }
1604
1605 emit_mir_instruction(ctx, ld);
1606 break;
1607
1608 case nir_intrinsic_load_blend_const_color_rgba: {
1609 assert(ctx->is_blend);
1610 reg = nir_dest_index(&instr->dest);
1611
1612 /* Blend constants are embedded directly in the shader and
1613 * patched in, so we use some magic routing */
1614
1615 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1616 ins.has_constants = true;
1617 ins.has_blend_constant = true;
1618 emit_mir_instruction(ctx, ins);
1619 break;
1620 }
1621
1622 case nir_intrinsic_store_zs_output_pan: {
1623 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1624 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1625 MIDGARD_ZS_RT);
1626
1627 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1628
1629 if (!nir_intrinsic_component(instr))
1630 br->writeout_depth = true;
1631 if (nir_intrinsic_component(instr) ||
1632 instr->num_components)
1633 br->writeout_stencil = true;
1634 assert(br->writeout_depth | br->writeout_stencil);
1635 break;
1636 }
1637
1638 case nir_intrinsic_store_output:
1639 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1640
1641 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1642
1643 reg = nir_src_index(ctx, &instr->src[0]);
1644
1645 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1646 const nir_variable *var;
1647 enum midgard_rt_id rt;
1648
1649 var = search_var(&ctx->nir->outputs,
1650 nir_intrinsic_base(instr));
1651 assert(var);
1652 if (var->data.location == FRAG_RESULT_COLOR)
1653 rt = MIDGARD_COLOR_RT0;
1654 else if (var->data.location >= FRAG_RESULT_DATA0)
1655 rt = MIDGARD_COLOR_RT0 + var->data.location -
1656 FRAG_RESULT_DATA0;
1657 else
1658 assert(0);
1659
1660 emit_fragment_store(ctx, reg, rt);
1661 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1662 /* We should have been vectorized, though we don't
1663 * currently check that st_vary is emitted only once
1664 * per slot (this is relevant, since there's not a mask
1665 * parameter available on the store [set to 0 by the
1666 * blob]). We do respect the component by adjusting the
1667 * swizzle. If this is a constant source, we'll need to
1668 * emit that explicitly. */
1669
1670 emit_explicit_constant(ctx, reg, reg);
1671
1672 unsigned dst_component = nir_intrinsic_component(instr);
1673 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1674
1675 midgard_instruction st = m_st_vary_32(reg, offset);
1676 st.load_store.arg_1 = 0x9E;
1677 st.load_store.arg_2 = 0x1E;
1678
1679 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1680 case nir_type_uint:
1681 case nir_type_bool:
1682 st.load_store.op = midgard_op_st_vary_32u;
1683 break;
1684 case nir_type_int:
1685 st.load_store.op = midgard_op_st_vary_32i;
1686 break;
1687 case nir_type_float:
1688 st.load_store.op = midgard_op_st_vary_32;
1689 break;
1690 default:
1691 unreachable("Attempted to store unknown type");
1692 break;
1693 }
1694
1695 /* nir_intrinsic_component(store_intr) encodes the
1696 * destination component start. Source component offset
1697 * adjustment is taken care of in
1698 * install_registers_instr(), when offset_swizzle() is
1699 * called.
1700 */
1701 unsigned src_component = COMPONENT_X;
1702
1703 assert(nr_comp > 0);
1704 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1705 st.swizzle[0][i] = src_component;
1706 if (i >= dst_component && i < dst_component + nr_comp - 1)
1707 src_component++;
1708 }
1709
1710 emit_mir_instruction(ctx, st);
1711 } else {
1712 DBG("Unknown store\n");
1713 assert(0);
1714 }
1715
1716 break;
1717
1718 /* Special case of store_output for lowered blend shaders */
1719 case nir_intrinsic_store_raw_output_pan:
1720 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1721 reg = nir_src_index(ctx, &instr->src[0]);
1722 emit_fragment_store(ctx, reg, ctx->blend_rt);
1723 break;
1724
1725 case nir_intrinsic_store_global:
1726 case nir_intrinsic_store_shared:
1727 reg = nir_src_index(ctx, &instr->src[0]);
1728 emit_explicit_constant(ctx, reg, reg);
1729
1730 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1731 break;
1732
1733 case nir_intrinsic_load_ssbo_address:
1734 emit_sysval_read(ctx, &instr->instr, 1, 0);
1735 break;
1736
1737 case nir_intrinsic_get_buffer_size:
1738 emit_sysval_read(ctx, &instr->instr, 1, 8);
1739 break;
1740
1741 case nir_intrinsic_load_viewport_scale:
1742 case nir_intrinsic_load_viewport_offset:
1743 case nir_intrinsic_load_num_work_groups:
1744 case nir_intrinsic_load_sampler_lod_parameters_pan:
1745 emit_sysval_read(ctx, &instr->instr, 3, 0);
1746 break;
1747
1748 case nir_intrinsic_load_work_group_id:
1749 case nir_intrinsic_load_local_invocation_id:
1750 emit_compute_builtin(ctx, instr);
1751 break;
1752
1753 case nir_intrinsic_load_vertex_id:
1754 case nir_intrinsic_load_instance_id:
1755 emit_vertex_builtin(ctx, instr);
1756 break;
1757
1758 case nir_intrinsic_memory_barrier_buffer:
1759 case nir_intrinsic_memory_barrier_shared:
1760 break;
1761
1762 case nir_intrinsic_control_barrier:
1763 schedule_barrier(ctx);
1764 emit_control_barrier(ctx);
1765 schedule_barrier(ctx);
1766 break;
1767
1768 default:
1769 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1770 assert(0);
1771 break;
1772 }
1773 }
1774
1775 static unsigned
1776 midgard_tex_format(enum glsl_sampler_dim dim)
1777 {
1778 switch (dim) {
1779 case GLSL_SAMPLER_DIM_1D:
1780 case GLSL_SAMPLER_DIM_BUF:
1781 return MALI_TEX_1D;
1782
1783 case GLSL_SAMPLER_DIM_2D:
1784 case GLSL_SAMPLER_DIM_EXTERNAL:
1785 case GLSL_SAMPLER_DIM_RECT:
1786 return MALI_TEX_2D;
1787
1788 case GLSL_SAMPLER_DIM_3D:
1789 return MALI_TEX_3D;
1790
1791 case GLSL_SAMPLER_DIM_CUBE:
1792 return MALI_TEX_CUBE;
1793
1794 default:
1795 DBG("Unknown sampler dim type\n");
1796 assert(0);
1797 return 0;
1798 }
1799 }
1800
1801 /* Tries to attach an explicit LOD or bias as a constant. Returns whether this
1802 * was successful */
1803
1804 static bool
1805 pan_attach_constant_bias(
1806 compiler_context *ctx,
1807 nir_src lod,
1808 midgard_texture_word *word)
1809 {
1810 /* To attach as constant, it has to *be* constant */
1811
1812 if (!nir_src_is_const(lod))
1813 return false;
1814
1815 float f = nir_src_as_float(lod);
1816
1817 /* Break into fixed-point */
1818 signed lod_int = f;
1819 float lod_frac = f - lod_int;
1820
1821 /* Carry over negative fractions */
1822 if (lod_frac < 0.0) {
1823 lod_int--;
1824 lod_frac += 1.0;
1825 }
1826
1827 /* Encode */
1828 word->bias = float_to_ubyte(lod_frac);
1829 word->bias_int = lod_int;
1830
1831 return true;
1832 }
1833
1834 static void
1835 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1836 unsigned midgard_texop)
1837 {
1838 /* TODO */
1839 //assert (!instr->sampler);
1840
1841 int texture_index = instr->texture_index;
1842 int sampler_index = texture_index;
1843
1844 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1845 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1846
1847 midgard_instruction ins = {
1848 .type = TAG_TEXTURE_4,
1849 .mask = 0xF,
1850 .dest = nir_dest_index(&instr->dest),
1851 .src = { ~0, ~0, ~0, ~0 },
1852 .dest_type = dest_type,
1853 .swizzle = SWIZZLE_IDENTITY_4,
1854 .texture = {
1855 .op = midgard_texop,
1856 .format = midgard_tex_format(instr->sampler_dim),
1857 .texture_handle = texture_index,
1858 .sampler_handle = sampler_index,
1859 .shadow = instr->is_shadow,
1860 }
1861 };
1862
1863 if (instr->is_shadow && !instr->is_new_style_shadow)
1864 for (int i = 0; i < 4; ++i)
1865 ins.swizzle[0][i] = COMPONENT_X;
1866
1867 /* We may need a temporary for the coordinate */
1868
1869 bool needs_temp_coord =
1870 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1871 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1872 (instr->is_shadow);
1873
1874 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1875
1876 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1877 int index = nir_src_index(ctx, &instr->src[i].src);
1878 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1879 unsigned sz = nir_src_bit_size(instr->src[i].src);
1880 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1881
1882 switch (instr->src[i].src_type) {
1883 case nir_tex_src_coord: {
1884 emit_explicit_constant(ctx, index, index);
1885
1886 unsigned coord_mask = mask_of(instr->coord_components);
1887
1888 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1889
1890 if (flip_zw)
1891 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1892
1893 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1894 /* texelFetch is undefined on samplerCube */
1895 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1896
1897 /* For cubemaps, we use a special ld/st op to
1898 * select the face and copy the xy into the
1899 * texture register */
1900
1901 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1902 ld.src[1] = index;
1903 ld.src_types[1] = T;
1904 ld.mask = 0x3; /* xy */
1905 ld.load_store.arg_1 = 0x20;
1906 ld.swizzle[1][3] = COMPONENT_X;
1907 emit_mir_instruction(ctx, ld);
1908
1909 /* xyzw -> xyxx */
1910 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1911 ins.swizzle[1][3] = COMPONENT_X;
1912 } else if (needs_temp_coord) {
1913 /* mov coord_temp, coords */
1914 midgard_instruction mov = v_mov(index, coords);
1915 mov.mask = coord_mask;
1916
1917 if (flip_zw)
1918 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1919
1920 emit_mir_instruction(ctx, mov);
1921 } else {
1922 coords = index;
1923 }
1924
1925 ins.src[1] = coords;
1926 ins.src_types[1] = T;
1927
1928 /* Texelfetch coordinates uses all four elements
1929 * (xyz/index) regardless of texture dimensionality,
1930 * which means it's necessary to zero the unused
1931 * components to keep everything happy */
1932
1933 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1934 /* mov index.zw, #0, or generalized */
1935 midgard_instruction mov =
1936 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1937 mov.has_constants = true;
1938 mov.mask = coord_mask ^ 0xF;
1939 emit_mir_instruction(ctx, mov);
1940 }
1941
1942 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1943 /* Array component in w but NIR wants it in z,
1944 * but if we have a temp coord we already fixed
1945 * that up */
1946
1947 if (nr_components == 3) {
1948 ins.swizzle[1][2] = COMPONENT_Z;
1949 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1950 } else if (nr_components == 2) {
1951 ins.swizzle[1][2] =
1952 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1953 ins.swizzle[1][3] = COMPONENT_X;
1954 } else
1955 unreachable("Invalid texture 2D components");
1956 }
1957
1958 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1959 /* We zeroed */
1960 ins.swizzle[1][2] = COMPONENT_Z;
1961 ins.swizzle[1][3] = COMPONENT_W;
1962 }
1963
1964 break;
1965 }
1966
1967 case nir_tex_src_bias:
1968 case nir_tex_src_lod: {
1969 /* Try as a constant if we can */
1970
1971 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1972 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1973 break;
1974
1975 ins.texture.lod_register = true;
1976 ins.src[2] = index;
1977 ins.src_types[2] = T;
1978
1979 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1980 ins.swizzle[2][c] = COMPONENT_X;
1981
1982 emit_explicit_constant(ctx, index, index);
1983
1984 break;
1985 };
1986
1987 case nir_tex_src_offset: {
1988 ins.texture.offset_register = true;
1989 ins.src[3] = index;
1990 ins.src_types[3] = T;
1991
1992 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1993 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
1994
1995 emit_explicit_constant(ctx, index, index);
1996 break;
1997 };
1998
1999 case nir_tex_src_comparator: {
2000 unsigned comp = COMPONENT_Z;
2001
2002 /* mov coord_temp.foo, coords */
2003 midgard_instruction mov = v_mov(index, coords);
2004 mov.mask = 1 << comp;
2005
2006 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
2007 mov.swizzle[1][i] = COMPONENT_X;
2008
2009 emit_mir_instruction(ctx, mov);
2010 break;
2011 }
2012
2013 default: {
2014 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
2015 assert(0);
2016 }
2017 }
2018 }
2019
2020 emit_mir_instruction(ctx, ins);
2021 }
2022
2023 static void
2024 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
2025 {
2026 switch (instr->op) {
2027 case nir_texop_tex:
2028 case nir_texop_txb:
2029 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
2030 break;
2031 case nir_texop_txl:
2032 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
2033 break;
2034 case nir_texop_txf:
2035 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
2036 break;
2037 case nir_texop_txs:
2038 emit_sysval_read(ctx, &instr->instr, 4, 0);
2039 break;
2040 default: {
2041 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
2042 assert(0);
2043 }
2044 }
2045 }
2046
2047 static void
2048 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
2049 {
2050 switch (instr->type) {
2051 case nir_jump_break: {
2052 /* Emit a branch out of the loop */
2053 struct midgard_instruction br = v_branch(false, false);
2054 br.branch.target_type = TARGET_BREAK;
2055 br.branch.target_break = ctx->current_loop_depth;
2056 emit_mir_instruction(ctx, br);
2057 break;
2058 }
2059
2060 default:
2061 DBG("Unknown jump type %d\n", instr->type);
2062 break;
2063 }
2064 }
2065
2066 static void
2067 emit_instr(compiler_context *ctx, struct nir_instr *instr)
2068 {
2069 switch (instr->type) {
2070 case nir_instr_type_load_const:
2071 emit_load_const(ctx, nir_instr_as_load_const(instr));
2072 break;
2073
2074 case nir_instr_type_intrinsic:
2075 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2076 break;
2077
2078 case nir_instr_type_alu:
2079 emit_alu(ctx, nir_instr_as_alu(instr));
2080 break;
2081
2082 case nir_instr_type_tex:
2083 emit_tex(ctx, nir_instr_as_tex(instr));
2084 break;
2085
2086 case nir_instr_type_jump:
2087 emit_jump(ctx, nir_instr_as_jump(instr));
2088 break;
2089
2090 case nir_instr_type_ssa_undef:
2091 /* Spurious */
2092 break;
2093
2094 default:
2095 DBG("Unhandled instruction type\n");
2096 break;
2097 }
2098 }
2099
2100
2101 /* ALU instructions can inline or embed constants, which decreases register
2102 * pressure and saves space. */
2103
2104 #define CONDITIONAL_ATTACH(idx) { \
2105 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2106 \
2107 if (entry) { \
2108 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2109 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2110 } \
2111 }
2112
2113 static void
2114 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2115 {
2116 mir_foreach_instr_in_block(block, alu) {
2117 /* Other instructions cannot inline constants */
2118 if (alu->type != TAG_ALU_4) continue;
2119 if (alu->compact_branch) continue;
2120
2121 /* If there is already a constant here, we can do nothing */
2122 if (alu->has_constants) continue;
2123
2124 CONDITIONAL_ATTACH(0);
2125
2126 if (!alu->has_constants) {
2127 CONDITIONAL_ATTACH(1)
2128 } else if (!alu->inline_constant) {
2129 /* Corner case: _two_ vec4 constants, for instance with a
2130 * csel. For this case, we can only use a constant
2131 * register for one, we'll have to emit a move for the
2132 * other. */
2133
2134 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2135 unsigned scratch = make_compiler_temp(ctx);
2136
2137 if (entry) {
2138 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2139 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2140
2141 /* Set the source */
2142 alu->src[1] = scratch;
2143
2144 /* Inject us -before- the last instruction which set r31 */
2145 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2146 }
2147 }
2148 }
2149 }
2150
2151 /* Midgard supports two types of constants, embedded constants (128-bit) and
2152 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2153 * constants can be demoted to inline constants, for space savings and
2154 * sometimes a performance boost */
2155
2156 static void
2157 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2158 {
2159 mir_foreach_instr_in_block(block, ins) {
2160 if (!ins->has_constants) continue;
2161 if (ins->has_inline_constant) continue;
2162
2163 /* Blend constants must not be inlined by definition */
2164 if (ins->has_blend_constant) continue;
2165
2166 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2167 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2168 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2169
2170 if (!(is_16 || is_32))
2171 continue;
2172
2173 /* src1 cannot be an inline constant due to encoding
2174 * restrictions. So, if possible we try to flip the arguments
2175 * in that case */
2176
2177 int op = ins->alu.op;
2178
2179 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2180 alu_opcode_props[op].props & OP_COMMUTES) {
2181 mir_flip(ins);
2182 }
2183
2184 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2185 /* Component is from the swizzle. Take a nonzero component */
2186 assert(ins->mask);
2187 unsigned first_comp = ffs(ins->mask) - 1;
2188 unsigned component = ins->swizzle[1][first_comp];
2189
2190 /* Scale constant appropriately, if we can legally */
2191 uint16_t scaled_constant = 0;
2192
2193 if (is_16) {
2194 scaled_constant = ins->constants.u16[component];
2195 } else if (midgard_is_integer_op(op)) {
2196 scaled_constant = ins->constants.u32[component];
2197
2198 /* Constant overflow after resize */
2199 if (scaled_constant != ins->constants.u32[component])
2200 continue;
2201 } else {
2202 float original = ins->constants.f32[component];
2203 scaled_constant = _mesa_float_to_half(original);
2204
2205 /* Check for loss of precision. If this is
2206 * mediump, we don't care, but for a highp
2207 * shader, we need to pay attention. NIR
2208 * doesn't yet tell us which mode we're in!
2209 * Practically this prevents most constants
2210 * from being inlined, sadly. */
2211
2212 float fp32 = _mesa_half_to_float(scaled_constant);
2213
2214 if (fp32 != original)
2215 continue;
2216 }
2217
2218 /* Should've been const folded */
2219 if (ins->src_abs[1] || ins->src_neg[1])
2220 continue;
2221
2222 /* Make sure that the constant is not itself a vector
2223 * by checking if all accessed values are the same. */
2224
2225 const midgard_constants *cons = &ins->constants;
2226 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2227
2228 bool is_vector = false;
2229 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2230
2231 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2232 /* We only care if this component is actually used */
2233 if (!(mask & (1 << c)))
2234 continue;
2235
2236 uint32_t test = is_16 ?
2237 cons->u16[ins->swizzle[1][c]] :
2238 cons->u32[ins->swizzle[1][c]];
2239
2240 if (test != value) {
2241 is_vector = true;
2242 break;
2243 }
2244 }
2245
2246 if (is_vector)
2247 continue;
2248
2249 /* Get rid of the embedded constant */
2250 ins->has_constants = false;
2251 ins->src[1] = ~0;
2252 ins->has_inline_constant = true;
2253 ins->inline_constant = scaled_constant;
2254 }
2255 }
2256 }
2257
2258 /* Dead code elimination for branches at the end of a block - only one branch
2259 * per block is legal semantically */
2260
2261 static void
2262 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2263 {
2264 bool branched = false;
2265
2266 mir_foreach_instr_in_block_safe(block, ins) {
2267 if (!midgard_is_branch_unit(ins->unit)) continue;
2268
2269 if (branched)
2270 mir_remove_instruction(ins);
2271
2272 branched = true;
2273 }
2274 }
2275
2276 static unsigned
2277 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2278 {
2279 /* Loop to ourselves */
2280 midgard_instruction *br = ctx->writeout_branch[rt];
2281 struct midgard_instruction ins = v_branch(false, false);
2282 ins.writeout = true;
2283 ins.writeout_depth = br->writeout_depth;
2284 ins.writeout_stencil = br->writeout_stencil;
2285 ins.branch.target_block = ctx->block_count - 1;
2286 ins.constants.u32[0] = br->constants.u32[0];
2287 emit_mir_instruction(ctx, ins);
2288
2289 ctx->current_block->epilogue = true;
2290 schedule_barrier(ctx);
2291 return ins.branch.target_block;
2292 }
2293
2294 static midgard_block *
2295 emit_block(compiler_context *ctx, nir_block *block)
2296 {
2297 midgard_block *this_block = ctx->after_block;
2298 ctx->after_block = NULL;
2299
2300 if (!this_block)
2301 this_block = create_empty_block(ctx);
2302
2303 list_addtail(&this_block->base.link, &ctx->blocks);
2304
2305 this_block->scheduled = false;
2306 ++ctx->block_count;
2307
2308 /* Set up current block */
2309 list_inithead(&this_block->base.instructions);
2310 ctx->current_block = this_block;
2311
2312 nir_foreach_instr(instr, block) {
2313 emit_instr(ctx, instr);
2314 ++ctx->instruction_count;
2315 }
2316
2317 return this_block;
2318 }
2319
2320 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2321
2322 static void
2323 emit_if(struct compiler_context *ctx, nir_if *nif)
2324 {
2325 midgard_block *before_block = ctx->current_block;
2326
2327 /* Speculatively emit the branch, but we can't fill it in until later */
2328 bool inv = false;
2329 EMIT(branch, true, true);
2330 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2331 then_branch->src[0] = mir_get_branch_cond(&nif->condition, &inv);
2332 then_branch->src_types[0] = nir_type_uint32;
2333 then_branch->branch.invert_conditional = !inv;
2334
2335 /* Emit the two subblocks. */
2336 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2337 midgard_block *end_then_block = ctx->current_block;
2338
2339 /* Emit a jump from the end of the then block to the end of the else */
2340 EMIT(branch, false, false);
2341 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2342
2343 /* Emit second block, and check if it's empty */
2344
2345 int else_idx = ctx->block_count;
2346 int count_in = ctx->instruction_count;
2347 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2348 midgard_block *end_else_block = ctx->current_block;
2349 int after_else_idx = ctx->block_count;
2350
2351 /* Now that we have the subblocks emitted, fix up the branches */
2352
2353 assert(then_block);
2354 assert(else_block);
2355
2356 if (ctx->instruction_count == count_in) {
2357 /* The else block is empty, so don't emit an exit jump */
2358 mir_remove_instruction(then_exit);
2359 then_branch->branch.target_block = after_else_idx;
2360 } else {
2361 then_branch->branch.target_block = else_idx;
2362 then_exit->branch.target_block = after_else_idx;
2363 }
2364
2365 /* Wire up the successors */
2366
2367 ctx->after_block = create_empty_block(ctx);
2368
2369 pan_block_add_successor(&before_block->base, &then_block->base);
2370 pan_block_add_successor(&before_block->base, &else_block->base);
2371
2372 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2373 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2374 }
2375
2376 static void
2377 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2378 {
2379 /* Remember where we are */
2380 midgard_block *start_block = ctx->current_block;
2381
2382 /* Allocate a loop number, growing the current inner loop depth */
2383 int loop_idx = ++ctx->current_loop_depth;
2384
2385 /* Get index from before the body so we can loop back later */
2386 int start_idx = ctx->block_count;
2387
2388 /* Emit the body itself */
2389 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2390
2391 /* Branch back to loop back */
2392 struct midgard_instruction br_back = v_branch(false, false);
2393 br_back.branch.target_block = start_idx;
2394 emit_mir_instruction(ctx, br_back);
2395
2396 /* Mark down that branch in the graph. */
2397 pan_block_add_successor(&start_block->base, &loop_block->base);
2398 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2399
2400 /* Find the index of the block about to follow us (note: we don't add
2401 * one; blocks are 0-indexed so we get a fencepost problem) */
2402 int break_block_idx = ctx->block_count;
2403
2404 /* Fix up the break statements we emitted to point to the right place,
2405 * now that we can allocate a block number for them */
2406 ctx->after_block = create_empty_block(ctx);
2407
2408 mir_foreach_block_from(ctx, start_block, _block) {
2409 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2410 if (ins->type != TAG_ALU_4) continue;
2411 if (!ins->compact_branch) continue;
2412
2413 /* We found a branch -- check the type to see if we need to do anything */
2414 if (ins->branch.target_type != TARGET_BREAK) continue;
2415
2416 /* It's a break! Check if it's our break */
2417 if (ins->branch.target_break != loop_idx) continue;
2418
2419 /* Okay, cool, we're breaking out of this loop.
2420 * Rewrite from a break to a goto */
2421
2422 ins->branch.target_type = TARGET_GOTO;
2423 ins->branch.target_block = break_block_idx;
2424
2425 pan_block_add_successor(_block, &ctx->after_block->base);
2426 }
2427 }
2428
2429 /* Now that we've finished emitting the loop, free up the depth again
2430 * so we play nice with recursion amid nested loops */
2431 --ctx->current_loop_depth;
2432
2433 /* Dump loop stats */
2434 ++ctx->loop_count;
2435 }
2436
2437 static midgard_block *
2438 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2439 {
2440 midgard_block *start_block = NULL;
2441
2442 foreach_list_typed(nir_cf_node, node, node, list) {
2443 switch (node->type) {
2444 case nir_cf_node_block: {
2445 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2446
2447 if (!start_block)
2448 start_block = block;
2449
2450 break;
2451 }
2452
2453 case nir_cf_node_if:
2454 emit_if(ctx, nir_cf_node_as_if(node));
2455 break;
2456
2457 case nir_cf_node_loop:
2458 emit_loop(ctx, nir_cf_node_as_loop(node));
2459 break;
2460
2461 case nir_cf_node_function:
2462 assert(0);
2463 break;
2464 }
2465 }
2466
2467 return start_block;
2468 }
2469
2470 /* Due to lookahead, we need to report the first tag executed in the command
2471 * stream and in branch targets. An initial block might be empty, so iterate
2472 * until we find one that 'works' */
2473
2474 static unsigned
2475 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2476 {
2477 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2478
2479 mir_foreach_block_from(ctx, initial_block, _v) {
2480 midgard_block *v = (midgard_block *) _v;
2481 if (v->quadword_count) {
2482 midgard_bundle *initial_bundle =
2483 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2484
2485 return initial_bundle->tag;
2486 }
2487 }
2488
2489 /* Default to a tag 1 which will break from the shader, in case we jump
2490 * to the exit block (i.e. `return` in a compute shader) */
2491
2492 return 1;
2493 }
2494
2495 /* For each fragment writeout instruction, generate a writeout loop to
2496 * associate with it */
2497
2498 static void
2499 mir_add_writeout_loops(compiler_context *ctx)
2500 {
2501 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2502 midgard_instruction *br = ctx->writeout_branch[rt];
2503 if (!br) continue;
2504
2505 unsigned popped = br->branch.target_block;
2506 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2507 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2508 br->branch.target_type = TARGET_GOTO;
2509
2510 /* If we have more RTs, we'll need to restore back after our
2511 * loop terminates */
2512
2513 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2514 midgard_instruction uncond = v_branch(false, false);
2515 uncond.branch.target_block = popped;
2516 uncond.branch.target_type = TARGET_GOTO;
2517 emit_mir_instruction(ctx, uncond);
2518 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2519 schedule_barrier(ctx);
2520 } else {
2521 /* We're last, so we can terminate here */
2522 br->last_writeout = true;
2523 }
2524 }
2525 }
2526
2527 int
2528 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2529 {
2530 struct util_dynarray *compiled = &program->compiled;
2531
2532 midgard_debug = debug_get_option_midgard_debug();
2533
2534 /* TODO: Bound against what? */
2535 compiler_context *ctx = rzalloc(NULL, compiler_context);
2536
2537 ctx->nir = nir;
2538 ctx->stage = nir->info.stage;
2539 ctx->is_blend = is_blend;
2540 ctx->alpha_ref = program->alpha_ref;
2541 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2542 ctx->quirks = midgard_get_quirks(gpu_id);
2543
2544 /* Start off with a safe cutoff, allowing usage of all 16 work
2545 * registers. Later, we'll promote uniform reads to uniform registers
2546 * if we determine it is beneficial to do so */
2547 ctx->uniform_cutoff = 8;
2548
2549 /* Initialize at a global (not block) level hash tables */
2550
2551 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2552 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2553
2554 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2555 * (so we don't accidentally duplicate the epilogue since mesa/st has
2556 * messed with our I/O quite a bit already) */
2557
2558 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2559
2560 if (ctx->stage == MESA_SHADER_VERTEX) {
2561 NIR_PASS_V(nir, nir_lower_viewport_transform);
2562 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2563 }
2564
2565 NIR_PASS_V(nir, nir_lower_var_copies);
2566 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2567 NIR_PASS_V(nir, nir_split_var_copies);
2568 NIR_PASS_V(nir, nir_lower_var_copies);
2569 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2570 NIR_PASS_V(nir, nir_lower_var_copies);
2571 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2572
2573 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2574 NIR_PASS_V(nir, nir_lower_ssbo);
2575 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2576
2577 /* Optimisation passes */
2578
2579 optimise_nir(nir, ctx->quirks, is_blend);
2580
2581 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2582 nir_print_shader(nir, stdout);
2583 }
2584
2585 /* Assign sysvals and counts, now that we're sure
2586 * (post-optimisation) */
2587
2588 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2589 program->sysval_count = ctx->sysvals.sysval_count;
2590 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2591
2592 nir_foreach_function(func, nir) {
2593 if (!func->impl)
2594 continue;
2595
2596 list_inithead(&ctx->blocks);
2597 ctx->block_count = 0;
2598 ctx->func = func;
2599 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
2600
2601 emit_cf_list(ctx, &func->impl->body);
2602 free(ctx->already_emitted);
2603 break; /* TODO: Multi-function shaders */
2604 }
2605
2606 util_dynarray_init(compiled, NULL);
2607
2608 /* Per-block lowering before opts */
2609
2610 mir_foreach_block(ctx, _block) {
2611 midgard_block *block = (midgard_block *) _block;
2612 inline_alu_constants(ctx, block);
2613 embedded_to_inline_constant(ctx, block);
2614 }
2615 /* MIR-level optimizations */
2616
2617 bool progress = false;
2618
2619 do {
2620 progress = false;
2621 progress |= midgard_opt_dead_code_eliminate(ctx);
2622
2623 mir_foreach_block(ctx, _block) {
2624 midgard_block *block = (midgard_block *) _block;
2625 progress |= midgard_opt_copy_prop(ctx, block);
2626 progress |= midgard_opt_combine_projection(ctx, block);
2627 progress |= midgard_opt_varying_projection(ctx, block);
2628 }
2629 } while (progress);
2630
2631 mir_foreach_block(ctx, _block) {
2632 midgard_block *block = (midgard_block *) _block;
2633 midgard_lower_derivatives(ctx, block);
2634 midgard_cull_dead_branch(ctx, block);
2635 }
2636
2637 if (ctx->stage == MESA_SHADER_FRAGMENT)
2638 mir_add_writeout_loops(ctx);
2639
2640 /* Analyze now that the code is known but before scheduling creates
2641 * pipeline registers which are harder to track */
2642 mir_analyze_helper_terminate(ctx);
2643 mir_analyze_helper_requirements(ctx);
2644
2645 /* Schedule! */
2646 midgard_schedule_program(ctx);
2647 mir_ra(ctx);
2648
2649 /* Now that all the bundles are scheduled and we can calculate block
2650 * sizes, emit actual branch instructions rather than placeholders */
2651
2652 int br_block_idx = 0;
2653
2654 mir_foreach_block(ctx, _block) {
2655 midgard_block *block = (midgard_block *) _block;
2656 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2657 for (int c = 0; c < bundle->instruction_count; ++c) {
2658 midgard_instruction *ins = bundle->instructions[c];
2659
2660 if (!midgard_is_branch_unit(ins->unit)) continue;
2661
2662 /* Parse some basic branch info */
2663 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2664 bool is_conditional = ins->branch.conditional;
2665 bool is_inverted = ins->branch.invert_conditional;
2666 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2667 bool is_writeout = ins->writeout;
2668
2669 /* Determine the block we're jumping to */
2670 int target_number = ins->branch.target_block;
2671
2672 /* Report the destination tag */
2673 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2674
2675 /* Count up the number of quadwords we're
2676 * jumping over = number of quadwords until
2677 * (br_block_idx, target_number) */
2678
2679 int quadword_offset = 0;
2680
2681 if (is_discard) {
2682 /* Ignored */
2683 } else if (target_number > br_block_idx) {
2684 /* Jump forward */
2685
2686 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2687 midgard_block *blk = mir_get_block(ctx, idx);
2688 assert(blk);
2689
2690 quadword_offset += blk->quadword_count;
2691 }
2692 } else {
2693 /* Jump backwards */
2694
2695 for (int idx = br_block_idx; idx >= target_number; --idx) {
2696 midgard_block *blk = mir_get_block(ctx, idx);
2697 assert(blk);
2698
2699 quadword_offset -= blk->quadword_count;
2700 }
2701 }
2702
2703 /* Unconditional extended branches (far jumps)
2704 * have issues, so we always use a conditional
2705 * branch, setting the condition to always for
2706 * unconditional. For compact unconditional
2707 * branches, cond isn't used so it doesn't
2708 * matter what we pick. */
2709
2710 midgard_condition cond =
2711 !is_conditional ? midgard_condition_always :
2712 is_inverted ? midgard_condition_false :
2713 midgard_condition_true;
2714
2715 midgard_jmp_writeout_op op =
2716 is_discard ? midgard_jmp_writeout_op_discard :
2717 is_writeout ? midgard_jmp_writeout_op_writeout :
2718 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2719 midgard_jmp_writeout_op_branch_cond;
2720
2721 if (!is_compact) {
2722 midgard_branch_extended branch =
2723 midgard_create_branch_extended(
2724 cond, op,
2725 dest_tag,
2726 quadword_offset);
2727
2728 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2729 } else if (is_conditional || is_discard) {
2730 midgard_branch_cond branch = {
2731 .op = op,
2732 .dest_tag = dest_tag,
2733 .offset = quadword_offset,
2734 .cond = cond
2735 };
2736
2737 assert(branch.offset == quadword_offset);
2738
2739 memcpy(&ins->br_compact, &branch, sizeof(branch));
2740 } else {
2741 assert(op == midgard_jmp_writeout_op_branch_uncond);
2742
2743 midgard_branch_uncond branch = {
2744 .op = op,
2745 .dest_tag = dest_tag,
2746 .offset = quadword_offset,
2747 .unknown = 1
2748 };
2749
2750 assert(branch.offset == quadword_offset);
2751
2752 memcpy(&ins->br_compact, &branch, sizeof(branch));
2753 }
2754 }
2755 }
2756
2757 ++br_block_idx;
2758 }
2759
2760 /* Emit flat binary from the instruction arrays. Iterate each block in
2761 * sequence. Save instruction boundaries such that lookahead tags can
2762 * be assigned easily */
2763
2764 /* Cache _all_ bundles in source order for lookahead across failed branches */
2765
2766 int bundle_count = 0;
2767 mir_foreach_block(ctx, _block) {
2768 midgard_block *block = (midgard_block *) _block;
2769 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2770 }
2771 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2772 int bundle_idx = 0;
2773 mir_foreach_block(ctx, _block) {
2774 midgard_block *block = (midgard_block *) _block;
2775 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2776 source_order_bundles[bundle_idx++] = bundle;
2777 }
2778 }
2779
2780 int current_bundle = 0;
2781
2782 /* Midgard prefetches instruction types, so during emission we
2783 * need to lookahead. Unless this is the last instruction, in
2784 * which we return 1. */
2785
2786 mir_foreach_block(ctx, _block) {
2787 midgard_block *block = (midgard_block *) _block;
2788 mir_foreach_bundle_in_block(block, bundle) {
2789 int lookahead = 1;
2790
2791 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2792 lookahead = source_order_bundles[current_bundle + 1]->tag;
2793
2794 emit_binary_bundle(ctx, block, bundle, compiled, lookahead);
2795 ++current_bundle;
2796 }
2797
2798 /* TODO: Free deeper */
2799 //util_dynarray_fini(&block->instructions);
2800 }
2801
2802 free(source_order_bundles);
2803
2804 /* Report the very first tag executed */
2805 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2806
2807 /* Deal with off-by-one related to the fencepost problem */
2808 program->work_register_count = ctx->work_registers + 1;
2809 program->uniform_cutoff = ctx->uniform_cutoff;
2810
2811 program->blend_patch_offset = ctx->blend_constant_offset;
2812 program->tls_size = ctx->tls_size;
2813
2814 if (midgard_debug & MIDGARD_DBG_SHADERS)
2815 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2816
2817 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2818 unsigned nr_bundles = 0, nr_ins = 0;
2819
2820 /* Count instructions and bundles */
2821
2822 mir_foreach_block(ctx, _block) {
2823 midgard_block *block = (midgard_block *) _block;
2824 nr_bundles += util_dynarray_num_elements(
2825 &block->bundles, midgard_bundle);
2826
2827 mir_foreach_bundle_in_block(block, bun)
2828 nr_ins += bun->instruction_count;
2829 }
2830
2831 /* Calculate thread count. There are certain cutoffs by
2832 * register count for thread count */
2833
2834 unsigned nr_registers = program->work_register_count;
2835
2836 unsigned nr_threads =
2837 (nr_registers <= 4) ? 4 :
2838 (nr_registers <= 8) ? 2 :
2839 1;
2840
2841 /* Dump stats */
2842
2843 fprintf(stderr, "shader%d - %s shader: "
2844 "%u inst, %u bundles, %u quadwords, "
2845 "%u registers, %u threads, %u loops, "
2846 "%u:%u spills:fills\n",
2847 SHADER_DB_COUNT++,
2848 ctx->is_blend ? "PAN_SHADER_BLEND" :
2849 gl_shader_stage_name(ctx->stage),
2850 nr_ins, nr_bundles, ctx->quadword_count,
2851 nr_registers, nr_threads,
2852 ctx->loop_count,
2853 ctx->spills, ctx->fills);
2854 }
2855
2856 ralloc_free(ctx);
2857
2858 return 0;
2859 }