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pan/mdg: Streamline dest_override handling
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 i.dest_type = T; \
121 } else { \
122 i.dest = ssa; \
123 i.dest_type = T; \
124 } \
125 return i; \
126 }
127
128 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
129 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
130
131 M_LOAD(ld_attr_32, nir_type_uint32);
132 M_LOAD(ld_vary_32, nir_type_uint32);
133 M_LOAD(ld_ubo_int4, nir_type_uint32);
134 M_LOAD(ld_int4, nir_type_uint32);
135 M_STORE(st_int4, nir_type_uint32);
136 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
137 M_STORE(st_vary_32, nir_type_uint32);
138 M_LOAD(ld_cubemap_coords, nir_type_uint32);
139 M_LOAD(ld_compute_id, nir_type_uint32);
140
141 static midgard_instruction
142 v_branch(bool conditional, bool invert)
143 {
144 midgard_instruction ins = {
145 .type = TAG_ALU_4,
146 .unit = ALU_ENAB_BRANCH,
147 .compact_branch = true,
148 .branch = {
149 .conditional = conditional,
150 .invert_conditional = invert
151 },
152 .dest = ~0,
153 .src = { ~0, ~0, ~0, ~0 },
154 };
155
156 return ins;
157 }
158
159 static midgard_branch_extended
160 midgard_create_branch_extended( midgard_condition cond,
161 midgard_jmp_writeout_op op,
162 unsigned dest_tag,
163 signed quadword_offset)
164 {
165 /* The condition code is actually a LUT describing a function to
166 * combine multiple condition codes. However, we only support a single
167 * condition code at the moment, so we just duplicate over a bunch of
168 * times. */
169
170 uint16_t duplicated_cond =
171 (cond << 14) |
172 (cond << 12) |
173 (cond << 10) |
174 (cond << 8) |
175 (cond << 6) |
176 (cond << 4) |
177 (cond << 2) |
178 (cond << 0);
179
180 midgard_branch_extended branch = {
181 .op = op,
182 .dest_tag = dest_tag,
183 .offset = quadword_offset,
184 .cond = duplicated_cond
185 };
186
187 return branch;
188 }
189
190 static void
191 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
192 {
193 ins->has_constants = true;
194 memcpy(&ins->constants, constants, 16);
195 }
196
197 static int
198 glsl_type_size(const struct glsl_type *type, bool bindless)
199 {
200 return glsl_count_attribute_slots(type, false);
201 }
202
203 /* Lower fdot2 to a vector multiplication followed by channel addition */
204 static void
205 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
206 {
207 if (alu->op != nir_op_fdot2)
208 return;
209
210 b->cursor = nir_before_instr(&alu->instr);
211
212 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
213 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
214
215 nir_ssa_def *product = nir_fmul(b, src0, src1);
216
217 nir_ssa_def *sum = nir_fadd(b,
218 nir_channel(b, product, 0),
219 nir_channel(b, product, 1));
220
221 /* Replace the fdot2 with this sum */
222 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
223 }
224
225 static bool
226 midgard_nir_lower_fdot2(nir_shader *shader)
227 {
228 bool progress = false;
229
230 nir_foreach_function(function, shader) {
231 if (!function->impl) continue;
232
233 nir_builder _b;
234 nir_builder *b = &_b;
235 nir_builder_init(b, function->impl);
236
237 nir_foreach_block(block, function->impl) {
238 nir_foreach_instr_safe(instr, block) {
239 if (instr->type != nir_instr_type_alu) continue;
240
241 nir_alu_instr *alu = nir_instr_as_alu(instr);
242 midgard_nir_lower_fdot2_body(b, alu);
243
244 progress |= true;
245 }
246 }
247
248 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
249
250 }
251
252 return progress;
253 }
254
255 /* Midgard can't write depth and stencil separately. It has to happen in a
256 * single store operation containing both. Let's add a panfrost specific
257 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
258 * one.
259 */
260 static bool
261 midgard_nir_lower_zs_store(nir_shader *nir)
262 {
263 if (nir->info.stage != MESA_SHADER_FRAGMENT)
264 return false;
265
266 nir_variable *z_var = NULL, *s_var = NULL;
267
268 nir_foreach_variable(var, &nir->outputs) {
269 if (var->data.location == FRAG_RESULT_DEPTH)
270 z_var = var;
271 else if (var->data.location == FRAG_RESULT_STENCIL)
272 s_var = var;
273 }
274
275 if (!z_var && !s_var)
276 return false;
277
278 bool progress = false;
279
280 nir_foreach_function(function, nir) {
281 if (!function->impl) continue;
282
283 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
284
285 nir_foreach_block(block, function->impl) {
286 nir_foreach_instr_safe(instr, block) {
287 if (instr->type != nir_instr_type_intrinsic)
288 continue;
289
290 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
291 if (intr->intrinsic != nir_intrinsic_store_output)
292 continue;
293
294 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
295 assert(!z_store);
296 z_store = intr;
297 last_store = intr;
298 }
299
300 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
301 assert(!s_store);
302 s_store = intr;
303 last_store = intr;
304 }
305 }
306 }
307
308 if (!z_store && !s_store) continue;
309
310 nir_builder b;
311 nir_builder_init(&b, function->impl);
312
313 b.cursor = nir_before_instr(&last_store->instr);
314
315 nir_ssa_def *zs_store_src;
316
317 if (z_store && s_store) {
318 nir_ssa_def *srcs[2] = {
319 nir_ssa_for_src(&b, z_store->src[0], 1),
320 nir_ssa_for_src(&b, s_store->src[0], 1),
321 };
322
323 zs_store_src = nir_vec(&b, srcs, 2);
324 } else {
325 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
326 }
327
328 nir_intrinsic_instr *zs_store;
329
330 zs_store = nir_intrinsic_instr_create(b.shader,
331 nir_intrinsic_store_zs_output_pan);
332 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
333 zs_store->num_components = z_store && s_store ? 2 : 1;
334 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
335
336 /* Replace the Z and S store by a ZS store */
337 nir_builder_instr_insert(&b, &zs_store->instr);
338
339 if (z_store)
340 nir_instr_remove(&z_store->instr);
341
342 if (s_store)
343 nir_instr_remove(&s_store->instr);
344
345 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
346 progress = true;
347 }
348
349 return progress;
350 }
351
352 /* Flushes undefined values to zero */
353
354 static void
355 optimise_nir(nir_shader *nir, unsigned quirks)
356 {
357 bool progress;
358 unsigned lower_flrp =
359 (nir->options->lower_flrp16 ? 16 : 0) |
360 (nir->options->lower_flrp32 ? 32 : 0) |
361 (nir->options->lower_flrp64 ? 64 : 0);
362
363 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
364 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
365
366 nir_lower_tex_options lower_tex_options = {
367 .lower_txs_lod = true,
368 .lower_txp = ~0,
369 .lower_tex_without_implicit_lod =
370 (quirks & MIDGARD_EXPLICIT_LOD),
371
372 /* TODO: we have native gradient.. */
373 .lower_txd = true,
374 };
375
376 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
377
378 /* Must lower fdot2 after tex is lowered */
379 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
380
381 /* T720 is broken. */
382
383 if (quirks & MIDGARD_BROKEN_LOD)
384 NIR_PASS_V(nir, midgard_nir_lod_errata);
385
386 do {
387 progress = false;
388
389 NIR_PASS(progress, nir, nir_lower_var_copies);
390 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
391
392 NIR_PASS(progress, nir, nir_copy_prop);
393 NIR_PASS(progress, nir, nir_opt_remove_phis);
394 NIR_PASS(progress, nir, nir_opt_dce);
395 NIR_PASS(progress, nir, nir_opt_dead_cf);
396 NIR_PASS(progress, nir, nir_opt_cse);
397 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
398 NIR_PASS(progress, nir, nir_opt_algebraic);
399 NIR_PASS(progress, nir, nir_opt_constant_folding);
400
401 if (lower_flrp != 0) {
402 bool lower_flrp_progress = false;
403 NIR_PASS(lower_flrp_progress,
404 nir,
405 nir_lower_flrp,
406 lower_flrp,
407 false /* always_precise */,
408 nir->options->lower_ffma);
409 if (lower_flrp_progress) {
410 NIR_PASS(progress, nir,
411 nir_opt_constant_folding);
412 progress = true;
413 }
414
415 /* Nothing should rematerialize any flrps, so we only
416 * need to do this lowering once.
417 */
418 lower_flrp = 0;
419 }
420
421 NIR_PASS(progress, nir, nir_opt_undef);
422 NIR_PASS(progress, nir, nir_undef_to_zero);
423
424 NIR_PASS(progress, nir, nir_opt_loop_unroll,
425 nir_var_shader_in |
426 nir_var_shader_out |
427 nir_var_function_temp);
428
429 NIR_PASS(progress, nir, nir_opt_vectorize);
430 } while (progress);
431
432 /* Must be run at the end to prevent creation of fsin/fcos ops */
433 NIR_PASS(progress, nir, midgard_nir_scale_trig);
434
435 do {
436 progress = false;
437
438 NIR_PASS(progress, nir, nir_opt_dce);
439 NIR_PASS(progress, nir, nir_opt_algebraic);
440 NIR_PASS(progress, nir, nir_opt_constant_folding);
441 NIR_PASS(progress, nir, nir_copy_prop);
442 } while (progress);
443
444 NIR_PASS(progress, nir, nir_opt_algebraic_late);
445 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
446
447 /* We implement booleans as 32-bit 0/~0 */
448 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
449
450 /* Now that booleans are lowered, we can run out late opts */
451 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
452 NIR_PASS(progress, nir, midgard_nir_cancel_inot);
453
454 NIR_PASS(progress, nir, nir_copy_prop);
455 NIR_PASS(progress, nir, nir_opt_dce);
456
457 /* Take us out of SSA */
458 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
459 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
460
461 /* We are a vector architecture; write combine where possible */
462 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
463 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
464
465 NIR_PASS(progress, nir, nir_opt_dce);
466 }
467
468 /* Do not actually emit a load; instead, cache the constant for inlining */
469
470 static void
471 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
472 {
473 nir_ssa_def def = instr->def;
474
475 midgard_constants *consts = rzalloc(NULL, midgard_constants);
476
477 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
478
479 #define RAW_CONST_COPY(bits) \
480 nir_const_value_to_array(consts->u##bits, instr->value, \
481 instr->def.num_components, u##bits)
482
483 switch (instr->def.bit_size) {
484 case 64:
485 RAW_CONST_COPY(64);
486 break;
487 case 32:
488 RAW_CONST_COPY(32);
489 break;
490 case 16:
491 RAW_CONST_COPY(16);
492 break;
493 case 8:
494 RAW_CONST_COPY(8);
495 break;
496 default:
497 unreachable("Invalid bit_size for load_const instruction\n");
498 }
499
500 /* Shifted for SSA, +1 for off-by-one */
501 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
502 }
503
504 /* Normally constants are embedded implicitly, but for I/O and such we have to
505 * explicitly emit a move with the constant source */
506
507 static void
508 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
509 {
510 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
511
512 if (constant_value) {
513 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
514 attach_constants(ctx, &ins, constant_value, node + 1);
515 emit_mir_instruction(ctx, ins);
516 }
517 }
518
519 static bool
520 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
521 {
522 unsigned comp = src->swizzle[0];
523
524 for (unsigned c = 1; c < nr_components; ++c) {
525 if (src->swizzle[c] != comp)
526 return true;
527 }
528
529 return false;
530 }
531
532 #define ALU_CASE(nir, _op) \
533 case nir_op_##nir: \
534 op = midgard_alu_op_##_op; \
535 assert(src_bitsize == dst_bitsize); \
536 break;
537
538 #define ALU_CHECK_CMP(sext) \
539 assert(src_bitsize == 16 || src_bitsize == 32); \
540 assert(dst_bitsize == 16 || dst_bitsize == 32); \
541
542 #define ALU_CASE_BCAST(nir, _op, count) \
543 case nir_op_##nir: \
544 op = midgard_alu_op_##_op; \
545 broadcast_swizzle = count; \
546 ALU_CHECK_CMP(true); \
547 break;
548
549 #define ALU_CASE_CMP(nir, _op, sext) \
550 case nir_op_##nir: \
551 op = midgard_alu_op_##_op; \
552 ALU_CHECK_CMP(sext); \
553 break;
554
555 /* Analyze the sizes of the dest and inputs to determine reg mode. */
556
557 static midgard_reg_mode
558 reg_mode_for_nir(nir_alu_instr *instr)
559 {
560 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
561 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
562 unsigned max_bitsize = MAX2(src_bitsize, dst_bitsize);
563
564 switch (max_bitsize) {
565 case 8:
566 return midgard_reg_mode_8;
567 case 16:
568 return midgard_reg_mode_16;
569 case 32:
570 return midgard_reg_mode_32;
571 case 64:
572 return midgard_reg_mode_64;
573 default:
574 unreachable("Invalid bit size");
575 }
576 }
577
578 /* Compare mir_lower_invert */
579 static bool
580 nir_accepts_inot(nir_op op, unsigned src)
581 {
582 switch (op) {
583 case nir_op_ior:
584 case nir_op_iand:
585 case nir_op_ixor:
586 return true;
587 case nir_op_b32csel:
588 /* Only the condition */
589 return (src == 0);
590 default:
591 return false;
592 }
593 }
594
595 static bool
596 mir_accept_dest_mod(compiler_context *ctx, nir_dest **dest, nir_op op)
597 {
598 if (pan_has_dest_mod(dest, op)) {
599 assert((*dest)->is_ssa);
600 BITSET_SET(ctx->already_emitted, (*dest)->ssa.index);
601 return true;
602 }
603
604 return false;
605 }
606
607 static void
608 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool *not, bool is_int, unsigned bcast_count)
609 {
610 nir_alu_src src = instr->src[i];
611
612 if (!is_int) {
613 if (pan_has_source_mod(&src, nir_op_fneg))
614 *neg = !(*neg);
615
616 if (pan_has_source_mod(&src, nir_op_fabs))
617 *abs = true;
618 }
619
620 if (nir_accepts_inot(instr->op, i) && pan_has_source_mod(&src, nir_op_inot))
621 *not = true;
622
623 unsigned bits = nir_src_bit_size(src.src);
624
625 ins->src[to] = nir_src_index(NULL, &src.src);
626 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
627
628 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
629 ins->swizzle[to][c] = src.swizzle[
630 (!bcast_count || c < bcast_count) ? c :
631 (bcast_count - 1)];
632 }
633 }
634
635 /* Midgard features both fcsel and icsel, depending on whether you want int or
636 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
637 * we should emit an int or float csel depending on what modifiers could be
638 * placed. In the absense of modifiers, this is probably arbitrary. */
639
640 static bool
641 mir_is_bcsel_float(nir_alu_instr *instr)
642 {
643 nir_op intmods[] = {
644 nir_op_i2i8, nir_op_i2i16,
645 nir_op_i2i32, nir_op_i2i64
646 };
647
648 nir_op floatmods[] = {
649 nir_op_fabs, nir_op_fneg,
650 nir_op_f2f16, nir_op_f2f32,
651 nir_op_f2f64
652 };
653
654 nir_op floatdestmods[] = {
655 nir_op_fsat, nir_op_fsat_signed, nir_op_fclamp_pos,
656 nir_op_f2f16, nir_op_f2f32
657 };
658
659 signed score = 0;
660
661 for (unsigned i = 1; i < 3; ++i) {
662 nir_alu_src s = instr->src[i];
663 for (unsigned q = 0; q < ARRAY_SIZE(intmods); ++q) {
664 if (pan_has_source_mod(&s, intmods[q]))
665 score--;
666 }
667 }
668
669 for (unsigned i = 1; i < 3; ++i) {
670 nir_alu_src s = instr->src[i];
671 for (unsigned q = 0; q < ARRAY_SIZE(floatmods); ++q) {
672 if (pan_has_source_mod(&s, floatmods[q]))
673 score++;
674 }
675 }
676
677 for (unsigned q = 0; q < ARRAY_SIZE(floatdestmods); ++q) {
678 nir_dest *dest = &instr->dest.dest;
679 if (pan_has_dest_mod(&dest, floatdestmods[q]))
680 score++;
681 }
682
683 return (score > 0);
684 }
685
686 static void
687 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
688 {
689 nir_dest *dest = &instr->dest.dest;
690
691 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index))
692 return;
693
694 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
695 * is handled elsewhere */
696
697 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
698 midgard_emit_derivatives(ctx, instr);
699 return;
700 }
701
702 bool is_ssa = dest->is_ssa;
703
704 unsigned nr_components = nir_dest_num_components(*dest);
705 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
706 unsigned op = 0;
707
708 /* Number of components valid to check for the instruction (the rest
709 * will be forced to the last), or 0 to use as-is. Relevant as
710 * ball-type instructions have a channel count in NIR but are all vec4
711 * in Midgard */
712
713 unsigned broadcast_swizzle = 0;
714
715 /* What register mode should we operate in? */
716 midgard_reg_mode reg_mode =
717 reg_mode_for_nir(instr);
718
719 /* Should we swap arguments? */
720 bool flip_src12 = false;
721
722 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
723 unsigned dst_bitsize = nir_dest_bit_size(*dest);
724
725 switch (instr->op) {
726 ALU_CASE(fadd, fadd);
727 ALU_CASE(fmul, fmul);
728 ALU_CASE(fmin, fmin);
729 ALU_CASE(fmax, fmax);
730 ALU_CASE(imin, imin);
731 ALU_CASE(imax, imax);
732 ALU_CASE(umin, umin);
733 ALU_CASE(umax, umax);
734 ALU_CASE(ffloor, ffloor);
735 ALU_CASE(fround_even, froundeven);
736 ALU_CASE(ftrunc, ftrunc);
737 ALU_CASE(fceil, fceil);
738 ALU_CASE(fdot3, fdot3);
739 ALU_CASE(fdot4, fdot4);
740 ALU_CASE(iadd, iadd);
741 ALU_CASE(isub, isub);
742 ALU_CASE(imul, imul);
743
744 /* Zero shoved as second-arg */
745 ALU_CASE(iabs, iabsdiff);
746
747 ALU_CASE(mov, imov);
748
749 ALU_CASE_CMP(feq32, feq, false);
750 ALU_CASE_CMP(fne32, fne, false);
751 ALU_CASE_CMP(flt32, flt, false);
752 ALU_CASE_CMP(ieq32, ieq, true);
753 ALU_CASE_CMP(ine32, ine, true);
754 ALU_CASE_CMP(ilt32, ilt, true);
755 ALU_CASE_CMP(ult32, ult, false);
756
757 /* We don't have a native b2f32 instruction. Instead, like many
758 * GPUs, we exploit booleans as 0/~0 for false/true, and
759 * correspondingly AND
760 * by 1.0 to do the type conversion. For the moment, prime us
761 * to emit:
762 *
763 * iand [whatever], #0
764 *
765 * At the end of emit_alu (as MIR), we'll fix-up the constant
766 */
767
768 ALU_CASE_CMP(b2f32, iand, true);
769 ALU_CASE_CMP(b2i32, iand, true);
770
771 /* Likewise, we don't have a dedicated f2b32 instruction, but
772 * we can do a "not equal to 0.0" test. */
773
774 ALU_CASE_CMP(f2b32, fne, false);
775 ALU_CASE_CMP(i2b32, ine, true);
776
777 ALU_CASE(frcp, frcp);
778 ALU_CASE(frsq, frsqrt);
779 ALU_CASE(fsqrt, fsqrt);
780 ALU_CASE(fexp2, fexp2);
781 ALU_CASE(flog2, flog2);
782
783 ALU_CASE(f2i64, f2i_rtz);
784 ALU_CASE(f2u64, f2u_rtz);
785 ALU_CASE(i2f64, i2f_rtz);
786 ALU_CASE(u2f64, u2f_rtz);
787
788 ALU_CASE(f2i32, f2i_rtz);
789 ALU_CASE(f2u32, f2u_rtz);
790 ALU_CASE(i2f32, i2f_rtz);
791 ALU_CASE(u2f32, u2f_rtz);
792
793 ALU_CASE(f2i16, f2i_rtz);
794 ALU_CASE(f2u16, f2u_rtz);
795 ALU_CASE(i2f16, i2f_rtz);
796 ALU_CASE(u2f16, u2f_rtz);
797
798 ALU_CASE(fsin, fsin);
799 ALU_CASE(fcos, fcos);
800
801 /* We'll get 0 in the second arg, so:
802 * ~a = ~(a | 0) = nor(a, 0) */
803 ALU_CASE(inot, inor);
804 ALU_CASE(iand, iand);
805 ALU_CASE(ior, ior);
806 ALU_CASE(ixor, ixor);
807 ALU_CASE(ishl, ishl);
808 ALU_CASE(ishr, iasr);
809 ALU_CASE(ushr, ilsr);
810
811 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
812 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
813 ALU_CASE_CMP(b32all_fequal4, fball_eq, true);
814
815 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
816 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
817 ALU_CASE_CMP(b32any_fnequal4, fbany_neq, true);
818
819 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
820 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
821 ALU_CASE_CMP(b32all_iequal4, iball_eq, true);
822
823 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
824 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
825 ALU_CASE_CMP(b32any_inequal4, ibany_neq, true);
826
827 /* Source mods will be shoved in later */
828 ALU_CASE(fabs, fmov);
829 ALU_CASE(fneg, fmov);
830 ALU_CASE(fsat, fmov);
831 ALU_CASE(fsat_signed, fmov);
832 ALU_CASE(fclamp_pos, fmov);
833
834 /* For size conversion, we use a move. Ideally though we would squash
835 * these ops together; maybe that has to happen after in NIR as part of
836 * propagation...? An earlier algebraic pass ensured we step down by
837 * only / exactly one size. If stepping down, we use a dest override to
838 * reduce the size; if stepping up, we use a larger-sized move with a
839 * half source and a sign/zero-extension modifier */
840
841 case nir_op_i2i8:
842 case nir_op_i2i16:
843 case nir_op_i2i32:
844 case nir_op_i2i64:
845 case nir_op_u2u8:
846 case nir_op_u2u16:
847 case nir_op_u2u32:
848 case nir_op_u2u64:
849 case nir_op_f2f16:
850 case nir_op_f2f32:
851 case nir_op_f2f64: {
852 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
853 instr->op == nir_op_f2f64)
854 op = midgard_alu_op_fmov;
855 else
856 op = midgard_alu_op_imov;
857
858 break;
859 }
860
861 /* For greater-or-equal, we lower to less-or-equal and flip the
862 * arguments */
863
864 case nir_op_fge:
865 case nir_op_fge32:
866 case nir_op_ige32:
867 case nir_op_uge32: {
868 op =
869 instr->op == nir_op_fge ? midgard_alu_op_fle :
870 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
871 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
872 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
873 0;
874
875 flip_src12 = true;
876 ALU_CHECK_CMP(false);
877 break;
878 }
879
880 case nir_op_b32csel: {
881 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
882 bool is_float = mir_is_bcsel_float(instr);
883 op = is_float ?
884 (mixed ? midgard_alu_op_fcsel_v : midgard_alu_op_fcsel) :
885 (mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel);
886
887 break;
888 }
889
890 default:
891 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
892 assert(0);
893 return;
894 }
895
896 /* Promote imov to fmov if it might help inline a constant */
897 if (op == midgard_alu_op_imov && nir_src_is_const(instr->src[0].src)
898 && nir_src_bit_size(instr->src[0].src) == 32
899 && nir_is_same_comp_swizzle(instr->src[0].swizzle,
900 nir_src_num_components(instr->src[0].src))) {
901 op = midgard_alu_op_fmov;
902 }
903
904 /* Midgard can perform certain modifiers on output of an ALU op */
905
906 unsigned outmod = 0;
907 bool is_int = midgard_is_integer_op(op);
908
909 if (midgard_is_integer_out_op(op)) {
910 outmod = midgard_outmod_int_wrap;
911 } else if (instr->op == nir_op_fsat) {
912 outmod = midgard_outmod_sat;
913 } else if (instr->op == nir_op_fsat_signed) {
914 outmod = midgard_outmod_sat_signed;
915 } else if (instr->op == nir_op_fclamp_pos) {
916 outmod = midgard_outmod_pos;
917 }
918
919 /* Fetch unit, quirks, etc information */
920 unsigned opcode_props = alu_opcode_props[op].props;
921 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
922
923 /* Look for floating point mods. We have the mods fsat, fsat_signed,
924 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
925 *
926 * fsat_signed(fpos(x)) = fsat(x)
927 * fsat_signed(fsat(x)) = fsat(x)
928 * fpos(fsat_signed(x)) = fsat(x)
929 * fpos(fsat(x)) = fsat(x)
930 * fsat(fsat_signed(x)) = fsat(x)
931 * fsat(fpos(x)) = fsat(x)
932 *
933 * So by cases any composition of output modifiers is equivalent to
934 * fsat alone.
935 */
936
937 if (!is_int && !(opcode_props & OP_TYPE_CONVERT)) {
938 bool fpos = mir_accept_dest_mod(ctx, &dest, nir_op_fclamp_pos);
939 bool fsat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat);
940 bool ssat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat_signed);
941 bool prior = (outmod != midgard_outmod_none);
942 int count = (int) prior + (int) fpos + (int) ssat + (int) fsat;
943
944 outmod = ((count > 1) || fsat) ? midgard_outmod_sat :
945 fpos ? midgard_outmod_pos :
946 ssat ? midgard_outmod_sat_signed :
947 outmod;
948 }
949
950 midgard_instruction ins = {
951 .type = TAG_ALU_4,
952 .dest = nir_dest_index(dest),
953 .dest_type = nir_op_infos[instr->op].output_type
954 | nir_dest_bit_size(*dest),
955 };
956
957 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
958 ins.src[i] = ~0;
959
960 if (quirk_flipped_r24) {
961 ins.src[0] = ~0;
962 mir_copy_src(&ins, instr, 0, 1, &ins.src_abs[1], &ins.src_neg[1], &ins.src_invert[1], is_int, broadcast_swizzle);
963 } else {
964 for (unsigned i = 0; i < nr_inputs; ++i) {
965 unsigned to = i;
966
967 if (instr->op == nir_op_b32csel) {
968 /* The condition is the first argument; move
969 * the other arguments up one to be a binary
970 * instruction for Midgard with the condition
971 * last */
972
973 if (i == 0)
974 to = 2;
975 else if (flip_src12)
976 to = 2 - i;
977 else
978 to = i - 1;
979 } else if (flip_src12) {
980 to = 1 - to;
981 }
982
983 mir_copy_src(&ins, instr, i, to, &ins.src_abs[to], &ins.src_neg[to], &ins.src_invert[to], is_int, broadcast_swizzle);
984
985 /* (!c) ? a : b = c ? b : a */
986 if (instr->op == nir_op_b32csel && ins.src_invert[2]) {
987 ins.src_invert[2] = false;
988 flip_src12 ^= true;
989 }
990 }
991 }
992
993 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
994 /* Lowered to move */
995 if (instr->op == nir_op_fneg)
996 ins.src_neg[1] ^= true;
997
998 if (instr->op == nir_op_fabs)
999 ins.src_abs[1] = true;
1000 }
1001
1002 ins.mask = mask_of(nr_components);
1003
1004 midgard_vector_alu alu = {
1005 .op = op,
1006 .reg_mode = reg_mode,
1007 .outmod = outmod,
1008 };
1009
1010 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1011 * components that don't exist. Note modifier => SSA => !reg => no
1012 * writemask, so we don't have to worry about writemasks here.*/
1013
1014 if (!is_ssa)
1015 ins.mask &= instr->dest.write_mask;
1016
1017 ins.alu = alu;
1018
1019 /* Arrange for creation of iandnot/iornot */
1020 if (ins.src_invert[0] && !ins.src_invert[1]) {
1021 mir_flip(&ins);
1022 ins.src_invert[0] = false;
1023 ins.src_invert[1] = true;
1024 }
1025
1026 /* Late fixup for emulated instructions */
1027
1028 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1029 /* Presently, our second argument is an inline #0 constant.
1030 * Switch over to an embedded 1.0 constant (that can't fit
1031 * inline, since we're 32-bit, not 16-bit like the inline
1032 * constants) */
1033
1034 ins.has_inline_constant = false;
1035 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1036 ins.src_types[1] = nir_type_float32;
1037 ins.has_constants = true;
1038
1039 if (instr->op == nir_op_b2f32)
1040 ins.constants.f32[0] = 1.0f;
1041 else
1042 ins.constants.i32[0] = 1;
1043
1044 for (unsigned c = 0; c < 16; ++c)
1045 ins.swizzle[1][c] = 0;
1046 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1047 /* Lots of instructions need a 0 plonked in */
1048 ins.has_inline_constant = false;
1049 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1050 ins.src_types[1] = nir_type_uint32;
1051 ins.has_constants = true;
1052 ins.constants.u32[0] = 0;
1053
1054 for (unsigned c = 0; c < 16; ++c)
1055 ins.swizzle[1][c] = 0;
1056 }
1057
1058 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1059 /* To avoid duplicating the lookup tables (probably), true LUT
1060 * instructions can only operate as if they were scalars. Lower
1061 * them here by changing the component. */
1062
1063 unsigned orig_mask = ins.mask;
1064
1065 unsigned swizzle_back[MIR_VEC_COMPONENTS];
1066 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
1067
1068 for (int i = 0; i < nr_components; ++i) {
1069 /* Mask the associated component, dropping the
1070 * instruction if needed */
1071
1072 ins.mask = 1 << i;
1073 ins.mask &= orig_mask;
1074
1075 if (!ins.mask)
1076 continue;
1077
1078 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1079 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1080
1081 emit_mir_instruction(ctx, ins);
1082 }
1083 } else {
1084 emit_mir_instruction(ctx, ins);
1085 }
1086 }
1087
1088 #undef ALU_CASE
1089
1090 static void
1091 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1092 {
1093 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1094 unsigned nir_mask = 0;
1095 unsigned dsize = 0;
1096
1097 if (is_read) {
1098 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1099 dsize = nir_dest_bit_size(intr->dest);
1100 } else {
1101 nir_mask = nir_intrinsic_write_mask(intr);
1102 dsize = 32;
1103 }
1104
1105 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1106 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1107 mir_set_bytemask(ins, bytemask);
1108
1109 if (dsize == 64)
1110 ins->load_64 = true;
1111 }
1112
1113 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1114 * optimized) versions of UBO #0 */
1115
1116 static midgard_instruction *
1117 emit_ubo_read(
1118 compiler_context *ctx,
1119 nir_instr *instr,
1120 unsigned dest,
1121 unsigned offset,
1122 nir_src *indirect_offset,
1123 unsigned indirect_shift,
1124 unsigned index)
1125 {
1126 /* TODO: half-floats */
1127
1128 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1129 ins.constants.u32[0] = offset;
1130
1131 if (instr->type == nir_instr_type_intrinsic)
1132 mir_set_intr_mask(instr, &ins, true);
1133
1134 if (indirect_offset) {
1135 ins.src[2] = nir_src_index(ctx, indirect_offset);
1136 ins.src_types[2] = nir_type_uint32;
1137 ins.load_store.arg_2 = (indirect_shift << 5);
1138 } else {
1139 ins.load_store.arg_2 = 0x1E;
1140 }
1141
1142 ins.load_store.arg_1 = index;
1143
1144 return emit_mir_instruction(ctx, ins);
1145 }
1146
1147 /* Globals are like UBOs if you squint. And shared memory is like globals if
1148 * you squint even harder */
1149
1150 static void
1151 emit_global(
1152 compiler_context *ctx,
1153 nir_instr *instr,
1154 bool is_read,
1155 unsigned srcdest,
1156 nir_src *offset,
1157 bool is_shared)
1158 {
1159 /* TODO: types */
1160
1161 midgard_instruction ins;
1162
1163 if (is_read)
1164 ins = m_ld_int4(srcdest, 0);
1165 else
1166 ins = m_st_int4(srcdest, 0);
1167
1168 mir_set_offset(ctx, &ins, offset, is_shared);
1169 mir_set_intr_mask(instr, &ins, is_read);
1170
1171 emit_mir_instruction(ctx, ins);
1172 }
1173
1174 static void
1175 emit_varying_read(
1176 compiler_context *ctx,
1177 unsigned dest, unsigned offset,
1178 unsigned nr_comp, unsigned component,
1179 nir_src *indirect_offset, nir_alu_type type, bool flat)
1180 {
1181 /* XXX: Half-floats? */
1182 /* TODO: swizzle, mask */
1183
1184 midgard_instruction ins = m_ld_vary_32(dest, offset);
1185 ins.mask = mask_of(nr_comp);
1186
1187 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1188 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1189
1190 midgard_varying_parameter p = {
1191 .is_varying = 1,
1192 .interpolation = midgard_interp_default,
1193 .flat = flat,
1194 };
1195
1196 unsigned u;
1197 memcpy(&u, &p, sizeof(p));
1198 ins.load_store.varying_parameters = u;
1199
1200 if (indirect_offset) {
1201 ins.src[2] = nir_src_index(ctx, indirect_offset);
1202 ins.src_types[2] = nir_type_uint32;
1203 } else
1204 ins.load_store.arg_2 = 0x1E;
1205
1206 ins.load_store.arg_1 = 0x9E;
1207
1208 /* Use the type appropriate load */
1209 switch (type) {
1210 case nir_type_uint:
1211 case nir_type_bool:
1212 ins.load_store.op = midgard_op_ld_vary_32u;
1213 break;
1214 case nir_type_int:
1215 ins.load_store.op = midgard_op_ld_vary_32i;
1216 break;
1217 case nir_type_float:
1218 ins.load_store.op = midgard_op_ld_vary_32;
1219 break;
1220 default:
1221 unreachable("Attempted to load unknown type");
1222 break;
1223 }
1224
1225 emit_mir_instruction(ctx, ins);
1226 }
1227
1228 static void
1229 emit_attr_read(
1230 compiler_context *ctx,
1231 unsigned dest, unsigned offset,
1232 unsigned nr_comp, nir_alu_type t)
1233 {
1234 midgard_instruction ins = m_ld_attr_32(dest, offset);
1235 ins.load_store.arg_1 = 0x1E;
1236 ins.load_store.arg_2 = 0x1E;
1237 ins.mask = mask_of(nr_comp);
1238
1239 /* Use the type appropriate load */
1240 switch (t) {
1241 case nir_type_uint:
1242 case nir_type_bool:
1243 ins.load_store.op = midgard_op_ld_attr_32u;
1244 break;
1245 case nir_type_int:
1246 ins.load_store.op = midgard_op_ld_attr_32i;
1247 break;
1248 case nir_type_float:
1249 ins.load_store.op = midgard_op_ld_attr_32;
1250 break;
1251 default:
1252 unreachable("Attempted to load unknown type");
1253 break;
1254 }
1255
1256 emit_mir_instruction(ctx, ins);
1257 }
1258
1259 static void
1260 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1261 unsigned nr_components, unsigned offset)
1262 {
1263 nir_dest nir_dest;
1264
1265 /* Figure out which uniform this is */
1266 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1267 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1268
1269 unsigned dest = nir_dest_index(&nir_dest);
1270
1271 /* Sysvals are prefix uniforms */
1272 unsigned uniform = ((uintptr_t) val) - 1;
1273
1274 /* Emit the read itself -- this is never indirect */
1275 midgard_instruction *ins =
1276 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1277
1278 ins->mask = mask_of(nr_components);
1279 }
1280
1281 static unsigned
1282 compute_builtin_arg(nir_op op)
1283 {
1284 switch (op) {
1285 case nir_intrinsic_load_work_group_id:
1286 return 0x14;
1287 case nir_intrinsic_load_local_invocation_id:
1288 return 0x10;
1289 default:
1290 unreachable("Invalid compute paramater loaded");
1291 }
1292 }
1293
1294 static void
1295 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1296 {
1297 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1298
1299 midgard_instruction *br = ctx->writeout_branch[rt];
1300
1301 assert(!br);
1302
1303 emit_explicit_constant(ctx, src, src);
1304
1305 struct midgard_instruction ins =
1306 v_branch(false, false);
1307
1308 ins.writeout = true;
1309
1310 /* Add dependencies */
1311 ins.src[0] = src;
1312 ins.src_types[0] = nir_type_uint32;
1313 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1314 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1315
1316 /* Emit the branch */
1317 br = emit_mir_instruction(ctx, ins);
1318 schedule_barrier(ctx);
1319 ctx->writeout_branch[rt] = br;
1320
1321 /* Push our current location = current block count - 1 = where we'll
1322 * jump to. Maybe a bit too clever for my own good */
1323
1324 br->branch.target_block = ctx->block_count - 1;
1325 }
1326
1327 static void
1328 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1329 {
1330 unsigned reg = nir_dest_index(&instr->dest);
1331 midgard_instruction ins = m_ld_compute_id(reg, 0);
1332 ins.mask = mask_of(3);
1333 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1334 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1335 emit_mir_instruction(ctx, ins);
1336 }
1337
1338 static unsigned
1339 vertex_builtin_arg(nir_op op)
1340 {
1341 switch (op) {
1342 case nir_intrinsic_load_vertex_id:
1343 return PAN_VERTEX_ID;
1344 case nir_intrinsic_load_instance_id:
1345 return PAN_INSTANCE_ID;
1346 default:
1347 unreachable("Invalid vertex builtin");
1348 }
1349 }
1350
1351 static void
1352 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1353 {
1354 unsigned reg = nir_dest_index(&instr->dest);
1355 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1356 }
1357
1358 static void
1359 emit_control_barrier(compiler_context *ctx)
1360 {
1361 midgard_instruction ins = {
1362 .type = TAG_TEXTURE_4,
1363 .src = { ~0, ~0, ~0, ~0 },
1364 .texture = {
1365 .op = TEXTURE_OP_BARRIER,
1366
1367 /* TODO: optimize */
1368 .barrier_buffer = 1,
1369 .barrier_shared = 1
1370 }
1371 };
1372
1373 emit_mir_instruction(ctx, ins);
1374 }
1375
1376 static const nir_variable *
1377 search_var(struct exec_list *vars, unsigned driver_loc)
1378 {
1379 nir_foreach_variable(var, vars) {
1380 if (var->data.driver_location == driver_loc)
1381 return var;
1382 }
1383
1384 return NULL;
1385 }
1386
1387 static unsigned
1388 mir_get_branch_cond(nir_src *src, bool *invert)
1389 {
1390 /* Wrap it. No swizzle since it's a scalar */
1391
1392 nir_alu_src alu = {
1393 .src = *src
1394 };
1395
1396 *invert = pan_has_source_mod(&alu, nir_op_inot);
1397 return nir_src_index(NULL, &alu.src);
1398 }
1399
1400 static void
1401 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1402 {
1403 unsigned offset = 0, reg;
1404
1405 switch (instr->intrinsic) {
1406 case nir_intrinsic_discard_if:
1407 case nir_intrinsic_discard: {
1408 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1409 struct midgard_instruction discard = v_branch(conditional, false);
1410 discard.branch.target_type = TARGET_DISCARD;
1411
1412 if (conditional) {
1413 discard.src[0] = mir_get_branch_cond(&instr->src[0],
1414 &discard.branch.invert_conditional);
1415 discard.src_types[0] = nir_type_uint32;
1416 }
1417
1418 emit_mir_instruction(ctx, discard);
1419 schedule_barrier(ctx);
1420
1421 break;
1422 }
1423
1424 case nir_intrinsic_load_uniform:
1425 case nir_intrinsic_load_ubo:
1426 case nir_intrinsic_load_global:
1427 case nir_intrinsic_load_shared:
1428 case nir_intrinsic_load_input:
1429 case nir_intrinsic_load_interpolated_input: {
1430 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1431 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1432 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1433 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1434 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1435 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1436
1437 /* Get the base type of the intrinsic */
1438 /* TODO: Infer type? Does it matter? */
1439 nir_alu_type t =
1440 (is_ubo || is_global || is_shared) ? nir_type_uint :
1441 (is_interp) ? nir_type_float :
1442 nir_intrinsic_type(instr);
1443
1444 t = nir_alu_type_get_base_type(t);
1445
1446 if (!(is_ubo || is_global)) {
1447 offset = nir_intrinsic_base(instr);
1448 }
1449
1450 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1451
1452 nir_src *src_offset = nir_get_io_offset_src(instr);
1453
1454 bool direct = nir_src_is_const(*src_offset);
1455 nir_src *indirect_offset = direct ? NULL : src_offset;
1456
1457 if (direct)
1458 offset += nir_src_as_uint(*src_offset);
1459
1460 /* We may need to apply a fractional offset */
1461 int component = (is_flat || is_interp) ?
1462 nir_intrinsic_component(instr) : 0;
1463 reg = nir_dest_index(&instr->dest);
1464
1465 if (is_uniform && !ctx->is_blend) {
1466 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1467 } else if (is_ubo) {
1468 nir_src index = instr->src[0];
1469
1470 /* TODO: Is indirect block number possible? */
1471 assert(nir_src_is_const(index));
1472
1473 uint32_t uindex = nir_src_as_uint(index) + 1;
1474 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1475 } else if (is_global || is_shared) {
1476 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1477 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1478 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1479 } else if (ctx->is_blend) {
1480 /* For blend shaders, load the input color, which is
1481 * preloaded to r0 */
1482
1483 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1484 emit_mir_instruction(ctx, move);
1485 schedule_barrier(ctx);
1486 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1487 emit_attr_read(ctx, reg, offset, nr_comp, t);
1488 } else {
1489 DBG("Unknown load\n");
1490 assert(0);
1491 }
1492
1493 break;
1494 }
1495
1496 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1497 case nir_intrinsic_load_barycentric_pixel:
1498 case nir_intrinsic_load_barycentric_centroid:
1499 break;
1500
1501 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1502
1503 case nir_intrinsic_load_raw_output_pan:
1504 case nir_intrinsic_load_output_u8_as_fp16_pan:
1505 reg = nir_dest_index(&instr->dest);
1506 assert(ctx->is_blend);
1507
1508 /* T720 and below use different blend opcodes with slightly
1509 * different semantics than T760 and up */
1510
1511 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1512 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1513
1514 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1515 ld.load_store.op = old_blend ?
1516 midgard_op_ld_color_buffer_u8_as_fp16_old :
1517 midgard_op_ld_color_buffer_u8_as_fp16;
1518
1519 if (old_blend) {
1520 ld.load_store.address = 1;
1521 ld.load_store.arg_2 = 0x1E;
1522 }
1523
1524 for (unsigned c = 4; c < 16; ++c)
1525 ld.swizzle[0][c] = 0;
1526
1527 ld.dest_type = nir_type_float16;
1528 }
1529
1530 emit_mir_instruction(ctx, ld);
1531 break;
1532
1533 case nir_intrinsic_load_blend_const_color_rgba: {
1534 assert(ctx->is_blend);
1535 reg = nir_dest_index(&instr->dest);
1536
1537 /* Blend constants are embedded directly in the shader and
1538 * patched in, so we use some magic routing */
1539
1540 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1541 ins.has_constants = true;
1542 ins.has_blend_constant = true;
1543 emit_mir_instruction(ctx, ins);
1544 break;
1545 }
1546
1547 case nir_intrinsic_store_zs_output_pan: {
1548 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1549 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1550 MIDGARD_ZS_RT);
1551
1552 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1553
1554 if (!nir_intrinsic_component(instr))
1555 br->writeout_depth = true;
1556 if (nir_intrinsic_component(instr) ||
1557 instr->num_components)
1558 br->writeout_stencil = true;
1559 assert(br->writeout_depth | br->writeout_stencil);
1560 break;
1561 }
1562
1563 case nir_intrinsic_store_output:
1564 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1565
1566 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1567
1568 reg = nir_src_index(ctx, &instr->src[0]);
1569
1570 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1571 const nir_variable *var;
1572 enum midgard_rt_id rt;
1573
1574 var = search_var(&ctx->nir->outputs,
1575 nir_intrinsic_base(instr));
1576 assert(var);
1577 if (var->data.location == FRAG_RESULT_COLOR)
1578 rt = MIDGARD_COLOR_RT0;
1579 else if (var->data.location >= FRAG_RESULT_DATA0)
1580 rt = MIDGARD_COLOR_RT0 + var->data.location -
1581 FRAG_RESULT_DATA0;
1582 else
1583 assert(0);
1584
1585 emit_fragment_store(ctx, reg, rt);
1586 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1587 /* We should have been vectorized, though we don't
1588 * currently check that st_vary is emitted only once
1589 * per slot (this is relevant, since there's not a mask
1590 * parameter available on the store [set to 0 by the
1591 * blob]). We do respect the component by adjusting the
1592 * swizzle. If this is a constant source, we'll need to
1593 * emit that explicitly. */
1594
1595 emit_explicit_constant(ctx, reg, reg);
1596
1597 unsigned dst_component = nir_intrinsic_component(instr);
1598 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1599
1600 midgard_instruction st = m_st_vary_32(reg, offset);
1601 st.load_store.arg_1 = 0x9E;
1602 st.load_store.arg_2 = 0x1E;
1603
1604 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1605 case nir_type_uint:
1606 case nir_type_bool:
1607 st.load_store.op = midgard_op_st_vary_32u;
1608 break;
1609 case nir_type_int:
1610 st.load_store.op = midgard_op_st_vary_32i;
1611 break;
1612 case nir_type_float:
1613 st.load_store.op = midgard_op_st_vary_32;
1614 break;
1615 default:
1616 unreachable("Attempted to store unknown type");
1617 break;
1618 }
1619
1620 /* nir_intrinsic_component(store_intr) encodes the
1621 * destination component start. Source component offset
1622 * adjustment is taken care of in
1623 * install_registers_instr(), when offset_swizzle() is
1624 * called.
1625 */
1626 unsigned src_component = COMPONENT_X;
1627
1628 assert(nr_comp > 0);
1629 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1630 st.swizzle[0][i] = src_component;
1631 if (i >= dst_component && i < dst_component + nr_comp - 1)
1632 src_component++;
1633 }
1634
1635 emit_mir_instruction(ctx, st);
1636 } else {
1637 DBG("Unknown store\n");
1638 assert(0);
1639 }
1640
1641 break;
1642
1643 /* Special case of store_output for lowered blend shaders */
1644 case nir_intrinsic_store_raw_output_pan:
1645 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1646 reg = nir_src_index(ctx, &instr->src[0]);
1647
1648 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1649 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1650 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1651 * of:
1652 *
1653 * imov r0.xyzw, r0.xxxx
1654 */
1655
1656 unsigned expanded = make_compiler_temp(ctx);
1657
1658 midgard_instruction splatter = v_mov(reg, expanded);
1659
1660 for (unsigned c = 0; c < 16; ++c)
1661 splatter.swizzle[1][c] = 0;
1662
1663 emit_mir_instruction(ctx, splatter);
1664 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1665 } else
1666 emit_fragment_store(ctx, reg, ctx->blend_rt);
1667
1668 break;
1669
1670 case nir_intrinsic_store_global:
1671 case nir_intrinsic_store_shared:
1672 reg = nir_src_index(ctx, &instr->src[0]);
1673 emit_explicit_constant(ctx, reg, reg);
1674
1675 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1676 break;
1677
1678 case nir_intrinsic_load_ssbo_address:
1679 emit_sysval_read(ctx, &instr->instr, 1, 0);
1680 break;
1681
1682 case nir_intrinsic_get_buffer_size:
1683 emit_sysval_read(ctx, &instr->instr, 1, 8);
1684 break;
1685
1686 case nir_intrinsic_load_viewport_scale:
1687 case nir_intrinsic_load_viewport_offset:
1688 case nir_intrinsic_load_num_work_groups:
1689 case nir_intrinsic_load_sampler_lod_parameters_pan:
1690 emit_sysval_read(ctx, &instr->instr, 3, 0);
1691 break;
1692
1693 case nir_intrinsic_load_work_group_id:
1694 case nir_intrinsic_load_local_invocation_id:
1695 emit_compute_builtin(ctx, instr);
1696 break;
1697
1698 case nir_intrinsic_load_vertex_id:
1699 case nir_intrinsic_load_instance_id:
1700 emit_vertex_builtin(ctx, instr);
1701 break;
1702
1703 case nir_intrinsic_memory_barrier_buffer:
1704 case nir_intrinsic_memory_barrier_shared:
1705 break;
1706
1707 case nir_intrinsic_control_barrier:
1708 schedule_barrier(ctx);
1709 emit_control_barrier(ctx);
1710 schedule_barrier(ctx);
1711 break;
1712
1713 default:
1714 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1715 assert(0);
1716 break;
1717 }
1718 }
1719
1720 static unsigned
1721 midgard_tex_format(enum glsl_sampler_dim dim)
1722 {
1723 switch (dim) {
1724 case GLSL_SAMPLER_DIM_1D:
1725 case GLSL_SAMPLER_DIM_BUF:
1726 return MALI_TEX_1D;
1727
1728 case GLSL_SAMPLER_DIM_2D:
1729 case GLSL_SAMPLER_DIM_EXTERNAL:
1730 case GLSL_SAMPLER_DIM_RECT:
1731 return MALI_TEX_2D;
1732
1733 case GLSL_SAMPLER_DIM_3D:
1734 return MALI_TEX_3D;
1735
1736 case GLSL_SAMPLER_DIM_CUBE:
1737 return MALI_TEX_CUBE;
1738
1739 default:
1740 DBG("Unknown sampler dim type\n");
1741 assert(0);
1742 return 0;
1743 }
1744 }
1745
1746 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1747 * was successful */
1748
1749 static bool
1750 pan_attach_constant_bias(
1751 compiler_context *ctx,
1752 nir_src lod,
1753 midgard_texture_word *word)
1754 {
1755 /* To attach as constant, it has to *be* constant */
1756
1757 if (!nir_src_is_const(lod))
1758 return false;
1759
1760 float f = nir_src_as_float(lod);
1761
1762 /* Break into fixed-point */
1763 signed lod_int = f;
1764 float lod_frac = f - lod_int;
1765
1766 /* Carry over negative fractions */
1767 if (lod_frac < 0.0) {
1768 lod_int--;
1769 lod_frac += 1.0;
1770 }
1771
1772 /* Encode */
1773 word->bias = float_to_ubyte(lod_frac);
1774 word->bias_int = lod_int;
1775
1776 return true;
1777 }
1778
1779 static void
1780 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1781 unsigned midgard_texop)
1782 {
1783 /* TODO */
1784 //assert (!instr->sampler);
1785
1786 int texture_index = instr->texture_index;
1787 int sampler_index = texture_index;
1788
1789 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1790 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1791
1792 midgard_instruction ins = {
1793 .type = TAG_TEXTURE_4,
1794 .mask = 0xF,
1795 .dest = nir_dest_index(&instr->dest),
1796 .src = { ~0, ~0, ~0, ~0 },
1797 .dest_type = dest_type,
1798 .swizzle = SWIZZLE_IDENTITY_4,
1799 .texture = {
1800 .op = midgard_texop,
1801 .format = midgard_tex_format(instr->sampler_dim),
1802 .texture_handle = texture_index,
1803 .sampler_handle = sampler_index,
1804 .shadow = instr->is_shadow,
1805 }
1806 };
1807
1808 if (instr->is_shadow && !instr->is_new_style_shadow)
1809 for (int i = 0; i < 4; ++i)
1810 ins.swizzle[0][i] = COMPONENT_X;
1811
1812 /* We may need a temporary for the coordinate */
1813
1814 bool needs_temp_coord =
1815 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1816 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1817 (instr->is_shadow);
1818
1819 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1820
1821 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1822 int index = nir_src_index(ctx, &instr->src[i].src);
1823 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1824 unsigned sz = nir_src_bit_size(instr->src[i].src);
1825 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1826
1827 switch (instr->src[i].src_type) {
1828 case nir_tex_src_coord: {
1829 emit_explicit_constant(ctx, index, index);
1830
1831 unsigned coord_mask = mask_of(instr->coord_components);
1832
1833 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1834
1835 if (flip_zw)
1836 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1837
1838 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1839 /* texelFetch is undefined on samplerCube */
1840 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1841
1842 /* For cubemaps, we use a special ld/st op to
1843 * select the face and copy the xy into the
1844 * texture register */
1845
1846 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1847 ld.src[1] = index;
1848 ld.src_types[1] = T;
1849 ld.mask = 0x3; /* xy */
1850 ld.load_store.arg_1 = 0x20;
1851 ld.swizzle[1][3] = COMPONENT_X;
1852 emit_mir_instruction(ctx, ld);
1853
1854 /* xyzw -> xyxx */
1855 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1856 ins.swizzle[1][3] = COMPONENT_X;
1857 } else if (needs_temp_coord) {
1858 /* mov coord_temp, coords */
1859 midgard_instruction mov = v_mov(index, coords);
1860 mov.mask = coord_mask;
1861
1862 if (flip_zw)
1863 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1864
1865 emit_mir_instruction(ctx, mov);
1866 } else {
1867 coords = index;
1868 }
1869
1870 ins.src[1] = coords;
1871 ins.src_types[1] = T;
1872
1873 /* Texelfetch coordinates uses all four elements
1874 * (xyz/index) regardless of texture dimensionality,
1875 * which means it's necessary to zero the unused
1876 * components to keep everything happy */
1877
1878 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1879 /* mov index.zw, #0, or generalized */
1880 midgard_instruction mov =
1881 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1882 mov.has_constants = true;
1883 mov.mask = coord_mask ^ 0xF;
1884 emit_mir_instruction(ctx, mov);
1885 }
1886
1887 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1888 /* Array component in w but NIR wants it in z,
1889 * but if we have a temp coord we already fixed
1890 * that up */
1891
1892 if (nr_components == 3) {
1893 ins.swizzle[1][2] = COMPONENT_Z;
1894 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1895 } else if (nr_components == 2) {
1896 ins.swizzle[1][2] =
1897 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1898 ins.swizzle[1][3] = COMPONENT_X;
1899 } else
1900 unreachable("Invalid texture 2D components");
1901 }
1902
1903 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1904 /* We zeroed */
1905 ins.swizzle[1][2] = COMPONENT_Z;
1906 ins.swizzle[1][3] = COMPONENT_W;
1907 }
1908
1909 break;
1910 }
1911
1912 case nir_tex_src_bias:
1913 case nir_tex_src_lod: {
1914 /* Try as a constant if we can */
1915
1916 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1917 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1918 break;
1919
1920 ins.texture.lod_register = true;
1921 ins.src[2] = index;
1922 ins.src_types[2] = T;
1923
1924 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1925 ins.swizzle[2][c] = COMPONENT_X;
1926
1927 emit_explicit_constant(ctx, index, index);
1928
1929 break;
1930 };
1931
1932 case nir_tex_src_offset: {
1933 ins.texture.offset_register = true;
1934 ins.src[3] = index;
1935 ins.src_types[3] = T;
1936
1937 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1938 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
1939
1940 emit_explicit_constant(ctx, index, index);
1941 break;
1942 };
1943
1944 case nir_tex_src_comparator: {
1945 unsigned comp = COMPONENT_Z;
1946
1947 /* mov coord_temp.foo, coords */
1948 midgard_instruction mov = v_mov(index, coords);
1949 mov.mask = 1 << comp;
1950
1951 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
1952 mov.swizzle[1][i] = COMPONENT_X;
1953
1954 emit_mir_instruction(ctx, mov);
1955 break;
1956 }
1957
1958 default: {
1959 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
1960 assert(0);
1961 }
1962 }
1963 }
1964
1965 emit_mir_instruction(ctx, ins);
1966 }
1967
1968 static void
1969 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1970 {
1971 switch (instr->op) {
1972 case nir_texop_tex:
1973 case nir_texop_txb:
1974 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
1975 break;
1976 case nir_texop_txl:
1977 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
1978 break;
1979 case nir_texop_txf:
1980 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
1981 break;
1982 case nir_texop_txs:
1983 emit_sysval_read(ctx, &instr->instr, 4, 0);
1984 break;
1985 default: {
1986 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
1987 assert(0);
1988 }
1989 }
1990 }
1991
1992 static void
1993 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1994 {
1995 switch (instr->type) {
1996 case nir_jump_break: {
1997 /* Emit a branch out of the loop */
1998 struct midgard_instruction br = v_branch(false, false);
1999 br.branch.target_type = TARGET_BREAK;
2000 br.branch.target_break = ctx->current_loop_depth;
2001 emit_mir_instruction(ctx, br);
2002 break;
2003 }
2004
2005 default:
2006 DBG("Unknown jump type %d\n", instr->type);
2007 break;
2008 }
2009 }
2010
2011 static void
2012 emit_instr(compiler_context *ctx, struct nir_instr *instr)
2013 {
2014 switch (instr->type) {
2015 case nir_instr_type_load_const:
2016 emit_load_const(ctx, nir_instr_as_load_const(instr));
2017 break;
2018
2019 case nir_instr_type_intrinsic:
2020 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2021 break;
2022
2023 case nir_instr_type_alu:
2024 emit_alu(ctx, nir_instr_as_alu(instr));
2025 break;
2026
2027 case nir_instr_type_tex:
2028 emit_tex(ctx, nir_instr_as_tex(instr));
2029 break;
2030
2031 case nir_instr_type_jump:
2032 emit_jump(ctx, nir_instr_as_jump(instr));
2033 break;
2034
2035 case nir_instr_type_ssa_undef:
2036 /* Spurious */
2037 break;
2038
2039 default:
2040 DBG("Unhandled instruction type\n");
2041 break;
2042 }
2043 }
2044
2045
2046 /* ALU instructions can inline or embed constants, which decreases register
2047 * pressure and saves space. */
2048
2049 #define CONDITIONAL_ATTACH(idx) { \
2050 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2051 \
2052 if (entry) { \
2053 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2054 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2055 } \
2056 }
2057
2058 static void
2059 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2060 {
2061 mir_foreach_instr_in_block(block, alu) {
2062 /* Other instructions cannot inline constants */
2063 if (alu->type != TAG_ALU_4) continue;
2064 if (alu->compact_branch) continue;
2065
2066 /* If there is already a constant here, we can do nothing */
2067 if (alu->has_constants) continue;
2068
2069 CONDITIONAL_ATTACH(0);
2070
2071 if (!alu->has_constants) {
2072 CONDITIONAL_ATTACH(1)
2073 } else if (!alu->inline_constant) {
2074 /* Corner case: _two_ vec4 constants, for instance with a
2075 * csel. For this case, we can only use a constant
2076 * register for one, we'll have to emit a move for the
2077 * other. */
2078
2079 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2080 unsigned scratch = make_compiler_temp(ctx);
2081
2082 if (entry) {
2083 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2084 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2085
2086 /* Set the source */
2087 alu->src[1] = scratch;
2088
2089 /* Inject us -before- the last instruction which set r31 */
2090 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2091 }
2092 }
2093 }
2094 }
2095
2096 /* Midgard supports two types of constants, embedded constants (128-bit) and
2097 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2098 * constants can be demoted to inline constants, for space savings and
2099 * sometimes a performance boost */
2100
2101 static void
2102 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2103 {
2104 mir_foreach_instr_in_block(block, ins) {
2105 if (!ins->has_constants) continue;
2106 if (ins->has_inline_constant) continue;
2107
2108 /* Blend constants must not be inlined by definition */
2109 if (ins->has_blend_constant) continue;
2110
2111 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2112 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2113 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2114
2115 if (!(is_16 || is_32))
2116 continue;
2117
2118 /* src1 cannot be an inline constant due to encoding
2119 * restrictions. So, if possible we try to flip the arguments
2120 * in that case */
2121
2122 int op = ins->alu.op;
2123
2124 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2125 alu_opcode_props[op].props & OP_COMMUTES) {
2126 mir_flip(ins);
2127 }
2128
2129 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2130 /* Component is from the swizzle. Take a nonzero component */
2131 assert(ins->mask);
2132 unsigned first_comp = ffs(ins->mask) - 1;
2133 unsigned component = ins->swizzle[1][first_comp];
2134
2135 /* Scale constant appropriately, if we can legally */
2136 uint16_t scaled_constant = 0;
2137
2138 if (is_16) {
2139 scaled_constant = ins->constants.u16[component];
2140 } else if (midgard_is_integer_op(op)) {
2141 scaled_constant = ins->constants.u32[component];
2142
2143 /* Constant overflow after resize */
2144 if (scaled_constant != ins->constants.u32[component])
2145 continue;
2146 } else {
2147 float original = ins->constants.f32[component];
2148 scaled_constant = _mesa_float_to_half(original);
2149
2150 /* Check for loss of precision. If this is
2151 * mediump, we don't care, but for a highp
2152 * shader, we need to pay attention. NIR
2153 * doesn't yet tell us which mode we're in!
2154 * Practically this prevents most constants
2155 * from being inlined, sadly. */
2156
2157 float fp32 = _mesa_half_to_float(scaled_constant);
2158
2159 if (fp32 != original)
2160 continue;
2161 }
2162
2163 /* Should've been const folded */
2164 if (ins->src_abs[1] || ins->src_neg[1])
2165 continue;
2166
2167 /* Make sure that the constant is not itself a vector
2168 * by checking if all accessed values are the same. */
2169
2170 const midgard_constants *cons = &ins->constants;
2171 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2172
2173 bool is_vector = false;
2174 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2175
2176 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2177 /* We only care if this component is actually used */
2178 if (!(mask & (1 << c)))
2179 continue;
2180
2181 uint32_t test = is_16 ?
2182 cons->u16[ins->swizzle[1][c]] :
2183 cons->u32[ins->swizzle[1][c]];
2184
2185 if (test != value) {
2186 is_vector = true;
2187 break;
2188 }
2189 }
2190
2191 if (is_vector)
2192 continue;
2193
2194 /* Get rid of the embedded constant */
2195 ins->has_constants = false;
2196 ins->src[1] = ~0;
2197 ins->has_inline_constant = true;
2198 ins->inline_constant = scaled_constant;
2199 }
2200 }
2201 }
2202
2203 /* Dead code elimination for branches at the end of a block - only one branch
2204 * per block is legal semantically */
2205
2206 static void
2207 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2208 {
2209 bool branched = false;
2210
2211 mir_foreach_instr_in_block_safe(block, ins) {
2212 if (!midgard_is_branch_unit(ins->unit)) continue;
2213
2214 if (branched)
2215 mir_remove_instruction(ins);
2216
2217 branched = true;
2218 }
2219 }
2220
2221 static unsigned
2222 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2223 {
2224 /* Loop to ourselves */
2225 midgard_instruction *br = ctx->writeout_branch[rt];
2226 struct midgard_instruction ins = v_branch(false, false);
2227 ins.writeout = true;
2228 ins.writeout_depth = br->writeout_depth;
2229 ins.writeout_stencil = br->writeout_stencil;
2230 ins.branch.target_block = ctx->block_count - 1;
2231 ins.constants.u32[0] = br->constants.u32[0];
2232 emit_mir_instruction(ctx, ins);
2233
2234 ctx->current_block->epilogue = true;
2235 schedule_barrier(ctx);
2236 return ins.branch.target_block;
2237 }
2238
2239 static midgard_block *
2240 emit_block(compiler_context *ctx, nir_block *block)
2241 {
2242 midgard_block *this_block = ctx->after_block;
2243 ctx->after_block = NULL;
2244
2245 if (!this_block)
2246 this_block = create_empty_block(ctx);
2247
2248 list_addtail(&this_block->base.link, &ctx->blocks);
2249
2250 this_block->scheduled = false;
2251 ++ctx->block_count;
2252
2253 /* Set up current block */
2254 list_inithead(&this_block->base.instructions);
2255 ctx->current_block = this_block;
2256
2257 nir_foreach_instr(instr, block) {
2258 emit_instr(ctx, instr);
2259 ++ctx->instruction_count;
2260 }
2261
2262 return this_block;
2263 }
2264
2265 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2266
2267 static void
2268 emit_if(struct compiler_context *ctx, nir_if *nif)
2269 {
2270 midgard_block *before_block = ctx->current_block;
2271
2272 /* Speculatively emit the branch, but we can't fill it in until later */
2273 bool inv = false;
2274 EMIT(branch, true, true);
2275 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2276 then_branch->src[0] = mir_get_branch_cond(&nif->condition, &inv);
2277 then_branch->src_types[0] = nir_type_uint32;
2278 then_branch->branch.invert_conditional = !inv;
2279
2280 /* Emit the two subblocks. */
2281 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2282 midgard_block *end_then_block = ctx->current_block;
2283
2284 /* Emit a jump from the end of the then block to the end of the else */
2285 EMIT(branch, false, false);
2286 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2287
2288 /* Emit second block, and check if it's empty */
2289
2290 int else_idx = ctx->block_count;
2291 int count_in = ctx->instruction_count;
2292 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2293 midgard_block *end_else_block = ctx->current_block;
2294 int after_else_idx = ctx->block_count;
2295
2296 /* Now that we have the subblocks emitted, fix up the branches */
2297
2298 assert(then_block);
2299 assert(else_block);
2300
2301 if (ctx->instruction_count == count_in) {
2302 /* The else block is empty, so don't emit an exit jump */
2303 mir_remove_instruction(then_exit);
2304 then_branch->branch.target_block = after_else_idx;
2305 } else {
2306 then_branch->branch.target_block = else_idx;
2307 then_exit->branch.target_block = after_else_idx;
2308 }
2309
2310 /* Wire up the successors */
2311
2312 ctx->after_block = create_empty_block(ctx);
2313
2314 pan_block_add_successor(&before_block->base, &then_block->base);
2315 pan_block_add_successor(&before_block->base, &else_block->base);
2316
2317 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2318 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2319 }
2320
2321 static void
2322 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2323 {
2324 /* Remember where we are */
2325 midgard_block *start_block = ctx->current_block;
2326
2327 /* Allocate a loop number, growing the current inner loop depth */
2328 int loop_idx = ++ctx->current_loop_depth;
2329
2330 /* Get index from before the body so we can loop back later */
2331 int start_idx = ctx->block_count;
2332
2333 /* Emit the body itself */
2334 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2335
2336 /* Branch back to loop back */
2337 struct midgard_instruction br_back = v_branch(false, false);
2338 br_back.branch.target_block = start_idx;
2339 emit_mir_instruction(ctx, br_back);
2340
2341 /* Mark down that branch in the graph. */
2342 pan_block_add_successor(&start_block->base, &loop_block->base);
2343 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2344
2345 /* Find the index of the block about to follow us (note: we don't add
2346 * one; blocks are 0-indexed so we get a fencepost problem) */
2347 int break_block_idx = ctx->block_count;
2348
2349 /* Fix up the break statements we emitted to point to the right place,
2350 * now that we can allocate a block number for them */
2351 ctx->after_block = create_empty_block(ctx);
2352
2353 mir_foreach_block_from(ctx, start_block, _block) {
2354 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2355 if (ins->type != TAG_ALU_4) continue;
2356 if (!ins->compact_branch) continue;
2357
2358 /* We found a branch -- check the type to see if we need to do anything */
2359 if (ins->branch.target_type != TARGET_BREAK) continue;
2360
2361 /* It's a break! Check if it's our break */
2362 if (ins->branch.target_break != loop_idx) continue;
2363
2364 /* Okay, cool, we're breaking out of this loop.
2365 * Rewrite from a break to a goto */
2366
2367 ins->branch.target_type = TARGET_GOTO;
2368 ins->branch.target_block = break_block_idx;
2369
2370 pan_block_add_successor(_block, &ctx->after_block->base);
2371 }
2372 }
2373
2374 /* Now that we've finished emitting the loop, free up the depth again
2375 * so we play nice with recursion amid nested loops */
2376 --ctx->current_loop_depth;
2377
2378 /* Dump loop stats */
2379 ++ctx->loop_count;
2380 }
2381
2382 static midgard_block *
2383 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2384 {
2385 midgard_block *start_block = NULL;
2386
2387 foreach_list_typed(nir_cf_node, node, node, list) {
2388 switch (node->type) {
2389 case nir_cf_node_block: {
2390 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2391
2392 if (!start_block)
2393 start_block = block;
2394
2395 break;
2396 }
2397
2398 case nir_cf_node_if:
2399 emit_if(ctx, nir_cf_node_as_if(node));
2400 break;
2401
2402 case nir_cf_node_loop:
2403 emit_loop(ctx, nir_cf_node_as_loop(node));
2404 break;
2405
2406 case nir_cf_node_function:
2407 assert(0);
2408 break;
2409 }
2410 }
2411
2412 return start_block;
2413 }
2414
2415 /* Due to lookahead, we need to report the first tag executed in the command
2416 * stream and in branch targets. An initial block might be empty, so iterate
2417 * until we find one that 'works' */
2418
2419 static unsigned
2420 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2421 {
2422 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2423
2424 mir_foreach_block_from(ctx, initial_block, _v) {
2425 midgard_block *v = (midgard_block *) _v;
2426 if (v->quadword_count) {
2427 midgard_bundle *initial_bundle =
2428 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2429
2430 return initial_bundle->tag;
2431 }
2432 }
2433
2434 /* Default to a tag 1 which will break from the shader, in case we jump
2435 * to the exit block (i.e. `return` in a compute shader) */
2436
2437 return 1;
2438 }
2439
2440 /* For each fragment writeout instruction, generate a writeout loop to
2441 * associate with it */
2442
2443 static void
2444 mir_add_writeout_loops(compiler_context *ctx)
2445 {
2446 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2447 midgard_instruction *br = ctx->writeout_branch[rt];
2448 if (!br) continue;
2449
2450 unsigned popped = br->branch.target_block;
2451 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2452 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2453 br->branch.target_type = TARGET_GOTO;
2454
2455 /* If we have more RTs, we'll need to restore back after our
2456 * loop terminates */
2457
2458 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2459 midgard_instruction uncond = v_branch(false, false);
2460 uncond.branch.target_block = popped;
2461 uncond.branch.target_type = TARGET_GOTO;
2462 emit_mir_instruction(ctx, uncond);
2463 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2464 schedule_barrier(ctx);
2465 } else {
2466 /* We're last, so we can terminate here */
2467 br->last_writeout = true;
2468 }
2469 }
2470 }
2471
2472 int
2473 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2474 {
2475 struct util_dynarray *compiled = &program->compiled;
2476
2477 midgard_debug = debug_get_option_midgard_debug();
2478
2479 /* TODO: Bound against what? */
2480 compiler_context *ctx = rzalloc(NULL, compiler_context);
2481
2482 ctx->nir = nir;
2483 ctx->stage = nir->info.stage;
2484 ctx->is_blend = is_blend;
2485 ctx->alpha_ref = program->alpha_ref;
2486 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2487 ctx->quirks = midgard_get_quirks(gpu_id);
2488
2489 /* Start off with a safe cutoff, allowing usage of all 16 work
2490 * registers. Later, we'll promote uniform reads to uniform registers
2491 * if we determine it is beneficial to do so */
2492 ctx->uniform_cutoff = 8;
2493
2494 /* Initialize at a global (not block) level hash tables */
2495
2496 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2497 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2498
2499 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2500 * (so we don't accidentally duplicate the epilogue since mesa/st has
2501 * messed with our I/O quite a bit already) */
2502
2503 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2504
2505 if (ctx->stage == MESA_SHADER_VERTEX) {
2506 NIR_PASS_V(nir, nir_lower_viewport_transform);
2507 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2508 }
2509
2510 NIR_PASS_V(nir, nir_lower_var_copies);
2511 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2512 NIR_PASS_V(nir, nir_split_var_copies);
2513 NIR_PASS_V(nir, nir_lower_var_copies);
2514 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2515 NIR_PASS_V(nir, nir_lower_var_copies);
2516 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2517
2518 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2519 NIR_PASS_V(nir, nir_lower_ssbo);
2520 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2521
2522 /* Optimisation passes */
2523
2524 optimise_nir(nir, ctx->quirks);
2525
2526 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2527 nir_print_shader(nir, stdout);
2528 }
2529
2530 /* Assign sysvals and counts, now that we're sure
2531 * (post-optimisation) */
2532
2533 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2534 program->sysval_count = ctx->sysvals.sysval_count;
2535 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2536
2537 nir_foreach_function(func, nir) {
2538 if (!func->impl)
2539 continue;
2540
2541 list_inithead(&ctx->blocks);
2542 ctx->block_count = 0;
2543 ctx->func = func;
2544 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
2545
2546 emit_cf_list(ctx, &func->impl->body);
2547 free(ctx->already_emitted);
2548 break; /* TODO: Multi-function shaders */
2549 }
2550
2551 util_dynarray_init(compiled, NULL);
2552
2553 /* Per-block lowering before opts */
2554
2555 mir_foreach_block(ctx, _block) {
2556 midgard_block *block = (midgard_block *) _block;
2557 inline_alu_constants(ctx, block);
2558 embedded_to_inline_constant(ctx, block);
2559 }
2560 /* MIR-level optimizations */
2561
2562 bool progress = false;
2563
2564 do {
2565 progress = false;
2566 progress |= midgard_opt_dead_code_eliminate(ctx);
2567
2568 mir_foreach_block(ctx, _block) {
2569 midgard_block *block = (midgard_block *) _block;
2570 progress |= midgard_opt_copy_prop(ctx, block);
2571 progress |= midgard_opt_combine_projection(ctx, block);
2572 progress |= midgard_opt_varying_projection(ctx, block);
2573 }
2574 } while (progress);
2575
2576 mir_foreach_block(ctx, _block) {
2577 midgard_block *block = (midgard_block *) _block;
2578 midgard_lower_derivatives(ctx, block);
2579 midgard_cull_dead_branch(ctx, block);
2580 }
2581
2582 if (ctx->stage == MESA_SHADER_FRAGMENT)
2583 mir_add_writeout_loops(ctx);
2584
2585 /* Analyze now that the code is known but before scheduling creates
2586 * pipeline registers which are harder to track */
2587 mir_analyze_helper_terminate(ctx);
2588 mir_analyze_helper_requirements(ctx);
2589
2590 /* Schedule! */
2591 midgard_schedule_program(ctx);
2592 mir_ra(ctx);
2593
2594 /* Now that all the bundles are scheduled and we can calculate block
2595 * sizes, emit actual branch instructions rather than placeholders */
2596
2597 int br_block_idx = 0;
2598
2599 mir_foreach_block(ctx, _block) {
2600 midgard_block *block = (midgard_block *) _block;
2601 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2602 for (int c = 0; c < bundle->instruction_count; ++c) {
2603 midgard_instruction *ins = bundle->instructions[c];
2604
2605 if (!midgard_is_branch_unit(ins->unit)) continue;
2606
2607 /* Parse some basic branch info */
2608 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2609 bool is_conditional = ins->branch.conditional;
2610 bool is_inverted = ins->branch.invert_conditional;
2611 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2612 bool is_writeout = ins->writeout;
2613
2614 /* Determine the block we're jumping to */
2615 int target_number = ins->branch.target_block;
2616
2617 /* Report the destination tag */
2618 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2619
2620 /* Count up the number of quadwords we're
2621 * jumping over = number of quadwords until
2622 * (br_block_idx, target_number) */
2623
2624 int quadword_offset = 0;
2625
2626 if (is_discard) {
2627 /* Ignored */
2628 } else if (target_number > br_block_idx) {
2629 /* Jump forward */
2630
2631 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2632 midgard_block *blk = mir_get_block(ctx, idx);
2633 assert(blk);
2634
2635 quadword_offset += blk->quadword_count;
2636 }
2637 } else {
2638 /* Jump backwards */
2639
2640 for (int idx = br_block_idx; idx >= target_number; --idx) {
2641 midgard_block *blk = mir_get_block(ctx, idx);
2642 assert(blk);
2643
2644 quadword_offset -= blk->quadword_count;
2645 }
2646 }
2647
2648 /* Unconditional extended branches (far jumps)
2649 * have issues, so we always use a conditional
2650 * branch, setting the condition to always for
2651 * unconditional. For compact unconditional
2652 * branches, cond isn't used so it doesn't
2653 * matter what we pick. */
2654
2655 midgard_condition cond =
2656 !is_conditional ? midgard_condition_always :
2657 is_inverted ? midgard_condition_false :
2658 midgard_condition_true;
2659
2660 midgard_jmp_writeout_op op =
2661 is_discard ? midgard_jmp_writeout_op_discard :
2662 is_writeout ? midgard_jmp_writeout_op_writeout :
2663 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2664 midgard_jmp_writeout_op_branch_cond;
2665
2666 if (!is_compact) {
2667 midgard_branch_extended branch =
2668 midgard_create_branch_extended(
2669 cond, op,
2670 dest_tag,
2671 quadword_offset);
2672
2673 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2674 } else if (is_conditional || is_discard) {
2675 midgard_branch_cond branch = {
2676 .op = op,
2677 .dest_tag = dest_tag,
2678 .offset = quadword_offset,
2679 .cond = cond
2680 };
2681
2682 assert(branch.offset == quadword_offset);
2683
2684 memcpy(&ins->br_compact, &branch, sizeof(branch));
2685 } else {
2686 assert(op == midgard_jmp_writeout_op_branch_uncond);
2687
2688 midgard_branch_uncond branch = {
2689 .op = op,
2690 .dest_tag = dest_tag,
2691 .offset = quadword_offset,
2692 .unknown = 1
2693 };
2694
2695 assert(branch.offset == quadword_offset);
2696
2697 memcpy(&ins->br_compact, &branch, sizeof(branch));
2698 }
2699 }
2700 }
2701
2702 ++br_block_idx;
2703 }
2704
2705 /* Emit flat binary from the instruction arrays. Iterate each block in
2706 * sequence. Save instruction boundaries such that lookahead tags can
2707 * be assigned easily */
2708
2709 /* Cache _all_ bundles in source order for lookahead across failed branches */
2710
2711 int bundle_count = 0;
2712 mir_foreach_block(ctx, _block) {
2713 midgard_block *block = (midgard_block *) _block;
2714 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2715 }
2716 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2717 int bundle_idx = 0;
2718 mir_foreach_block(ctx, _block) {
2719 midgard_block *block = (midgard_block *) _block;
2720 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2721 source_order_bundles[bundle_idx++] = bundle;
2722 }
2723 }
2724
2725 int current_bundle = 0;
2726
2727 /* Midgard prefetches instruction types, so during emission we
2728 * need to lookahead. Unless this is the last instruction, in
2729 * which we return 1. */
2730
2731 mir_foreach_block(ctx, _block) {
2732 midgard_block *block = (midgard_block *) _block;
2733 mir_foreach_bundle_in_block(block, bundle) {
2734 int lookahead = 1;
2735
2736 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2737 lookahead = source_order_bundles[current_bundle + 1]->tag;
2738
2739 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2740 ++current_bundle;
2741 }
2742
2743 /* TODO: Free deeper */
2744 //util_dynarray_fini(&block->instructions);
2745 }
2746
2747 free(source_order_bundles);
2748
2749 /* Report the very first tag executed */
2750 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2751
2752 /* Deal with off-by-one related to the fencepost problem */
2753 program->work_register_count = ctx->work_registers + 1;
2754 program->uniform_cutoff = ctx->uniform_cutoff;
2755
2756 program->blend_patch_offset = ctx->blend_constant_offset;
2757 program->tls_size = ctx->tls_size;
2758
2759 if (midgard_debug & MIDGARD_DBG_SHADERS)
2760 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2761
2762 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2763 unsigned nr_bundles = 0, nr_ins = 0;
2764
2765 /* Count instructions and bundles */
2766
2767 mir_foreach_block(ctx, _block) {
2768 midgard_block *block = (midgard_block *) _block;
2769 nr_bundles += util_dynarray_num_elements(
2770 &block->bundles, midgard_bundle);
2771
2772 mir_foreach_bundle_in_block(block, bun)
2773 nr_ins += bun->instruction_count;
2774 }
2775
2776 /* Calculate thread count. There are certain cutoffs by
2777 * register count for thread count */
2778
2779 unsigned nr_registers = program->work_register_count;
2780
2781 unsigned nr_threads =
2782 (nr_registers <= 4) ? 4 :
2783 (nr_registers <= 8) ? 2 :
2784 1;
2785
2786 /* Dump stats */
2787
2788 fprintf(stderr, "shader%d - %s shader: "
2789 "%u inst, %u bundles, %u quadwords, "
2790 "%u registers, %u threads, %u loops, "
2791 "%u:%u spills:fills\n",
2792 SHADER_DB_COUNT++,
2793 gl_shader_stage_name(ctx->stage),
2794 nr_ins, nr_bundles, ctx->quadword_count,
2795 nr_registers, nr_threads,
2796 ctx->loop_count,
2797 ctx->spills, ctx->fills);
2798 }
2799
2800 ralloc_free(ctx);
2801
2802 return 0;
2803 }