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pan/mdg: Defer modifier packing until emit time
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 i.dest_type = T; \
121 } else { \
122 i.dest = ssa; \
123 i.dest_type = T; \
124 } \
125 return i; \
126 }
127
128 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
129 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
130
131 M_LOAD(ld_attr_32, nir_type_uint32);
132 M_LOAD(ld_vary_32, nir_type_uint32);
133 M_LOAD(ld_ubo_int4, nir_type_uint32);
134 M_LOAD(ld_int4, nir_type_uint32);
135 M_STORE(st_int4, nir_type_uint32);
136 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
137 M_STORE(st_vary_32, nir_type_uint32);
138 M_LOAD(ld_cubemap_coords, nir_type_uint32);
139 M_LOAD(ld_compute_id, nir_type_uint32);
140
141 static midgard_instruction
142 v_branch(bool conditional, bool invert)
143 {
144 midgard_instruction ins = {
145 .type = TAG_ALU_4,
146 .unit = ALU_ENAB_BRANCH,
147 .compact_branch = true,
148 .branch = {
149 .conditional = conditional,
150 .invert_conditional = invert
151 },
152 .dest = ~0,
153 .src = { ~0, ~0, ~0, ~0 },
154 };
155
156 return ins;
157 }
158
159 static midgard_branch_extended
160 midgard_create_branch_extended( midgard_condition cond,
161 midgard_jmp_writeout_op op,
162 unsigned dest_tag,
163 signed quadword_offset)
164 {
165 /* The condition code is actually a LUT describing a function to
166 * combine multiple condition codes. However, we only support a single
167 * condition code at the moment, so we just duplicate over a bunch of
168 * times. */
169
170 uint16_t duplicated_cond =
171 (cond << 14) |
172 (cond << 12) |
173 (cond << 10) |
174 (cond << 8) |
175 (cond << 6) |
176 (cond << 4) |
177 (cond << 2) |
178 (cond << 0);
179
180 midgard_branch_extended branch = {
181 .op = op,
182 .dest_tag = dest_tag,
183 .offset = quadword_offset,
184 .cond = duplicated_cond
185 };
186
187 return branch;
188 }
189
190 static void
191 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
192 {
193 ins->has_constants = true;
194 memcpy(&ins->constants, constants, 16);
195 }
196
197 static int
198 glsl_type_size(const struct glsl_type *type, bool bindless)
199 {
200 return glsl_count_attribute_slots(type, false);
201 }
202
203 /* Lower fdot2 to a vector multiplication followed by channel addition */
204 static void
205 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
206 {
207 if (alu->op != nir_op_fdot2)
208 return;
209
210 b->cursor = nir_before_instr(&alu->instr);
211
212 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
213 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
214
215 nir_ssa_def *product = nir_fmul(b, src0, src1);
216
217 nir_ssa_def *sum = nir_fadd(b,
218 nir_channel(b, product, 0),
219 nir_channel(b, product, 1));
220
221 /* Replace the fdot2 with this sum */
222 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
223 }
224
225 static bool
226 midgard_nir_lower_fdot2(nir_shader *shader)
227 {
228 bool progress = false;
229
230 nir_foreach_function(function, shader) {
231 if (!function->impl) continue;
232
233 nir_builder _b;
234 nir_builder *b = &_b;
235 nir_builder_init(b, function->impl);
236
237 nir_foreach_block(block, function->impl) {
238 nir_foreach_instr_safe(instr, block) {
239 if (instr->type != nir_instr_type_alu) continue;
240
241 nir_alu_instr *alu = nir_instr_as_alu(instr);
242 midgard_nir_lower_fdot2_body(b, alu);
243
244 progress |= true;
245 }
246 }
247
248 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
249
250 }
251
252 return progress;
253 }
254
255 /* Midgard can't write depth and stencil separately. It has to happen in a
256 * single store operation containing both. Let's add a panfrost specific
257 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
258 * one.
259 */
260 static bool
261 midgard_nir_lower_zs_store(nir_shader *nir)
262 {
263 if (nir->info.stage != MESA_SHADER_FRAGMENT)
264 return false;
265
266 nir_variable *z_var = NULL, *s_var = NULL;
267
268 nir_foreach_variable(var, &nir->outputs) {
269 if (var->data.location == FRAG_RESULT_DEPTH)
270 z_var = var;
271 else if (var->data.location == FRAG_RESULT_STENCIL)
272 s_var = var;
273 }
274
275 if (!z_var && !s_var)
276 return false;
277
278 bool progress = false;
279
280 nir_foreach_function(function, nir) {
281 if (!function->impl) continue;
282
283 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
284
285 nir_foreach_block(block, function->impl) {
286 nir_foreach_instr_safe(instr, block) {
287 if (instr->type != nir_instr_type_intrinsic)
288 continue;
289
290 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
291 if (intr->intrinsic != nir_intrinsic_store_output)
292 continue;
293
294 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
295 assert(!z_store);
296 z_store = intr;
297 last_store = intr;
298 }
299
300 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
301 assert(!s_store);
302 s_store = intr;
303 last_store = intr;
304 }
305 }
306 }
307
308 if (!z_store && !s_store) continue;
309
310 nir_builder b;
311 nir_builder_init(&b, function->impl);
312
313 b.cursor = nir_before_instr(&last_store->instr);
314
315 nir_ssa_def *zs_store_src;
316
317 if (z_store && s_store) {
318 nir_ssa_def *srcs[2] = {
319 nir_ssa_for_src(&b, z_store->src[0], 1),
320 nir_ssa_for_src(&b, s_store->src[0], 1),
321 };
322
323 zs_store_src = nir_vec(&b, srcs, 2);
324 } else {
325 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
326 }
327
328 nir_intrinsic_instr *zs_store;
329
330 zs_store = nir_intrinsic_instr_create(b.shader,
331 nir_intrinsic_store_zs_output_pan);
332 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
333 zs_store->num_components = z_store && s_store ? 2 : 1;
334 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
335
336 /* Replace the Z and S store by a ZS store */
337 nir_builder_instr_insert(&b, &zs_store->instr);
338
339 if (z_store)
340 nir_instr_remove(&z_store->instr);
341
342 if (s_store)
343 nir_instr_remove(&s_store->instr);
344
345 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
346 progress = true;
347 }
348
349 return progress;
350 }
351
352 /* Flushes undefined values to zero */
353
354 static void
355 optimise_nir(nir_shader *nir, unsigned quirks)
356 {
357 bool progress;
358 unsigned lower_flrp =
359 (nir->options->lower_flrp16 ? 16 : 0) |
360 (nir->options->lower_flrp32 ? 32 : 0) |
361 (nir->options->lower_flrp64 ? 64 : 0);
362
363 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
364 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
365
366 nir_lower_tex_options lower_tex_options = {
367 .lower_txs_lod = true,
368 .lower_txp = ~0,
369 .lower_tex_without_implicit_lod =
370 (quirks & MIDGARD_EXPLICIT_LOD),
371
372 /* TODO: we have native gradient.. */
373 .lower_txd = true,
374 };
375
376 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
377
378 /* Must lower fdot2 after tex is lowered */
379 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
380
381 /* T720 is broken. */
382
383 if (quirks & MIDGARD_BROKEN_LOD)
384 NIR_PASS_V(nir, midgard_nir_lod_errata);
385
386 do {
387 progress = false;
388
389 NIR_PASS(progress, nir, nir_lower_var_copies);
390 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
391
392 NIR_PASS(progress, nir, nir_copy_prop);
393 NIR_PASS(progress, nir, nir_opt_remove_phis);
394 NIR_PASS(progress, nir, nir_opt_dce);
395 NIR_PASS(progress, nir, nir_opt_dead_cf);
396 NIR_PASS(progress, nir, nir_opt_cse);
397 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
398 NIR_PASS(progress, nir, nir_opt_algebraic);
399 NIR_PASS(progress, nir, nir_opt_constant_folding);
400
401 if (lower_flrp != 0) {
402 bool lower_flrp_progress = false;
403 NIR_PASS(lower_flrp_progress,
404 nir,
405 nir_lower_flrp,
406 lower_flrp,
407 false /* always_precise */,
408 nir->options->lower_ffma);
409 if (lower_flrp_progress) {
410 NIR_PASS(progress, nir,
411 nir_opt_constant_folding);
412 progress = true;
413 }
414
415 /* Nothing should rematerialize any flrps, so we only
416 * need to do this lowering once.
417 */
418 lower_flrp = 0;
419 }
420
421 NIR_PASS(progress, nir, nir_opt_undef);
422 NIR_PASS(progress, nir, nir_undef_to_zero);
423
424 NIR_PASS(progress, nir, nir_opt_loop_unroll,
425 nir_var_shader_in |
426 nir_var_shader_out |
427 nir_var_function_temp);
428
429 NIR_PASS(progress, nir, nir_opt_vectorize);
430 } while (progress);
431
432 /* Must be run at the end to prevent creation of fsin/fcos ops */
433 NIR_PASS(progress, nir, midgard_nir_scale_trig);
434
435 do {
436 progress = false;
437
438 NIR_PASS(progress, nir, nir_opt_dce);
439 NIR_PASS(progress, nir, nir_opt_algebraic);
440 NIR_PASS(progress, nir, nir_opt_constant_folding);
441 NIR_PASS(progress, nir, nir_copy_prop);
442 } while (progress);
443
444 NIR_PASS(progress, nir, nir_opt_algebraic_late);
445 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
446
447 /* We implement booleans as 32-bit 0/~0 */
448 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
449
450 /* Now that booleans are lowered, we can run out late opts */
451 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
452 NIR_PASS(progress, nir, midgard_nir_cancel_inot);
453
454 NIR_PASS(progress, nir, nir_copy_prop);
455 NIR_PASS(progress, nir, nir_opt_dce);
456
457 /* Take us out of SSA */
458 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
459 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
460
461 /* We are a vector architecture; write combine where possible */
462 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
463 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
464
465 NIR_PASS(progress, nir, nir_opt_dce);
466 }
467
468 /* Do not actually emit a load; instead, cache the constant for inlining */
469
470 static void
471 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
472 {
473 nir_ssa_def def = instr->def;
474
475 midgard_constants *consts = rzalloc(NULL, midgard_constants);
476
477 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
478
479 #define RAW_CONST_COPY(bits) \
480 nir_const_value_to_array(consts->u##bits, instr->value, \
481 instr->def.num_components, u##bits)
482
483 switch (instr->def.bit_size) {
484 case 64:
485 RAW_CONST_COPY(64);
486 break;
487 case 32:
488 RAW_CONST_COPY(32);
489 break;
490 case 16:
491 RAW_CONST_COPY(16);
492 break;
493 case 8:
494 RAW_CONST_COPY(8);
495 break;
496 default:
497 unreachable("Invalid bit_size for load_const instruction\n");
498 }
499
500 /* Shifted for SSA, +1 for off-by-one */
501 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
502 }
503
504 /* Normally constants are embedded implicitly, but for I/O and such we have to
505 * explicitly emit a move with the constant source */
506
507 static void
508 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
509 {
510 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
511
512 if (constant_value) {
513 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
514 attach_constants(ctx, &ins, constant_value, node + 1);
515 emit_mir_instruction(ctx, ins);
516 }
517 }
518
519 static bool
520 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
521 {
522 unsigned comp = src->swizzle[0];
523
524 for (unsigned c = 1; c < nr_components; ++c) {
525 if (src->swizzle[c] != comp)
526 return true;
527 }
528
529 return false;
530 }
531
532 #define ALU_CASE(nir, _op) \
533 case nir_op_##nir: \
534 op = midgard_alu_op_##_op; \
535 assert(src_bitsize == dst_bitsize); \
536 break;
537
538 #define ALU_CASE_BCAST(nir, _op, count) \
539 case nir_op_##nir: \
540 op = midgard_alu_op_##_op; \
541 broadcast_swizzle = count; \
542 assert(src_bitsize == dst_bitsize); \
543 break;
544
545 #define ALU_CHECK_CMP(sext) \
546 if (src_bitsize == 16 && dst_bitsize == 32) { \
547 /* inferred */ \
548 } else { \
549 assert(src_bitsize == dst_bitsize); \
550 } \
551
552 #define ALU_CASE_CMP(nir, _op, sext) \
553 case nir_op_##nir: \
554 op = midgard_alu_op_##_op; \
555 ALU_CHECK_CMP(sext); \
556 break;
557
558 /* Analyze the sizes of the dest and inputs to determine reg mode. */
559
560 static midgard_reg_mode
561 reg_mode_for_nir(nir_alu_instr *instr)
562 {
563 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
564 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
565 unsigned max_bitsize = MAX2(src_bitsize, dst_bitsize);
566
567 switch (max_bitsize) {
568 case 8:
569 return midgard_reg_mode_8;
570 case 16:
571 return midgard_reg_mode_16;
572 case 32:
573 return midgard_reg_mode_32;
574 case 64:
575 return midgard_reg_mode_64;
576 default:
577 unreachable("Invalid bit size");
578 }
579 }
580
581 /* Compare mir_lower_invert */
582 static bool
583 nir_accepts_inot(nir_op op, unsigned src)
584 {
585 switch (op) {
586 case nir_op_ior:
587 case nir_op_iand:
588 case nir_op_ixor:
589 return true;
590 case nir_op_b32csel:
591 /* Only the condition */
592 return (src == 0);
593 default:
594 return false;
595 }
596 }
597
598 static bool
599 mir_accept_dest_mod(compiler_context *ctx, nir_dest **dest, nir_op op)
600 {
601 if (pan_has_dest_mod(dest, op)) {
602 assert((*dest)->is_ssa);
603 BITSET_SET(ctx->already_emitted, (*dest)->ssa.index);
604 return true;
605 }
606
607 return false;
608 }
609
610 static void
611 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool *not, bool is_int, unsigned bcast_count)
612 {
613 nir_alu_src src = instr->src[i];
614
615 if (!is_int) {
616 if (pan_has_source_mod(&src, nir_op_fneg))
617 *neg = !(*neg);
618
619 if (pan_has_source_mod(&src, nir_op_fabs))
620 *abs = true;
621 }
622
623 if (nir_accepts_inot(instr->op, i) && pan_has_source_mod(&src, nir_op_inot))
624 *not = true;
625
626 unsigned bits = nir_src_bit_size(src.src);
627
628 ins->src[to] = nir_src_index(NULL, &src.src);
629 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
630
631 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
632 ins->swizzle[to][c] = src.swizzle[
633 (!bcast_count || c < bcast_count) ? c :
634 (bcast_count - 1)];
635 }
636 }
637
638 /* Midgard features both fcsel and icsel, depending on whether you want int or
639 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
640 * we should emit an int or float csel depending on what modifiers could be
641 * placed. In the absense of modifiers, this is probably arbitrary. */
642
643 static bool
644 mir_is_bcsel_float(nir_alu_instr *instr)
645 {
646 nir_op intmods[] = {
647 nir_op_i2i8, nir_op_i2i16,
648 nir_op_i2i32, nir_op_i2i64
649 };
650
651 nir_op floatmods[] = {
652 nir_op_fabs, nir_op_fneg,
653 nir_op_f2f16, nir_op_f2f32,
654 nir_op_f2f64
655 };
656
657 nir_op floatdestmods[] = {
658 nir_op_fsat, nir_op_fsat_signed, nir_op_fclamp_pos,
659 nir_op_f2f16, nir_op_f2f32
660 };
661
662 signed score = 0;
663
664 for (unsigned i = 1; i < 3; ++i) {
665 nir_alu_src s = instr->src[i];
666 for (unsigned q = 0; q < ARRAY_SIZE(intmods); ++q) {
667 if (pan_has_source_mod(&s, intmods[q]))
668 score--;
669 }
670 }
671
672 for (unsigned i = 1; i < 3; ++i) {
673 nir_alu_src s = instr->src[i];
674 for (unsigned q = 0; q < ARRAY_SIZE(floatmods); ++q) {
675 if (pan_has_source_mod(&s, floatmods[q]))
676 score++;
677 }
678 }
679
680 for (unsigned q = 0; q < ARRAY_SIZE(floatdestmods); ++q) {
681 nir_dest *dest = &instr->dest.dest;
682 if (pan_has_dest_mod(&dest, floatdestmods[q]))
683 score++;
684 }
685
686 return (score > 0);
687 }
688
689 static void
690 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
691 {
692 nir_dest *dest = &instr->dest.dest;
693
694 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index))
695 return;
696
697 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
698 * is handled elsewhere */
699
700 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
701 midgard_emit_derivatives(ctx, instr);
702 return;
703 }
704
705 bool is_ssa = dest->is_ssa;
706
707 unsigned nr_components = nir_dest_num_components(*dest);
708 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
709 unsigned op = 0;
710
711 /* Number of components valid to check for the instruction (the rest
712 * will be forced to the last), or 0 to use as-is. Relevant as
713 * ball-type instructions have a channel count in NIR but are all vec4
714 * in Midgard */
715
716 unsigned broadcast_swizzle = 0;
717
718 /* What register mode should we operate in? */
719 midgard_reg_mode reg_mode =
720 reg_mode_for_nir(instr);
721
722 /* Do we need a destination override? Used for inline
723 * type conversion */
724
725 midgard_dest_override dest_override =
726 midgard_dest_override_none;
727
728 /* Should we swap arguments? */
729 bool flip_src12 = false;
730
731 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
732 unsigned dst_bitsize = nir_dest_bit_size(*dest);
733
734 switch (instr->op) {
735 ALU_CASE(fadd, fadd);
736 ALU_CASE(fmul, fmul);
737 ALU_CASE(fmin, fmin);
738 ALU_CASE(fmax, fmax);
739 ALU_CASE(imin, imin);
740 ALU_CASE(imax, imax);
741 ALU_CASE(umin, umin);
742 ALU_CASE(umax, umax);
743 ALU_CASE(ffloor, ffloor);
744 ALU_CASE(fround_even, froundeven);
745 ALU_CASE(ftrunc, ftrunc);
746 ALU_CASE(fceil, fceil);
747 ALU_CASE(fdot3, fdot3);
748 ALU_CASE(fdot4, fdot4);
749 ALU_CASE(iadd, iadd);
750 ALU_CASE(isub, isub);
751 ALU_CASE(imul, imul);
752
753 /* Zero shoved as second-arg */
754 ALU_CASE(iabs, iabsdiff);
755
756 ALU_CASE(mov, imov);
757
758 ALU_CASE_CMP(feq32, feq, false);
759 ALU_CASE_CMP(fne32, fne, false);
760 ALU_CASE_CMP(flt32, flt, false);
761 ALU_CASE_CMP(ieq32, ieq, true);
762 ALU_CASE_CMP(ine32, ine, true);
763 ALU_CASE_CMP(ilt32, ilt, true);
764 ALU_CASE_CMP(ult32, ult, false);
765
766 /* We don't have a native b2f32 instruction. Instead, like many
767 * GPUs, we exploit booleans as 0/~0 for false/true, and
768 * correspondingly AND
769 * by 1.0 to do the type conversion. For the moment, prime us
770 * to emit:
771 *
772 * iand [whatever], #0
773 *
774 * At the end of emit_alu (as MIR), we'll fix-up the constant
775 */
776
777 ALU_CASE_CMP(b2f32, iand, true);
778 ALU_CASE_CMP(b2i32, iand, true);
779
780 /* Likewise, we don't have a dedicated f2b32 instruction, but
781 * we can do a "not equal to 0.0" test. */
782
783 ALU_CASE_CMP(f2b32, fne, false);
784 ALU_CASE_CMP(i2b32, ine, true);
785
786 ALU_CASE(frcp, frcp);
787 ALU_CASE(frsq, frsqrt);
788 ALU_CASE(fsqrt, fsqrt);
789 ALU_CASE(fexp2, fexp2);
790 ALU_CASE(flog2, flog2);
791
792 ALU_CASE(f2i64, f2i_rtz);
793 ALU_CASE(f2u64, f2u_rtz);
794 ALU_CASE(i2f64, i2f_rtz);
795 ALU_CASE(u2f64, u2f_rtz);
796
797 ALU_CASE(f2i32, f2i_rtz);
798 ALU_CASE(f2u32, f2u_rtz);
799 ALU_CASE(i2f32, i2f_rtz);
800 ALU_CASE(u2f32, u2f_rtz);
801
802 ALU_CASE(f2i16, f2i_rtz);
803 ALU_CASE(f2u16, f2u_rtz);
804 ALU_CASE(i2f16, i2f_rtz);
805 ALU_CASE(u2f16, u2f_rtz);
806
807 ALU_CASE(fsin, fsin);
808 ALU_CASE(fcos, fcos);
809
810 /* We'll get 0 in the second arg, so:
811 * ~a = ~(a | 0) = nor(a, 0) */
812 ALU_CASE(inot, inor);
813 ALU_CASE(iand, iand);
814 ALU_CASE(ior, ior);
815 ALU_CASE(ixor, ixor);
816 ALU_CASE(ishl, ishl);
817 ALU_CASE(ishr, iasr);
818 ALU_CASE(ushr, ilsr);
819
820 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
821 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
822 ALU_CASE(b32all_fequal4, fball_eq);
823
824 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
825 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
826 ALU_CASE(b32any_fnequal4, fbany_neq);
827
828 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
829 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
830 ALU_CASE(b32all_iequal4, iball_eq);
831
832 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
833 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
834 ALU_CASE(b32any_inequal4, ibany_neq);
835
836 /* Source mods will be shoved in later */
837 ALU_CASE(fabs, fmov);
838 ALU_CASE(fneg, fmov);
839 ALU_CASE(fsat, fmov);
840 ALU_CASE(fsat_signed, fmov);
841 ALU_CASE(fclamp_pos, fmov);
842
843 /* For size conversion, we use a move. Ideally though we would squash
844 * these ops together; maybe that has to happen after in NIR as part of
845 * propagation...? An earlier algebraic pass ensured we step down by
846 * only / exactly one size. If stepping down, we use a dest override to
847 * reduce the size; if stepping up, we use a larger-sized move with a
848 * half source and a sign/zero-extension modifier */
849
850 case nir_op_i2i8:
851 case nir_op_i2i16:
852 case nir_op_i2i32:
853 case nir_op_i2i64:
854 case nir_op_u2u8:
855 case nir_op_u2u16:
856 case nir_op_u2u32:
857 case nir_op_u2u64:
858 case nir_op_f2f16:
859 case nir_op_f2f32:
860 case nir_op_f2f64: {
861 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
862 instr->op == nir_op_f2f64)
863 op = midgard_alu_op_fmov;
864 else
865 op = midgard_alu_op_imov;
866
867 if (dst_bitsize == (src_bitsize * 2)) {
868 /* inferred */
869 } else if (src_bitsize == (dst_bitsize * 2)) {
870 /* Converting down */
871 dest_override = midgard_dest_override_lower;
872 }
873
874 break;
875 }
876
877 /* For greater-or-equal, we lower to less-or-equal and flip the
878 * arguments */
879
880 case nir_op_fge:
881 case nir_op_fge32:
882 case nir_op_ige32:
883 case nir_op_uge32: {
884 op =
885 instr->op == nir_op_fge ? midgard_alu_op_fle :
886 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
887 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
888 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
889 0;
890
891 flip_src12 = true;
892 ALU_CHECK_CMP(false);
893 break;
894 }
895
896 case nir_op_b32csel: {
897 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
898 bool is_float = mir_is_bcsel_float(instr);
899 op = is_float ?
900 (mixed ? midgard_alu_op_fcsel_v : midgard_alu_op_fcsel) :
901 (mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel);
902
903 break;
904 }
905
906 default:
907 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
908 assert(0);
909 return;
910 }
911
912 /* Promote imov to fmov if it might help inline a constant */
913 if (op == midgard_alu_op_imov && nir_src_is_const(instr->src[0].src)
914 && nir_src_bit_size(instr->src[0].src) == 32
915 && nir_is_same_comp_swizzle(instr->src[0].swizzle,
916 nir_src_num_components(instr->src[0].src))) {
917 op = midgard_alu_op_fmov;
918 }
919
920 /* Midgard can perform certain modifiers on output of an ALU op */
921
922 unsigned outmod = 0;
923 bool is_int = midgard_is_integer_op(op);
924
925 if (midgard_is_integer_out_op(op)) {
926 outmod = midgard_outmod_int_wrap;
927 } else if (instr->op == nir_op_fsat) {
928 outmod = midgard_outmod_sat;
929 } else if (instr->op == nir_op_fsat_signed) {
930 outmod = midgard_outmod_sat_signed;
931 } else if (instr->op == nir_op_fclamp_pos) {
932 outmod = midgard_outmod_pos;
933 }
934
935 /* Fetch unit, quirks, etc information */
936 unsigned opcode_props = alu_opcode_props[op].props;
937 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
938
939 /* Look for floating point mods. We have the mods fsat, fsat_signed,
940 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
941 *
942 * fsat_signed(fpos(x)) = fsat(x)
943 * fsat_signed(fsat(x)) = fsat(x)
944 * fpos(fsat_signed(x)) = fsat(x)
945 * fpos(fsat(x)) = fsat(x)
946 * fsat(fsat_signed(x)) = fsat(x)
947 * fsat(fpos(x)) = fsat(x)
948 *
949 * So by cases any composition of output modifiers is equivalent to
950 * fsat alone.
951 */
952
953 if (!is_int && !(opcode_props & OP_TYPE_CONVERT)) {
954 bool fpos = mir_accept_dest_mod(ctx, &dest, nir_op_fclamp_pos);
955 bool fsat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat);
956 bool ssat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat_signed);
957 bool prior = (outmod != midgard_outmod_none);
958 int count = (int) prior + (int) fpos + (int) ssat + (int) fsat;
959
960 outmod = ((count > 1) || fsat) ? midgard_outmod_sat :
961 fpos ? midgard_outmod_pos :
962 ssat ? midgard_outmod_sat_signed :
963 outmod;
964 }
965
966 midgard_instruction ins = {
967 .type = TAG_ALU_4,
968 .dest = nir_dest_index(dest),
969 .dest_type = nir_op_infos[instr->op].output_type
970 | nir_dest_bit_size(*dest),
971 };
972
973 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
974 ins.src[i] = ~0;
975
976 if (quirk_flipped_r24) {
977 ins.src[0] = ~0;
978 mir_copy_src(&ins, instr, 0, 1, &ins.src_abs[1], &ins.src_neg[1], &ins.src_invert[1], is_int, broadcast_swizzle);
979 } else {
980 for (unsigned i = 0; i < nr_inputs; ++i) {
981 unsigned to = i;
982
983 if (instr->op == nir_op_b32csel) {
984 /* The condition is the first argument; move
985 * the other arguments up one to be a binary
986 * instruction for Midgard with the condition
987 * last */
988
989 if (i == 0)
990 to = 2;
991 else if (flip_src12)
992 to = 2 - i;
993 else
994 to = i - 1;
995 } else if (flip_src12) {
996 to = 1 - to;
997 }
998
999 mir_copy_src(&ins, instr, i, to, &ins.src_abs[to], &ins.src_neg[to], &ins.src_invert[to], is_int, broadcast_swizzle);
1000
1001 /* (!c) ? a : b = c ? b : a */
1002 if (instr->op == nir_op_b32csel && ins.src_invert[2]) {
1003 ins.src_invert[2] = false;
1004 flip_src12 ^= true;
1005 }
1006 }
1007 }
1008
1009 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
1010 /* Lowered to move */
1011 if (instr->op == nir_op_fneg)
1012 ins.src_neg[1] ^= true;
1013
1014 if (instr->op == nir_op_fabs)
1015 ins.src_abs[1] = true;
1016 }
1017
1018 ins.mask = mask_of(nr_components);
1019
1020 midgard_vector_alu alu = {
1021 .op = op,
1022 .reg_mode = reg_mode,
1023 .dest_override = dest_override,
1024 .outmod = outmod,
1025 };
1026
1027 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1028 * components that don't exist. Note modifier => SSA => !reg => no
1029 * writemask, so we don't have to worry about writemasks here.*/
1030
1031 if (!is_ssa)
1032 ins.mask &= instr->dest.write_mask;
1033
1034 ins.alu = alu;
1035
1036 /* Arrange for creation of iandnot/iornot */
1037 if (ins.src_invert[0] && !ins.src_invert[1]) {
1038 mir_flip(&ins);
1039 ins.src_invert[0] = false;
1040 ins.src_invert[1] = true;
1041 }
1042
1043 /* Late fixup for emulated instructions */
1044
1045 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1046 /* Presently, our second argument is an inline #0 constant.
1047 * Switch over to an embedded 1.0 constant (that can't fit
1048 * inline, since we're 32-bit, not 16-bit like the inline
1049 * constants) */
1050
1051 ins.has_inline_constant = false;
1052 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1053 ins.src_types[1] = nir_type_float32;
1054 ins.has_constants = true;
1055
1056 if (instr->op == nir_op_b2f32)
1057 ins.constants.f32[0] = 1.0f;
1058 else
1059 ins.constants.i32[0] = 1;
1060
1061 for (unsigned c = 0; c < 16; ++c)
1062 ins.swizzle[1][c] = 0;
1063 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1064 /* Lots of instructions need a 0 plonked in */
1065 ins.has_inline_constant = false;
1066 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1067 ins.src_types[1] = nir_type_uint32;
1068 ins.has_constants = true;
1069 ins.constants.u32[0] = 0;
1070
1071 for (unsigned c = 0; c < 16; ++c)
1072 ins.swizzle[1][c] = 0;
1073 }
1074
1075 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1076 /* To avoid duplicating the lookup tables (probably), true LUT
1077 * instructions can only operate as if they were scalars. Lower
1078 * them here by changing the component. */
1079
1080 unsigned orig_mask = ins.mask;
1081
1082 unsigned swizzle_back[MIR_VEC_COMPONENTS];
1083 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
1084
1085 for (int i = 0; i < nr_components; ++i) {
1086 /* Mask the associated component, dropping the
1087 * instruction if needed */
1088
1089 ins.mask = 1 << i;
1090 ins.mask &= orig_mask;
1091
1092 if (!ins.mask)
1093 continue;
1094
1095 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1096 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1097
1098 emit_mir_instruction(ctx, ins);
1099 }
1100 } else {
1101 emit_mir_instruction(ctx, ins);
1102 }
1103 }
1104
1105 #undef ALU_CASE
1106
1107 static void
1108 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1109 {
1110 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1111 unsigned nir_mask = 0;
1112 unsigned dsize = 0;
1113
1114 if (is_read) {
1115 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1116 dsize = nir_dest_bit_size(intr->dest);
1117 } else {
1118 nir_mask = nir_intrinsic_write_mask(intr);
1119 dsize = 32;
1120 }
1121
1122 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1123 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1124 mir_set_bytemask(ins, bytemask);
1125
1126 if (dsize == 64)
1127 ins->load_64 = true;
1128 }
1129
1130 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1131 * optimized) versions of UBO #0 */
1132
1133 static midgard_instruction *
1134 emit_ubo_read(
1135 compiler_context *ctx,
1136 nir_instr *instr,
1137 unsigned dest,
1138 unsigned offset,
1139 nir_src *indirect_offset,
1140 unsigned indirect_shift,
1141 unsigned index)
1142 {
1143 /* TODO: half-floats */
1144
1145 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1146 ins.constants.u32[0] = offset;
1147
1148 if (instr->type == nir_instr_type_intrinsic)
1149 mir_set_intr_mask(instr, &ins, true);
1150
1151 if (indirect_offset) {
1152 ins.src[2] = nir_src_index(ctx, indirect_offset);
1153 ins.src_types[2] = nir_type_uint32;
1154 ins.load_store.arg_2 = (indirect_shift << 5);
1155 } else {
1156 ins.load_store.arg_2 = 0x1E;
1157 }
1158
1159 ins.load_store.arg_1 = index;
1160
1161 return emit_mir_instruction(ctx, ins);
1162 }
1163
1164 /* Globals are like UBOs if you squint. And shared memory is like globals if
1165 * you squint even harder */
1166
1167 static void
1168 emit_global(
1169 compiler_context *ctx,
1170 nir_instr *instr,
1171 bool is_read,
1172 unsigned srcdest,
1173 nir_src *offset,
1174 bool is_shared)
1175 {
1176 /* TODO: types */
1177
1178 midgard_instruction ins;
1179
1180 if (is_read)
1181 ins = m_ld_int4(srcdest, 0);
1182 else
1183 ins = m_st_int4(srcdest, 0);
1184
1185 mir_set_offset(ctx, &ins, offset, is_shared);
1186 mir_set_intr_mask(instr, &ins, is_read);
1187
1188 emit_mir_instruction(ctx, ins);
1189 }
1190
1191 static void
1192 emit_varying_read(
1193 compiler_context *ctx,
1194 unsigned dest, unsigned offset,
1195 unsigned nr_comp, unsigned component,
1196 nir_src *indirect_offset, nir_alu_type type, bool flat)
1197 {
1198 /* XXX: Half-floats? */
1199 /* TODO: swizzle, mask */
1200
1201 midgard_instruction ins = m_ld_vary_32(dest, offset);
1202 ins.mask = mask_of(nr_comp);
1203
1204 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1205 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1206
1207 midgard_varying_parameter p = {
1208 .is_varying = 1,
1209 .interpolation = midgard_interp_default,
1210 .flat = flat,
1211 };
1212
1213 unsigned u;
1214 memcpy(&u, &p, sizeof(p));
1215 ins.load_store.varying_parameters = u;
1216
1217 if (indirect_offset) {
1218 ins.src[2] = nir_src_index(ctx, indirect_offset);
1219 ins.src_types[2] = nir_type_uint32;
1220 } else
1221 ins.load_store.arg_2 = 0x1E;
1222
1223 ins.load_store.arg_1 = 0x9E;
1224
1225 /* Use the type appropriate load */
1226 switch (type) {
1227 case nir_type_uint:
1228 case nir_type_bool:
1229 ins.load_store.op = midgard_op_ld_vary_32u;
1230 break;
1231 case nir_type_int:
1232 ins.load_store.op = midgard_op_ld_vary_32i;
1233 break;
1234 case nir_type_float:
1235 ins.load_store.op = midgard_op_ld_vary_32;
1236 break;
1237 default:
1238 unreachable("Attempted to load unknown type");
1239 break;
1240 }
1241
1242 emit_mir_instruction(ctx, ins);
1243 }
1244
1245 static void
1246 emit_attr_read(
1247 compiler_context *ctx,
1248 unsigned dest, unsigned offset,
1249 unsigned nr_comp, nir_alu_type t)
1250 {
1251 midgard_instruction ins = m_ld_attr_32(dest, offset);
1252 ins.load_store.arg_1 = 0x1E;
1253 ins.load_store.arg_2 = 0x1E;
1254 ins.mask = mask_of(nr_comp);
1255
1256 /* Use the type appropriate load */
1257 switch (t) {
1258 case nir_type_uint:
1259 case nir_type_bool:
1260 ins.load_store.op = midgard_op_ld_attr_32u;
1261 break;
1262 case nir_type_int:
1263 ins.load_store.op = midgard_op_ld_attr_32i;
1264 break;
1265 case nir_type_float:
1266 ins.load_store.op = midgard_op_ld_attr_32;
1267 break;
1268 default:
1269 unreachable("Attempted to load unknown type");
1270 break;
1271 }
1272
1273 emit_mir_instruction(ctx, ins);
1274 }
1275
1276 static void
1277 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1278 unsigned nr_components, unsigned offset)
1279 {
1280 nir_dest nir_dest;
1281
1282 /* Figure out which uniform this is */
1283 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1284 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1285
1286 unsigned dest = nir_dest_index(&nir_dest);
1287
1288 /* Sysvals are prefix uniforms */
1289 unsigned uniform = ((uintptr_t) val) - 1;
1290
1291 /* Emit the read itself -- this is never indirect */
1292 midgard_instruction *ins =
1293 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1294
1295 ins->mask = mask_of(nr_components);
1296 }
1297
1298 static unsigned
1299 compute_builtin_arg(nir_op op)
1300 {
1301 switch (op) {
1302 case nir_intrinsic_load_work_group_id:
1303 return 0x14;
1304 case nir_intrinsic_load_local_invocation_id:
1305 return 0x10;
1306 default:
1307 unreachable("Invalid compute paramater loaded");
1308 }
1309 }
1310
1311 static void
1312 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1313 {
1314 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1315
1316 midgard_instruction *br = ctx->writeout_branch[rt];
1317
1318 assert(!br);
1319
1320 emit_explicit_constant(ctx, src, src);
1321
1322 struct midgard_instruction ins =
1323 v_branch(false, false);
1324
1325 ins.writeout = true;
1326
1327 /* Add dependencies */
1328 ins.src[0] = src;
1329 ins.src_types[0] = nir_type_uint32;
1330 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1331 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1332
1333 /* Emit the branch */
1334 br = emit_mir_instruction(ctx, ins);
1335 schedule_barrier(ctx);
1336 ctx->writeout_branch[rt] = br;
1337
1338 /* Push our current location = current block count - 1 = where we'll
1339 * jump to. Maybe a bit too clever for my own good */
1340
1341 br->branch.target_block = ctx->block_count - 1;
1342 }
1343
1344 static void
1345 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1346 {
1347 unsigned reg = nir_dest_index(&instr->dest);
1348 midgard_instruction ins = m_ld_compute_id(reg, 0);
1349 ins.mask = mask_of(3);
1350 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1351 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1352 emit_mir_instruction(ctx, ins);
1353 }
1354
1355 static unsigned
1356 vertex_builtin_arg(nir_op op)
1357 {
1358 switch (op) {
1359 case nir_intrinsic_load_vertex_id:
1360 return PAN_VERTEX_ID;
1361 case nir_intrinsic_load_instance_id:
1362 return PAN_INSTANCE_ID;
1363 default:
1364 unreachable("Invalid vertex builtin");
1365 }
1366 }
1367
1368 static void
1369 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1370 {
1371 unsigned reg = nir_dest_index(&instr->dest);
1372 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1373 }
1374
1375 static void
1376 emit_control_barrier(compiler_context *ctx)
1377 {
1378 midgard_instruction ins = {
1379 .type = TAG_TEXTURE_4,
1380 .src = { ~0, ~0, ~0, ~0 },
1381 .texture = {
1382 .op = TEXTURE_OP_BARRIER,
1383
1384 /* TODO: optimize */
1385 .barrier_buffer = 1,
1386 .barrier_shared = 1
1387 }
1388 };
1389
1390 emit_mir_instruction(ctx, ins);
1391 }
1392
1393 static const nir_variable *
1394 search_var(struct exec_list *vars, unsigned driver_loc)
1395 {
1396 nir_foreach_variable(var, vars) {
1397 if (var->data.driver_location == driver_loc)
1398 return var;
1399 }
1400
1401 return NULL;
1402 }
1403
1404 static unsigned
1405 mir_get_branch_cond(nir_src *src, bool *invert)
1406 {
1407 /* Wrap it. No swizzle since it's a scalar */
1408
1409 nir_alu_src alu = {
1410 .src = *src
1411 };
1412
1413 *invert = pan_has_source_mod(&alu, nir_op_inot);
1414 return nir_src_index(NULL, &alu.src);
1415 }
1416
1417 static void
1418 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1419 {
1420 unsigned offset = 0, reg;
1421
1422 switch (instr->intrinsic) {
1423 case nir_intrinsic_discard_if:
1424 case nir_intrinsic_discard: {
1425 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1426 struct midgard_instruction discard = v_branch(conditional, false);
1427 discard.branch.target_type = TARGET_DISCARD;
1428
1429 if (conditional) {
1430 discard.src[0] = mir_get_branch_cond(&instr->src[0],
1431 &discard.branch.invert_conditional);
1432 discard.src_types[0] = nir_type_uint32;
1433 }
1434
1435 emit_mir_instruction(ctx, discard);
1436 schedule_barrier(ctx);
1437
1438 break;
1439 }
1440
1441 case nir_intrinsic_load_uniform:
1442 case nir_intrinsic_load_ubo:
1443 case nir_intrinsic_load_global:
1444 case nir_intrinsic_load_shared:
1445 case nir_intrinsic_load_input:
1446 case nir_intrinsic_load_interpolated_input: {
1447 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1448 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1449 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1450 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1451 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1452 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1453
1454 /* Get the base type of the intrinsic */
1455 /* TODO: Infer type? Does it matter? */
1456 nir_alu_type t =
1457 (is_ubo || is_global || is_shared) ? nir_type_uint :
1458 (is_interp) ? nir_type_float :
1459 nir_intrinsic_type(instr);
1460
1461 t = nir_alu_type_get_base_type(t);
1462
1463 if (!(is_ubo || is_global)) {
1464 offset = nir_intrinsic_base(instr);
1465 }
1466
1467 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1468
1469 nir_src *src_offset = nir_get_io_offset_src(instr);
1470
1471 bool direct = nir_src_is_const(*src_offset);
1472 nir_src *indirect_offset = direct ? NULL : src_offset;
1473
1474 if (direct)
1475 offset += nir_src_as_uint(*src_offset);
1476
1477 /* We may need to apply a fractional offset */
1478 int component = (is_flat || is_interp) ?
1479 nir_intrinsic_component(instr) : 0;
1480 reg = nir_dest_index(&instr->dest);
1481
1482 if (is_uniform && !ctx->is_blend) {
1483 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1484 } else if (is_ubo) {
1485 nir_src index = instr->src[0];
1486
1487 /* TODO: Is indirect block number possible? */
1488 assert(nir_src_is_const(index));
1489
1490 uint32_t uindex = nir_src_as_uint(index) + 1;
1491 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1492 } else if (is_global || is_shared) {
1493 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1494 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1495 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1496 } else if (ctx->is_blend) {
1497 /* For blend shaders, load the input color, which is
1498 * preloaded to r0 */
1499
1500 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1501 emit_mir_instruction(ctx, move);
1502 schedule_barrier(ctx);
1503 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1504 emit_attr_read(ctx, reg, offset, nr_comp, t);
1505 } else {
1506 DBG("Unknown load\n");
1507 assert(0);
1508 }
1509
1510 break;
1511 }
1512
1513 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1514 case nir_intrinsic_load_barycentric_pixel:
1515 case nir_intrinsic_load_barycentric_centroid:
1516 break;
1517
1518 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1519
1520 case nir_intrinsic_load_raw_output_pan:
1521 case nir_intrinsic_load_output_u8_as_fp16_pan:
1522 reg = nir_dest_index(&instr->dest);
1523 assert(ctx->is_blend);
1524
1525 /* T720 and below use different blend opcodes with slightly
1526 * different semantics than T760 and up */
1527
1528 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1529 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1530
1531 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1532 ld.load_store.op = old_blend ?
1533 midgard_op_ld_color_buffer_u8_as_fp16_old :
1534 midgard_op_ld_color_buffer_u8_as_fp16;
1535
1536 if (old_blend) {
1537 ld.load_store.address = 1;
1538 ld.load_store.arg_2 = 0x1E;
1539 }
1540
1541 for (unsigned c = 4; c < 16; ++c)
1542 ld.swizzle[0][c] = 0;
1543
1544 ld.dest_type = nir_type_float16;
1545 }
1546
1547 emit_mir_instruction(ctx, ld);
1548 break;
1549
1550 case nir_intrinsic_load_blend_const_color_rgba: {
1551 assert(ctx->is_blend);
1552 reg = nir_dest_index(&instr->dest);
1553
1554 /* Blend constants are embedded directly in the shader and
1555 * patched in, so we use some magic routing */
1556
1557 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1558 ins.has_constants = true;
1559 ins.has_blend_constant = true;
1560 emit_mir_instruction(ctx, ins);
1561 break;
1562 }
1563
1564 case nir_intrinsic_store_zs_output_pan: {
1565 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1566 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1567 MIDGARD_ZS_RT);
1568
1569 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1570
1571 if (!nir_intrinsic_component(instr))
1572 br->writeout_depth = true;
1573 if (nir_intrinsic_component(instr) ||
1574 instr->num_components)
1575 br->writeout_stencil = true;
1576 assert(br->writeout_depth | br->writeout_stencil);
1577 break;
1578 }
1579
1580 case nir_intrinsic_store_output:
1581 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1582
1583 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1584
1585 reg = nir_src_index(ctx, &instr->src[0]);
1586
1587 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1588 const nir_variable *var;
1589 enum midgard_rt_id rt;
1590
1591 var = search_var(&ctx->nir->outputs,
1592 nir_intrinsic_base(instr));
1593 assert(var);
1594 if (var->data.location == FRAG_RESULT_COLOR)
1595 rt = MIDGARD_COLOR_RT0;
1596 else if (var->data.location >= FRAG_RESULT_DATA0)
1597 rt = MIDGARD_COLOR_RT0 + var->data.location -
1598 FRAG_RESULT_DATA0;
1599 else
1600 assert(0);
1601
1602 emit_fragment_store(ctx, reg, rt);
1603 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1604 /* We should have been vectorized, though we don't
1605 * currently check that st_vary is emitted only once
1606 * per slot (this is relevant, since there's not a mask
1607 * parameter available on the store [set to 0 by the
1608 * blob]). We do respect the component by adjusting the
1609 * swizzle. If this is a constant source, we'll need to
1610 * emit that explicitly. */
1611
1612 emit_explicit_constant(ctx, reg, reg);
1613
1614 unsigned dst_component = nir_intrinsic_component(instr);
1615 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1616
1617 midgard_instruction st = m_st_vary_32(reg, offset);
1618 st.load_store.arg_1 = 0x9E;
1619 st.load_store.arg_2 = 0x1E;
1620
1621 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1622 case nir_type_uint:
1623 case nir_type_bool:
1624 st.load_store.op = midgard_op_st_vary_32u;
1625 break;
1626 case nir_type_int:
1627 st.load_store.op = midgard_op_st_vary_32i;
1628 break;
1629 case nir_type_float:
1630 st.load_store.op = midgard_op_st_vary_32;
1631 break;
1632 default:
1633 unreachable("Attempted to store unknown type");
1634 break;
1635 }
1636
1637 /* nir_intrinsic_component(store_intr) encodes the
1638 * destination component start. Source component offset
1639 * adjustment is taken care of in
1640 * install_registers_instr(), when offset_swizzle() is
1641 * called.
1642 */
1643 unsigned src_component = COMPONENT_X;
1644
1645 assert(nr_comp > 0);
1646 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1647 st.swizzle[0][i] = src_component;
1648 if (i >= dst_component && i < dst_component + nr_comp - 1)
1649 src_component++;
1650 }
1651
1652 emit_mir_instruction(ctx, st);
1653 } else {
1654 DBG("Unknown store\n");
1655 assert(0);
1656 }
1657
1658 break;
1659
1660 /* Special case of store_output for lowered blend shaders */
1661 case nir_intrinsic_store_raw_output_pan:
1662 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1663 reg = nir_src_index(ctx, &instr->src[0]);
1664
1665 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1666 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1667 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1668 * of:
1669 *
1670 * imov r0.xyzw, r0.xxxx
1671 */
1672
1673 unsigned expanded = make_compiler_temp(ctx);
1674
1675 midgard_instruction splatter = v_mov(reg, expanded);
1676
1677 for (unsigned c = 0; c < 16; ++c)
1678 splatter.swizzle[1][c] = 0;
1679
1680 emit_mir_instruction(ctx, splatter);
1681 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1682 } else
1683 emit_fragment_store(ctx, reg, ctx->blend_rt);
1684
1685 break;
1686
1687 case nir_intrinsic_store_global:
1688 case nir_intrinsic_store_shared:
1689 reg = nir_src_index(ctx, &instr->src[0]);
1690 emit_explicit_constant(ctx, reg, reg);
1691
1692 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1693 break;
1694
1695 case nir_intrinsic_load_ssbo_address:
1696 emit_sysval_read(ctx, &instr->instr, 1, 0);
1697 break;
1698
1699 case nir_intrinsic_get_buffer_size:
1700 emit_sysval_read(ctx, &instr->instr, 1, 8);
1701 break;
1702
1703 case nir_intrinsic_load_viewport_scale:
1704 case nir_intrinsic_load_viewport_offset:
1705 case nir_intrinsic_load_num_work_groups:
1706 case nir_intrinsic_load_sampler_lod_parameters_pan:
1707 emit_sysval_read(ctx, &instr->instr, 3, 0);
1708 break;
1709
1710 case nir_intrinsic_load_work_group_id:
1711 case nir_intrinsic_load_local_invocation_id:
1712 emit_compute_builtin(ctx, instr);
1713 break;
1714
1715 case nir_intrinsic_load_vertex_id:
1716 case nir_intrinsic_load_instance_id:
1717 emit_vertex_builtin(ctx, instr);
1718 break;
1719
1720 case nir_intrinsic_memory_barrier_buffer:
1721 case nir_intrinsic_memory_barrier_shared:
1722 break;
1723
1724 case nir_intrinsic_control_barrier:
1725 schedule_barrier(ctx);
1726 emit_control_barrier(ctx);
1727 schedule_barrier(ctx);
1728 break;
1729
1730 default:
1731 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1732 assert(0);
1733 break;
1734 }
1735 }
1736
1737 static unsigned
1738 midgard_tex_format(enum glsl_sampler_dim dim)
1739 {
1740 switch (dim) {
1741 case GLSL_SAMPLER_DIM_1D:
1742 case GLSL_SAMPLER_DIM_BUF:
1743 return MALI_TEX_1D;
1744
1745 case GLSL_SAMPLER_DIM_2D:
1746 case GLSL_SAMPLER_DIM_EXTERNAL:
1747 case GLSL_SAMPLER_DIM_RECT:
1748 return MALI_TEX_2D;
1749
1750 case GLSL_SAMPLER_DIM_3D:
1751 return MALI_TEX_3D;
1752
1753 case GLSL_SAMPLER_DIM_CUBE:
1754 return MALI_TEX_CUBE;
1755
1756 default:
1757 DBG("Unknown sampler dim type\n");
1758 assert(0);
1759 return 0;
1760 }
1761 }
1762
1763 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1764 * was successful */
1765
1766 static bool
1767 pan_attach_constant_bias(
1768 compiler_context *ctx,
1769 nir_src lod,
1770 midgard_texture_word *word)
1771 {
1772 /* To attach as constant, it has to *be* constant */
1773
1774 if (!nir_src_is_const(lod))
1775 return false;
1776
1777 float f = nir_src_as_float(lod);
1778
1779 /* Break into fixed-point */
1780 signed lod_int = f;
1781 float lod_frac = f - lod_int;
1782
1783 /* Carry over negative fractions */
1784 if (lod_frac < 0.0) {
1785 lod_int--;
1786 lod_frac += 1.0;
1787 }
1788
1789 /* Encode */
1790 word->bias = float_to_ubyte(lod_frac);
1791 word->bias_int = lod_int;
1792
1793 return true;
1794 }
1795
1796 static void
1797 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1798 unsigned midgard_texop)
1799 {
1800 /* TODO */
1801 //assert (!instr->sampler);
1802
1803 int texture_index = instr->texture_index;
1804 int sampler_index = texture_index;
1805
1806 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1807 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1808
1809 midgard_instruction ins = {
1810 .type = TAG_TEXTURE_4,
1811 .mask = 0xF,
1812 .dest = nir_dest_index(&instr->dest),
1813 .src = { ~0, ~0, ~0, ~0 },
1814 .dest_type = dest_type,
1815 .swizzle = SWIZZLE_IDENTITY_4,
1816 .texture = {
1817 .op = midgard_texop,
1818 .format = midgard_tex_format(instr->sampler_dim),
1819 .texture_handle = texture_index,
1820 .sampler_handle = sampler_index,
1821 .shadow = instr->is_shadow,
1822 }
1823 };
1824
1825 if (instr->is_shadow && !instr->is_new_style_shadow)
1826 for (int i = 0; i < 4; ++i)
1827 ins.swizzle[0][i] = COMPONENT_X;
1828
1829 /* We may need a temporary for the coordinate */
1830
1831 bool needs_temp_coord =
1832 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1833 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1834 (instr->is_shadow);
1835
1836 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1837
1838 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1839 int index = nir_src_index(ctx, &instr->src[i].src);
1840 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1841 unsigned sz = nir_src_bit_size(instr->src[i].src);
1842 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1843
1844 switch (instr->src[i].src_type) {
1845 case nir_tex_src_coord: {
1846 emit_explicit_constant(ctx, index, index);
1847
1848 unsigned coord_mask = mask_of(instr->coord_components);
1849
1850 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1851
1852 if (flip_zw)
1853 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1854
1855 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1856 /* texelFetch is undefined on samplerCube */
1857 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1858
1859 /* For cubemaps, we use a special ld/st op to
1860 * select the face and copy the xy into the
1861 * texture register */
1862
1863 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1864 ld.src[1] = index;
1865 ld.src_types[1] = T;
1866 ld.mask = 0x3; /* xy */
1867 ld.load_store.arg_1 = 0x20;
1868 ld.swizzle[1][3] = COMPONENT_X;
1869 emit_mir_instruction(ctx, ld);
1870
1871 /* xyzw -> xyxx */
1872 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1873 ins.swizzle[1][3] = COMPONENT_X;
1874 } else if (needs_temp_coord) {
1875 /* mov coord_temp, coords */
1876 midgard_instruction mov = v_mov(index, coords);
1877 mov.mask = coord_mask;
1878
1879 if (flip_zw)
1880 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1881
1882 emit_mir_instruction(ctx, mov);
1883 } else {
1884 coords = index;
1885 }
1886
1887 ins.src[1] = coords;
1888 ins.src_types[1] = T;
1889
1890 /* Texelfetch coordinates uses all four elements
1891 * (xyz/index) regardless of texture dimensionality,
1892 * which means it's necessary to zero the unused
1893 * components to keep everything happy */
1894
1895 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1896 /* mov index.zw, #0, or generalized */
1897 midgard_instruction mov =
1898 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1899 mov.has_constants = true;
1900 mov.mask = coord_mask ^ 0xF;
1901 emit_mir_instruction(ctx, mov);
1902 }
1903
1904 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1905 /* Array component in w but NIR wants it in z,
1906 * but if we have a temp coord we already fixed
1907 * that up */
1908
1909 if (nr_components == 3) {
1910 ins.swizzle[1][2] = COMPONENT_Z;
1911 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1912 } else if (nr_components == 2) {
1913 ins.swizzle[1][2] =
1914 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1915 ins.swizzle[1][3] = COMPONENT_X;
1916 } else
1917 unreachable("Invalid texture 2D components");
1918 }
1919
1920 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1921 /* We zeroed */
1922 ins.swizzle[1][2] = COMPONENT_Z;
1923 ins.swizzle[1][3] = COMPONENT_W;
1924 }
1925
1926 break;
1927 }
1928
1929 case nir_tex_src_bias:
1930 case nir_tex_src_lod: {
1931 /* Try as a constant if we can */
1932
1933 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1934 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1935 break;
1936
1937 ins.texture.lod_register = true;
1938 ins.src[2] = index;
1939 ins.src_types[2] = T;
1940
1941 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1942 ins.swizzle[2][c] = COMPONENT_X;
1943
1944 emit_explicit_constant(ctx, index, index);
1945
1946 break;
1947 };
1948
1949 case nir_tex_src_offset: {
1950 ins.texture.offset_register = true;
1951 ins.src[3] = index;
1952 ins.src_types[3] = T;
1953
1954 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1955 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
1956
1957 emit_explicit_constant(ctx, index, index);
1958 break;
1959 };
1960
1961 case nir_tex_src_comparator: {
1962 unsigned comp = COMPONENT_Z;
1963
1964 /* mov coord_temp.foo, coords */
1965 midgard_instruction mov = v_mov(index, coords);
1966 mov.mask = 1 << comp;
1967
1968 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
1969 mov.swizzle[1][i] = COMPONENT_X;
1970
1971 emit_mir_instruction(ctx, mov);
1972 break;
1973 }
1974
1975 default: {
1976 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
1977 assert(0);
1978 }
1979 }
1980 }
1981
1982 emit_mir_instruction(ctx, ins);
1983 }
1984
1985 static void
1986 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1987 {
1988 switch (instr->op) {
1989 case nir_texop_tex:
1990 case nir_texop_txb:
1991 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
1992 break;
1993 case nir_texop_txl:
1994 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
1995 break;
1996 case nir_texop_txf:
1997 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
1998 break;
1999 case nir_texop_txs:
2000 emit_sysval_read(ctx, &instr->instr, 4, 0);
2001 break;
2002 default: {
2003 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
2004 assert(0);
2005 }
2006 }
2007 }
2008
2009 static void
2010 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
2011 {
2012 switch (instr->type) {
2013 case nir_jump_break: {
2014 /* Emit a branch out of the loop */
2015 struct midgard_instruction br = v_branch(false, false);
2016 br.branch.target_type = TARGET_BREAK;
2017 br.branch.target_break = ctx->current_loop_depth;
2018 emit_mir_instruction(ctx, br);
2019 break;
2020 }
2021
2022 default:
2023 DBG("Unknown jump type %d\n", instr->type);
2024 break;
2025 }
2026 }
2027
2028 static void
2029 emit_instr(compiler_context *ctx, struct nir_instr *instr)
2030 {
2031 switch (instr->type) {
2032 case nir_instr_type_load_const:
2033 emit_load_const(ctx, nir_instr_as_load_const(instr));
2034 break;
2035
2036 case nir_instr_type_intrinsic:
2037 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2038 break;
2039
2040 case nir_instr_type_alu:
2041 emit_alu(ctx, nir_instr_as_alu(instr));
2042 break;
2043
2044 case nir_instr_type_tex:
2045 emit_tex(ctx, nir_instr_as_tex(instr));
2046 break;
2047
2048 case nir_instr_type_jump:
2049 emit_jump(ctx, nir_instr_as_jump(instr));
2050 break;
2051
2052 case nir_instr_type_ssa_undef:
2053 /* Spurious */
2054 break;
2055
2056 default:
2057 DBG("Unhandled instruction type\n");
2058 break;
2059 }
2060 }
2061
2062
2063 /* ALU instructions can inline or embed constants, which decreases register
2064 * pressure and saves space. */
2065
2066 #define CONDITIONAL_ATTACH(idx) { \
2067 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2068 \
2069 if (entry) { \
2070 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2071 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2072 } \
2073 }
2074
2075 static void
2076 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2077 {
2078 mir_foreach_instr_in_block(block, alu) {
2079 /* Other instructions cannot inline constants */
2080 if (alu->type != TAG_ALU_4) continue;
2081 if (alu->compact_branch) continue;
2082
2083 /* If there is already a constant here, we can do nothing */
2084 if (alu->has_constants) continue;
2085
2086 CONDITIONAL_ATTACH(0);
2087
2088 if (!alu->has_constants) {
2089 CONDITIONAL_ATTACH(1)
2090 } else if (!alu->inline_constant) {
2091 /* Corner case: _two_ vec4 constants, for instance with a
2092 * csel. For this case, we can only use a constant
2093 * register for one, we'll have to emit a move for the
2094 * other. */
2095
2096 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2097 unsigned scratch = make_compiler_temp(ctx);
2098
2099 if (entry) {
2100 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2101 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2102
2103 /* Set the source */
2104 alu->src[1] = scratch;
2105
2106 /* Inject us -before- the last instruction which set r31 */
2107 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2108 }
2109 }
2110 }
2111 }
2112
2113 /* Midgard supports two types of constants, embedded constants (128-bit) and
2114 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2115 * constants can be demoted to inline constants, for space savings and
2116 * sometimes a performance boost */
2117
2118 static void
2119 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2120 {
2121 mir_foreach_instr_in_block(block, ins) {
2122 if (!ins->has_constants) continue;
2123 if (ins->has_inline_constant) continue;
2124
2125 /* Blend constants must not be inlined by definition */
2126 if (ins->has_blend_constant) continue;
2127
2128 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2129 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2130 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2131
2132 if (!(is_16 || is_32))
2133 continue;
2134
2135 /* src1 cannot be an inline constant due to encoding
2136 * restrictions. So, if possible we try to flip the arguments
2137 * in that case */
2138
2139 int op = ins->alu.op;
2140
2141 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2142 alu_opcode_props[op].props & OP_COMMUTES) {
2143 mir_flip(ins);
2144 }
2145
2146 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2147 /* Extract the source information */
2148
2149 midgard_vector_alu_src *src;
2150 int q = ins->alu.src2;
2151 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
2152 src = m;
2153
2154 /* Component is from the swizzle. Take a nonzero component */
2155 assert(ins->mask);
2156 unsigned first_comp = ffs(ins->mask) - 1;
2157 unsigned component = ins->swizzle[1][first_comp];
2158
2159 /* Scale constant appropriately, if we can legally */
2160 uint16_t scaled_constant = 0;
2161
2162 if (is_16) {
2163 scaled_constant = ins->constants.u16[component];
2164 } else if (midgard_is_integer_op(op)) {
2165 scaled_constant = ins->constants.u32[component];
2166
2167 /* Constant overflow after resize */
2168 if (scaled_constant != ins->constants.u32[component])
2169 continue;
2170 } else {
2171 float original = ins->constants.f32[component];
2172 scaled_constant = _mesa_float_to_half(original);
2173
2174 /* Check for loss of precision. If this is
2175 * mediump, we don't care, but for a highp
2176 * shader, we need to pay attention. NIR
2177 * doesn't yet tell us which mode we're in!
2178 * Practically this prevents most constants
2179 * from being inlined, sadly. */
2180
2181 float fp32 = _mesa_half_to_float(scaled_constant);
2182
2183 if (fp32 != original)
2184 continue;
2185 }
2186
2187 /* Should've been const folded */
2188 if (ins->src_abs[1] || ins->src_neg[1])
2189 continue;
2190
2191 /* Make sure that the constant is not itself a vector
2192 * by checking if all accessed values are the same. */
2193
2194 const midgard_constants *cons = &ins->constants;
2195 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2196
2197 bool is_vector = false;
2198 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2199
2200 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2201 /* We only care if this component is actually used */
2202 if (!(mask & (1 << c)))
2203 continue;
2204
2205 uint32_t test = is_16 ?
2206 cons->u16[ins->swizzle[1][c]] :
2207 cons->u32[ins->swizzle[1][c]];
2208
2209 if (test != value) {
2210 is_vector = true;
2211 break;
2212 }
2213 }
2214
2215 if (is_vector)
2216 continue;
2217
2218 /* Get rid of the embedded constant */
2219 ins->has_constants = false;
2220 ins->src[1] = ~0;
2221 ins->has_inline_constant = true;
2222 ins->inline_constant = scaled_constant;
2223 }
2224 }
2225 }
2226
2227 /* Dead code elimination for branches at the end of a block - only one branch
2228 * per block is legal semantically */
2229
2230 static void
2231 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2232 {
2233 bool branched = false;
2234
2235 mir_foreach_instr_in_block_safe(block, ins) {
2236 if (!midgard_is_branch_unit(ins->unit)) continue;
2237
2238 if (branched)
2239 mir_remove_instruction(ins);
2240
2241 branched = true;
2242 }
2243 }
2244
2245 static unsigned
2246 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2247 {
2248 /* Loop to ourselves */
2249 midgard_instruction *br = ctx->writeout_branch[rt];
2250 struct midgard_instruction ins = v_branch(false, false);
2251 ins.writeout = true;
2252 ins.writeout_depth = br->writeout_depth;
2253 ins.writeout_stencil = br->writeout_stencil;
2254 ins.branch.target_block = ctx->block_count - 1;
2255 ins.constants.u32[0] = br->constants.u32[0];
2256 emit_mir_instruction(ctx, ins);
2257
2258 ctx->current_block->epilogue = true;
2259 schedule_barrier(ctx);
2260 return ins.branch.target_block;
2261 }
2262
2263 static midgard_block *
2264 emit_block(compiler_context *ctx, nir_block *block)
2265 {
2266 midgard_block *this_block = ctx->after_block;
2267 ctx->after_block = NULL;
2268
2269 if (!this_block)
2270 this_block = create_empty_block(ctx);
2271
2272 list_addtail(&this_block->base.link, &ctx->blocks);
2273
2274 this_block->scheduled = false;
2275 ++ctx->block_count;
2276
2277 /* Set up current block */
2278 list_inithead(&this_block->base.instructions);
2279 ctx->current_block = this_block;
2280
2281 nir_foreach_instr(instr, block) {
2282 emit_instr(ctx, instr);
2283 ++ctx->instruction_count;
2284 }
2285
2286 return this_block;
2287 }
2288
2289 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2290
2291 static void
2292 emit_if(struct compiler_context *ctx, nir_if *nif)
2293 {
2294 midgard_block *before_block = ctx->current_block;
2295
2296 /* Speculatively emit the branch, but we can't fill it in until later */
2297 bool inv = false;
2298 EMIT(branch, true, true);
2299 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2300 then_branch->src[0] = mir_get_branch_cond(&nif->condition, &inv);
2301 then_branch->src_types[0] = nir_type_uint32;
2302 then_branch->branch.invert_conditional = !inv;
2303
2304 /* Emit the two subblocks. */
2305 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2306 midgard_block *end_then_block = ctx->current_block;
2307
2308 /* Emit a jump from the end of the then block to the end of the else */
2309 EMIT(branch, false, false);
2310 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2311
2312 /* Emit second block, and check if it's empty */
2313
2314 int else_idx = ctx->block_count;
2315 int count_in = ctx->instruction_count;
2316 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2317 midgard_block *end_else_block = ctx->current_block;
2318 int after_else_idx = ctx->block_count;
2319
2320 /* Now that we have the subblocks emitted, fix up the branches */
2321
2322 assert(then_block);
2323 assert(else_block);
2324
2325 if (ctx->instruction_count == count_in) {
2326 /* The else block is empty, so don't emit an exit jump */
2327 mir_remove_instruction(then_exit);
2328 then_branch->branch.target_block = after_else_idx;
2329 } else {
2330 then_branch->branch.target_block = else_idx;
2331 then_exit->branch.target_block = after_else_idx;
2332 }
2333
2334 /* Wire up the successors */
2335
2336 ctx->after_block = create_empty_block(ctx);
2337
2338 pan_block_add_successor(&before_block->base, &then_block->base);
2339 pan_block_add_successor(&before_block->base, &else_block->base);
2340
2341 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2342 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2343 }
2344
2345 static void
2346 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2347 {
2348 /* Remember where we are */
2349 midgard_block *start_block = ctx->current_block;
2350
2351 /* Allocate a loop number, growing the current inner loop depth */
2352 int loop_idx = ++ctx->current_loop_depth;
2353
2354 /* Get index from before the body so we can loop back later */
2355 int start_idx = ctx->block_count;
2356
2357 /* Emit the body itself */
2358 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2359
2360 /* Branch back to loop back */
2361 struct midgard_instruction br_back = v_branch(false, false);
2362 br_back.branch.target_block = start_idx;
2363 emit_mir_instruction(ctx, br_back);
2364
2365 /* Mark down that branch in the graph. */
2366 pan_block_add_successor(&start_block->base, &loop_block->base);
2367 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2368
2369 /* Find the index of the block about to follow us (note: we don't add
2370 * one; blocks are 0-indexed so we get a fencepost problem) */
2371 int break_block_idx = ctx->block_count;
2372
2373 /* Fix up the break statements we emitted to point to the right place,
2374 * now that we can allocate a block number for them */
2375 ctx->after_block = create_empty_block(ctx);
2376
2377 mir_foreach_block_from(ctx, start_block, _block) {
2378 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2379 if (ins->type != TAG_ALU_4) continue;
2380 if (!ins->compact_branch) continue;
2381
2382 /* We found a branch -- check the type to see if we need to do anything */
2383 if (ins->branch.target_type != TARGET_BREAK) continue;
2384
2385 /* It's a break! Check if it's our break */
2386 if (ins->branch.target_break != loop_idx) continue;
2387
2388 /* Okay, cool, we're breaking out of this loop.
2389 * Rewrite from a break to a goto */
2390
2391 ins->branch.target_type = TARGET_GOTO;
2392 ins->branch.target_block = break_block_idx;
2393
2394 pan_block_add_successor(_block, &ctx->after_block->base);
2395 }
2396 }
2397
2398 /* Now that we've finished emitting the loop, free up the depth again
2399 * so we play nice with recursion amid nested loops */
2400 --ctx->current_loop_depth;
2401
2402 /* Dump loop stats */
2403 ++ctx->loop_count;
2404 }
2405
2406 static midgard_block *
2407 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2408 {
2409 midgard_block *start_block = NULL;
2410
2411 foreach_list_typed(nir_cf_node, node, node, list) {
2412 switch (node->type) {
2413 case nir_cf_node_block: {
2414 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2415
2416 if (!start_block)
2417 start_block = block;
2418
2419 break;
2420 }
2421
2422 case nir_cf_node_if:
2423 emit_if(ctx, nir_cf_node_as_if(node));
2424 break;
2425
2426 case nir_cf_node_loop:
2427 emit_loop(ctx, nir_cf_node_as_loop(node));
2428 break;
2429
2430 case nir_cf_node_function:
2431 assert(0);
2432 break;
2433 }
2434 }
2435
2436 return start_block;
2437 }
2438
2439 /* Due to lookahead, we need to report the first tag executed in the command
2440 * stream and in branch targets. An initial block might be empty, so iterate
2441 * until we find one that 'works' */
2442
2443 static unsigned
2444 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2445 {
2446 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2447
2448 mir_foreach_block_from(ctx, initial_block, _v) {
2449 midgard_block *v = (midgard_block *) _v;
2450 if (v->quadword_count) {
2451 midgard_bundle *initial_bundle =
2452 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2453
2454 return initial_bundle->tag;
2455 }
2456 }
2457
2458 /* Default to a tag 1 which will break from the shader, in case we jump
2459 * to the exit block (i.e. `return` in a compute shader) */
2460
2461 return 1;
2462 }
2463
2464 /* For each fragment writeout instruction, generate a writeout loop to
2465 * associate with it */
2466
2467 static void
2468 mir_add_writeout_loops(compiler_context *ctx)
2469 {
2470 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2471 midgard_instruction *br = ctx->writeout_branch[rt];
2472 if (!br) continue;
2473
2474 unsigned popped = br->branch.target_block;
2475 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2476 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2477 br->branch.target_type = TARGET_GOTO;
2478
2479 /* If we have more RTs, we'll need to restore back after our
2480 * loop terminates */
2481
2482 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2483 midgard_instruction uncond = v_branch(false, false);
2484 uncond.branch.target_block = popped;
2485 uncond.branch.target_type = TARGET_GOTO;
2486 emit_mir_instruction(ctx, uncond);
2487 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2488 schedule_barrier(ctx);
2489 } else {
2490 /* We're last, so we can terminate here */
2491 br->last_writeout = true;
2492 }
2493 }
2494 }
2495
2496 int
2497 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2498 {
2499 struct util_dynarray *compiled = &program->compiled;
2500
2501 midgard_debug = debug_get_option_midgard_debug();
2502
2503 /* TODO: Bound against what? */
2504 compiler_context *ctx = rzalloc(NULL, compiler_context);
2505
2506 ctx->nir = nir;
2507 ctx->stage = nir->info.stage;
2508 ctx->is_blend = is_blend;
2509 ctx->alpha_ref = program->alpha_ref;
2510 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2511 ctx->quirks = midgard_get_quirks(gpu_id);
2512
2513 /* Start off with a safe cutoff, allowing usage of all 16 work
2514 * registers. Later, we'll promote uniform reads to uniform registers
2515 * if we determine it is beneficial to do so */
2516 ctx->uniform_cutoff = 8;
2517
2518 /* Initialize at a global (not block) level hash tables */
2519
2520 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2521 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2522
2523 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2524 * (so we don't accidentally duplicate the epilogue since mesa/st has
2525 * messed with our I/O quite a bit already) */
2526
2527 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2528
2529 if (ctx->stage == MESA_SHADER_VERTEX) {
2530 NIR_PASS_V(nir, nir_lower_viewport_transform);
2531 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2532 }
2533
2534 NIR_PASS_V(nir, nir_lower_var_copies);
2535 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2536 NIR_PASS_V(nir, nir_split_var_copies);
2537 NIR_PASS_V(nir, nir_lower_var_copies);
2538 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2539 NIR_PASS_V(nir, nir_lower_var_copies);
2540 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2541
2542 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2543 NIR_PASS_V(nir, nir_lower_ssbo);
2544 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2545
2546 /* Optimisation passes */
2547
2548 optimise_nir(nir, ctx->quirks);
2549
2550 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2551 nir_print_shader(nir, stdout);
2552 }
2553
2554 /* Assign sysvals and counts, now that we're sure
2555 * (post-optimisation) */
2556
2557 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2558 program->sysval_count = ctx->sysvals.sysval_count;
2559 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2560
2561 nir_foreach_function(func, nir) {
2562 if (!func->impl)
2563 continue;
2564
2565 list_inithead(&ctx->blocks);
2566 ctx->block_count = 0;
2567 ctx->func = func;
2568 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
2569
2570 emit_cf_list(ctx, &func->impl->body);
2571 free(ctx->already_emitted);
2572 break; /* TODO: Multi-function shaders */
2573 }
2574
2575 util_dynarray_init(compiled, NULL);
2576
2577 /* Per-block lowering before opts */
2578
2579 mir_foreach_block(ctx, _block) {
2580 midgard_block *block = (midgard_block *) _block;
2581 inline_alu_constants(ctx, block);
2582 embedded_to_inline_constant(ctx, block);
2583 }
2584 /* MIR-level optimizations */
2585
2586 bool progress = false;
2587
2588 do {
2589 progress = false;
2590 progress |= midgard_opt_dead_code_eliminate(ctx);
2591
2592 mir_foreach_block(ctx, _block) {
2593 midgard_block *block = (midgard_block *) _block;
2594 progress |= midgard_opt_copy_prop(ctx, block);
2595 progress |= midgard_opt_combine_projection(ctx, block);
2596 progress |= midgard_opt_varying_projection(ctx, block);
2597 }
2598 } while (progress);
2599
2600 mir_foreach_block(ctx, _block) {
2601 midgard_block *block = (midgard_block *) _block;
2602 midgard_lower_derivatives(ctx, block);
2603 midgard_cull_dead_branch(ctx, block);
2604 }
2605
2606 if (ctx->stage == MESA_SHADER_FRAGMENT)
2607 mir_add_writeout_loops(ctx);
2608
2609 /* Analyze now that the code is known but before scheduling creates
2610 * pipeline registers which are harder to track */
2611 mir_analyze_helper_terminate(ctx);
2612 mir_analyze_helper_requirements(ctx);
2613
2614 /* Schedule! */
2615 midgard_schedule_program(ctx);
2616 mir_ra(ctx);
2617
2618 /* Now that all the bundles are scheduled and we can calculate block
2619 * sizes, emit actual branch instructions rather than placeholders */
2620
2621 int br_block_idx = 0;
2622
2623 mir_foreach_block(ctx, _block) {
2624 midgard_block *block = (midgard_block *) _block;
2625 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2626 for (int c = 0; c < bundle->instruction_count; ++c) {
2627 midgard_instruction *ins = bundle->instructions[c];
2628
2629 if (!midgard_is_branch_unit(ins->unit)) continue;
2630
2631 /* Parse some basic branch info */
2632 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2633 bool is_conditional = ins->branch.conditional;
2634 bool is_inverted = ins->branch.invert_conditional;
2635 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2636 bool is_writeout = ins->writeout;
2637
2638 /* Determine the block we're jumping to */
2639 int target_number = ins->branch.target_block;
2640
2641 /* Report the destination tag */
2642 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2643
2644 /* Count up the number of quadwords we're
2645 * jumping over = number of quadwords until
2646 * (br_block_idx, target_number) */
2647
2648 int quadword_offset = 0;
2649
2650 if (is_discard) {
2651 /* Ignored */
2652 } else if (target_number > br_block_idx) {
2653 /* Jump forward */
2654
2655 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2656 midgard_block *blk = mir_get_block(ctx, idx);
2657 assert(blk);
2658
2659 quadword_offset += blk->quadword_count;
2660 }
2661 } else {
2662 /* Jump backwards */
2663
2664 for (int idx = br_block_idx; idx >= target_number; --idx) {
2665 midgard_block *blk = mir_get_block(ctx, idx);
2666 assert(blk);
2667
2668 quadword_offset -= blk->quadword_count;
2669 }
2670 }
2671
2672 /* Unconditional extended branches (far jumps)
2673 * have issues, so we always use a conditional
2674 * branch, setting the condition to always for
2675 * unconditional. For compact unconditional
2676 * branches, cond isn't used so it doesn't
2677 * matter what we pick. */
2678
2679 midgard_condition cond =
2680 !is_conditional ? midgard_condition_always :
2681 is_inverted ? midgard_condition_false :
2682 midgard_condition_true;
2683
2684 midgard_jmp_writeout_op op =
2685 is_discard ? midgard_jmp_writeout_op_discard :
2686 is_writeout ? midgard_jmp_writeout_op_writeout :
2687 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2688 midgard_jmp_writeout_op_branch_cond;
2689
2690 if (!is_compact) {
2691 midgard_branch_extended branch =
2692 midgard_create_branch_extended(
2693 cond, op,
2694 dest_tag,
2695 quadword_offset);
2696
2697 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2698 } else if (is_conditional || is_discard) {
2699 midgard_branch_cond branch = {
2700 .op = op,
2701 .dest_tag = dest_tag,
2702 .offset = quadword_offset,
2703 .cond = cond
2704 };
2705
2706 assert(branch.offset == quadword_offset);
2707
2708 memcpy(&ins->br_compact, &branch, sizeof(branch));
2709 } else {
2710 assert(op == midgard_jmp_writeout_op_branch_uncond);
2711
2712 midgard_branch_uncond branch = {
2713 .op = op,
2714 .dest_tag = dest_tag,
2715 .offset = quadword_offset,
2716 .unknown = 1
2717 };
2718
2719 assert(branch.offset == quadword_offset);
2720
2721 memcpy(&ins->br_compact, &branch, sizeof(branch));
2722 }
2723 }
2724 }
2725
2726 ++br_block_idx;
2727 }
2728
2729 /* Emit flat binary from the instruction arrays. Iterate each block in
2730 * sequence. Save instruction boundaries such that lookahead tags can
2731 * be assigned easily */
2732
2733 /* Cache _all_ bundles in source order for lookahead across failed branches */
2734
2735 int bundle_count = 0;
2736 mir_foreach_block(ctx, _block) {
2737 midgard_block *block = (midgard_block *) _block;
2738 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2739 }
2740 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2741 int bundle_idx = 0;
2742 mir_foreach_block(ctx, _block) {
2743 midgard_block *block = (midgard_block *) _block;
2744 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2745 source_order_bundles[bundle_idx++] = bundle;
2746 }
2747 }
2748
2749 int current_bundle = 0;
2750
2751 /* Midgard prefetches instruction types, so during emission we
2752 * need to lookahead. Unless this is the last instruction, in
2753 * which we return 1. */
2754
2755 mir_foreach_block(ctx, _block) {
2756 midgard_block *block = (midgard_block *) _block;
2757 mir_foreach_bundle_in_block(block, bundle) {
2758 int lookahead = 1;
2759
2760 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2761 lookahead = source_order_bundles[current_bundle + 1]->tag;
2762
2763 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2764 ++current_bundle;
2765 }
2766
2767 /* TODO: Free deeper */
2768 //util_dynarray_fini(&block->instructions);
2769 }
2770
2771 free(source_order_bundles);
2772
2773 /* Report the very first tag executed */
2774 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2775
2776 /* Deal with off-by-one related to the fencepost problem */
2777 program->work_register_count = ctx->work_registers + 1;
2778 program->uniform_cutoff = ctx->uniform_cutoff;
2779
2780 program->blend_patch_offset = ctx->blend_constant_offset;
2781 program->tls_size = ctx->tls_size;
2782
2783 if (midgard_debug & MIDGARD_DBG_SHADERS)
2784 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2785
2786 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2787 unsigned nr_bundles = 0, nr_ins = 0;
2788
2789 /* Count instructions and bundles */
2790
2791 mir_foreach_block(ctx, _block) {
2792 midgard_block *block = (midgard_block *) _block;
2793 nr_bundles += util_dynarray_num_elements(
2794 &block->bundles, midgard_bundle);
2795
2796 mir_foreach_bundle_in_block(block, bun)
2797 nr_ins += bun->instruction_count;
2798 }
2799
2800 /* Calculate thread count. There are certain cutoffs by
2801 * register count for thread count */
2802
2803 unsigned nr_registers = program->work_register_count;
2804
2805 unsigned nr_threads =
2806 (nr_registers <= 4) ? 4 :
2807 (nr_registers <= 8) ? 2 :
2808 1;
2809
2810 /* Dump stats */
2811
2812 fprintf(stderr, "shader%d - %s shader: "
2813 "%u inst, %u bundles, %u quadwords, "
2814 "%u registers, %u threads, %u loops, "
2815 "%u:%u spills:fills\n",
2816 SHADER_DB_COUNT++,
2817 gl_shader_stage_name(ctx->stage),
2818 nr_ins, nr_bundles, ctx->quadword_count,
2819 nr_registers, nr_threads,
2820 ctx->loop_count,
2821 ctx->spills, ctx->fills);
2822 }
2823
2824 ralloc_free(ctx);
2825
2826 return 0;
2827 }