2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
50 #include "midgard_quirks.h"
51 #include "panfrost-quirks.h"
52 #include "panfrost/util/pan_lower_framebuffer.h"
54 #include "disassemble.h"
56 static const struct debug_named_value debug_options
[] = {
57 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
58 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
59 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
63 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
65 unsigned SHADER_DB_COUNT
= 0;
67 int midgard_debug
= 0;
69 #define DBG(fmt, ...) \
70 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
71 fprintf(stderr, "%s:%d: "fmt, \
72 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
73 static midgard_block
*
74 create_empty_block(compiler_context
*ctx
)
76 midgard_block
*blk
= rzalloc(ctx
, midgard_block
);
78 blk
->base
.predecessors
= _mesa_set_create(blk
,
80 _mesa_key_pointer_equal
);
82 blk
->base
.name
= ctx
->block_source_count
++;
88 schedule_barrier(compiler_context
*ctx
)
90 midgard_block
*temp
= ctx
->after_block
;
91 ctx
->after_block
= create_empty_block(ctx
);
93 list_addtail(&ctx
->after_block
->base
.link
, &ctx
->blocks
);
94 list_inithead(&ctx
->after_block
->base
.instructions
);
95 pan_block_add_successor(&ctx
->current_block
->base
, &ctx
->after_block
->base
);
96 ctx
->current_block
= ctx
->after_block
;
97 ctx
->after_block
= temp
;
100 /* Helpers to generate midgard_instruction's using macro magic, since every
101 * driver seems to do it that way */
103 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
105 #define M_LOAD_STORE(name, store, T) \
106 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
107 midgard_instruction i = { \
108 .type = TAG_LOAD_STORE_4, \
111 .src = { ~0, ~0, ~0, ~0 }, \
112 .swizzle = SWIZZLE_IDENTITY_4, \
114 .op = midgard_op_##name, \
121 i.src_types[0] = T; \
130 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
131 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
133 M_LOAD(ld_attr_32
, nir_type_uint32
);
134 M_LOAD(ld_vary_32
, nir_type_uint32
);
135 M_LOAD(ld_ubo_int4
, nir_type_uint32
);
136 M_LOAD(ld_int4
, nir_type_uint32
);
137 M_STORE(st_int4
, nir_type_uint32
);
138 M_LOAD(ld_color_buffer_32u
, nir_type_uint32
);
139 M_LOAD(ld_color_buffer_as_fp16
, nir_type_float16
);
140 M_LOAD(ld_color_buffer_as_fp32
, nir_type_float32
);
141 M_STORE(st_vary_32
, nir_type_uint32
);
142 M_LOAD(ld_cubemap_coords
, nir_type_uint32
);
143 M_LOAD(ld_compute_id
, nir_type_uint32
);
145 static midgard_instruction
146 v_branch(bool conditional
, bool invert
)
148 midgard_instruction ins
= {
150 .unit
= ALU_ENAB_BRANCH
,
151 .compact_branch
= true,
153 .conditional
= conditional
,
154 .invert_conditional
= invert
157 .src
= { ~0, ~0, ~0, ~0 },
163 static midgard_branch_extended
164 midgard_create_branch_extended( midgard_condition cond
,
165 midgard_jmp_writeout_op op
,
167 signed quadword_offset
)
169 /* The condition code is actually a LUT describing a function to
170 * combine multiple condition codes. However, we only support a single
171 * condition code at the moment, so we just duplicate over a bunch of
174 uint16_t duplicated_cond
=
184 midgard_branch_extended branch
= {
186 .dest_tag
= dest_tag
,
187 .offset
= quadword_offset
,
188 .cond
= duplicated_cond
195 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
197 ins
->has_constants
= true;
198 memcpy(&ins
->constants
, constants
, 16);
202 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
204 return glsl_count_attribute_slots(type
, false);
207 /* Lower fdot2 to a vector multiplication followed by channel addition */
209 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
211 if (alu
->op
!= nir_op_fdot2
)
214 b
->cursor
= nir_before_instr(&alu
->instr
);
216 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
217 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
219 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
221 nir_ssa_def
*sum
= nir_fadd(b
,
222 nir_channel(b
, product
, 0),
223 nir_channel(b
, product
, 1));
225 /* Replace the fdot2 with this sum */
226 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
230 midgard_nir_lower_fdot2(nir_shader
*shader
)
232 bool progress
= false;
234 nir_foreach_function(function
, shader
) {
235 if (!function
->impl
) continue;
238 nir_builder
*b
= &_b
;
239 nir_builder_init(b
, function
->impl
);
241 nir_foreach_block(block
, function
->impl
) {
242 nir_foreach_instr_safe(instr
, block
) {
243 if (instr
->type
!= nir_instr_type_alu
) continue;
245 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
246 midgard_nir_lower_fdot2_body(b
, alu
);
252 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
259 static const nir_variable
*
260 search_var(struct exec_list
*vars
, unsigned driver_loc
)
262 nir_foreach_variable(var
, vars
) {
263 if (var
->data
.driver_location
== driver_loc
)
270 /* Midgard can write all of color, depth and stencil in a single writeout
271 * operation, so we merge depth/stencil stores with color stores.
272 * If there are no color stores, we add a write to the "depth RT".
275 midgard_nir_lower_zs_store(nir_shader
*nir
)
277 if (nir
->info
.stage
!= MESA_SHADER_FRAGMENT
)
280 nir_variable
*z_var
= NULL
, *s_var
= NULL
;
282 nir_foreach_variable(var
, &nir
->outputs
) {
283 if (var
->data
.location
== FRAG_RESULT_DEPTH
)
285 else if (var
->data
.location
== FRAG_RESULT_STENCIL
)
289 if (!z_var
&& !s_var
)
292 bool progress
= false;
294 nir_foreach_function(function
, nir
) {
295 if (!function
->impl
) continue;
297 nir_intrinsic_instr
*z_store
= NULL
, *s_store
= NULL
;
299 nir_foreach_block(block
, function
->impl
) {
300 nir_foreach_instr_safe(instr
, block
) {
301 if (instr
->type
!= nir_instr_type_intrinsic
)
304 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
305 if (intr
->intrinsic
!= nir_intrinsic_store_output
)
308 if (z_var
&& nir_intrinsic_base(intr
) == z_var
->data
.driver_location
) {
313 if (s_var
&& nir_intrinsic_base(intr
) == s_var
->data
.driver_location
) {
320 if (!z_store
&& !s_store
) continue;
322 bool replaced
= false;
324 nir_foreach_block(block
, function
->impl
) {
325 nir_foreach_instr_safe(instr
, block
) {
326 if (instr
->type
!= nir_instr_type_intrinsic
)
329 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
330 if (intr
->intrinsic
!= nir_intrinsic_store_output
)
333 const nir_variable
*var
= search_var(&nir
->outputs
, nir_intrinsic_base(intr
));
336 if (var
->data
.location
!= FRAG_RESULT_COLOR
&&
337 var
->data
.location
< FRAG_RESULT_DATA0
)
340 assert(nir_src_is_const(intr
->src
[1]) && "no indirect outputs");
343 nir_builder_init(&b
, function
->impl
);
345 assert(!z_store
|| z_store
->instr
.block
== instr
->block
);
346 assert(!s_store
|| s_store
->instr
.block
== instr
->block
);
347 b
.cursor
= nir_after_block_before_jump(instr
->block
);
349 nir_intrinsic_instr
*combined_store
;
350 combined_store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_combined_output_pan
);
352 combined_store
->num_components
= intr
->src
[0].ssa
->num_components
;
354 nir_intrinsic_set_base(combined_store
, nir_intrinsic_base(intr
));
356 unsigned writeout
= PAN_WRITEOUT_C
;
358 writeout
|= PAN_WRITEOUT_Z
;
360 writeout
|= PAN_WRITEOUT_S
;
362 nir_intrinsic_set_component(combined_store
, writeout
);
364 struct nir_ssa_def
*zero
= nir_imm_int(&b
, 0);
366 struct nir_ssa_def
*src
[4] = {
369 z_store
? z_store
->src
[0].ssa
: zero
,
370 s_store
? s_store
->src
[0].ssa
: zero
,
373 for (int i
= 0; i
< 4; ++i
)
374 combined_store
->src
[i
] = nir_src_for_ssa(src
[i
]);
376 nir_builder_instr_insert(&b
, &combined_store
->instr
);
378 nir_instr_remove(instr
);
384 /* Insert a store to the depth RT (0xff) if needed */
387 nir_builder_init(&b
, function
->impl
);
389 nir_block
*block
= NULL
;
390 if (z_store
&& s_store
)
391 assert(z_store
->instr
.block
== s_store
->instr
.block
);
394 block
= z_store
->instr
.block
;
396 block
= s_store
->instr
.block
;
398 b
.cursor
= nir_after_block_before_jump(block
);
400 nir_intrinsic_instr
*combined_store
;
401 combined_store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_combined_output_pan
);
403 combined_store
->num_components
= 4;
407 base
= nir_intrinsic_base(z_store
);
409 base
= nir_intrinsic_base(s_store
);
410 nir_intrinsic_set_base(combined_store
, base
);
412 unsigned writeout
= 0;
414 writeout
|= PAN_WRITEOUT_Z
;
416 writeout
|= PAN_WRITEOUT_S
;
418 nir_intrinsic_set_component(combined_store
, writeout
);
420 struct nir_ssa_def
*zero
= nir_imm_int(&b
, 0);
422 struct nir_ssa_def
*src
[4] = {
423 nir_imm_vec4(&b
, 0, 0, 0, 0),
425 z_store
? z_store
->src
[0].ssa
: zero
,
426 s_store
? s_store
->src
[0].ssa
: zero
,
429 for (int i
= 0; i
< 4; ++i
)
430 combined_store
->src
[i
] = nir_src_for_ssa(src
[i
]);
432 nir_builder_instr_insert(&b
, &combined_store
->instr
);
436 nir_instr_remove(&z_store
->instr
);
439 nir_instr_remove(&s_store
->instr
);
441 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
448 /* Flushes undefined values to zero */
451 optimise_nir(nir_shader
*nir
, unsigned quirks
, bool is_blend
)
454 unsigned lower_flrp
=
455 (nir
->options
->lower_flrp16
? 16 : 0) |
456 (nir
->options
->lower_flrp32
? 32 : 0) |
457 (nir
->options
->lower_flrp64
? 64 : 0);
459 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
460 NIR_PASS(progress
, nir
, nir_lower_idiv
, nir_lower_idiv_fast
);
462 nir_lower_tex_options lower_tex_options
= {
463 .lower_txs_lod
= true,
465 .lower_tex_without_implicit_lod
=
466 (quirks
& MIDGARD_EXPLICIT_LOD
),
468 /* TODO: we have native gradient.. */
472 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
474 /* Must lower fdot2 after tex is lowered */
475 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
477 /* T720 is broken. */
479 if (quirks
& MIDGARD_BROKEN_LOD
)
480 NIR_PASS_V(nir
, midgard_nir_lod_errata
);
482 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_early
);
487 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
488 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
490 NIR_PASS(progress
, nir
, nir_copy_prop
);
491 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
492 NIR_PASS(progress
, nir
, nir_opt_dce
);
493 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
494 NIR_PASS(progress
, nir
, nir_opt_cse
);
495 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
496 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
497 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
499 if (lower_flrp
!= 0) {
500 bool lower_flrp_progress
= false;
501 NIR_PASS(lower_flrp_progress
,
505 false /* always_precise */,
506 nir
->options
->lower_ffma
);
507 if (lower_flrp_progress
) {
508 NIR_PASS(progress
, nir
,
509 nir_opt_constant_folding
);
513 /* Nothing should rematerialize any flrps, so we only
514 * need to do this lowering once.
519 NIR_PASS(progress
, nir
, nir_opt_undef
);
520 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
522 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
525 nir_var_function_temp
);
527 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
530 /* Run after opts so it can hit more */
532 NIR_PASS(progress
, nir
, nir_fuse_io_16
);
534 /* Must be run at the end to prevent creation of fsin/fcos ops */
535 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
540 NIR_PASS(progress
, nir
, nir_opt_dce
);
541 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
542 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
543 NIR_PASS(progress
, nir
, nir_copy_prop
);
546 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
547 NIR_PASS(progress
, nir
, nir_opt_algebraic_distribute_src_mods
);
549 /* We implement booleans as 32-bit 0/~0 */
550 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
552 /* Now that booleans are lowered, we can run out late opts */
553 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
554 NIR_PASS(progress
, nir
, midgard_nir_cancel_inot
);
556 NIR_PASS(progress
, nir
, nir_copy_prop
);
557 NIR_PASS(progress
, nir
, nir_opt_dce
);
559 /* Take us out of SSA */
560 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
561 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
563 /* We are a vector architecture; write combine where possible */
564 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
565 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
567 NIR_PASS(progress
, nir
, nir_opt_dce
);
570 /* Do not actually emit a load; instead, cache the constant for inlining */
573 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
575 nir_ssa_def def
= instr
->def
;
577 midgard_constants
*consts
= rzalloc(NULL
, midgard_constants
);
579 assert(instr
->def
.num_components
* instr
->def
.bit_size
<= sizeof(*consts
) * 8);
581 #define RAW_CONST_COPY(bits) \
582 nir_const_value_to_array(consts->u##bits, instr->value, \
583 instr->def.num_components, u##bits)
585 switch (instr
->def
.bit_size
) {
599 unreachable("Invalid bit_size for load_const instruction\n");
602 /* Shifted for SSA, +1 for off-by-one */
603 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (def
.index
<< 1) + 1, consts
);
606 /* Normally constants are embedded implicitly, but for I/O and such we have to
607 * explicitly emit a move with the constant source */
610 emit_explicit_constant(compiler_context
*ctx
, unsigned node
, unsigned to
)
612 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, node
+ 1);
614 if (constant_value
) {
615 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), to
);
616 attach_constants(ctx
, &ins
, constant_value
, node
+ 1);
617 emit_mir_instruction(ctx
, ins
);
622 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
624 unsigned comp
= src
->swizzle
[0];
626 for (unsigned c
= 1; c
< nr_components
; ++c
) {
627 if (src
->swizzle
[c
] != comp
)
634 #define ALU_CASE(nir, _op) \
636 op = midgard_alu_op_##_op; \
637 assert(src_bitsize == dst_bitsize); \
640 #define ALU_CASE_RTZ(nir, _op) \
642 op = midgard_alu_op_##_op; \
643 roundmode = MIDGARD_RTZ; \
646 #define ALU_CHECK_CMP(sext) \
647 assert(src_bitsize == 16 || src_bitsize == 32); \
648 assert(dst_bitsize == 16 || dst_bitsize == 32); \
650 #define ALU_CASE_BCAST(nir, _op, count) \
652 op = midgard_alu_op_##_op; \
653 broadcast_swizzle = count; \
654 ALU_CHECK_CMP(true); \
657 #define ALU_CASE_CMP(nir, _op, sext) \
659 op = midgard_alu_op_##_op; \
660 ALU_CHECK_CMP(sext); \
663 /* Analyze the sizes of the dest and inputs to determine reg mode. */
665 static midgard_reg_mode
666 reg_mode_for_nir(nir_alu_instr
*instr
)
668 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
669 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
670 unsigned max_bitsize
= MAX2(src_bitsize
, dst_bitsize
);
672 /* We don't have fp16 LUTs, so we'll want to emit code like:
674 * vlut.fsinr hr0, hr0
676 * where both input and output are 16-bit but the operation is carried
688 max_bitsize
= MAX2(max_bitsize
, 32);
691 /* These get lowered to moves */
692 case nir_op_pack_32_4x8
:
695 case nir_op_pack_32_2x16
:
703 switch (max_bitsize
) {
704 /* Use 16 pipe for 8 since we don't support vec16 yet */
707 return midgard_reg_mode_16
;
709 return midgard_reg_mode_32
;
711 return midgard_reg_mode_64
;
713 unreachable("Invalid bit size");
717 /* Compare mir_lower_invert */
719 nir_accepts_inot(nir_op op
, unsigned src
)
723 case nir_op_iand
: /* TODO: b2f16 */
727 /* Only the condition */
735 mir_accept_dest_mod(compiler_context
*ctx
, nir_dest
**dest
, nir_op op
)
737 if (pan_has_dest_mod(dest
, op
)) {
738 assert((*dest
)->is_ssa
);
739 BITSET_SET(ctx
->already_emitted
, (*dest
)->ssa
.index
);
747 mir_copy_src(midgard_instruction
*ins
, nir_alu_instr
*instr
, unsigned i
, unsigned to
, bool *abs
, bool *neg
, bool *not, enum midgard_roundmode
*roundmode
, bool is_int
, unsigned bcast_count
)
749 nir_alu_src src
= instr
->src
[i
];
752 if (pan_has_source_mod(&src
, nir_op_fneg
))
755 if (pan_has_source_mod(&src
, nir_op_fabs
))
759 if (nir_accepts_inot(instr
->op
, i
) && pan_has_source_mod(&src
, nir_op_inot
))
763 if (pan_has_source_mod(&src
, nir_op_fround_even
))
764 *roundmode
= MIDGARD_RTE
;
766 if (pan_has_source_mod(&src
, nir_op_ftrunc
))
767 *roundmode
= MIDGARD_RTZ
;
769 if (pan_has_source_mod(&src
, nir_op_ffloor
))
770 *roundmode
= MIDGARD_RTN
;
772 if (pan_has_source_mod(&src
, nir_op_fceil
))
773 *roundmode
= MIDGARD_RTP
;
776 unsigned bits
= nir_src_bit_size(src
.src
);
778 ins
->src
[to
] = nir_src_index(NULL
, &src
.src
);
779 ins
->src_types
[to
] = nir_op_infos
[instr
->op
].input_types
[i
] | bits
;
781 for (unsigned c
= 0; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
782 ins
->swizzle
[to
][c
] = src
.swizzle
[
783 (!bcast_count
|| c
< bcast_count
) ? c
:
788 /* Midgard features both fcsel and icsel, depending on whether you want int or
789 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
790 * we should emit an int or float csel depending on what modifiers could be
791 * placed. In the absense of modifiers, this is probably arbitrary. */
794 mir_is_bcsel_float(nir_alu_instr
*instr
)
797 nir_op_i2i8
, nir_op_i2i16
,
798 nir_op_i2i32
, nir_op_i2i64
801 nir_op floatmods
[] = {
802 nir_op_fabs
, nir_op_fneg
,
803 nir_op_f2f16
, nir_op_f2f32
,
807 nir_op floatdestmods
[] = {
808 nir_op_fsat
, nir_op_fsat_signed
, nir_op_fclamp_pos
,
809 nir_op_f2f16
, nir_op_f2f32
814 for (unsigned i
= 1; i
< 3; ++i
) {
815 nir_alu_src s
= instr
->src
[i
];
816 for (unsigned q
= 0; q
< ARRAY_SIZE(intmods
); ++q
) {
817 if (pan_has_source_mod(&s
, intmods
[q
]))
822 for (unsigned i
= 1; i
< 3; ++i
) {
823 nir_alu_src s
= instr
->src
[i
];
824 for (unsigned q
= 0; q
< ARRAY_SIZE(floatmods
); ++q
) {
825 if (pan_has_source_mod(&s
, floatmods
[q
]))
830 for (unsigned q
= 0; q
< ARRAY_SIZE(floatdestmods
); ++q
) {
831 nir_dest
*dest
= &instr
->dest
.dest
;
832 if (pan_has_dest_mod(&dest
, floatdestmods
[q
]))
840 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
842 nir_dest
*dest
= &instr
->dest
.dest
;
844 if (dest
->is_ssa
&& BITSET_TEST(ctx
->already_emitted
, dest
->ssa
.index
))
847 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
848 * is handled elsewhere */
850 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddy
) {
851 midgard_emit_derivatives(ctx
, instr
);
855 bool is_ssa
= dest
->is_ssa
;
857 unsigned nr_components
= nir_dest_num_components(*dest
);
858 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
861 /* Number of components valid to check for the instruction (the rest
862 * will be forced to the last), or 0 to use as-is. Relevant as
863 * ball-type instructions have a channel count in NIR but are all vec4
866 unsigned broadcast_swizzle
= 0;
868 /* What register mode should we operate in? */
869 midgard_reg_mode reg_mode
=
870 reg_mode_for_nir(instr
);
872 /* Should we swap arguments? */
873 bool flip_src12
= false;
875 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
876 unsigned dst_bitsize
= nir_dest_bit_size(*dest
);
878 enum midgard_roundmode roundmode
= MIDGARD_RTE
;
881 ALU_CASE(fadd
, fadd
);
882 ALU_CASE(fmul
, fmul
);
883 ALU_CASE(fmin
, fmin
);
884 ALU_CASE(fmax
, fmax
);
885 ALU_CASE(imin
, imin
);
886 ALU_CASE(imax
, imax
);
887 ALU_CASE(umin
, umin
);
888 ALU_CASE(umax
, umax
);
889 ALU_CASE(ffloor
, ffloor
);
890 ALU_CASE(fround_even
, froundeven
);
891 ALU_CASE(ftrunc
, ftrunc
);
892 ALU_CASE(fceil
, fceil
);
893 ALU_CASE(fdot3
, fdot3
);
894 ALU_CASE(fdot4
, fdot4
);
895 ALU_CASE(iadd
, iadd
);
896 ALU_CASE(isub
, isub
);
897 ALU_CASE(imul
, imul
);
899 /* Zero shoved as second-arg */
900 ALU_CASE(iabs
, iabsdiff
);
904 ALU_CASE_CMP(feq32
, feq
, false);
905 ALU_CASE_CMP(fne32
, fne
, false);
906 ALU_CASE_CMP(flt32
, flt
, false);
907 ALU_CASE_CMP(ieq32
, ieq
, true);
908 ALU_CASE_CMP(ine32
, ine
, true);
909 ALU_CASE_CMP(ilt32
, ilt
, true);
910 ALU_CASE_CMP(ult32
, ult
, false);
912 /* We don't have a native b2f32 instruction. Instead, like many
913 * GPUs, we exploit booleans as 0/~0 for false/true, and
914 * correspondingly AND
915 * by 1.0 to do the type conversion. For the moment, prime us
918 * iand [whatever], #0
920 * At the end of emit_alu (as MIR), we'll fix-up the constant
923 ALU_CASE_CMP(b2f32
, iand
, true);
924 ALU_CASE_CMP(b2f16
, iand
, true);
925 ALU_CASE_CMP(b2i32
, iand
, true);
927 /* Likewise, we don't have a dedicated f2b32 instruction, but
928 * we can do a "not equal to 0.0" test. */
930 ALU_CASE_CMP(f2b32
, fne
, false);
931 ALU_CASE_CMP(i2b32
, ine
, true);
933 ALU_CASE(frcp
, frcp
);
934 ALU_CASE(frsq
, frsqrt
);
935 ALU_CASE(fsqrt
, fsqrt
);
936 ALU_CASE(fexp2
, fexp2
);
937 ALU_CASE(flog2
, flog2
);
939 ALU_CASE_RTZ(f2i64
, f2i_rte
);
940 ALU_CASE_RTZ(f2u64
, f2u_rte
);
941 ALU_CASE_RTZ(i2f64
, i2f_rte
);
942 ALU_CASE_RTZ(u2f64
, u2f_rte
);
944 ALU_CASE_RTZ(f2i32
, f2i_rte
);
945 ALU_CASE_RTZ(f2u32
, f2u_rte
);
946 ALU_CASE_RTZ(i2f32
, i2f_rte
);
947 ALU_CASE_RTZ(u2f32
, u2f_rte
);
949 ALU_CASE_RTZ(f2i8
, f2i_rte
);
950 ALU_CASE_RTZ(f2u8
, f2u_rte
);
952 ALU_CASE_RTZ(f2i16
, f2i_rte
);
953 ALU_CASE_RTZ(f2u16
, f2u_rte
);
954 ALU_CASE_RTZ(i2f16
, i2f_rte
);
955 ALU_CASE_RTZ(u2f16
, u2f_rte
);
957 ALU_CASE(fsin
, fsin
);
958 ALU_CASE(fcos
, fcos
);
960 /* We'll get 0 in the second arg, so:
961 * ~a = ~(a | 0) = nor(a, 0) */
962 ALU_CASE(inot
, inor
);
963 ALU_CASE(iand
, iand
);
965 ALU_CASE(ixor
, ixor
);
966 ALU_CASE(ishl
, ishl
);
967 ALU_CASE(ishr
, iasr
);
968 ALU_CASE(ushr
, ilsr
);
970 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
971 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
972 ALU_CASE_CMP(b32all_fequal4
, fball_eq
, true);
974 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
975 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
976 ALU_CASE_CMP(b32any_fnequal4
, fbany_neq
, true);
978 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
979 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
980 ALU_CASE_CMP(b32all_iequal4
, iball_eq
, true);
982 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
983 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
984 ALU_CASE_CMP(b32any_inequal4
, ibany_neq
, true);
986 /* Source mods will be shoved in later */
987 ALU_CASE(fabs
, fmov
);
988 ALU_CASE(fneg
, fmov
);
989 ALU_CASE(fsat
, fmov
);
990 ALU_CASE(fsat_signed
, fmov
);
991 ALU_CASE(fclamp_pos
, fmov
);
993 /* For size conversion, we use a move. Ideally though we would squash
994 * these ops together; maybe that has to happen after in NIR as part of
995 * propagation...? An earlier algebraic pass ensured we step down by
996 * only / exactly one size. If stepping down, we use a dest override to
997 * reduce the size; if stepping up, we use a larger-sized move with a
998 * half source and a sign/zero-extension modifier */
1010 case nir_op_f2f64
: {
1011 if (instr
->op
== nir_op_f2f16
|| instr
->op
== nir_op_f2f32
||
1012 instr
->op
== nir_op_f2f64
)
1013 op
= midgard_alu_op_fmov
;
1015 op
= midgard_alu_op_imov
;
1020 /* For greater-or-equal, we lower to less-or-equal and flip the
1026 case nir_op_uge32
: {
1028 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
1029 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
1030 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
1031 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
1035 ALU_CHECK_CMP(false);
1039 case nir_op_b32csel
: {
1040 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
1041 bool is_float
= mir_is_bcsel_float(instr
);
1043 (mixed
? midgard_alu_op_fcsel_v
: midgard_alu_op_fcsel
) :
1044 (mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
);
1049 case nir_op_unpack_32_2x16
:
1050 case nir_op_unpack_32_4x8
:
1051 case nir_op_pack_32_2x16
:
1052 case nir_op_pack_32_4x8
: {
1053 op
= midgard_alu_op_imov
;
1058 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1063 /* Promote imov to fmov if it might help inline a constant */
1064 if (op
== midgard_alu_op_imov
&& nir_src_is_const(instr
->src
[0].src
)
1065 && nir_src_bit_size(instr
->src
[0].src
) == 32
1066 && nir_is_same_comp_swizzle(instr
->src
[0].swizzle
,
1067 nir_src_num_components(instr
->src
[0].src
))) {
1068 op
= midgard_alu_op_fmov
;
1071 /* Midgard can perform certain modifiers on output of an ALU op */
1073 unsigned outmod
= 0;
1074 bool is_int
= midgard_is_integer_op(op
);
1076 if (midgard_is_integer_out_op(op
)) {
1077 outmod
= midgard_outmod_int_wrap
;
1078 } else if (instr
->op
== nir_op_fsat
) {
1079 outmod
= midgard_outmod_sat
;
1080 } else if (instr
->op
== nir_op_fsat_signed
) {
1081 outmod
= midgard_outmod_sat_signed
;
1082 } else if (instr
->op
== nir_op_fclamp_pos
) {
1083 outmod
= midgard_outmod_pos
;
1086 /* Fetch unit, quirks, etc information */
1087 unsigned opcode_props
= alu_opcode_props
[op
].props
;
1088 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1090 /* Look for floating point mods. We have the mods fsat, fsat_signed,
1091 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
1093 * fsat_signed(fpos(x)) = fsat(x)
1094 * fsat_signed(fsat(x)) = fsat(x)
1095 * fpos(fsat_signed(x)) = fsat(x)
1096 * fpos(fsat(x)) = fsat(x)
1097 * fsat(fsat_signed(x)) = fsat(x)
1098 * fsat(fpos(x)) = fsat(x)
1100 * So by cases any composition of output modifiers is equivalent to
1104 if (!midgard_is_integer_out_op(op
)) {
1105 bool fpos
= mir_accept_dest_mod(ctx
, &dest
, nir_op_fclamp_pos
);
1106 bool fsat
= mir_accept_dest_mod(ctx
, &dest
, nir_op_fsat
);
1107 bool ssat
= mir_accept_dest_mod(ctx
, &dest
, nir_op_fsat_signed
);
1108 bool prior
= (outmod
!= midgard_outmod_none
);
1109 int count
= (int) prior
+ (int) fpos
+ (int) ssat
+ (int) fsat
;
1111 outmod
= ((count
> 1) || fsat
) ? midgard_outmod_sat
:
1112 fpos
? midgard_outmod_pos
:
1113 ssat
? midgard_outmod_sat_signed
:
1117 midgard_instruction ins
= {
1119 .dest
= nir_dest_index(dest
),
1120 .dest_type
= nir_op_infos
[instr
->op
].output_type
1121 | nir_dest_bit_size(*dest
),
1122 .roundmode
= roundmode
,
1125 enum midgard_roundmode
*roundptr
= (opcode_props
& MIDGARD_ROUNDS
) ?
1126 &ins
.roundmode
: NULL
;
1128 for (unsigned i
= nr_inputs
; i
< ARRAY_SIZE(ins
.src
); ++i
)
1131 if (quirk_flipped_r24
) {
1133 mir_copy_src(&ins
, instr
, 0, 1, &ins
.src_abs
[1], &ins
.src_neg
[1], &ins
.src_invert
[1], roundptr
, is_int
, broadcast_swizzle
);
1135 for (unsigned i
= 0; i
< nr_inputs
; ++i
) {
1138 if (instr
->op
== nir_op_b32csel
) {
1139 /* The condition is the first argument; move
1140 * the other arguments up one to be a binary
1141 * instruction for Midgard with the condition
1146 else if (flip_src12
)
1150 } else if (flip_src12
) {
1154 mir_copy_src(&ins
, instr
, i
, to
, &ins
.src_abs
[to
], &ins
.src_neg
[to
], &ins
.src_invert
[to
], roundptr
, is_int
, broadcast_swizzle
);
1156 /* (!c) ? a : b = c ? b : a */
1157 if (instr
->op
== nir_op_b32csel
&& ins
.src_invert
[2]) {
1158 ins
.src_invert
[2] = false;
1164 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
1165 /* Lowered to move */
1166 if (instr
->op
== nir_op_fneg
)
1167 ins
.src_neg
[1] ^= true;
1169 if (instr
->op
== nir_op_fabs
)
1170 ins
.src_abs
[1] = true;
1173 ins
.mask
= mask_of(nr_components
);
1175 midgard_vector_alu alu
= {
1177 .reg_mode
= reg_mode
,
1181 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1182 * components that don't exist. Note modifier => SSA => !reg => no
1183 * writemask, so we don't have to worry about writemasks here.*/
1186 ins
.mask
&= instr
->dest
.write_mask
;
1190 /* Late fixup for emulated instructions */
1192 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1193 /* Presently, our second argument is an inline #0 constant.
1194 * Switch over to an embedded 1.0 constant (that can't fit
1195 * inline, since we're 32-bit, not 16-bit like the inline
1198 ins
.has_inline_constant
= false;
1199 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1200 ins
.src_types
[1] = nir_type_float32
;
1201 ins
.has_constants
= true;
1203 if (instr
->op
== nir_op_b2f32
)
1204 ins
.constants
.f32
[0] = 1.0f
;
1206 ins
.constants
.i32
[0] = 1;
1208 for (unsigned c
= 0; c
< 16; ++c
)
1209 ins
.swizzle
[1][c
] = 0;
1210 } else if (instr
->op
== nir_op_b2f16
) {
1211 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1212 ins
.src_types
[1] = nir_type_float16
;
1213 ins
.has_constants
= true;
1214 ins
.constants
.i16
[0] = _mesa_float_to_half(1.0);
1216 for (unsigned c
= 0; c
< 16; ++c
)
1217 ins
.swizzle
[1][c
] = 0;
1218 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1219 /* Lots of instructions need a 0 plonked in */
1220 ins
.has_inline_constant
= false;
1221 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1222 ins
.src_types
[1] = nir_type_uint32
;
1223 ins
.has_constants
= true;
1224 ins
.constants
.u32
[0] = 0;
1226 for (unsigned c
= 0; c
< 16; ++c
)
1227 ins
.swizzle
[1][c
] = 0;
1228 } else if (instr
->op
== nir_op_pack_32_2x16
) {
1229 ins
.dest_type
= nir_type_uint16
;
1230 ins
.mask
= mask_of(nr_components
* 2);
1232 } else if (instr
->op
== nir_op_pack_32_4x8
) {
1233 ins
.dest_type
= nir_type_uint8
;
1234 ins
.mask
= mask_of(nr_components
* 4);
1236 } else if (instr
->op
== nir_op_unpack_32_2x16
) {
1237 ins
.dest_type
= nir_type_uint32
;
1238 ins
.mask
= mask_of(nr_components
>> 1);
1240 } else if (instr
->op
== nir_op_unpack_32_4x8
) {
1241 ins
.dest_type
= nir_type_uint32
;
1242 ins
.mask
= mask_of(nr_components
>> 2);
1246 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1247 /* To avoid duplicating the lookup tables (probably), true LUT
1248 * instructions can only operate as if they were scalars. Lower
1249 * them here by changing the component. */
1251 unsigned orig_mask
= ins
.mask
;
1253 unsigned swizzle_back
[MIR_VEC_COMPONENTS
];
1254 memcpy(&swizzle_back
, ins
.swizzle
[0], sizeof(swizzle_back
));
1256 midgard_instruction ins_split
[MIR_VEC_COMPONENTS
];
1257 unsigned ins_count
= 0;
1259 for (int i
= 0; i
< nr_components
; ++i
) {
1260 /* Mask the associated component, dropping the
1261 * instruction if needed */
1264 ins
.mask
&= orig_mask
;
1266 for (unsigned j
= 0; j
< ins_count
; ++j
) {
1267 if (swizzle_back
[i
] == ins_split
[j
].swizzle
[0][0]) {
1268 ins_split
[j
].mask
|= ins
.mask
;
1277 for (unsigned j
= 0; j
< MIR_VEC_COMPONENTS
; ++j
)
1278 ins
.swizzle
[0][j
] = swizzle_back
[i
]; /* Pull from the correct component */
1280 ins_split
[ins_count
] = ins
;
1285 for (unsigned i
= 0; i
< ins_count
; ++i
) {
1286 emit_mir_instruction(ctx
, ins_split
[i
]);
1289 emit_mir_instruction(ctx
, ins
);
1296 mir_set_intr_mask(nir_instr
*instr
, midgard_instruction
*ins
, bool is_read
)
1298 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
1299 unsigned nir_mask
= 0;
1303 nir_mask
= mask_of(nir_intrinsic_dest_components(intr
));
1304 dsize
= nir_dest_bit_size(intr
->dest
);
1306 nir_mask
= nir_intrinsic_write_mask(intr
);
1310 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1311 unsigned bytemask
= pan_to_bytemask(dsize
, nir_mask
);
1312 mir_set_bytemask(ins
, bytemask
);
1313 ins
->dest_type
= nir_type_uint
| dsize
;
1316 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1317 * optimized) versions of UBO #0 */
1319 static midgard_instruction
*
1321 compiler_context
*ctx
,
1325 nir_src
*indirect_offset
,
1326 unsigned indirect_shift
,
1329 /* TODO: half-floats */
1331 midgard_instruction ins
= m_ld_ubo_int4(dest
, 0);
1332 ins
.constants
.u32
[0] = offset
;
1334 if (instr
->type
== nir_instr_type_intrinsic
)
1335 mir_set_intr_mask(instr
, &ins
, true);
1337 if (indirect_offset
) {
1338 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1339 ins
.src_types
[2] = nir_type_uint32
;
1340 ins
.load_store
.arg_2
= (indirect_shift
<< 5);
1342 /* X component for the whole swizzle to prevent register
1343 * pressure from ballooning from the extra components */
1344 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
.swizzle
[2]); ++i
)
1345 ins
.swizzle
[2][i
] = 0;
1347 ins
.load_store
.arg_2
= 0x1E;
1350 ins
.load_store
.arg_1
= index
;
1352 return emit_mir_instruction(ctx
, ins
);
1355 /* Globals are like UBOs if you squint. And shared memory is like globals if
1356 * you squint even harder */
1360 compiler_context
*ctx
,
1369 midgard_instruction ins
;
1372 ins
= m_ld_int4(srcdest
, 0);
1374 ins
= m_st_int4(srcdest
, 0);
1376 mir_set_offset(ctx
, &ins
, offset
, is_shared
);
1377 mir_set_intr_mask(instr
, &ins
, is_read
);
1379 emit_mir_instruction(ctx
, ins
);
1384 compiler_context
*ctx
,
1385 unsigned dest
, unsigned offset
,
1386 unsigned nr_comp
, unsigned component
,
1387 nir_src
*indirect_offset
, nir_alu_type type
, bool flat
)
1389 /* XXX: Half-floats? */
1390 /* TODO: swizzle, mask */
1392 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1393 ins
.mask
= mask_of(nr_comp
);
1394 ins
.dest_type
= type
;
1396 if (type
== nir_type_float16
) {
1397 /* Ensure we are aligned so we can pack it later */
1398 ins
.mask
= mask_of(ALIGN_POT(nr_comp
, 2));
1401 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
.swizzle
[0]); ++i
)
1402 ins
.swizzle
[0][i
] = MIN2(i
+ component
, COMPONENT_W
);
1404 midgard_varying_parameter p
= {
1406 .interpolation
= midgard_interp_default
,
1411 memcpy(&u
, &p
, sizeof(p
));
1412 ins
.load_store
.varying_parameters
= u
;
1414 if (indirect_offset
) {
1415 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1416 ins
.src_types
[2] = nir_type_uint32
;
1418 ins
.load_store
.arg_2
= 0x1E;
1420 ins
.load_store
.arg_1
= 0x9E;
1422 /* Use the type appropriate load */
1424 case nir_type_uint32
:
1425 case nir_type_bool32
:
1426 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1428 case nir_type_int32
:
1429 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1431 case nir_type_float32
:
1432 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1434 case nir_type_float16
:
1435 ins
.load_store
.op
= midgard_op_ld_vary_16
;
1438 unreachable("Attempted to load unknown type");
1442 emit_mir_instruction(ctx
, ins
);
1447 compiler_context
*ctx
,
1448 unsigned dest
, unsigned offset
,
1449 unsigned nr_comp
, nir_alu_type t
)
1451 midgard_instruction ins
= m_ld_attr_32(dest
, offset
);
1452 ins
.load_store
.arg_1
= 0x1E;
1453 ins
.load_store
.arg_2
= 0x1E;
1454 ins
.mask
= mask_of(nr_comp
);
1456 /* Use the type appropriate load */
1460 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1463 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1465 case nir_type_float
:
1466 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1469 unreachable("Attempted to load unknown type");
1473 emit_mir_instruction(ctx
, ins
);
1477 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
,
1478 unsigned nr_components
, unsigned offset
)
1482 /* Figure out which uniform this is */
1483 int sysval
= panfrost_sysval_for_instr(instr
, &nir_dest
);
1484 void *val
= _mesa_hash_table_u64_search(ctx
->sysvals
.sysval_to_id
, sysval
);
1486 unsigned dest
= nir_dest_index(&nir_dest
);
1488 /* Sysvals are prefix uniforms */
1489 unsigned uniform
= ((uintptr_t) val
) - 1;
1491 /* Emit the read itself -- this is never indirect */
1492 midgard_instruction
*ins
=
1493 emit_ubo_read(ctx
, instr
, dest
, (uniform
* 16) + offset
, NULL
, 0, 0);
1495 ins
->mask
= mask_of(nr_components
);
1499 compute_builtin_arg(nir_op op
)
1502 case nir_intrinsic_load_work_group_id
:
1504 case nir_intrinsic_load_local_invocation_id
:
1507 unreachable("Invalid compute paramater loaded");
1512 emit_fragment_store(compiler_context
*ctx
, unsigned src
, unsigned src_z
, unsigned src_s
, enum midgard_rt_id rt
)
1514 assert(rt
< ARRAY_SIZE(ctx
->writeout_branch
));
1516 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
1520 emit_explicit_constant(ctx
, src
, src
);
1522 struct midgard_instruction ins
=
1523 v_branch(false, false);
1525 bool depth_only
= (rt
== MIDGARD_ZS_RT
);
1527 ins
.writeout
= depth_only
? 0 : PAN_WRITEOUT_C
;
1529 /* Add dependencies */
1531 ins
.src_types
[0] = nir_type_uint32
;
1532 ins
.constants
.u32
[0] = depth_only
? 0xFF : (rt
- MIDGARD_COLOR_RT0
) * 0x100;
1533 for (int i
= 0; i
< 4; ++i
)
1534 ins
.swizzle
[0][i
] = i
;
1537 emit_explicit_constant(ctx
, src_z
, src_z
);
1539 ins
.src_types
[2] = nir_type_uint32
;
1540 ins
.writeout
|= PAN_WRITEOUT_Z
;
1543 emit_explicit_constant(ctx
, src_s
, src_s
);
1545 ins
.src_types
[3] = nir_type_uint32
;
1546 ins
.writeout
|= PAN_WRITEOUT_S
;
1549 /* Emit the branch */
1550 br
= emit_mir_instruction(ctx
, ins
);
1551 schedule_barrier(ctx
);
1552 ctx
->writeout_branch
[rt
] = br
;
1554 /* Push our current location = current block count - 1 = where we'll
1555 * jump to. Maybe a bit too clever for my own good */
1557 br
->branch
.target_block
= ctx
->block_count
- 1;
1561 emit_compute_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1563 unsigned reg
= nir_dest_index(&instr
->dest
);
1564 midgard_instruction ins
= m_ld_compute_id(reg
, 0);
1565 ins
.mask
= mask_of(3);
1566 ins
.swizzle
[0][3] = COMPONENT_X
; /* xyzx */
1567 ins
.load_store
.arg_1
= compute_builtin_arg(instr
->intrinsic
);
1568 emit_mir_instruction(ctx
, ins
);
1572 vertex_builtin_arg(nir_op op
)
1575 case nir_intrinsic_load_vertex_id
:
1576 return PAN_VERTEX_ID
;
1577 case nir_intrinsic_load_instance_id
:
1578 return PAN_INSTANCE_ID
;
1580 unreachable("Invalid vertex builtin");
1585 emit_vertex_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1587 unsigned reg
= nir_dest_index(&instr
->dest
);
1588 emit_attr_read(ctx
, reg
, vertex_builtin_arg(instr
->intrinsic
), 1, nir_type_int
);
1592 emit_control_barrier(compiler_context
*ctx
)
1594 midgard_instruction ins
= {
1595 .type
= TAG_TEXTURE_4
,
1597 .src
= { ~0, ~0, ~0, ~0 },
1599 .op
= TEXTURE_OP_BARRIER
,
1601 /* TODO: optimize */
1602 .out_of_order
= MIDGARD_BARRIER_BUFFER
|
1603 MIDGARD_BARRIER_SHARED
,
1607 emit_mir_instruction(ctx
, ins
);
1611 mir_get_branch_cond(nir_src
*src
, bool *invert
)
1613 /* Wrap it. No swizzle since it's a scalar */
1619 *invert
= pan_has_source_mod(&alu
, nir_op_inot
);
1620 return nir_src_index(NULL
, &alu
.src
);
1624 output_load_rt_addr(nir_shader
*nir
, nir_intrinsic_instr
*instr
)
1626 const nir_variable
*var
;
1627 var
= search_var(&nir
->outputs
, nir_intrinsic_base(instr
));
1630 unsigned loc
= var
->data
.location
;
1632 if (loc
== FRAG_RESULT_COLOR
)
1633 loc
= FRAG_RESULT_DATA0
;
1635 if (loc
>= FRAG_RESULT_DATA0
)
1636 return loc
- FRAG_RESULT_DATA0
;
1638 if (loc
== FRAG_RESULT_DEPTH
)
1640 if (loc
== FRAG_RESULT_STENCIL
)
1647 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1649 unsigned offset
= 0, reg
;
1651 switch (instr
->intrinsic
) {
1652 case nir_intrinsic_discard_if
:
1653 case nir_intrinsic_discard
: {
1654 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1655 struct midgard_instruction discard
= v_branch(conditional
, false);
1656 discard
.branch
.target_type
= TARGET_DISCARD
;
1659 discard
.src
[0] = mir_get_branch_cond(&instr
->src
[0],
1660 &discard
.branch
.invert_conditional
);
1661 discard
.src_types
[0] = nir_type_uint32
;
1664 emit_mir_instruction(ctx
, discard
);
1665 schedule_barrier(ctx
);
1670 case nir_intrinsic_load_uniform
:
1671 case nir_intrinsic_load_ubo
:
1672 case nir_intrinsic_load_global
:
1673 case nir_intrinsic_load_shared
:
1674 case nir_intrinsic_load_input
:
1675 case nir_intrinsic_load_interpolated_input
: {
1676 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1677 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1678 bool is_global
= instr
->intrinsic
== nir_intrinsic_load_global
;
1679 bool is_shared
= instr
->intrinsic
== nir_intrinsic_load_shared
;
1680 bool is_flat
= instr
->intrinsic
== nir_intrinsic_load_input
;
1681 bool is_interp
= instr
->intrinsic
== nir_intrinsic_load_interpolated_input
;
1683 /* Get the base type of the intrinsic */
1684 /* TODO: Infer type? Does it matter? */
1686 (is_ubo
|| is_global
|| is_shared
) ? nir_type_uint
:
1687 (is_interp
) ? nir_type_float
:
1688 nir_intrinsic_type(instr
);
1690 t
= nir_alu_type_get_base_type(t
);
1692 if (!(is_ubo
|| is_global
)) {
1693 offset
= nir_intrinsic_base(instr
);
1696 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1698 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1700 bool direct
= nir_src_is_const(*src_offset
);
1701 nir_src
*indirect_offset
= direct
? NULL
: src_offset
;
1704 offset
+= nir_src_as_uint(*src_offset
);
1706 /* We may need to apply a fractional offset */
1707 int component
= (is_flat
|| is_interp
) ?
1708 nir_intrinsic_component(instr
) : 0;
1709 reg
= nir_dest_index(&instr
->dest
);
1711 if (is_uniform
&& !ctx
->is_blend
) {
1712 emit_ubo_read(ctx
, &instr
->instr
, reg
, (ctx
->sysvals
.sysval_count
+ offset
) * 16, indirect_offset
, 4, 0);
1713 } else if (is_ubo
) {
1714 nir_src index
= instr
->src
[0];
1716 /* TODO: Is indirect block number possible? */
1717 assert(nir_src_is_const(index
));
1719 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1720 emit_ubo_read(ctx
, &instr
->instr
, reg
, offset
, indirect_offset
, 0, uindex
);
1721 } else if (is_global
|| is_shared
) {
1722 emit_global(ctx
, &instr
->instr
, true, reg
, src_offset
, is_shared
);
1723 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1724 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, indirect_offset
, t
| nir_dest_bit_size(instr
->dest
), is_flat
);
1725 } else if (ctx
->is_blend
) {
1726 /* ctx->blend_input will be precoloured to r0, where
1727 * the input is preloaded */
1729 if (ctx
->blend_input
== ~0)
1730 ctx
->blend_input
= reg
;
1732 emit_mir_instruction(ctx
, v_mov(ctx
->blend_input
, reg
));
1733 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1734 emit_attr_read(ctx
, reg
, offset
, nr_comp
, t
);
1736 DBG("Unknown load\n");
1743 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1744 case nir_intrinsic_load_barycentric_pixel
:
1745 case nir_intrinsic_load_barycentric_centroid
:
1748 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1750 case nir_intrinsic_load_raw_output_pan
: {
1751 reg
= nir_dest_index(&instr
->dest
);
1753 /* T720 and below use different blend opcodes with slightly
1754 * different semantics than T760 and up */
1756 midgard_instruction ld
= m_ld_color_buffer_32u(reg
, 0);
1758 ld
.load_store
.arg_2
= output_load_rt_addr(ctx
->nir
, instr
);
1760 if (ctx
->quirks
& MIDGARD_OLD_BLEND
) {
1761 ld
.load_store
.op
= midgard_op_ld_color_buffer_32u_old
;
1762 ld
.load_store
.address
= 16;
1763 ld
.load_store
.arg_2
= 0x1E;
1766 emit_mir_instruction(ctx
, ld
);
1770 case nir_intrinsic_load_output
: {
1771 reg
= nir_dest_index(&instr
->dest
);
1773 unsigned bits
= nir_dest_bit_size(instr
->dest
);
1775 midgard_instruction ld
;
1777 ld
= m_ld_color_buffer_as_fp16(reg
, 0);
1779 ld
= m_ld_color_buffer_as_fp32(reg
, 0);
1781 ld
.load_store
.arg_2
= output_load_rt_addr(ctx
->nir
, instr
);
1783 for (unsigned c
= 4; c
< 16; ++c
)
1784 ld
.swizzle
[0][c
] = 0;
1786 if (ctx
->quirks
& MIDGARD_OLD_BLEND
) {
1788 ld
.load_store
.op
= midgard_op_ld_color_buffer_as_fp16_old
;
1790 ld
.load_store
.op
= midgard_op_ld_color_buffer_as_fp32_old
;
1791 ld
.load_store
.address
= 1;
1792 ld
.load_store
.arg_2
= 0x1E;
1795 emit_mir_instruction(ctx
, ld
);
1799 case nir_intrinsic_load_blend_const_color_rgba
: {
1800 assert(ctx
->is_blend
);
1801 reg
= nir_dest_index(&instr
->dest
);
1803 /* Blend constants are embedded directly in the shader and
1804 * patched in, so we use some magic routing */
1806 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), reg
);
1807 ins
.has_constants
= true;
1808 ins
.has_blend_constant
= true;
1809 emit_mir_instruction(ctx
, ins
);
1813 case nir_intrinsic_store_output
:
1814 case nir_intrinsic_store_combined_output_pan
:
1815 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1817 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1819 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1821 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1822 bool combined
= instr
->intrinsic
==
1823 nir_intrinsic_store_combined_output_pan
;
1825 const nir_variable
*var
;
1826 enum midgard_rt_id rt
;
1828 var
= search_var(&ctx
->nir
->outputs
,
1829 nir_intrinsic_base(instr
));
1831 if (var
->data
.location
== FRAG_RESULT_COLOR
)
1832 rt
= MIDGARD_COLOR_RT0
;
1833 else if (var
->data
.location
>= FRAG_RESULT_DATA0
)
1834 rt
= MIDGARD_COLOR_RT0
+ var
->data
.location
-
1841 unsigned reg_z
= ~0, reg_s
= ~0;
1843 unsigned writeout
= nir_intrinsic_component(instr
);
1844 if (writeout
& PAN_WRITEOUT_Z
)
1845 reg_z
= nir_src_index(ctx
, &instr
->src
[2]);
1846 if (writeout
& PAN_WRITEOUT_S
)
1847 reg_s
= nir_src_index(ctx
, &instr
->src
[3]);
1850 emit_fragment_store(ctx
, reg
, reg_z
, reg_s
, rt
);
1851 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1852 assert(instr
->intrinsic
== nir_intrinsic_store_output
);
1854 /* We should have been vectorized, though we don't
1855 * currently check that st_vary is emitted only once
1856 * per slot (this is relevant, since there's not a mask
1857 * parameter available on the store [set to 0 by the
1858 * blob]). We do respect the component by adjusting the
1859 * swizzle. If this is a constant source, we'll need to
1860 * emit that explicitly. */
1862 emit_explicit_constant(ctx
, reg
, reg
);
1864 unsigned dst_component
= nir_intrinsic_component(instr
);
1865 unsigned nr_comp
= nir_src_num_components(instr
->src
[0]);
1867 midgard_instruction st
= m_st_vary_32(reg
, offset
);
1868 st
.load_store
.arg_1
= 0x9E;
1869 st
.load_store
.arg_2
= 0x1E;
1871 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr
))) {
1874 st
.load_store
.op
= midgard_op_st_vary_32u
;
1877 st
.load_store
.op
= midgard_op_st_vary_32i
;
1879 case nir_type_float
:
1880 st
.load_store
.op
= midgard_op_st_vary_32
;
1883 unreachable("Attempted to store unknown type");
1887 /* nir_intrinsic_component(store_intr) encodes the
1888 * destination component start. Source component offset
1889 * adjustment is taken care of in
1890 * install_registers_instr(), when offset_swizzle() is
1893 unsigned src_component
= COMPONENT_X
;
1895 assert(nr_comp
> 0);
1896 for (unsigned i
= 0; i
< ARRAY_SIZE(st
.swizzle
); ++i
) {
1897 st
.swizzle
[0][i
] = src_component
;
1898 if (i
>= dst_component
&& i
< dst_component
+ nr_comp
- 1)
1902 emit_mir_instruction(ctx
, st
);
1904 DBG("Unknown store\n");
1910 /* Special case of store_output for lowered blend shaders */
1911 case nir_intrinsic_store_raw_output_pan
:
1912 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1913 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1914 emit_fragment_store(ctx
, reg
, ~0, ~0, ctx
->blend_rt
);
1917 case nir_intrinsic_store_global
:
1918 case nir_intrinsic_store_shared
:
1919 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1920 emit_explicit_constant(ctx
, reg
, reg
);
1922 emit_global(ctx
, &instr
->instr
, false, reg
, &instr
->src
[1], instr
->intrinsic
== nir_intrinsic_store_shared
);
1925 case nir_intrinsic_load_ssbo_address
:
1926 emit_sysval_read(ctx
, &instr
->instr
, 1, 0);
1929 case nir_intrinsic_get_buffer_size
:
1930 emit_sysval_read(ctx
, &instr
->instr
, 1, 8);
1933 case nir_intrinsic_load_viewport_scale
:
1934 case nir_intrinsic_load_viewport_offset
:
1935 case nir_intrinsic_load_num_work_groups
:
1936 case nir_intrinsic_load_sampler_lod_parameters_pan
:
1937 emit_sysval_read(ctx
, &instr
->instr
, 3, 0);
1940 case nir_intrinsic_load_work_group_id
:
1941 case nir_intrinsic_load_local_invocation_id
:
1942 emit_compute_builtin(ctx
, instr
);
1945 case nir_intrinsic_load_vertex_id
:
1946 case nir_intrinsic_load_instance_id
:
1947 emit_vertex_builtin(ctx
, instr
);
1950 case nir_intrinsic_memory_barrier_buffer
:
1951 case nir_intrinsic_memory_barrier_shared
:
1954 case nir_intrinsic_control_barrier
:
1955 schedule_barrier(ctx
);
1956 emit_control_barrier(ctx
);
1957 schedule_barrier(ctx
);
1961 fprintf(stderr
, "Unhandled intrinsic %s\n", nir_intrinsic_infos
[instr
->intrinsic
].name
);
1968 midgard_tex_format(enum glsl_sampler_dim dim
)
1971 case GLSL_SAMPLER_DIM_1D
:
1972 case GLSL_SAMPLER_DIM_BUF
:
1975 case GLSL_SAMPLER_DIM_2D
:
1976 case GLSL_SAMPLER_DIM_MS
:
1977 case GLSL_SAMPLER_DIM_EXTERNAL
:
1978 case GLSL_SAMPLER_DIM_RECT
:
1981 case GLSL_SAMPLER_DIM_3D
:
1984 case GLSL_SAMPLER_DIM_CUBE
:
1985 return MALI_TEX_CUBE
;
1988 DBG("Unknown sampler dim type\n");
1994 /* Tries to attach an explicit LOD or bias as a constant. Returns whether this
1998 pan_attach_constant_bias(
1999 compiler_context
*ctx
,
2001 midgard_texture_word
*word
)
2003 /* To attach as constant, it has to *be* constant */
2005 if (!nir_src_is_const(lod
))
2008 float f
= nir_src_as_float(lod
);
2010 /* Break into fixed-point */
2012 float lod_frac
= f
- lod_int
;
2014 /* Carry over negative fractions */
2015 if (lod_frac
< 0.0) {
2021 word
->bias
= float_to_ubyte(lod_frac
);
2022 word
->bias_int
= lod_int
;
2028 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
2029 unsigned midgard_texop
)
2032 //assert (!instr->sampler);
2034 int texture_index
= instr
->texture_index
;
2035 int sampler_index
= texture_index
;
2037 nir_alu_type dest_base
= nir_alu_type_get_base_type(instr
->dest_type
);
2038 nir_alu_type dest_type
= dest_base
| nir_dest_bit_size(instr
->dest
);
2040 midgard_instruction ins
= {
2041 .type
= TAG_TEXTURE_4
,
2043 .dest
= nir_dest_index(&instr
->dest
),
2044 .src
= { ~0, ~0, ~0, ~0 },
2045 .dest_type
= dest_type
,
2046 .swizzle
= SWIZZLE_IDENTITY_4
,
2048 .op
= midgard_texop
,
2049 .format
= midgard_tex_format(instr
->sampler_dim
),
2050 .texture_handle
= texture_index
,
2051 .sampler_handle
= sampler_index
,
2052 .shadow
= instr
->is_shadow
,
2056 if (instr
->is_shadow
&& !instr
->is_new_style_shadow
)
2057 for (int i
= 0; i
< 4; ++i
)
2058 ins
.swizzle
[0][i
] = COMPONENT_X
;
2060 /* We may need a temporary for the coordinate */
2062 bool needs_temp_coord
=
2063 (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) ||
2064 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) ||
2067 unsigned coords
= needs_temp_coord
? make_compiler_temp_reg(ctx
) : 0;
2069 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
2070 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
2071 unsigned nr_components
= nir_src_num_components(instr
->src
[i
].src
);
2072 unsigned sz
= nir_src_bit_size(instr
->src
[i
].src
);
2073 nir_alu_type T
= nir_tex_instr_src_type(instr
, i
) | sz
;
2075 switch (instr
->src
[i
].src_type
) {
2076 case nir_tex_src_coord
: {
2077 emit_explicit_constant(ctx
, index
, index
);
2079 unsigned coord_mask
= mask_of(instr
->coord_components
);
2081 bool flip_zw
= (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) && (coord_mask
& (1 << COMPONENT_Z
));
2084 coord_mask
^= ((1 << COMPONENT_Z
) | (1 << COMPONENT_W
));
2086 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2087 /* texelFetch is undefined on samplerCube */
2088 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
2090 /* For cubemaps, we use a special ld/st op to
2091 * select the face and copy the xy into the
2092 * texture register */
2094 midgard_instruction ld
= m_ld_cubemap_coords(coords
, 0);
2096 ld
.src_types
[1] = T
;
2097 ld
.mask
= 0x3; /* xy */
2098 ld
.load_store
.arg_1
= 0x20;
2099 ld
.swizzle
[1][3] = COMPONENT_X
;
2100 emit_mir_instruction(ctx
, ld
);
2103 ins
.swizzle
[1][2] = instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
2104 ins
.swizzle
[1][3] = COMPONENT_X
;
2105 } else if (needs_temp_coord
) {
2106 /* mov coord_temp, coords */
2107 midgard_instruction mov
= v_mov(index
, coords
);
2108 mov
.mask
= coord_mask
;
2111 mov
.swizzle
[1][COMPONENT_W
] = COMPONENT_Z
;
2113 emit_mir_instruction(ctx
, mov
);
2118 ins
.src
[1] = coords
;
2119 ins
.src_types
[1] = T
;
2121 /* Texelfetch coordinates uses all four elements
2122 * (xyz/index) regardless of texture dimensionality,
2123 * which means it's necessary to zero the unused
2124 * components to keep everything happy */
2126 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
2127 /* mov index.zw, #0, or generalized */
2128 midgard_instruction mov
=
2129 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), coords
);
2130 mov
.has_constants
= true;
2131 mov
.mask
= coord_mask
^ 0xF;
2132 emit_mir_instruction(ctx
, mov
);
2135 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) {
2136 /* Array component in w but NIR wants it in z,
2137 * but if we have a temp coord we already fixed
2140 if (nr_components
== 3) {
2141 ins
.swizzle
[1][2] = COMPONENT_Z
;
2142 ins
.swizzle
[1][3] = needs_temp_coord
? COMPONENT_W
: COMPONENT_Z
;
2143 } else if (nr_components
== 2) {
2145 instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
2146 ins
.swizzle
[1][3] = COMPONENT_X
;
2148 unreachable("Invalid texture 2D components");
2151 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
2153 ins
.swizzle
[1][2] = COMPONENT_Z
;
2154 ins
.swizzle
[1][3] = COMPONENT_W
;
2160 case nir_tex_src_bias
:
2161 case nir_tex_src_lod
: {
2162 /* Try as a constant if we can */
2164 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
2165 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
2168 ins
.texture
.lod_register
= true;
2170 ins
.src_types
[2] = T
;
2172 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
2173 ins
.swizzle
[2][c
] = COMPONENT_X
;
2175 emit_explicit_constant(ctx
, index
, index
);
2180 case nir_tex_src_offset
: {
2181 ins
.texture
.offset_register
= true;
2183 ins
.src_types
[3] = T
;
2185 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
2186 ins
.swizzle
[3][c
] = (c
> COMPONENT_Z
) ? 0 : c
;
2188 emit_explicit_constant(ctx
, index
, index
);
2192 case nir_tex_src_comparator
:
2193 case nir_tex_src_ms_index
: {
2194 unsigned comp
= COMPONENT_Z
;
2196 /* mov coord_temp.foo, coords */
2197 midgard_instruction mov
= v_mov(index
, coords
);
2198 mov
.mask
= 1 << comp
;
2200 for (unsigned i
= 0; i
< MIR_VEC_COMPONENTS
; ++i
)
2201 mov
.swizzle
[1][i
] = COMPONENT_X
;
2203 emit_mir_instruction(ctx
, mov
);
2208 fprintf(stderr
, "Unknown texture source type: %d\n", instr
->src
[i
].src_type
);
2214 emit_mir_instruction(ctx
, ins
);
2218 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
2220 switch (instr
->op
) {
2223 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
2226 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
2229 case nir_texop_txf_ms
:
2230 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
2233 emit_sysval_read(ctx
, &instr
->instr
, 4, 0);
2236 fprintf(stderr
, "Unhandled texture op: %d\n", instr
->op
);
2243 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
2245 switch (instr
->type
) {
2246 case nir_jump_break
: {
2247 /* Emit a branch out of the loop */
2248 struct midgard_instruction br
= v_branch(false, false);
2249 br
.branch
.target_type
= TARGET_BREAK
;
2250 br
.branch
.target_break
= ctx
->current_loop_depth
;
2251 emit_mir_instruction(ctx
, br
);
2256 DBG("Unknown jump type %d\n", instr
->type
);
2262 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
2264 switch (instr
->type
) {
2265 case nir_instr_type_load_const
:
2266 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2269 case nir_instr_type_intrinsic
:
2270 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2273 case nir_instr_type_alu
:
2274 emit_alu(ctx
, nir_instr_as_alu(instr
));
2277 case nir_instr_type_tex
:
2278 emit_tex(ctx
, nir_instr_as_tex(instr
));
2281 case nir_instr_type_jump
:
2282 emit_jump(ctx
, nir_instr_as_jump(instr
));
2285 case nir_instr_type_ssa_undef
:
2290 DBG("Unhandled instruction type\n");
2296 /* ALU instructions can inline or embed constants, which decreases register
2297 * pressure and saves space. */
2299 #define CONDITIONAL_ATTACH(idx) { \
2300 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2303 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2304 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2309 inline_alu_constants(compiler_context
*ctx
, midgard_block
*block
)
2311 mir_foreach_instr_in_block(block
, alu
) {
2312 /* Other instructions cannot inline constants */
2313 if (alu
->type
!= TAG_ALU_4
) continue;
2314 if (alu
->compact_branch
) continue;
2316 /* If there is already a constant here, we can do nothing */
2317 if (alu
->has_constants
) continue;
2319 CONDITIONAL_ATTACH(0);
2321 if (!alu
->has_constants
) {
2322 CONDITIONAL_ATTACH(1)
2323 } else if (!alu
->inline_constant
) {
2324 /* Corner case: _two_ vec4 constants, for instance with a
2325 * csel. For this case, we can only use a constant
2326 * register for one, we'll have to emit a move for the
2329 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->src
[1] + 1);
2330 unsigned scratch
= make_compiler_temp(ctx
);
2333 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), scratch
);
2334 attach_constants(ctx
, &ins
, entry
, alu
->src
[1] + 1);
2336 /* Set the source */
2337 alu
->src
[1] = scratch
;
2339 /* Inject us -before- the last instruction which set r31 */
2340 mir_insert_instruction_before(ctx
, mir_prev_op(alu
), ins
);
2346 /* Midgard supports two types of constants, embedded constants (128-bit) and
2347 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2348 * constants can be demoted to inline constants, for space savings and
2349 * sometimes a performance boost */
2352 embedded_to_inline_constant(compiler_context
*ctx
, midgard_block
*block
)
2354 mir_foreach_instr_in_block(block
, ins
) {
2355 if (!ins
->has_constants
) continue;
2356 if (ins
->has_inline_constant
) continue;
2358 /* Blend constants must not be inlined by definition */
2359 if (ins
->has_blend_constant
) continue;
2361 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2362 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
2363 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
2365 if (!(is_16
|| is_32
))
2368 /* src1 cannot be an inline constant due to encoding
2369 * restrictions. So, if possible we try to flip the arguments
2372 int op
= ins
->alu
.op
;
2374 if (ins
->src
[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
) &&
2375 alu_opcode_props
[op
].props
& OP_COMMUTES
) {
2379 if (ins
->src
[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2380 /* Component is from the swizzle. Take a nonzero component */
2382 unsigned first_comp
= ffs(ins
->mask
) - 1;
2383 unsigned component
= ins
->swizzle
[1][first_comp
];
2385 /* Scale constant appropriately, if we can legally */
2386 int16_t scaled_constant
= 0;
2389 scaled_constant
= ins
->constants
.u16
[component
];
2390 } else if (midgard_is_integer_op(op
)) {
2391 scaled_constant
= ins
->constants
.u32
[component
];
2393 /* Constant overflow after resize */
2394 if (scaled_constant
!= ins
->constants
.u32
[component
])
2397 float original
= ins
->constants
.f32
[component
];
2398 scaled_constant
= _mesa_float_to_half(original
);
2400 /* Check for loss of precision. If this is
2401 * mediump, we don't care, but for a highp
2402 * shader, we need to pay attention. NIR
2403 * doesn't yet tell us which mode we're in!
2404 * Practically this prevents most constants
2405 * from being inlined, sadly. */
2407 float fp32
= _mesa_half_to_float(scaled_constant
);
2409 if (fp32
!= original
)
2413 /* Should've been const folded */
2414 if (ins
->src_abs
[1] || ins
->src_neg
[1])
2417 /* Make sure that the constant is not itself a vector
2418 * by checking if all accessed values are the same. */
2420 const midgard_constants
*cons
= &ins
->constants
;
2421 uint32_t value
= is_16
? cons
->u16
[component
] : cons
->u32
[component
];
2423 bool is_vector
= false;
2424 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
2426 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
) {
2427 /* We only care if this component is actually used */
2428 if (!(mask
& (1 << c
)))
2431 uint32_t test
= is_16
?
2432 cons
->u16
[ins
->swizzle
[1][c
]] :
2433 cons
->u32
[ins
->swizzle
[1][c
]];
2435 if (test
!= value
) {
2444 /* Get rid of the embedded constant */
2445 ins
->has_constants
= false;
2447 ins
->has_inline_constant
= true;
2448 ins
->inline_constant
= scaled_constant
;
2453 /* Dead code elimination for branches at the end of a block - only one branch
2454 * per block is legal semantically */
2457 midgard_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
2459 bool branched
= false;
2461 mir_foreach_instr_in_block_safe(block
, ins
) {
2462 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2465 mir_remove_instruction(ins
);
2471 /* We want to force the invert on AND/OR to the second slot to legalize into
2472 * iandnot/iornot. The relevant patterns are for AND (and OR respectively)
2474 * ~a & #b = ~a & ~(#~b)
2479 midgard_legalize_invert(compiler_context
*ctx
, midgard_block
*block
)
2481 mir_foreach_instr_in_block(block
, ins
) {
2482 if (ins
->type
!= TAG_ALU_4
) continue;
2484 if (ins
->alu
.op
!= midgard_alu_op_iand
&&
2485 ins
->alu
.op
!= midgard_alu_op_ior
) continue;
2487 if (ins
->src_invert
[1] || !ins
->src_invert
[0]) continue;
2489 if (ins
->has_inline_constant
) {
2490 /* ~(#~a) = ~(~#a) = a, so valid, and forces both
2492 ins
->inline_constant
= ~ins
->inline_constant
;
2493 ins
->src_invert
[1] = true;
2495 /* Flip to the right invert order. Note
2496 * has_inline_constant false by assumption on the
2497 * branch, so flipping makes sense. */
2504 emit_fragment_epilogue(compiler_context
*ctx
, unsigned rt
)
2506 /* Loop to ourselves */
2507 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
2508 struct midgard_instruction ins
= v_branch(false, false);
2509 ins
.writeout
= br
->writeout
;
2510 ins
.branch
.target_block
= ctx
->block_count
- 1;
2511 ins
.constants
.u32
[0] = br
->constants
.u32
[0];
2512 memcpy(&ins
.src_types
, &br
->src_types
, sizeof(ins
.src_types
));
2513 emit_mir_instruction(ctx
, ins
);
2515 ctx
->current_block
->epilogue
= true;
2516 schedule_barrier(ctx
);
2517 return ins
.branch
.target_block
;
2520 static midgard_block
*
2521 emit_block_init(compiler_context
*ctx
)
2523 midgard_block
*this_block
= ctx
->after_block
;
2524 ctx
->after_block
= NULL
;
2527 this_block
= create_empty_block(ctx
);
2529 list_addtail(&this_block
->base
.link
, &ctx
->blocks
);
2531 this_block
->scheduled
= false;
2534 /* Set up current block */
2535 list_inithead(&this_block
->base
.instructions
);
2536 ctx
->current_block
= this_block
;
2541 static midgard_block
*
2542 emit_block(compiler_context
*ctx
, nir_block
*block
)
2544 midgard_block
*this_block
= emit_block_init(ctx
);
2546 nir_foreach_instr(instr
, block
) {
2547 emit_instr(ctx
, instr
);
2548 ++ctx
->instruction_count
;
2554 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2557 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2559 midgard_block
*before_block
= ctx
->current_block
;
2561 /* Speculatively emit the branch, but we can't fill it in until later */
2563 EMIT(branch
, true, true);
2564 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2565 then_branch
->src
[0] = mir_get_branch_cond(&nif
->condition
, &inv
);
2566 then_branch
->src_types
[0] = nir_type_uint32
;
2567 then_branch
->branch
.invert_conditional
= !inv
;
2569 /* Emit the two subblocks. */
2570 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2571 midgard_block
*end_then_block
= ctx
->current_block
;
2573 /* Emit a jump from the end of the then block to the end of the else */
2574 EMIT(branch
, false, false);
2575 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2577 /* Emit second block, and check if it's empty */
2579 int else_idx
= ctx
->block_count
;
2580 int count_in
= ctx
->instruction_count
;
2581 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2582 midgard_block
*end_else_block
= ctx
->current_block
;
2583 int after_else_idx
= ctx
->block_count
;
2585 /* Now that we have the subblocks emitted, fix up the branches */
2590 if (ctx
->instruction_count
== count_in
) {
2591 /* The else block is empty, so don't emit an exit jump */
2592 mir_remove_instruction(then_exit
);
2593 then_branch
->branch
.target_block
= after_else_idx
;
2595 then_branch
->branch
.target_block
= else_idx
;
2596 then_exit
->branch
.target_block
= after_else_idx
;
2599 /* Wire up the successors */
2601 ctx
->after_block
= create_empty_block(ctx
);
2603 pan_block_add_successor(&before_block
->base
, &then_block
->base
);
2604 pan_block_add_successor(&before_block
->base
, &else_block
->base
);
2606 pan_block_add_successor(&end_then_block
->base
, &ctx
->after_block
->base
);
2607 pan_block_add_successor(&end_else_block
->base
, &ctx
->after_block
->base
);
2611 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2613 /* Remember where we are */
2614 midgard_block
*start_block
= ctx
->current_block
;
2616 /* Allocate a loop number, growing the current inner loop depth */
2617 int loop_idx
= ++ctx
->current_loop_depth
;
2619 /* Get index from before the body so we can loop back later */
2620 int start_idx
= ctx
->block_count
;
2622 /* Emit the body itself */
2623 midgard_block
*loop_block
= emit_cf_list(ctx
, &nloop
->body
);
2625 /* Branch back to loop back */
2626 struct midgard_instruction br_back
= v_branch(false, false);
2627 br_back
.branch
.target_block
= start_idx
;
2628 emit_mir_instruction(ctx
, br_back
);
2630 /* Mark down that branch in the graph. */
2631 pan_block_add_successor(&start_block
->base
, &loop_block
->base
);
2632 pan_block_add_successor(&ctx
->current_block
->base
, &loop_block
->base
);
2634 /* Find the index of the block about to follow us (note: we don't add
2635 * one; blocks are 0-indexed so we get a fencepost problem) */
2636 int break_block_idx
= ctx
->block_count
;
2638 /* Fix up the break statements we emitted to point to the right place,
2639 * now that we can allocate a block number for them */
2640 ctx
->after_block
= create_empty_block(ctx
);
2642 mir_foreach_block_from(ctx
, start_block
, _block
) {
2643 mir_foreach_instr_in_block(((midgard_block
*) _block
), ins
) {
2644 if (ins
->type
!= TAG_ALU_4
) continue;
2645 if (!ins
->compact_branch
) continue;
2647 /* We found a branch -- check the type to see if we need to do anything */
2648 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2650 /* It's a break! Check if it's our break */
2651 if (ins
->branch
.target_break
!= loop_idx
) continue;
2653 /* Okay, cool, we're breaking out of this loop.
2654 * Rewrite from a break to a goto */
2656 ins
->branch
.target_type
= TARGET_GOTO
;
2657 ins
->branch
.target_block
= break_block_idx
;
2659 pan_block_add_successor(_block
, &ctx
->after_block
->base
);
2663 /* Now that we've finished emitting the loop, free up the depth again
2664 * so we play nice with recursion amid nested loops */
2665 --ctx
->current_loop_depth
;
2667 /* Dump loop stats */
2671 static midgard_block
*
2672 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2674 midgard_block
*start_block
= NULL
;
2676 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2677 switch (node
->type
) {
2678 case nir_cf_node_block
: {
2679 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2682 start_block
= block
;
2687 case nir_cf_node_if
:
2688 emit_if(ctx
, nir_cf_node_as_if(node
));
2691 case nir_cf_node_loop
:
2692 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2695 case nir_cf_node_function
:
2704 /* Due to lookahead, we need to report the first tag executed in the command
2705 * stream and in branch targets. An initial block might be empty, so iterate
2706 * until we find one that 'works' */
2709 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2711 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2713 mir_foreach_block_from(ctx
, initial_block
, _v
) {
2714 midgard_block
*v
= (midgard_block
*) _v
;
2715 if (v
->quadword_count
) {
2716 midgard_bundle
*initial_bundle
=
2717 util_dynarray_element(&v
->bundles
, midgard_bundle
, 0);
2719 return initial_bundle
->tag
;
2723 /* Default to a tag 1 which will break from the shader, in case we jump
2724 * to the exit block (i.e. `return` in a compute shader) */
2729 /* For each fragment writeout instruction, generate a writeout loop to
2730 * associate with it */
2733 mir_add_writeout_loops(compiler_context
*ctx
)
2735 for (unsigned rt
= 0; rt
< ARRAY_SIZE(ctx
->writeout_branch
); ++rt
) {
2736 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
2739 unsigned popped
= br
->branch
.target_block
;
2740 pan_block_add_successor(&(mir_get_block(ctx
, popped
- 1)->base
), &ctx
->current_block
->base
);
2741 br
->branch
.target_block
= emit_fragment_epilogue(ctx
, rt
);
2742 br
->branch
.target_type
= TARGET_GOTO
;
2744 /* If we have more RTs, we'll need to restore back after our
2745 * loop terminates */
2747 if ((rt
+ 1) < ARRAY_SIZE(ctx
->writeout_branch
) && ctx
->writeout_branch
[rt
+ 1]) {
2748 midgard_instruction uncond
= v_branch(false, false);
2749 uncond
.branch
.target_block
= popped
;
2750 uncond
.branch
.target_type
= TARGET_GOTO
;
2751 emit_mir_instruction(ctx
, uncond
);
2752 pan_block_add_successor(&ctx
->current_block
->base
, &(mir_get_block(ctx
, popped
)->base
));
2753 schedule_barrier(ctx
);
2755 /* We're last, so we can terminate here */
2756 br
->last_writeout
= true;
2762 midgard_compile_shader_nir(nir_shader
*nir
, panfrost_program
*program
, bool is_blend
, unsigned blend_rt
, unsigned gpu_id
, bool shaderdb
)
2764 struct util_dynarray
*compiled
= &program
->compiled
;
2766 midgard_debug
= debug_get_option_midgard_debug();
2768 /* TODO: Bound against what? */
2769 compiler_context
*ctx
= rzalloc(NULL
, compiler_context
);
2772 ctx
->stage
= nir
->info
.stage
;
2773 ctx
->is_blend
= is_blend
;
2774 ctx
->alpha_ref
= program
->alpha_ref
;
2775 ctx
->blend_rt
= MIDGARD_COLOR_RT0
+ blend_rt
;
2776 ctx
->blend_input
= ~0;
2777 ctx
->quirks
= midgard_get_quirks(gpu_id
);
2779 /* Start off with a safe cutoff, allowing usage of all 16 work
2780 * registers. Later, we'll promote uniform reads to uniform registers
2781 * if we determine it is beneficial to do so */
2782 ctx
->uniform_cutoff
= 8;
2784 /* Initialize at a global (not block) level hash tables */
2786 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2787 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2789 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2790 * (so we don't accidentally duplicate the epilogue since mesa/st has
2791 * messed with our I/O quite a bit already) */
2793 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2795 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2796 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2797 NIR_PASS_V(nir
, nir_lower_point_size
, 1.0, 1024.0);
2800 NIR_PASS_V(nir
, nir_lower_var_copies
);
2801 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2802 NIR_PASS_V(nir
, nir_split_var_copies
);
2803 NIR_PASS_V(nir
, nir_lower_var_copies
);
2804 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2805 NIR_PASS_V(nir
, nir_lower_var_copies
);
2806 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2808 unsigned pan_quirks
= panfrost_get_quirks(gpu_id
);
2809 NIR_PASS_V(nir
, pan_lower_framebuffer
,
2810 program
->rt_formats
, is_blend
, pan_quirks
);
2812 NIR_PASS_V(nir
, nir_lower_io
, nir_var_shader_in
| nir_var_shader_out
,
2814 NIR_PASS_V(nir
, nir_lower_ssbo
);
2815 NIR_PASS_V(nir
, midgard_nir_lower_zs_store
);
2817 /* Optimisation passes */
2819 optimise_nir(nir
, ctx
->quirks
, is_blend
);
2821 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2822 nir_print_shader(nir
, stdout
);
2825 /* Assign sysvals and counts, now that we're sure
2826 * (post-optimisation) */
2828 panfrost_nir_assign_sysvals(&ctx
->sysvals
, nir
);
2829 program
->sysval_count
= ctx
->sysvals
.sysval_count
;
2830 memcpy(program
->sysvals
, ctx
->sysvals
.sysvals
, sizeof(ctx
->sysvals
.sysvals
[0]) * ctx
->sysvals
.sysval_count
);
2832 nir_foreach_function(func
, nir
) {
2836 list_inithead(&ctx
->blocks
);
2837 ctx
->block_count
= 0;
2839 ctx
->already_emitted
= calloc(BITSET_WORDS(func
->impl
->ssa_alloc
), sizeof(BITSET_WORD
));
2841 if (nir
->info
.outputs_read
&& !is_blend
) {
2842 emit_block_init(ctx
);
2844 struct midgard_instruction wait
= v_branch(false, false);
2845 wait
.branch
.target_type
= TARGET_TILEBUF_WAIT
;
2847 emit_mir_instruction(ctx
, wait
);
2849 ++ctx
->instruction_count
;
2852 emit_cf_list(ctx
, &func
->impl
->body
);
2853 free(ctx
->already_emitted
);
2854 break; /* TODO: Multi-function shaders */
2857 util_dynarray_init(compiled
, NULL
);
2859 /* Per-block lowering before opts */
2861 mir_foreach_block(ctx
, _block
) {
2862 midgard_block
*block
= (midgard_block
*) _block
;
2863 inline_alu_constants(ctx
, block
);
2864 embedded_to_inline_constant(ctx
, block
);
2866 /* MIR-level optimizations */
2868 bool progress
= false;
2872 progress
|= midgard_opt_dead_code_eliminate(ctx
);
2874 mir_foreach_block(ctx
, _block
) {
2875 midgard_block
*block
= (midgard_block
*) _block
;
2876 progress
|= midgard_opt_copy_prop(ctx
, block
);
2877 progress
|= midgard_opt_combine_projection(ctx
, block
);
2878 progress
|= midgard_opt_varying_projection(ctx
, block
);
2882 mir_foreach_block(ctx
, _block
) {
2883 midgard_block
*block
= (midgard_block
*) _block
;
2884 midgard_lower_derivatives(ctx
, block
);
2885 midgard_legalize_invert(ctx
, block
);
2886 midgard_cull_dead_branch(ctx
, block
);
2889 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
2890 mir_add_writeout_loops(ctx
);
2892 /* Analyze now that the code is known but before scheduling creates
2893 * pipeline registers which are harder to track */
2894 mir_analyze_helper_terminate(ctx
);
2895 mir_analyze_helper_requirements(ctx
);
2898 midgard_schedule_program(ctx
);
2901 /* Now that all the bundles are scheduled and we can calculate block
2902 * sizes, emit actual branch instructions rather than placeholders */
2904 int br_block_idx
= 0;
2906 mir_foreach_block(ctx
, _block
) {
2907 midgard_block
*block
= (midgard_block
*) _block
;
2908 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2909 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2910 midgard_instruction
*ins
= bundle
->instructions
[c
];
2912 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2914 /* Parse some basic branch info */
2915 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2916 bool is_conditional
= ins
->branch
.conditional
;
2917 bool is_inverted
= ins
->branch
.invert_conditional
;
2918 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2919 bool is_tilebuf_wait
= ins
->branch
.target_type
== TARGET_TILEBUF_WAIT
;
2920 bool is_special
= is_discard
|| is_tilebuf_wait
;
2921 bool is_writeout
= ins
->writeout
;
2923 /* Determine the block we're jumping to */
2924 int target_number
= ins
->branch
.target_block
;
2926 /* Report the destination tag */
2927 int dest_tag
= is_discard
? 0 :
2928 is_tilebuf_wait
? bundle
->tag
:
2929 midgard_get_first_tag_from_block(ctx
, target_number
);
2931 /* Count up the number of quadwords we're
2932 * jumping over = number of quadwords until
2933 * (br_block_idx, target_number) */
2935 int quadword_offset
= 0;
2939 } else if (is_tilebuf_wait
) {
2940 quadword_offset
= -1;
2941 } else if (target_number
> br_block_idx
) {
2944 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2945 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2948 quadword_offset
+= blk
->quadword_count
;
2951 /* Jump backwards */
2953 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2954 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2957 quadword_offset
-= blk
->quadword_count
;
2961 /* Unconditional extended branches (far jumps)
2962 * have issues, so we always use a conditional
2963 * branch, setting the condition to always for
2964 * unconditional. For compact unconditional
2965 * branches, cond isn't used so it doesn't
2966 * matter what we pick. */
2968 midgard_condition cond
=
2969 !is_conditional
? midgard_condition_always
:
2970 is_inverted
? midgard_condition_false
:
2971 midgard_condition_true
;
2973 midgard_jmp_writeout_op op
=
2974 is_discard
? midgard_jmp_writeout_op_discard
:
2975 is_tilebuf_wait
? midgard_jmp_writeout_op_tilebuffer_pending
:
2976 is_writeout
? midgard_jmp_writeout_op_writeout
:
2977 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2978 midgard_jmp_writeout_op_branch_cond
;
2981 midgard_branch_extended branch
=
2982 midgard_create_branch_extended(
2987 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2988 } else if (is_conditional
|| is_special
) {
2989 midgard_branch_cond branch
= {
2991 .dest_tag
= dest_tag
,
2992 .offset
= quadword_offset
,
2996 assert(branch
.offset
== quadword_offset
);
2998 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3000 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
3002 midgard_branch_uncond branch
= {
3004 .dest_tag
= dest_tag
,
3005 .offset
= quadword_offset
,
3009 assert(branch
.offset
== quadword_offset
);
3011 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3019 /* Emit flat binary from the instruction arrays. Iterate each block in
3020 * sequence. Save instruction boundaries such that lookahead tags can
3021 * be assigned easily */
3023 /* Cache _all_ bundles in source order for lookahead across failed branches */
3025 int bundle_count
= 0;
3026 mir_foreach_block(ctx
, _block
) {
3027 midgard_block
*block
= (midgard_block
*) _block
;
3028 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3030 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3032 mir_foreach_block(ctx
, _block
) {
3033 midgard_block
*block
= (midgard_block
*) _block
;
3034 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3035 source_order_bundles
[bundle_idx
++] = bundle
;
3039 int current_bundle
= 0;
3041 /* Midgard prefetches instruction types, so during emission we
3042 * need to lookahead. Unless this is the last instruction, in
3043 * which we return 1. */
3045 mir_foreach_block(ctx
, _block
) {
3046 midgard_block
*block
= (midgard_block
*) _block
;
3047 mir_foreach_bundle_in_block(block
, bundle
) {
3050 if (!bundle
->last_writeout
&& (current_bundle
+ 1 < bundle_count
))
3051 lookahead
= source_order_bundles
[current_bundle
+ 1]->tag
;
3053 emit_binary_bundle(ctx
, block
, bundle
, compiled
, lookahead
);
3057 /* TODO: Free deeper */
3058 //util_dynarray_fini(&block->instructions);
3061 free(source_order_bundles
);
3063 /* Report the very first tag executed */
3064 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3066 /* Deal with off-by-one related to the fencepost problem */
3067 program
->work_register_count
= ctx
->work_registers
+ 1;
3068 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3070 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3071 program
->tls_size
= ctx
->tls_size
;
3073 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3074 disassemble_midgard(stdout
, program
->compiled
.data
, program
->compiled
.size
, gpu_id
, ctx
->stage
);
3076 if (midgard_debug
& MIDGARD_DBG_SHADERDB
|| shaderdb
) {
3077 unsigned nr_bundles
= 0, nr_ins
= 0;
3079 /* Count instructions and bundles */
3081 mir_foreach_block(ctx
, _block
) {
3082 midgard_block
*block
= (midgard_block
*) _block
;
3083 nr_bundles
+= util_dynarray_num_elements(
3084 &block
->bundles
, midgard_bundle
);
3086 mir_foreach_bundle_in_block(block
, bun
)
3087 nr_ins
+= bun
->instruction_count
;
3090 /* Calculate thread count. There are certain cutoffs by
3091 * register count for thread count */
3093 unsigned nr_registers
= program
->work_register_count
;
3095 unsigned nr_threads
=
3096 (nr_registers
<= 4) ? 4 :
3097 (nr_registers
<= 8) ? 2 :
3102 fprintf(stderr
, "shader%d - %s shader: "
3103 "%u inst, %u bundles, %u quadwords, "
3104 "%u registers, %u threads, %u loops, "
3105 "%u:%u spills:fills\n",
3107 ctx
->is_blend
? "PAN_SHADER_BLEND" :
3108 gl_shader_stage_name(ctx
->stage
),
3109 nr_ins
, nr_bundles
, ctx
->quadword_count
,
3110 nr_registers
, nr_threads
,
3112 ctx
->spills
, ctx
->fills
);