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pan/mdg: Ingest fsat_signed/fclamp_pos
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 } else { \
121 i.dest = ssa; \
122 i.dest_type = T; \
123 } \
124 return i; \
125 }
126
127 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
128 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
129
130 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
131 * the corresponding Midgard source */
132
133 static midgard_vector_alu_src
134 vector_alu_modifiers(bool abs, bool neg, bool is_int,
135 bool half, bool sext)
136 {
137 /* Figure out how many components there are so we can adjust.
138 * Specifically we want to broadcast the last channel so things like
139 * ball2/3 work.
140 */
141
142 midgard_vector_alu_src alu_src = {
143 .rep_low = 0,
144 .rep_high = 0,
145 .half = half
146 };
147
148 if (is_int) {
149 alu_src.mod = midgard_int_normal;
150
151 /* Sign/zero-extend if needed */
152
153 if (half) {
154 alu_src.mod = sext ?
155 midgard_int_sign_extend
156 : midgard_int_zero_extend;
157 }
158
159 /* These should have been lowered away */
160 assert(!(abs || neg));
161 } else {
162 alu_src.mod = (abs << 0) | (neg << 1);
163 }
164
165 return alu_src;
166 }
167
168 M_LOAD(ld_attr_32, nir_type_uint32);
169 M_LOAD(ld_vary_32, nir_type_uint32);
170 M_LOAD(ld_ubo_int4, nir_type_uint32);
171 M_LOAD(ld_int4, nir_type_uint32);
172 M_STORE(st_int4, nir_type_uint32);
173 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
174 M_STORE(st_vary_32, nir_type_uint32);
175 M_LOAD(ld_cubemap_coords, nir_type_uint32);
176 M_LOAD(ld_compute_id, nir_type_uint32);
177
178 static midgard_instruction
179 v_branch(bool conditional, bool invert)
180 {
181 midgard_instruction ins = {
182 .type = TAG_ALU_4,
183 .unit = ALU_ENAB_BRANCH,
184 .compact_branch = true,
185 .branch = {
186 .conditional = conditional,
187 .invert_conditional = invert
188 },
189 .dest = ~0,
190 .src = { ~0, ~0, ~0, ~0 },
191 };
192
193 return ins;
194 }
195
196 static midgard_branch_extended
197 midgard_create_branch_extended( midgard_condition cond,
198 midgard_jmp_writeout_op op,
199 unsigned dest_tag,
200 signed quadword_offset)
201 {
202 /* The condition code is actually a LUT describing a function to
203 * combine multiple condition codes. However, we only support a single
204 * condition code at the moment, so we just duplicate over a bunch of
205 * times. */
206
207 uint16_t duplicated_cond =
208 (cond << 14) |
209 (cond << 12) |
210 (cond << 10) |
211 (cond << 8) |
212 (cond << 6) |
213 (cond << 4) |
214 (cond << 2) |
215 (cond << 0);
216
217 midgard_branch_extended branch = {
218 .op = op,
219 .dest_tag = dest_tag,
220 .offset = quadword_offset,
221 .cond = duplicated_cond
222 };
223
224 return branch;
225 }
226
227 static void
228 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
229 {
230 ins->has_constants = true;
231 memcpy(&ins->constants, constants, 16);
232 }
233
234 static int
235 glsl_type_size(const struct glsl_type *type, bool bindless)
236 {
237 return glsl_count_attribute_slots(type, false);
238 }
239
240 /* Lower fdot2 to a vector multiplication followed by channel addition */
241 static void
242 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
243 {
244 if (alu->op != nir_op_fdot2)
245 return;
246
247 b->cursor = nir_before_instr(&alu->instr);
248
249 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
250 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
251
252 nir_ssa_def *product = nir_fmul(b, src0, src1);
253
254 nir_ssa_def *sum = nir_fadd(b,
255 nir_channel(b, product, 0),
256 nir_channel(b, product, 1));
257
258 /* Replace the fdot2 with this sum */
259 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
260 }
261
262 static bool
263 midgard_nir_lower_fdot2(nir_shader *shader)
264 {
265 bool progress = false;
266
267 nir_foreach_function(function, shader) {
268 if (!function->impl) continue;
269
270 nir_builder _b;
271 nir_builder *b = &_b;
272 nir_builder_init(b, function->impl);
273
274 nir_foreach_block(block, function->impl) {
275 nir_foreach_instr_safe(instr, block) {
276 if (instr->type != nir_instr_type_alu) continue;
277
278 nir_alu_instr *alu = nir_instr_as_alu(instr);
279 midgard_nir_lower_fdot2_body(b, alu);
280
281 progress |= true;
282 }
283 }
284
285 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
286
287 }
288
289 return progress;
290 }
291
292 /* Midgard can't write depth and stencil separately. It has to happen in a
293 * single store operation containing both. Let's add a panfrost specific
294 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
295 * one.
296 */
297 static bool
298 midgard_nir_lower_zs_store(nir_shader *nir)
299 {
300 if (nir->info.stage != MESA_SHADER_FRAGMENT)
301 return false;
302
303 nir_variable *z_var = NULL, *s_var = NULL;
304
305 nir_foreach_variable(var, &nir->outputs) {
306 if (var->data.location == FRAG_RESULT_DEPTH)
307 z_var = var;
308 else if (var->data.location == FRAG_RESULT_STENCIL)
309 s_var = var;
310 }
311
312 if (!z_var && !s_var)
313 return false;
314
315 bool progress = false;
316
317 nir_foreach_function(function, nir) {
318 if (!function->impl) continue;
319
320 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
321
322 nir_foreach_block(block, function->impl) {
323 nir_foreach_instr_safe(instr, block) {
324 if (instr->type != nir_instr_type_intrinsic)
325 continue;
326
327 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
328 if (intr->intrinsic != nir_intrinsic_store_output)
329 continue;
330
331 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
332 assert(!z_store);
333 z_store = intr;
334 last_store = intr;
335 }
336
337 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
338 assert(!s_store);
339 s_store = intr;
340 last_store = intr;
341 }
342 }
343 }
344
345 if (!z_store && !s_store) continue;
346
347 nir_builder b;
348 nir_builder_init(&b, function->impl);
349
350 b.cursor = nir_before_instr(&last_store->instr);
351
352 nir_ssa_def *zs_store_src;
353
354 if (z_store && s_store) {
355 nir_ssa_def *srcs[2] = {
356 nir_ssa_for_src(&b, z_store->src[0], 1),
357 nir_ssa_for_src(&b, s_store->src[0], 1),
358 };
359
360 zs_store_src = nir_vec(&b, srcs, 2);
361 } else {
362 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
363 }
364
365 nir_intrinsic_instr *zs_store;
366
367 zs_store = nir_intrinsic_instr_create(b.shader,
368 nir_intrinsic_store_zs_output_pan);
369 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
370 zs_store->num_components = z_store && s_store ? 2 : 1;
371 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
372
373 /* Replace the Z and S store by a ZS store */
374 nir_builder_instr_insert(&b, &zs_store->instr);
375
376 if (z_store)
377 nir_instr_remove(&z_store->instr);
378
379 if (s_store)
380 nir_instr_remove(&s_store->instr);
381
382 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
383 progress = true;
384 }
385
386 return progress;
387 }
388
389 /* Flushes undefined values to zero */
390
391 static void
392 optimise_nir(nir_shader *nir, unsigned quirks)
393 {
394 bool progress;
395 unsigned lower_flrp =
396 (nir->options->lower_flrp16 ? 16 : 0) |
397 (nir->options->lower_flrp32 ? 32 : 0) |
398 (nir->options->lower_flrp64 ? 64 : 0);
399
400 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
401 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
402
403 nir_lower_tex_options lower_tex_options = {
404 .lower_txs_lod = true,
405 .lower_txp = ~0,
406 .lower_tex_without_implicit_lod =
407 (quirks & MIDGARD_EXPLICIT_LOD),
408
409 /* TODO: we have native gradient.. */
410 .lower_txd = true,
411 };
412
413 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
414
415 /* Must lower fdot2 after tex is lowered */
416 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
417
418 /* T720 is broken. */
419
420 if (quirks & MIDGARD_BROKEN_LOD)
421 NIR_PASS_V(nir, midgard_nir_lod_errata);
422
423 do {
424 progress = false;
425
426 NIR_PASS(progress, nir, nir_lower_var_copies);
427 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
428
429 NIR_PASS(progress, nir, nir_copy_prop);
430 NIR_PASS(progress, nir, nir_opt_remove_phis);
431 NIR_PASS(progress, nir, nir_opt_dce);
432 NIR_PASS(progress, nir, nir_opt_dead_cf);
433 NIR_PASS(progress, nir, nir_opt_cse);
434 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
435 NIR_PASS(progress, nir, nir_opt_algebraic);
436 NIR_PASS(progress, nir, nir_opt_constant_folding);
437
438 if (lower_flrp != 0) {
439 bool lower_flrp_progress = false;
440 NIR_PASS(lower_flrp_progress,
441 nir,
442 nir_lower_flrp,
443 lower_flrp,
444 false /* always_precise */,
445 nir->options->lower_ffma);
446 if (lower_flrp_progress) {
447 NIR_PASS(progress, nir,
448 nir_opt_constant_folding);
449 progress = true;
450 }
451
452 /* Nothing should rematerialize any flrps, so we only
453 * need to do this lowering once.
454 */
455 lower_flrp = 0;
456 }
457
458 NIR_PASS(progress, nir, nir_opt_undef);
459 NIR_PASS(progress, nir, nir_undef_to_zero);
460
461 NIR_PASS(progress, nir, nir_opt_loop_unroll,
462 nir_var_shader_in |
463 nir_var_shader_out |
464 nir_var_function_temp);
465
466 NIR_PASS(progress, nir, nir_opt_vectorize);
467 } while (progress);
468
469 /* Must be run at the end to prevent creation of fsin/fcos ops */
470 NIR_PASS(progress, nir, midgard_nir_scale_trig);
471
472 do {
473 progress = false;
474
475 NIR_PASS(progress, nir, nir_opt_dce);
476 NIR_PASS(progress, nir, nir_opt_algebraic);
477 NIR_PASS(progress, nir, nir_opt_constant_folding);
478 NIR_PASS(progress, nir, nir_copy_prop);
479 } while (progress);
480
481 NIR_PASS(progress, nir, nir_opt_algebraic_late);
482 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
483
484 /* We implement booleans as 32-bit 0/~0 */
485 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
486
487 /* Now that booleans are lowered, we can run out late opts */
488 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
489
490 NIR_PASS(progress, nir, nir_copy_prop);
491 NIR_PASS(progress, nir, nir_opt_dce);
492
493 /* Take us out of SSA */
494 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
495 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
496
497 /* We are a vector architecture; write combine where possible */
498 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
499 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
500
501 NIR_PASS(progress, nir, nir_opt_dce);
502 }
503
504 /* Do not actually emit a load; instead, cache the constant for inlining */
505
506 static void
507 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
508 {
509 nir_ssa_def def = instr->def;
510
511 midgard_constants *consts = rzalloc(NULL, midgard_constants);
512
513 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
514
515 #define RAW_CONST_COPY(bits) \
516 nir_const_value_to_array(consts->u##bits, instr->value, \
517 instr->def.num_components, u##bits)
518
519 switch (instr->def.bit_size) {
520 case 64:
521 RAW_CONST_COPY(64);
522 break;
523 case 32:
524 RAW_CONST_COPY(32);
525 break;
526 case 16:
527 RAW_CONST_COPY(16);
528 break;
529 case 8:
530 RAW_CONST_COPY(8);
531 break;
532 default:
533 unreachable("Invalid bit_size for load_const instruction\n");
534 }
535
536 /* Shifted for SSA, +1 for off-by-one */
537 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
538 }
539
540 /* Normally constants are embedded implicitly, but for I/O and such we have to
541 * explicitly emit a move with the constant source */
542
543 static void
544 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
545 {
546 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
547
548 if (constant_value) {
549 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
550 attach_constants(ctx, &ins, constant_value, node + 1);
551 emit_mir_instruction(ctx, ins);
552 }
553 }
554
555 static bool
556 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
557 {
558 unsigned comp = src->swizzle[0];
559
560 for (unsigned c = 1; c < nr_components; ++c) {
561 if (src->swizzle[c] != comp)
562 return true;
563 }
564
565 return false;
566 }
567
568 #define ALU_CASE(nir, _op) \
569 case nir_op_##nir: \
570 op = midgard_alu_op_##_op; \
571 assert(src_bitsize == dst_bitsize); \
572 break;
573
574 #define ALU_CASE_BCAST(nir, _op, count) \
575 case nir_op_##nir: \
576 op = midgard_alu_op_##_op; \
577 broadcast_swizzle = count; \
578 assert(src_bitsize == dst_bitsize); \
579 break;
580 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
581 * special treatment override this anyway. */
582
583 static midgard_reg_mode
584 reg_mode_for_nir(nir_alu_instr *instr)
585 {
586 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
587
588 switch (src_bitsize) {
589 case 8:
590 return midgard_reg_mode_8;
591 case 16:
592 return midgard_reg_mode_16;
593 case 32:
594 return midgard_reg_mode_32;
595 case 64:
596 return midgard_reg_mode_64;
597 default:
598 unreachable("Invalid bit size");
599 }
600 }
601
602 static void
603 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool is_int, unsigned bcast_count)
604 {
605 nir_alu_src src = instr->src[i];
606 unsigned bits = nir_src_bit_size(src.src);
607
608 ins->src[to] = nir_src_index(NULL, &src.src);
609 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
610
611 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
612 ins->swizzle[to][c] = src.swizzle[
613 (!bcast_count || c < bcast_count) ? c :
614 (bcast_count - 1)];
615 }
616 }
617
618 static void
619 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
620 {
621 nir_dest *dest = &instr->dest.dest;
622
623 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index))
624 return;
625
626 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
627 * is handled elsewhere */
628
629 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
630 midgard_emit_derivatives(ctx, instr);
631 return;
632 }
633
634 bool is_ssa = dest->is_ssa;
635
636 unsigned nr_components = nir_dest_num_components(*dest);
637 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
638 unsigned op = 0;
639
640 /* Number of components valid to check for the instruction (the rest
641 * will be forced to the last), or 0 to use as-is. Relevant as
642 * ball-type instructions have a channel count in NIR but are all vec4
643 * in Midgard */
644
645 unsigned broadcast_swizzle = 0;
646
647 /* What register mode should we operate in? */
648 midgard_reg_mode reg_mode =
649 reg_mode_for_nir(instr);
650
651 /* Do we need a destination override? Used for inline
652 * type conversion */
653
654 midgard_dest_override dest_override =
655 midgard_dest_override_none;
656
657 /* Should we use a smaller respective source and sign-extend? */
658
659 bool half_1 = false, sext_1 = false;
660 bool half_2 = false, sext_2 = false;
661
662 /* Should we swap arguments? */
663 bool flip_src12 = false;
664
665 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
666 unsigned dst_bitsize = nir_dest_bit_size(*dest);
667
668 switch (instr->op) {
669 ALU_CASE(fadd, fadd);
670 ALU_CASE(fmul, fmul);
671 ALU_CASE(fmin, fmin);
672 ALU_CASE(fmax, fmax);
673 ALU_CASE(imin, imin);
674 ALU_CASE(imax, imax);
675 ALU_CASE(umin, umin);
676 ALU_CASE(umax, umax);
677 ALU_CASE(ffloor, ffloor);
678 ALU_CASE(fround_even, froundeven);
679 ALU_CASE(ftrunc, ftrunc);
680 ALU_CASE(fceil, fceil);
681 ALU_CASE(fdot3, fdot3);
682 ALU_CASE(fdot4, fdot4);
683 ALU_CASE(iadd, iadd);
684 ALU_CASE(isub, isub);
685 ALU_CASE(imul, imul);
686
687 /* Zero shoved as second-arg */
688 ALU_CASE(iabs, iabsdiff);
689
690 ALU_CASE(mov, imov);
691
692 ALU_CASE(feq32, feq);
693 ALU_CASE(fne32, fne);
694 ALU_CASE(flt32, flt);
695 ALU_CASE(ieq32, ieq);
696 ALU_CASE(ine32, ine);
697 ALU_CASE(ilt32, ilt);
698 ALU_CASE(ult32, ult);
699
700 /* We don't have a native b2f32 instruction. Instead, like many
701 * GPUs, we exploit booleans as 0/~0 for false/true, and
702 * correspondingly AND
703 * by 1.0 to do the type conversion. For the moment, prime us
704 * to emit:
705 *
706 * iand [whatever], #0
707 *
708 * At the end of emit_alu (as MIR), we'll fix-up the constant
709 */
710
711 ALU_CASE(b2f32, iand);
712 ALU_CASE(b2i32, iand);
713
714 /* Likewise, we don't have a dedicated f2b32 instruction, but
715 * we can do a "not equal to 0.0" test. */
716
717 ALU_CASE(f2b32, fne);
718 ALU_CASE(i2b32, ine);
719
720 ALU_CASE(frcp, frcp);
721 ALU_CASE(frsq, frsqrt);
722 ALU_CASE(fsqrt, fsqrt);
723 ALU_CASE(fexp2, fexp2);
724 ALU_CASE(flog2, flog2);
725
726 ALU_CASE(f2i64, f2i_rtz);
727 ALU_CASE(f2u64, f2u_rtz);
728 ALU_CASE(i2f64, i2f_rtz);
729 ALU_CASE(u2f64, u2f_rtz);
730
731 ALU_CASE(f2i32, f2i_rtz);
732 ALU_CASE(f2u32, f2u_rtz);
733 ALU_CASE(i2f32, i2f_rtz);
734 ALU_CASE(u2f32, u2f_rtz);
735
736 ALU_CASE(f2i16, f2i_rtz);
737 ALU_CASE(f2u16, f2u_rtz);
738 ALU_CASE(i2f16, i2f_rtz);
739 ALU_CASE(u2f16, u2f_rtz);
740
741 ALU_CASE(fsin, fsin);
742 ALU_CASE(fcos, fcos);
743
744 /* We'll set invert */
745 ALU_CASE(inot, imov);
746 ALU_CASE(iand, iand);
747 ALU_CASE(ior, ior);
748 ALU_CASE(ixor, ixor);
749 ALU_CASE(ishl, ishl);
750 ALU_CASE(ishr, iasr);
751 ALU_CASE(ushr, ilsr);
752
753 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
754 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
755 ALU_CASE(b32all_fequal4, fball_eq);
756
757 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
758 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
759 ALU_CASE(b32any_fnequal4, fbany_neq);
760
761 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
762 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
763 ALU_CASE(b32all_iequal4, iball_eq);
764
765 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
766 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
767 ALU_CASE(b32any_inequal4, ibany_neq);
768
769 /* Source mods will be shoved in later */
770 ALU_CASE(fabs, fmov);
771 ALU_CASE(fneg, fmov);
772 ALU_CASE(fsat, fmov);
773 ALU_CASE(fsat_signed, fmov);
774 ALU_CASE(fclamp_pos, fmov);
775
776 /* For size conversion, we use a move. Ideally though we would squash
777 * these ops together; maybe that has to happen after in NIR as part of
778 * propagation...? An earlier algebraic pass ensured we step down by
779 * only / exactly one size. If stepping down, we use a dest override to
780 * reduce the size; if stepping up, we use a larger-sized move with a
781 * half source and a sign/zero-extension modifier */
782
783 case nir_op_i2i8:
784 case nir_op_i2i16:
785 case nir_op_i2i32:
786 case nir_op_i2i64:
787 /* If we end up upscale, we'll need a sign-extend on the
788 * operand (the second argument) */
789
790 sext_2 = true;
791 /* fallthrough */
792 case nir_op_u2u8:
793 case nir_op_u2u16:
794 case nir_op_u2u32:
795 case nir_op_u2u64:
796 case nir_op_f2f16:
797 case nir_op_f2f32:
798 case nir_op_f2f64: {
799 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
800 instr->op == nir_op_f2f64)
801 op = midgard_alu_op_fmov;
802 else
803 op = midgard_alu_op_imov;
804
805 if (dst_bitsize == (src_bitsize * 2)) {
806 /* Converting up */
807 half_2 = true;
808
809 /* Use a greater register mode */
810 reg_mode++;
811 } else if (src_bitsize == (dst_bitsize * 2)) {
812 /* Converting down */
813 dest_override = midgard_dest_override_lower;
814 }
815
816 break;
817 }
818
819 /* For greater-or-equal, we lower to less-or-equal and flip the
820 * arguments */
821
822 case nir_op_fge:
823 case nir_op_fge32:
824 case nir_op_ige32:
825 case nir_op_uge32: {
826 op =
827 instr->op == nir_op_fge ? midgard_alu_op_fle :
828 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
829 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
830 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
831 0;
832
833 flip_src12 = true;
834 break;
835 }
836
837 case nir_op_b32csel: {
838 /* Midgard features both fcsel and icsel, depending on
839 * the type of the arguments/output. However, as long
840 * as we're careful we can _always_ use icsel and
841 * _never_ need fcsel, since the latter does additional
842 * floating-point-specific processing whereas the
843 * former just moves bits on the wire. It's not obvious
844 * why these are separate opcodes, save for the ability
845 * to do things like sat/pos/abs/neg for free */
846
847 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
848 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
849
850 break;
851 }
852
853 default:
854 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
855 assert(0);
856 return;
857 }
858
859 /* Midgard can perform certain modifiers on output of an ALU op */
860
861 unsigned outmod = 0;
862
863 bool abs[4] = { false };
864 bool neg[4] = { false };
865 bool is_int = midgard_is_integer_op(op);
866
867 if (midgard_is_integer_out_op(op)) {
868 outmod = midgard_outmod_int_wrap;
869 } else if (instr->op == nir_op_fsat) {
870 outmod = midgard_outmod_sat;
871 } else if (instr->op == nir_op_fsat_signed) {
872 outmod = midgard_outmod_sat_signed;
873 } else if (instr->op == nir_op_fclamp_pos) {
874 outmod = midgard_outmod_pos;
875 }
876
877 /* Fetch unit, quirks, etc information */
878 unsigned opcode_props = alu_opcode_props[op].props;
879 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
880
881 midgard_instruction ins = {
882 .type = TAG_ALU_4,
883 .dest = nir_dest_index(dest),
884 .dest_type = nir_op_infos[instr->op].output_type
885 | nir_dest_bit_size(*dest),
886 };
887
888 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
889 ins.src[i] = ~0;
890
891 if (quirk_flipped_r24) {
892 ins.src[0] = ~0;
893 mir_copy_src(&ins, instr, 0, 1, &abs[1], &neg[1], is_int, broadcast_swizzle);
894 } else {
895 for (unsigned i = 0; i < nr_inputs; ++i) {
896 unsigned to = i;
897
898 if (instr->op == nir_op_b32csel) {
899 /* The condition is the first argument; move
900 * the other arguments up one to be a binary
901 * instruction for Midgard with the condition
902 * last */
903
904 if (i == 0)
905 to = 2;
906 else
907 to = i - 1;
908 } else if (flip_src12) {
909 to = 1 - to;
910 }
911
912 mir_copy_src(&ins, instr, i, to, &abs[to], &neg[to], is_int, broadcast_swizzle);
913 }
914 }
915
916 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
917 /* Lowered to move */
918 if (instr->op == nir_op_fneg)
919 neg[1] = !neg[1];
920
921 if (instr->op == nir_op_fabs)
922 abs[1] = true;
923 }
924
925 ins.mask = mask_of(nr_components);
926
927 midgard_vector_alu alu = {
928 .op = op,
929 .reg_mode = reg_mode,
930 .dest_override = dest_override,
931 .outmod = outmod,
932
933 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(abs[0], neg[0], is_int, half_1, sext_1)),
934 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(abs[1], neg[1], is_int, half_2, sext_2)),
935 };
936
937 /* Apply writemask if non-SSA, keeping in mind that we can't write to
938 * components that don't exist. Note modifier => SSA => !reg => no
939 * writemask, so we don't have to worry about writemasks here.*/
940
941 if (!is_ssa)
942 ins.mask &= instr->dest.write_mask;
943
944 ins.alu = alu;
945
946 /* Late fixup for emulated instructions */
947
948 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
949 /* Presently, our second argument is an inline #0 constant.
950 * Switch over to an embedded 1.0 constant (that can't fit
951 * inline, since we're 32-bit, not 16-bit like the inline
952 * constants) */
953
954 ins.has_inline_constant = false;
955 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
956 ins.src_types[1] = nir_type_float32;
957 ins.has_constants = true;
958
959 if (instr->op == nir_op_b2f32)
960 ins.constants.f32[0] = 1.0f;
961 else
962 ins.constants.i32[0] = 1;
963
964 for (unsigned c = 0; c < 16; ++c)
965 ins.swizzle[1][c] = 0;
966 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
967 /* Lots of instructions need a 0 plonked in */
968 ins.has_inline_constant = false;
969 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
970 ins.src_types[1] = nir_type_uint32;
971 ins.has_constants = true;
972 ins.constants.u32[0] = 0;
973
974 for (unsigned c = 0; c < 16; ++c)
975 ins.swizzle[1][c] = 0;
976 } else if (instr->op == nir_op_inot) {
977 ins.invert = true;
978 }
979
980 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
981 /* To avoid duplicating the lookup tables (probably), true LUT
982 * instructions can only operate as if they were scalars. Lower
983 * them here by changing the component. */
984
985 unsigned orig_mask = ins.mask;
986
987 unsigned swizzle_back[MIR_VEC_COMPONENTS];
988 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
989
990 for (int i = 0; i < nr_components; ++i) {
991 /* Mask the associated component, dropping the
992 * instruction if needed */
993
994 ins.mask = 1 << i;
995 ins.mask &= orig_mask;
996
997 if (!ins.mask)
998 continue;
999
1000 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1001 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1002
1003 emit_mir_instruction(ctx, ins);
1004 }
1005 } else {
1006 emit_mir_instruction(ctx, ins);
1007 }
1008 }
1009
1010 #undef ALU_CASE
1011
1012 static void
1013 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1014 {
1015 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1016 unsigned nir_mask = 0;
1017 unsigned dsize = 0;
1018
1019 if (is_read) {
1020 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1021 dsize = nir_dest_bit_size(intr->dest);
1022 } else {
1023 nir_mask = nir_intrinsic_write_mask(intr);
1024 dsize = 32;
1025 }
1026
1027 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1028 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1029 mir_set_bytemask(ins, bytemask);
1030
1031 if (dsize == 64)
1032 ins->load_64 = true;
1033 }
1034
1035 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1036 * optimized) versions of UBO #0 */
1037
1038 static midgard_instruction *
1039 emit_ubo_read(
1040 compiler_context *ctx,
1041 nir_instr *instr,
1042 unsigned dest,
1043 unsigned offset,
1044 nir_src *indirect_offset,
1045 unsigned indirect_shift,
1046 unsigned index)
1047 {
1048 /* TODO: half-floats */
1049
1050 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1051 ins.constants.u32[0] = offset;
1052
1053 if (instr->type == nir_instr_type_intrinsic)
1054 mir_set_intr_mask(instr, &ins, true);
1055
1056 if (indirect_offset) {
1057 ins.src[2] = nir_src_index(ctx, indirect_offset);
1058 ins.src_types[2] = nir_type_uint32;
1059 ins.load_store.arg_2 = (indirect_shift << 5);
1060 } else {
1061 ins.load_store.arg_2 = 0x1E;
1062 }
1063
1064 ins.load_store.arg_1 = index;
1065
1066 return emit_mir_instruction(ctx, ins);
1067 }
1068
1069 /* Globals are like UBOs if you squint. And shared memory is like globals if
1070 * you squint even harder */
1071
1072 static void
1073 emit_global(
1074 compiler_context *ctx,
1075 nir_instr *instr,
1076 bool is_read,
1077 unsigned srcdest,
1078 nir_src *offset,
1079 bool is_shared)
1080 {
1081 /* TODO: types */
1082
1083 midgard_instruction ins;
1084
1085 if (is_read)
1086 ins = m_ld_int4(srcdest, 0);
1087 else
1088 ins = m_st_int4(srcdest, 0);
1089
1090 mir_set_offset(ctx, &ins, offset, is_shared);
1091 mir_set_intr_mask(instr, &ins, is_read);
1092
1093 emit_mir_instruction(ctx, ins);
1094 }
1095
1096 static void
1097 emit_varying_read(
1098 compiler_context *ctx,
1099 unsigned dest, unsigned offset,
1100 unsigned nr_comp, unsigned component,
1101 nir_src *indirect_offset, nir_alu_type type, bool flat)
1102 {
1103 /* XXX: Half-floats? */
1104 /* TODO: swizzle, mask */
1105
1106 midgard_instruction ins = m_ld_vary_32(dest, offset);
1107 ins.mask = mask_of(nr_comp);
1108
1109 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1110 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1111
1112 midgard_varying_parameter p = {
1113 .is_varying = 1,
1114 .interpolation = midgard_interp_default,
1115 .flat = flat,
1116 };
1117
1118 unsigned u;
1119 memcpy(&u, &p, sizeof(p));
1120 ins.load_store.varying_parameters = u;
1121
1122 if (indirect_offset) {
1123 ins.src[2] = nir_src_index(ctx, indirect_offset);
1124 ins.src_types[2] = nir_type_uint32;
1125 } else
1126 ins.load_store.arg_2 = 0x1E;
1127
1128 ins.load_store.arg_1 = 0x9E;
1129
1130 /* Use the type appropriate load */
1131 switch (type) {
1132 case nir_type_uint:
1133 case nir_type_bool:
1134 ins.load_store.op = midgard_op_ld_vary_32u;
1135 break;
1136 case nir_type_int:
1137 ins.load_store.op = midgard_op_ld_vary_32i;
1138 break;
1139 case nir_type_float:
1140 ins.load_store.op = midgard_op_ld_vary_32;
1141 break;
1142 default:
1143 unreachable("Attempted to load unknown type");
1144 break;
1145 }
1146
1147 emit_mir_instruction(ctx, ins);
1148 }
1149
1150 static void
1151 emit_attr_read(
1152 compiler_context *ctx,
1153 unsigned dest, unsigned offset,
1154 unsigned nr_comp, nir_alu_type t)
1155 {
1156 midgard_instruction ins = m_ld_attr_32(dest, offset);
1157 ins.load_store.arg_1 = 0x1E;
1158 ins.load_store.arg_2 = 0x1E;
1159 ins.mask = mask_of(nr_comp);
1160
1161 /* Use the type appropriate load */
1162 switch (t) {
1163 case nir_type_uint:
1164 case nir_type_bool:
1165 ins.load_store.op = midgard_op_ld_attr_32u;
1166 break;
1167 case nir_type_int:
1168 ins.load_store.op = midgard_op_ld_attr_32i;
1169 break;
1170 case nir_type_float:
1171 ins.load_store.op = midgard_op_ld_attr_32;
1172 break;
1173 default:
1174 unreachable("Attempted to load unknown type");
1175 break;
1176 }
1177
1178 emit_mir_instruction(ctx, ins);
1179 }
1180
1181 static void
1182 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1183 unsigned nr_components, unsigned offset)
1184 {
1185 nir_dest nir_dest;
1186
1187 /* Figure out which uniform this is */
1188 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1189 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1190
1191 unsigned dest = nir_dest_index(&nir_dest);
1192
1193 /* Sysvals are prefix uniforms */
1194 unsigned uniform = ((uintptr_t) val) - 1;
1195
1196 /* Emit the read itself -- this is never indirect */
1197 midgard_instruction *ins =
1198 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1199
1200 ins->mask = mask_of(nr_components);
1201 }
1202
1203 static unsigned
1204 compute_builtin_arg(nir_op op)
1205 {
1206 switch (op) {
1207 case nir_intrinsic_load_work_group_id:
1208 return 0x14;
1209 case nir_intrinsic_load_local_invocation_id:
1210 return 0x10;
1211 default:
1212 unreachable("Invalid compute paramater loaded");
1213 }
1214 }
1215
1216 static void
1217 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1218 {
1219 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1220
1221 midgard_instruction *br = ctx->writeout_branch[rt];
1222
1223 assert(!br);
1224
1225 emit_explicit_constant(ctx, src, src);
1226
1227 struct midgard_instruction ins =
1228 v_branch(false, false);
1229
1230 ins.writeout = true;
1231
1232 /* Add dependencies */
1233 ins.src[0] = src;
1234 ins.src_types[0] = nir_type_uint32;
1235 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1236 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1237
1238 /* Emit the branch */
1239 br = emit_mir_instruction(ctx, ins);
1240 schedule_barrier(ctx);
1241 ctx->writeout_branch[rt] = br;
1242
1243 /* Push our current location = current block count - 1 = where we'll
1244 * jump to. Maybe a bit too clever for my own good */
1245
1246 br->branch.target_block = ctx->block_count - 1;
1247 }
1248
1249 static void
1250 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1251 {
1252 unsigned reg = nir_dest_index(&instr->dest);
1253 midgard_instruction ins = m_ld_compute_id(reg, 0);
1254 ins.mask = mask_of(3);
1255 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1256 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1257 emit_mir_instruction(ctx, ins);
1258 }
1259
1260 static unsigned
1261 vertex_builtin_arg(nir_op op)
1262 {
1263 switch (op) {
1264 case nir_intrinsic_load_vertex_id:
1265 return PAN_VERTEX_ID;
1266 case nir_intrinsic_load_instance_id:
1267 return PAN_INSTANCE_ID;
1268 default:
1269 unreachable("Invalid vertex builtin");
1270 }
1271 }
1272
1273 static void
1274 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1275 {
1276 unsigned reg = nir_dest_index(&instr->dest);
1277 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1278 }
1279
1280 static void
1281 emit_control_barrier(compiler_context *ctx)
1282 {
1283 midgard_instruction ins = {
1284 .type = TAG_TEXTURE_4,
1285 .src = { ~0, ~0, ~0, ~0 },
1286 .texture = {
1287 .op = TEXTURE_OP_BARRIER,
1288
1289 /* TODO: optimize */
1290 .barrier_buffer = 1,
1291 .barrier_shared = 1
1292 }
1293 };
1294
1295 emit_mir_instruction(ctx, ins);
1296 }
1297
1298 static const nir_variable *
1299 search_var(struct exec_list *vars, unsigned driver_loc)
1300 {
1301 nir_foreach_variable(var, vars) {
1302 if (var->data.driver_location == driver_loc)
1303 return var;
1304 }
1305
1306 return NULL;
1307 }
1308
1309 static void
1310 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1311 {
1312 unsigned offset = 0, reg;
1313
1314 switch (instr->intrinsic) {
1315 case nir_intrinsic_discard_if:
1316 case nir_intrinsic_discard: {
1317 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1318 struct midgard_instruction discard = v_branch(conditional, false);
1319 discard.branch.target_type = TARGET_DISCARD;
1320
1321 if (conditional) {
1322 discard.src[0] = nir_src_index(ctx, &instr->src[0]);
1323 discard.src_types[0] = nir_type_uint32;
1324 }
1325
1326 emit_mir_instruction(ctx, discard);
1327 schedule_barrier(ctx);
1328
1329 break;
1330 }
1331
1332 case nir_intrinsic_load_uniform:
1333 case nir_intrinsic_load_ubo:
1334 case nir_intrinsic_load_global:
1335 case nir_intrinsic_load_shared:
1336 case nir_intrinsic_load_input:
1337 case nir_intrinsic_load_interpolated_input: {
1338 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1339 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1340 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1341 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1342 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1343 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1344
1345 /* Get the base type of the intrinsic */
1346 /* TODO: Infer type? Does it matter? */
1347 nir_alu_type t =
1348 (is_ubo || is_global || is_shared) ? nir_type_uint :
1349 (is_interp) ? nir_type_float :
1350 nir_intrinsic_type(instr);
1351
1352 t = nir_alu_type_get_base_type(t);
1353
1354 if (!(is_ubo || is_global)) {
1355 offset = nir_intrinsic_base(instr);
1356 }
1357
1358 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1359
1360 nir_src *src_offset = nir_get_io_offset_src(instr);
1361
1362 bool direct = nir_src_is_const(*src_offset);
1363 nir_src *indirect_offset = direct ? NULL : src_offset;
1364
1365 if (direct)
1366 offset += nir_src_as_uint(*src_offset);
1367
1368 /* We may need to apply a fractional offset */
1369 int component = (is_flat || is_interp) ?
1370 nir_intrinsic_component(instr) : 0;
1371 reg = nir_dest_index(&instr->dest);
1372
1373 if (is_uniform && !ctx->is_blend) {
1374 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1375 } else if (is_ubo) {
1376 nir_src index = instr->src[0];
1377
1378 /* TODO: Is indirect block number possible? */
1379 assert(nir_src_is_const(index));
1380
1381 uint32_t uindex = nir_src_as_uint(index) + 1;
1382 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1383 } else if (is_global || is_shared) {
1384 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1385 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1386 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1387 } else if (ctx->is_blend) {
1388 /* For blend shaders, load the input color, which is
1389 * preloaded to r0 */
1390
1391 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1392 emit_mir_instruction(ctx, move);
1393 schedule_barrier(ctx);
1394 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1395 emit_attr_read(ctx, reg, offset, nr_comp, t);
1396 } else {
1397 DBG("Unknown load\n");
1398 assert(0);
1399 }
1400
1401 break;
1402 }
1403
1404 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1405 case nir_intrinsic_load_barycentric_pixel:
1406 case nir_intrinsic_load_barycentric_centroid:
1407 break;
1408
1409 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1410
1411 case nir_intrinsic_load_raw_output_pan:
1412 case nir_intrinsic_load_output_u8_as_fp16_pan:
1413 reg = nir_dest_index(&instr->dest);
1414 assert(ctx->is_blend);
1415
1416 /* T720 and below use different blend opcodes with slightly
1417 * different semantics than T760 and up */
1418
1419 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1420 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1421
1422 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1423 ld.load_store.op = old_blend ?
1424 midgard_op_ld_color_buffer_u8_as_fp16_old :
1425 midgard_op_ld_color_buffer_u8_as_fp16;
1426
1427 if (old_blend) {
1428 ld.load_store.address = 1;
1429 ld.load_store.arg_2 = 0x1E;
1430 }
1431
1432 for (unsigned c = 2; c < 16; ++c)
1433 ld.swizzle[0][c] = 0;
1434 }
1435
1436 emit_mir_instruction(ctx, ld);
1437 break;
1438
1439 case nir_intrinsic_load_blend_const_color_rgba: {
1440 assert(ctx->is_blend);
1441 reg = nir_dest_index(&instr->dest);
1442
1443 /* Blend constants are embedded directly in the shader and
1444 * patched in, so we use some magic routing */
1445
1446 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1447 ins.has_constants = true;
1448 ins.has_blend_constant = true;
1449 emit_mir_instruction(ctx, ins);
1450 break;
1451 }
1452
1453 case nir_intrinsic_store_zs_output_pan: {
1454 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1455 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1456 MIDGARD_ZS_RT);
1457
1458 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1459
1460 if (!nir_intrinsic_component(instr))
1461 br->writeout_depth = true;
1462 if (nir_intrinsic_component(instr) ||
1463 instr->num_components)
1464 br->writeout_stencil = true;
1465 assert(br->writeout_depth | br->writeout_stencil);
1466 break;
1467 }
1468
1469 case nir_intrinsic_store_output:
1470 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1471
1472 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1473
1474 reg = nir_src_index(ctx, &instr->src[0]);
1475
1476 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1477 const nir_variable *var;
1478 enum midgard_rt_id rt;
1479
1480 var = search_var(&ctx->nir->outputs,
1481 nir_intrinsic_base(instr));
1482 assert(var);
1483 if (var->data.location == FRAG_RESULT_COLOR)
1484 rt = MIDGARD_COLOR_RT0;
1485 else if (var->data.location >= FRAG_RESULT_DATA0)
1486 rt = MIDGARD_COLOR_RT0 + var->data.location -
1487 FRAG_RESULT_DATA0;
1488 else
1489 assert(0);
1490
1491 emit_fragment_store(ctx, reg, rt);
1492 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1493 /* We should have been vectorized, though we don't
1494 * currently check that st_vary is emitted only once
1495 * per slot (this is relevant, since there's not a mask
1496 * parameter available on the store [set to 0 by the
1497 * blob]). We do respect the component by adjusting the
1498 * swizzle. If this is a constant source, we'll need to
1499 * emit that explicitly. */
1500
1501 emit_explicit_constant(ctx, reg, reg);
1502
1503 unsigned dst_component = nir_intrinsic_component(instr);
1504 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1505
1506 midgard_instruction st = m_st_vary_32(reg, offset);
1507 st.load_store.arg_1 = 0x9E;
1508 st.load_store.arg_2 = 0x1E;
1509
1510 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1511 case nir_type_uint:
1512 case nir_type_bool:
1513 st.load_store.op = midgard_op_st_vary_32u;
1514 break;
1515 case nir_type_int:
1516 st.load_store.op = midgard_op_st_vary_32i;
1517 break;
1518 case nir_type_float:
1519 st.load_store.op = midgard_op_st_vary_32;
1520 break;
1521 default:
1522 unreachable("Attempted to store unknown type");
1523 break;
1524 }
1525
1526 /* nir_intrinsic_component(store_intr) encodes the
1527 * destination component start. Source component offset
1528 * adjustment is taken care of in
1529 * install_registers_instr(), when offset_swizzle() is
1530 * called.
1531 */
1532 unsigned src_component = COMPONENT_X;
1533
1534 assert(nr_comp > 0);
1535 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1536 st.swizzle[0][i] = src_component;
1537 if (i >= dst_component && i < dst_component + nr_comp - 1)
1538 src_component++;
1539 }
1540
1541 emit_mir_instruction(ctx, st);
1542 } else {
1543 DBG("Unknown store\n");
1544 assert(0);
1545 }
1546
1547 break;
1548
1549 /* Special case of store_output for lowered blend shaders */
1550 case nir_intrinsic_store_raw_output_pan:
1551 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1552 reg = nir_src_index(ctx, &instr->src[0]);
1553
1554 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1555 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1556 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1557 * of:
1558 *
1559 * imov r0.xyzw, r0.xxxx
1560 */
1561
1562 unsigned expanded = make_compiler_temp(ctx);
1563
1564 midgard_instruction splatter = v_mov(reg, expanded);
1565
1566 for (unsigned c = 0; c < 16; ++c)
1567 splatter.swizzle[1][c] = 0;
1568
1569 emit_mir_instruction(ctx, splatter);
1570 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1571 } else
1572 emit_fragment_store(ctx, reg, ctx->blend_rt);
1573
1574 break;
1575
1576 case nir_intrinsic_store_global:
1577 case nir_intrinsic_store_shared:
1578 reg = nir_src_index(ctx, &instr->src[0]);
1579 emit_explicit_constant(ctx, reg, reg);
1580
1581 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1582 break;
1583
1584 case nir_intrinsic_load_ssbo_address:
1585 emit_sysval_read(ctx, &instr->instr, 1, 0);
1586 break;
1587
1588 case nir_intrinsic_get_buffer_size:
1589 emit_sysval_read(ctx, &instr->instr, 1, 8);
1590 break;
1591
1592 case nir_intrinsic_load_viewport_scale:
1593 case nir_intrinsic_load_viewport_offset:
1594 case nir_intrinsic_load_num_work_groups:
1595 case nir_intrinsic_load_sampler_lod_parameters_pan:
1596 emit_sysval_read(ctx, &instr->instr, 3, 0);
1597 break;
1598
1599 case nir_intrinsic_load_work_group_id:
1600 case nir_intrinsic_load_local_invocation_id:
1601 emit_compute_builtin(ctx, instr);
1602 break;
1603
1604 case nir_intrinsic_load_vertex_id:
1605 case nir_intrinsic_load_instance_id:
1606 emit_vertex_builtin(ctx, instr);
1607 break;
1608
1609 case nir_intrinsic_memory_barrier_buffer:
1610 case nir_intrinsic_memory_barrier_shared:
1611 break;
1612
1613 case nir_intrinsic_control_barrier:
1614 schedule_barrier(ctx);
1615 emit_control_barrier(ctx);
1616 schedule_barrier(ctx);
1617 break;
1618
1619 default:
1620 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1621 assert(0);
1622 break;
1623 }
1624 }
1625
1626 static unsigned
1627 midgard_tex_format(enum glsl_sampler_dim dim)
1628 {
1629 switch (dim) {
1630 case GLSL_SAMPLER_DIM_1D:
1631 case GLSL_SAMPLER_DIM_BUF:
1632 return MALI_TEX_1D;
1633
1634 case GLSL_SAMPLER_DIM_2D:
1635 case GLSL_SAMPLER_DIM_EXTERNAL:
1636 case GLSL_SAMPLER_DIM_RECT:
1637 return MALI_TEX_2D;
1638
1639 case GLSL_SAMPLER_DIM_3D:
1640 return MALI_TEX_3D;
1641
1642 case GLSL_SAMPLER_DIM_CUBE:
1643 return MALI_TEX_CUBE;
1644
1645 default:
1646 DBG("Unknown sampler dim type\n");
1647 assert(0);
1648 return 0;
1649 }
1650 }
1651
1652 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1653 * was successful */
1654
1655 static bool
1656 pan_attach_constant_bias(
1657 compiler_context *ctx,
1658 nir_src lod,
1659 midgard_texture_word *word)
1660 {
1661 /* To attach as constant, it has to *be* constant */
1662
1663 if (!nir_src_is_const(lod))
1664 return false;
1665
1666 float f = nir_src_as_float(lod);
1667
1668 /* Break into fixed-point */
1669 signed lod_int = f;
1670 float lod_frac = f - lod_int;
1671
1672 /* Carry over negative fractions */
1673 if (lod_frac < 0.0) {
1674 lod_int--;
1675 lod_frac += 1.0;
1676 }
1677
1678 /* Encode */
1679 word->bias = float_to_ubyte(lod_frac);
1680 word->bias_int = lod_int;
1681
1682 return true;
1683 }
1684
1685 static void
1686 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1687 unsigned midgard_texop)
1688 {
1689 /* TODO */
1690 //assert (!instr->sampler);
1691
1692 int texture_index = instr->texture_index;
1693 int sampler_index = texture_index;
1694
1695 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1696 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1697
1698 midgard_instruction ins = {
1699 .type = TAG_TEXTURE_4,
1700 .mask = 0xF,
1701 .dest = nir_dest_index(&instr->dest),
1702 .src = { ~0, ~0, ~0, ~0 },
1703 .dest_type = dest_type,
1704 .swizzle = SWIZZLE_IDENTITY_4,
1705 .texture = {
1706 .op = midgard_texop,
1707 .format = midgard_tex_format(instr->sampler_dim),
1708 .texture_handle = texture_index,
1709 .sampler_handle = sampler_index,
1710 .shadow = instr->is_shadow,
1711 }
1712 };
1713
1714 if (instr->is_shadow && !instr->is_new_style_shadow)
1715 for (int i = 0; i < 4; ++i)
1716 ins.swizzle[0][i] = COMPONENT_X;
1717
1718 /* We may need a temporary for the coordinate */
1719
1720 bool needs_temp_coord =
1721 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1722 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1723 (instr->is_shadow);
1724
1725 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1726
1727 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1728 int index = nir_src_index(ctx, &instr->src[i].src);
1729 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1730 unsigned sz = nir_src_bit_size(instr->src[i].src);
1731 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1732
1733 switch (instr->src[i].src_type) {
1734 case nir_tex_src_coord: {
1735 emit_explicit_constant(ctx, index, index);
1736
1737 unsigned coord_mask = mask_of(instr->coord_components);
1738
1739 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1740
1741 if (flip_zw)
1742 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1743
1744 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1745 /* texelFetch is undefined on samplerCube */
1746 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1747
1748 /* For cubemaps, we use a special ld/st op to
1749 * select the face and copy the xy into the
1750 * texture register */
1751
1752 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1753 ld.src[1] = index;
1754 ld.src_types[1] = T;
1755 ld.mask = 0x3; /* xy */
1756 ld.load_store.arg_1 = 0x20;
1757 ld.swizzle[1][3] = COMPONENT_X;
1758 emit_mir_instruction(ctx, ld);
1759
1760 /* xyzw -> xyxx */
1761 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1762 ins.swizzle[1][3] = COMPONENT_X;
1763 } else if (needs_temp_coord) {
1764 /* mov coord_temp, coords */
1765 midgard_instruction mov = v_mov(index, coords);
1766 mov.mask = coord_mask;
1767
1768 if (flip_zw)
1769 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1770
1771 emit_mir_instruction(ctx, mov);
1772 } else {
1773 coords = index;
1774 }
1775
1776 ins.src[1] = coords;
1777 ins.src_types[1] = T;
1778
1779 /* Texelfetch coordinates uses all four elements
1780 * (xyz/index) regardless of texture dimensionality,
1781 * which means it's necessary to zero the unused
1782 * components to keep everything happy */
1783
1784 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1785 /* mov index.zw, #0, or generalized */
1786 midgard_instruction mov =
1787 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1788 mov.has_constants = true;
1789 mov.mask = coord_mask ^ 0xF;
1790 emit_mir_instruction(ctx, mov);
1791 }
1792
1793 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1794 /* Array component in w but NIR wants it in z,
1795 * but if we have a temp coord we already fixed
1796 * that up */
1797
1798 if (nr_components == 3) {
1799 ins.swizzle[1][2] = COMPONENT_Z;
1800 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1801 } else if (nr_components == 2) {
1802 ins.swizzle[1][2] =
1803 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1804 ins.swizzle[1][3] = COMPONENT_X;
1805 } else
1806 unreachable("Invalid texture 2D components");
1807 }
1808
1809 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1810 /* We zeroed */
1811 ins.swizzle[1][2] = COMPONENT_Z;
1812 ins.swizzle[1][3] = COMPONENT_W;
1813 }
1814
1815 break;
1816 }
1817
1818 case nir_tex_src_bias:
1819 case nir_tex_src_lod: {
1820 /* Try as a constant if we can */
1821
1822 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1823 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1824 break;
1825
1826 ins.texture.lod_register = true;
1827 ins.src[2] = index;
1828 ins.src_types[2] = T;
1829
1830 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1831 ins.swizzle[2][c] = COMPONENT_X;
1832
1833 emit_explicit_constant(ctx, index, index);
1834
1835 break;
1836 };
1837
1838 case nir_tex_src_offset: {
1839 ins.texture.offset_register = true;
1840 ins.src[3] = index;
1841 ins.src_types[3] = T;
1842
1843 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1844 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
1845
1846 emit_explicit_constant(ctx, index, index);
1847 break;
1848 };
1849
1850 case nir_tex_src_comparator: {
1851 unsigned comp = COMPONENT_Z;
1852
1853 /* mov coord_temp.foo, coords */
1854 midgard_instruction mov = v_mov(index, coords);
1855 mov.mask = 1 << comp;
1856
1857 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
1858 mov.swizzle[1][i] = COMPONENT_X;
1859
1860 emit_mir_instruction(ctx, mov);
1861 break;
1862 }
1863
1864 default: {
1865 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
1866 assert(0);
1867 }
1868 }
1869 }
1870
1871 emit_mir_instruction(ctx, ins);
1872 }
1873
1874 static void
1875 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1876 {
1877 switch (instr->op) {
1878 case nir_texop_tex:
1879 case nir_texop_txb:
1880 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
1881 break;
1882 case nir_texop_txl:
1883 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
1884 break;
1885 case nir_texop_txf:
1886 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
1887 break;
1888 case nir_texop_txs:
1889 emit_sysval_read(ctx, &instr->instr, 4, 0);
1890 break;
1891 default: {
1892 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
1893 assert(0);
1894 }
1895 }
1896 }
1897
1898 static void
1899 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1900 {
1901 switch (instr->type) {
1902 case nir_jump_break: {
1903 /* Emit a branch out of the loop */
1904 struct midgard_instruction br = v_branch(false, false);
1905 br.branch.target_type = TARGET_BREAK;
1906 br.branch.target_break = ctx->current_loop_depth;
1907 emit_mir_instruction(ctx, br);
1908 break;
1909 }
1910
1911 default:
1912 DBG("Unknown jump type %d\n", instr->type);
1913 break;
1914 }
1915 }
1916
1917 static void
1918 emit_instr(compiler_context *ctx, struct nir_instr *instr)
1919 {
1920 switch (instr->type) {
1921 case nir_instr_type_load_const:
1922 emit_load_const(ctx, nir_instr_as_load_const(instr));
1923 break;
1924
1925 case nir_instr_type_intrinsic:
1926 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1927 break;
1928
1929 case nir_instr_type_alu:
1930 emit_alu(ctx, nir_instr_as_alu(instr));
1931 break;
1932
1933 case nir_instr_type_tex:
1934 emit_tex(ctx, nir_instr_as_tex(instr));
1935 break;
1936
1937 case nir_instr_type_jump:
1938 emit_jump(ctx, nir_instr_as_jump(instr));
1939 break;
1940
1941 case nir_instr_type_ssa_undef:
1942 /* Spurious */
1943 break;
1944
1945 default:
1946 DBG("Unhandled instruction type\n");
1947 break;
1948 }
1949 }
1950
1951
1952 /* ALU instructions can inline or embed constants, which decreases register
1953 * pressure and saves space. */
1954
1955 #define CONDITIONAL_ATTACH(idx) { \
1956 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
1957 \
1958 if (entry) { \
1959 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
1960 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1961 } \
1962 }
1963
1964 static void
1965 inline_alu_constants(compiler_context *ctx, midgard_block *block)
1966 {
1967 mir_foreach_instr_in_block(block, alu) {
1968 /* Other instructions cannot inline constants */
1969 if (alu->type != TAG_ALU_4) continue;
1970 if (alu->compact_branch) continue;
1971
1972 /* If there is already a constant here, we can do nothing */
1973 if (alu->has_constants) continue;
1974
1975 CONDITIONAL_ATTACH(0);
1976
1977 if (!alu->has_constants) {
1978 CONDITIONAL_ATTACH(1)
1979 } else if (!alu->inline_constant) {
1980 /* Corner case: _two_ vec4 constants, for instance with a
1981 * csel. For this case, we can only use a constant
1982 * register for one, we'll have to emit a move for the
1983 * other. */
1984
1985 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
1986 unsigned scratch = make_compiler_temp(ctx);
1987
1988 if (entry) {
1989 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
1990 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
1991
1992 /* Set the source */
1993 alu->src[1] = scratch;
1994
1995 /* Inject us -before- the last instruction which set r31 */
1996 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
1997 }
1998 }
1999 }
2000 }
2001
2002 /* Midgard supports two types of constants, embedded constants (128-bit) and
2003 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2004 * constants can be demoted to inline constants, for space savings and
2005 * sometimes a performance boost */
2006
2007 static void
2008 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2009 {
2010 mir_foreach_instr_in_block(block, ins) {
2011 if (!ins->has_constants) continue;
2012 if (ins->has_inline_constant) continue;
2013
2014 /* Blend constants must not be inlined by definition */
2015 if (ins->has_blend_constant) continue;
2016
2017 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2018 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2019 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2020
2021 if (!(is_16 || is_32))
2022 continue;
2023
2024 /* src1 cannot be an inline constant due to encoding
2025 * restrictions. So, if possible we try to flip the arguments
2026 * in that case */
2027
2028 int op = ins->alu.op;
2029
2030 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2031 alu_opcode_props[op].props & OP_COMMUTES) {
2032 mir_flip(ins);
2033 }
2034
2035 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2036 /* Extract the source information */
2037
2038 midgard_vector_alu_src *src;
2039 int q = ins->alu.src2;
2040 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
2041 src = m;
2042
2043 /* Component is from the swizzle. Take a nonzero component */
2044 assert(ins->mask);
2045 unsigned first_comp = ffs(ins->mask) - 1;
2046 unsigned component = ins->swizzle[1][first_comp];
2047
2048 /* Scale constant appropriately, if we can legally */
2049 uint16_t scaled_constant = 0;
2050
2051 if (is_16) {
2052 scaled_constant = ins->constants.u16[component];
2053 } else if (midgard_is_integer_op(op)) {
2054 scaled_constant = ins->constants.u32[component];
2055
2056 /* Constant overflow after resize */
2057 if (scaled_constant != ins->constants.u32[component])
2058 continue;
2059 } else {
2060 float original = ins->constants.f32[component];
2061 scaled_constant = _mesa_float_to_half(original);
2062
2063 /* Check for loss of precision. If this is
2064 * mediump, we don't care, but for a highp
2065 * shader, we need to pay attention. NIR
2066 * doesn't yet tell us which mode we're in!
2067 * Practically this prevents most constants
2068 * from being inlined, sadly. */
2069
2070 float fp32 = _mesa_half_to_float(scaled_constant);
2071
2072 if (fp32 != original)
2073 continue;
2074 }
2075
2076 /* We don't know how to handle these with a constant */
2077
2078 if (mir_nontrivial_source2_mod_simple(ins) || src->rep_low || src->rep_high) {
2079 DBG("Bailing inline constant...\n");
2080 continue;
2081 }
2082
2083 /* Make sure that the constant is not itself a vector
2084 * by checking if all accessed values are the same. */
2085
2086 const midgard_constants *cons = &ins->constants;
2087 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2088
2089 bool is_vector = false;
2090 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2091
2092 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2093 /* We only care if this component is actually used */
2094 if (!(mask & (1 << c)))
2095 continue;
2096
2097 uint32_t test = is_16 ?
2098 cons->u16[ins->swizzle[1][c]] :
2099 cons->u32[ins->swizzle[1][c]];
2100
2101 if (test != value) {
2102 is_vector = true;
2103 break;
2104 }
2105 }
2106
2107 if (is_vector)
2108 continue;
2109
2110 /* Get rid of the embedded constant */
2111 ins->has_constants = false;
2112 ins->src[1] = ~0;
2113 ins->has_inline_constant = true;
2114 ins->inline_constant = scaled_constant;
2115 }
2116 }
2117 }
2118
2119 /* Dead code elimination for branches at the end of a block - only one branch
2120 * per block is legal semantically */
2121
2122 static void
2123 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2124 {
2125 bool branched = false;
2126
2127 mir_foreach_instr_in_block_safe(block, ins) {
2128 if (!midgard_is_branch_unit(ins->unit)) continue;
2129
2130 if (branched)
2131 mir_remove_instruction(ins);
2132
2133 branched = true;
2134 }
2135 }
2136
2137 static unsigned
2138 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2139 {
2140 /* Loop to ourselves */
2141 midgard_instruction *br = ctx->writeout_branch[rt];
2142 struct midgard_instruction ins = v_branch(false, false);
2143 ins.writeout = true;
2144 ins.writeout_depth = br->writeout_depth;
2145 ins.writeout_stencil = br->writeout_stencil;
2146 ins.branch.target_block = ctx->block_count - 1;
2147 ins.constants.u32[0] = br->constants.u32[0];
2148 emit_mir_instruction(ctx, ins);
2149
2150 ctx->current_block->epilogue = true;
2151 schedule_barrier(ctx);
2152 return ins.branch.target_block;
2153 }
2154
2155 static midgard_block *
2156 emit_block(compiler_context *ctx, nir_block *block)
2157 {
2158 midgard_block *this_block = ctx->after_block;
2159 ctx->after_block = NULL;
2160
2161 if (!this_block)
2162 this_block = create_empty_block(ctx);
2163
2164 list_addtail(&this_block->base.link, &ctx->blocks);
2165
2166 this_block->scheduled = false;
2167 ++ctx->block_count;
2168
2169 /* Set up current block */
2170 list_inithead(&this_block->base.instructions);
2171 ctx->current_block = this_block;
2172
2173 nir_foreach_instr(instr, block) {
2174 emit_instr(ctx, instr);
2175 ++ctx->instruction_count;
2176 }
2177
2178 return this_block;
2179 }
2180
2181 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2182
2183 static void
2184 emit_if(struct compiler_context *ctx, nir_if *nif)
2185 {
2186 midgard_block *before_block = ctx->current_block;
2187
2188 /* Speculatively emit the branch, but we can't fill it in until later */
2189 EMIT(branch, true, true);
2190 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2191 then_branch->src[0] = nir_src_index(ctx, &nif->condition);
2192 then_branch->src_types[0] = nir_type_uint32;
2193
2194 /* Emit the two subblocks. */
2195 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2196 midgard_block *end_then_block = ctx->current_block;
2197
2198 /* Emit a jump from the end of the then block to the end of the else */
2199 EMIT(branch, false, false);
2200 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2201
2202 /* Emit second block, and check if it's empty */
2203
2204 int else_idx = ctx->block_count;
2205 int count_in = ctx->instruction_count;
2206 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2207 midgard_block *end_else_block = ctx->current_block;
2208 int after_else_idx = ctx->block_count;
2209
2210 /* Now that we have the subblocks emitted, fix up the branches */
2211
2212 assert(then_block);
2213 assert(else_block);
2214
2215 if (ctx->instruction_count == count_in) {
2216 /* The else block is empty, so don't emit an exit jump */
2217 mir_remove_instruction(then_exit);
2218 then_branch->branch.target_block = after_else_idx;
2219 } else {
2220 then_branch->branch.target_block = else_idx;
2221 then_exit->branch.target_block = after_else_idx;
2222 }
2223
2224 /* Wire up the successors */
2225
2226 ctx->after_block = create_empty_block(ctx);
2227
2228 pan_block_add_successor(&before_block->base, &then_block->base);
2229 pan_block_add_successor(&before_block->base, &else_block->base);
2230
2231 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2232 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2233 }
2234
2235 static void
2236 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2237 {
2238 /* Remember where we are */
2239 midgard_block *start_block = ctx->current_block;
2240
2241 /* Allocate a loop number, growing the current inner loop depth */
2242 int loop_idx = ++ctx->current_loop_depth;
2243
2244 /* Get index from before the body so we can loop back later */
2245 int start_idx = ctx->block_count;
2246
2247 /* Emit the body itself */
2248 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2249
2250 /* Branch back to loop back */
2251 struct midgard_instruction br_back = v_branch(false, false);
2252 br_back.branch.target_block = start_idx;
2253 emit_mir_instruction(ctx, br_back);
2254
2255 /* Mark down that branch in the graph. */
2256 pan_block_add_successor(&start_block->base, &loop_block->base);
2257 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2258
2259 /* Find the index of the block about to follow us (note: we don't add
2260 * one; blocks are 0-indexed so we get a fencepost problem) */
2261 int break_block_idx = ctx->block_count;
2262
2263 /* Fix up the break statements we emitted to point to the right place,
2264 * now that we can allocate a block number for them */
2265 ctx->after_block = create_empty_block(ctx);
2266
2267 mir_foreach_block_from(ctx, start_block, _block) {
2268 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2269 if (ins->type != TAG_ALU_4) continue;
2270 if (!ins->compact_branch) continue;
2271
2272 /* We found a branch -- check the type to see if we need to do anything */
2273 if (ins->branch.target_type != TARGET_BREAK) continue;
2274
2275 /* It's a break! Check if it's our break */
2276 if (ins->branch.target_break != loop_idx) continue;
2277
2278 /* Okay, cool, we're breaking out of this loop.
2279 * Rewrite from a break to a goto */
2280
2281 ins->branch.target_type = TARGET_GOTO;
2282 ins->branch.target_block = break_block_idx;
2283
2284 pan_block_add_successor(_block, &ctx->after_block->base);
2285 }
2286 }
2287
2288 /* Now that we've finished emitting the loop, free up the depth again
2289 * so we play nice with recursion amid nested loops */
2290 --ctx->current_loop_depth;
2291
2292 /* Dump loop stats */
2293 ++ctx->loop_count;
2294 }
2295
2296 static midgard_block *
2297 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2298 {
2299 midgard_block *start_block = NULL;
2300
2301 foreach_list_typed(nir_cf_node, node, node, list) {
2302 switch (node->type) {
2303 case nir_cf_node_block: {
2304 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2305
2306 if (!start_block)
2307 start_block = block;
2308
2309 break;
2310 }
2311
2312 case nir_cf_node_if:
2313 emit_if(ctx, nir_cf_node_as_if(node));
2314 break;
2315
2316 case nir_cf_node_loop:
2317 emit_loop(ctx, nir_cf_node_as_loop(node));
2318 break;
2319
2320 case nir_cf_node_function:
2321 assert(0);
2322 break;
2323 }
2324 }
2325
2326 return start_block;
2327 }
2328
2329 /* Due to lookahead, we need to report the first tag executed in the command
2330 * stream and in branch targets. An initial block might be empty, so iterate
2331 * until we find one that 'works' */
2332
2333 static unsigned
2334 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2335 {
2336 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2337
2338 mir_foreach_block_from(ctx, initial_block, _v) {
2339 midgard_block *v = (midgard_block *) _v;
2340 if (v->quadword_count) {
2341 midgard_bundle *initial_bundle =
2342 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2343
2344 return initial_bundle->tag;
2345 }
2346 }
2347
2348 /* Default to a tag 1 which will break from the shader, in case we jump
2349 * to the exit block (i.e. `return` in a compute shader) */
2350
2351 return 1;
2352 }
2353
2354 /* For each fragment writeout instruction, generate a writeout loop to
2355 * associate with it */
2356
2357 static void
2358 mir_add_writeout_loops(compiler_context *ctx)
2359 {
2360 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2361 midgard_instruction *br = ctx->writeout_branch[rt];
2362 if (!br) continue;
2363
2364 unsigned popped = br->branch.target_block;
2365 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2366 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2367 br->branch.target_type = TARGET_GOTO;
2368
2369 /* If we have more RTs, we'll need to restore back after our
2370 * loop terminates */
2371
2372 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2373 midgard_instruction uncond = v_branch(false, false);
2374 uncond.branch.target_block = popped;
2375 uncond.branch.target_type = TARGET_GOTO;
2376 emit_mir_instruction(ctx, uncond);
2377 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2378 schedule_barrier(ctx);
2379 } else {
2380 /* We're last, so we can terminate here */
2381 br->last_writeout = true;
2382 }
2383 }
2384 }
2385
2386 int
2387 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2388 {
2389 struct util_dynarray *compiled = &program->compiled;
2390
2391 midgard_debug = debug_get_option_midgard_debug();
2392
2393 /* TODO: Bound against what? */
2394 compiler_context *ctx = rzalloc(NULL, compiler_context);
2395
2396 ctx->nir = nir;
2397 ctx->stage = nir->info.stage;
2398 ctx->is_blend = is_blend;
2399 ctx->alpha_ref = program->alpha_ref;
2400 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2401 ctx->quirks = midgard_get_quirks(gpu_id);
2402
2403 /* Start off with a safe cutoff, allowing usage of all 16 work
2404 * registers. Later, we'll promote uniform reads to uniform registers
2405 * if we determine it is beneficial to do so */
2406 ctx->uniform_cutoff = 8;
2407
2408 /* Initialize at a global (not block) level hash tables */
2409
2410 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2411 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2412
2413 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2414 * (so we don't accidentally duplicate the epilogue since mesa/st has
2415 * messed with our I/O quite a bit already) */
2416
2417 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2418
2419 if (ctx->stage == MESA_SHADER_VERTEX) {
2420 NIR_PASS_V(nir, nir_lower_viewport_transform);
2421 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2422 }
2423
2424 NIR_PASS_V(nir, nir_lower_var_copies);
2425 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2426 NIR_PASS_V(nir, nir_split_var_copies);
2427 NIR_PASS_V(nir, nir_lower_var_copies);
2428 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2429 NIR_PASS_V(nir, nir_lower_var_copies);
2430 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2431
2432 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2433 NIR_PASS_V(nir, nir_lower_ssbo);
2434 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2435
2436 /* Optimisation passes */
2437
2438 optimise_nir(nir, ctx->quirks);
2439
2440 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2441 nir_print_shader(nir, stdout);
2442 }
2443
2444 /* Assign sysvals and counts, now that we're sure
2445 * (post-optimisation) */
2446
2447 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2448 program->sysval_count = ctx->sysvals.sysval_count;
2449 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2450
2451 nir_foreach_function(func, nir) {
2452 if (!func->impl)
2453 continue;
2454
2455 list_inithead(&ctx->blocks);
2456 ctx->block_count = 0;
2457 ctx->func = func;
2458 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
2459
2460 emit_cf_list(ctx, &func->impl->body);
2461 free(ctx->already_emitted);
2462 break; /* TODO: Multi-function shaders */
2463 }
2464
2465 util_dynarray_init(compiled, NULL);
2466
2467 /* Per-block lowering before opts */
2468
2469 mir_foreach_block(ctx, _block) {
2470 midgard_block *block = (midgard_block *) _block;
2471 inline_alu_constants(ctx, block);
2472 midgard_opt_promote_fmov(ctx, block);
2473 embedded_to_inline_constant(ctx, block);
2474 }
2475 /* MIR-level optimizations */
2476
2477 bool progress = false;
2478
2479 do {
2480 progress = false;
2481
2482 mir_foreach_block(ctx, _block) {
2483 midgard_block *block = (midgard_block *) _block;
2484 progress |= midgard_opt_copy_prop(ctx, block);
2485 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2486 progress |= midgard_opt_combine_projection(ctx, block);
2487 progress |= midgard_opt_varying_projection(ctx, block);
2488 progress |= midgard_opt_not_propagate(ctx, block);
2489 progress |= midgard_opt_fuse_src_invert(ctx, block);
2490 progress |= midgard_opt_fuse_dest_invert(ctx, block);
2491 progress |= midgard_opt_csel_invert(ctx, block);
2492 progress |= midgard_opt_drop_cmp_invert(ctx, block);
2493 progress |= midgard_opt_invert_branch(ctx, block);
2494 }
2495 } while (progress);
2496
2497 mir_foreach_block(ctx, _block) {
2498 midgard_block *block = (midgard_block *) _block;
2499 midgard_lower_invert(ctx, block);
2500 midgard_lower_derivatives(ctx, block);
2501 }
2502
2503 /* Nested control-flow can result in dead branches at the end of the
2504 * block. This messes with our analysis and is just dead code, so cull
2505 * them */
2506 mir_foreach_block(ctx, _block) {
2507 midgard_block *block = (midgard_block *) _block;
2508 midgard_cull_dead_branch(ctx, block);
2509 }
2510
2511 /* Ensure we were lowered */
2512 mir_foreach_instr_global(ctx, ins) {
2513 assert(!ins->invert);
2514 }
2515
2516 if (ctx->stage == MESA_SHADER_FRAGMENT)
2517 mir_add_writeout_loops(ctx);
2518
2519 /* Analyze now that the code is known but before scheduling creates
2520 * pipeline registers which are harder to track */
2521 mir_analyze_helper_terminate(ctx);
2522 mir_analyze_helper_requirements(ctx);
2523
2524 /* Schedule! */
2525 midgard_schedule_program(ctx);
2526 mir_ra(ctx);
2527
2528 /* Now that all the bundles are scheduled and we can calculate block
2529 * sizes, emit actual branch instructions rather than placeholders */
2530
2531 int br_block_idx = 0;
2532
2533 mir_foreach_block(ctx, _block) {
2534 midgard_block *block = (midgard_block *) _block;
2535 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2536 for (int c = 0; c < bundle->instruction_count; ++c) {
2537 midgard_instruction *ins = bundle->instructions[c];
2538
2539 if (!midgard_is_branch_unit(ins->unit)) continue;
2540
2541 /* Parse some basic branch info */
2542 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2543 bool is_conditional = ins->branch.conditional;
2544 bool is_inverted = ins->branch.invert_conditional;
2545 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2546 bool is_writeout = ins->writeout;
2547
2548 /* Determine the block we're jumping to */
2549 int target_number = ins->branch.target_block;
2550
2551 /* Report the destination tag */
2552 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2553
2554 /* Count up the number of quadwords we're
2555 * jumping over = number of quadwords until
2556 * (br_block_idx, target_number) */
2557
2558 int quadword_offset = 0;
2559
2560 if (is_discard) {
2561 /* Ignored */
2562 } else if (target_number > br_block_idx) {
2563 /* Jump forward */
2564
2565 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2566 midgard_block *blk = mir_get_block(ctx, idx);
2567 assert(blk);
2568
2569 quadword_offset += blk->quadword_count;
2570 }
2571 } else {
2572 /* Jump backwards */
2573
2574 for (int idx = br_block_idx; idx >= target_number; --idx) {
2575 midgard_block *blk = mir_get_block(ctx, idx);
2576 assert(blk);
2577
2578 quadword_offset -= blk->quadword_count;
2579 }
2580 }
2581
2582 /* Unconditional extended branches (far jumps)
2583 * have issues, so we always use a conditional
2584 * branch, setting the condition to always for
2585 * unconditional. For compact unconditional
2586 * branches, cond isn't used so it doesn't
2587 * matter what we pick. */
2588
2589 midgard_condition cond =
2590 !is_conditional ? midgard_condition_always :
2591 is_inverted ? midgard_condition_false :
2592 midgard_condition_true;
2593
2594 midgard_jmp_writeout_op op =
2595 is_discard ? midgard_jmp_writeout_op_discard :
2596 is_writeout ? midgard_jmp_writeout_op_writeout :
2597 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2598 midgard_jmp_writeout_op_branch_cond;
2599
2600 if (!is_compact) {
2601 midgard_branch_extended branch =
2602 midgard_create_branch_extended(
2603 cond, op,
2604 dest_tag,
2605 quadword_offset);
2606
2607 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2608 } else if (is_conditional || is_discard) {
2609 midgard_branch_cond branch = {
2610 .op = op,
2611 .dest_tag = dest_tag,
2612 .offset = quadword_offset,
2613 .cond = cond
2614 };
2615
2616 assert(branch.offset == quadword_offset);
2617
2618 memcpy(&ins->br_compact, &branch, sizeof(branch));
2619 } else {
2620 assert(op == midgard_jmp_writeout_op_branch_uncond);
2621
2622 midgard_branch_uncond branch = {
2623 .op = op,
2624 .dest_tag = dest_tag,
2625 .offset = quadword_offset,
2626 .unknown = 1
2627 };
2628
2629 assert(branch.offset == quadword_offset);
2630
2631 memcpy(&ins->br_compact, &branch, sizeof(branch));
2632 }
2633 }
2634 }
2635
2636 ++br_block_idx;
2637 }
2638
2639 /* Emit flat binary from the instruction arrays. Iterate each block in
2640 * sequence. Save instruction boundaries such that lookahead tags can
2641 * be assigned easily */
2642
2643 /* Cache _all_ bundles in source order for lookahead across failed branches */
2644
2645 int bundle_count = 0;
2646 mir_foreach_block(ctx, _block) {
2647 midgard_block *block = (midgard_block *) _block;
2648 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2649 }
2650 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2651 int bundle_idx = 0;
2652 mir_foreach_block(ctx, _block) {
2653 midgard_block *block = (midgard_block *) _block;
2654 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2655 source_order_bundles[bundle_idx++] = bundle;
2656 }
2657 }
2658
2659 int current_bundle = 0;
2660
2661 /* Midgard prefetches instruction types, so during emission we
2662 * need to lookahead. Unless this is the last instruction, in
2663 * which we return 1. */
2664
2665 mir_foreach_block(ctx, _block) {
2666 midgard_block *block = (midgard_block *) _block;
2667 mir_foreach_bundle_in_block(block, bundle) {
2668 int lookahead = 1;
2669
2670 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2671 lookahead = source_order_bundles[current_bundle + 1]->tag;
2672
2673 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2674 ++current_bundle;
2675 }
2676
2677 /* TODO: Free deeper */
2678 //util_dynarray_fini(&block->instructions);
2679 }
2680
2681 free(source_order_bundles);
2682
2683 /* Report the very first tag executed */
2684 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2685
2686 /* Deal with off-by-one related to the fencepost problem */
2687 program->work_register_count = ctx->work_registers + 1;
2688 program->uniform_cutoff = ctx->uniform_cutoff;
2689
2690 program->blend_patch_offset = ctx->blend_constant_offset;
2691 program->tls_size = ctx->tls_size;
2692
2693 if (midgard_debug & MIDGARD_DBG_SHADERS)
2694 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2695
2696 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2697 unsigned nr_bundles = 0, nr_ins = 0;
2698
2699 /* Count instructions and bundles */
2700
2701 mir_foreach_block(ctx, _block) {
2702 midgard_block *block = (midgard_block *) _block;
2703 nr_bundles += util_dynarray_num_elements(
2704 &block->bundles, midgard_bundle);
2705
2706 mir_foreach_bundle_in_block(block, bun)
2707 nr_ins += bun->instruction_count;
2708 }
2709
2710 /* Calculate thread count. There are certain cutoffs by
2711 * register count for thread count */
2712
2713 unsigned nr_registers = program->work_register_count;
2714
2715 unsigned nr_threads =
2716 (nr_registers <= 4) ? 4 :
2717 (nr_registers <= 8) ? 2 :
2718 1;
2719
2720 /* Dump stats */
2721
2722 fprintf(stderr, "shader%d - %s shader: "
2723 "%u inst, %u bundles, %u quadwords, "
2724 "%u registers, %u threads, %u loops, "
2725 "%u:%u spills:fills\n",
2726 SHADER_DB_COUNT++,
2727 gl_shader_stage_name(ctx->stage),
2728 nr_ins, nr_bundles, ctx->quadword_count,
2729 nr_registers, nr_threads,
2730 ctx->loop_count,
2731 ctx->spills, ctx->fills);
2732 }
2733
2734 ralloc_free(ctx);
2735
2736 return 0;
2737 }