2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
50 #include "midgard_quirks.h"
52 #include "disassemble.h"
54 static const struct debug_named_value debug_options
[] = {
55 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
63 unsigned SHADER_DB_COUNT
= 0;
65 int midgard_debug
= 0;
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block
*
72 create_empty_block(compiler_context
*ctx
)
74 midgard_block
*blk
= rzalloc(ctx
, midgard_block
);
76 blk
->base
.predecessors
= _mesa_set_create(blk
,
78 _mesa_key_pointer_equal
);
80 blk
->base
.name
= ctx
->block_source_count
++;
86 schedule_barrier(compiler_context
*ctx
)
88 midgard_block
*temp
= ctx
->after_block
;
89 ctx
->after_block
= create_empty_block(ctx
);
91 list_addtail(&ctx
->after_block
->base
.link
, &ctx
->blocks
);
92 list_inithead(&ctx
->after_block
->base
.instructions
);
93 pan_block_add_successor(&ctx
->current_block
->base
, &ctx
->after_block
->base
);
94 ctx
->current_block
= ctx
->after_block
;
95 ctx
->after_block
= temp
;
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
112 .op = midgard_op_##name, \
119 i.src_types[0] = T; \
128 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
129 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
131 M_LOAD(ld_attr_32
, nir_type_uint32
);
132 M_LOAD(ld_vary_32
, nir_type_uint32
);
133 M_LOAD(ld_ubo_int4
, nir_type_uint32
);
134 M_LOAD(ld_int4
, nir_type_uint32
);
135 M_STORE(st_int4
, nir_type_uint32
);
136 M_LOAD(ld_color_buffer_32u
, nir_type_uint32
);
137 M_LOAD(ld_color_buffer_as_fp16
, nir_type_float16
);
138 M_STORE(st_vary_32
, nir_type_uint32
);
139 M_LOAD(ld_cubemap_coords
, nir_type_uint32
);
140 M_LOAD(ld_compute_id
, nir_type_uint32
);
142 static midgard_instruction
143 v_branch(bool conditional
, bool invert
)
145 midgard_instruction ins
= {
147 .unit
= ALU_ENAB_BRANCH
,
148 .compact_branch
= true,
150 .conditional
= conditional
,
151 .invert_conditional
= invert
154 .src
= { ~0, ~0, ~0, ~0 },
160 static midgard_branch_extended
161 midgard_create_branch_extended( midgard_condition cond
,
162 midgard_jmp_writeout_op op
,
164 signed quadword_offset
)
166 /* The condition code is actually a LUT describing a function to
167 * combine multiple condition codes. However, we only support a single
168 * condition code at the moment, so we just duplicate over a bunch of
171 uint16_t duplicated_cond
=
181 midgard_branch_extended branch
= {
183 .dest_tag
= dest_tag
,
184 .offset
= quadword_offset
,
185 .cond
= duplicated_cond
192 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
194 ins
->has_constants
= true;
195 memcpy(&ins
->constants
, constants
, 16);
199 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
201 return glsl_count_attribute_slots(type
, false);
204 /* Lower fdot2 to a vector multiplication followed by channel addition */
206 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
208 if (alu
->op
!= nir_op_fdot2
)
211 b
->cursor
= nir_before_instr(&alu
->instr
);
213 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
214 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
216 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
218 nir_ssa_def
*sum
= nir_fadd(b
,
219 nir_channel(b
, product
, 0),
220 nir_channel(b
, product
, 1));
222 /* Replace the fdot2 with this sum */
223 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
227 midgard_nir_lower_fdot2(nir_shader
*shader
)
229 bool progress
= false;
231 nir_foreach_function(function
, shader
) {
232 if (!function
->impl
) continue;
235 nir_builder
*b
= &_b
;
236 nir_builder_init(b
, function
->impl
);
238 nir_foreach_block(block
, function
->impl
) {
239 nir_foreach_instr_safe(instr
, block
) {
240 if (instr
->type
!= nir_instr_type_alu
) continue;
242 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
243 midgard_nir_lower_fdot2_body(b
, alu
);
249 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
256 static const nir_variable
*
257 search_var(struct exec_list
*vars
, unsigned driver_loc
)
259 nir_foreach_variable(var
, vars
) {
260 if (var
->data
.driver_location
== driver_loc
)
267 /* Midgard can write all of color, depth and stencil in a single writeout
268 * operation, so we merge depth/stencil stores with color stores.
269 * If there are no color stores, we add a write to the "depth RT".
272 midgard_nir_lower_zs_store(nir_shader
*nir
)
274 if (nir
->info
.stage
!= MESA_SHADER_FRAGMENT
)
277 nir_variable
*z_var
= NULL
, *s_var
= NULL
;
279 nir_foreach_variable(var
, &nir
->outputs
) {
280 if (var
->data
.location
== FRAG_RESULT_DEPTH
)
282 else if (var
->data
.location
== FRAG_RESULT_STENCIL
)
286 if (!z_var
&& !s_var
)
289 bool progress
= false;
291 nir_foreach_function(function
, nir
) {
292 if (!function
->impl
) continue;
294 nir_intrinsic_instr
*z_store
= NULL
, *s_store
= NULL
;
296 nir_foreach_block(block
, function
->impl
) {
297 nir_foreach_instr_safe(instr
, block
) {
298 if (instr
->type
!= nir_instr_type_intrinsic
)
301 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
302 if (intr
->intrinsic
!= nir_intrinsic_store_output
)
305 if (z_var
&& nir_intrinsic_base(intr
) == z_var
->data
.driver_location
) {
310 if (s_var
&& nir_intrinsic_base(intr
) == s_var
->data
.driver_location
) {
317 if (!z_store
&& !s_store
) continue;
319 bool replaced
= false;
321 nir_foreach_block(block
, function
->impl
) {
322 nir_foreach_instr_safe(instr
, block
) {
323 if (instr
->type
!= nir_instr_type_intrinsic
)
326 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
327 if (intr
->intrinsic
!= nir_intrinsic_store_output
)
330 const nir_variable
*var
= search_var(&nir
->outputs
, nir_intrinsic_base(intr
));
333 if (var
->data
.location
!= FRAG_RESULT_COLOR
&&
334 var
->data
.location
< FRAG_RESULT_DATA0
)
337 assert(nir_src_is_const(intr
->src
[1]) && "no indirect outputs");
340 nir_builder_init(&b
, function
->impl
);
342 assert(!z_store
|| z_store
->instr
.block
== instr
->block
);
343 assert(!s_store
|| s_store
->instr
.block
== instr
->block
);
344 b
.cursor
= nir_after_block_before_jump(instr
->block
);
346 nir_intrinsic_instr
*combined_store
;
347 combined_store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_combined_output_pan
);
349 combined_store
->num_components
= intr
->src
[0].ssa
->num_components
;
351 nir_intrinsic_set_base(combined_store
, nir_intrinsic_base(intr
));
353 unsigned writeout
= PAN_WRITEOUT_C
;
355 writeout
|= PAN_WRITEOUT_Z
;
357 writeout
|= PAN_WRITEOUT_S
;
359 nir_intrinsic_set_component(combined_store
, writeout
);
361 struct nir_ssa_def
*zero
= nir_imm_int(&b
, 0);
363 struct nir_ssa_def
*src
[4] = {
366 z_store
? z_store
->src
[0].ssa
: zero
,
367 s_store
? s_store
->src
[0].ssa
: zero
,
370 for (int i
= 0; i
< 4; ++i
)
371 combined_store
->src
[i
] = nir_src_for_ssa(src
[i
]);
373 nir_builder_instr_insert(&b
, &combined_store
->instr
);
375 nir_instr_remove(instr
);
381 /* Insert a store to the depth RT (0xff) if needed */
384 nir_builder_init(&b
, function
->impl
);
386 nir_block
*block
= NULL
;
387 if (z_store
&& s_store
)
388 assert(z_store
->instr
.block
== s_store
->instr
.block
);
391 block
= z_store
->instr
.block
;
393 block
= s_store
->instr
.block
;
395 b
.cursor
= nir_after_block_before_jump(block
);
397 nir_intrinsic_instr
*combined_store
;
398 combined_store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_combined_output_pan
);
400 combined_store
->num_components
= 4;
402 nir_intrinsic_set_base(combined_store
, 0);
404 unsigned writeout
= 0;
406 writeout
|= PAN_WRITEOUT_Z
;
408 writeout
|= PAN_WRITEOUT_S
;
410 nir_intrinsic_set_component(combined_store
, writeout
);
412 struct nir_ssa_def
*zero
= nir_imm_int(&b
, 0);
414 struct nir_ssa_def
*src
[4] = {
415 nir_imm_vec4(&b
, 0, 0, 0, 0),
417 z_store
? z_store
->src
[0].ssa
: zero
,
418 s_store
? s_store
->src
[0].ssa
: zero
,
421 for (int i
= 0; i
< 4; ++i
)
422 combined_store
->src
[i
] = nir_src_for_ssa(src
[i
]);
424 nir_builder_instr_insert(&b
, &combined_store
->instr
);
428 nir_instr_remove(&z_store
->instr
);
431 nir_instr_remove(&s_store
->instr
);
433 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
440 /* Flushes undefined values to zero */
443 optimise_nir(nir_shader
*nir
, unsigned quirks
, bool is_blend
)
446 unsigned lower_flrp
=
447 (nir
->options
->lower_flrp16
? 16 : 0) |
448 (nir
->options
->lower_flrp32
? 32 : 0) |
449 (nir
->options
->lower_flrp64
? 64 : 0);
451 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
452 NIR_PASS(progress
, nir
, nir_lower_idiv
, nir_lower_idiv_fast
);
454 nir_lower_tex_options lower_tex_options
= {
455 .lower_txs_lod
= true,
457 .lower_tex_without_implicit_lod
=
458 (quirks
& MIDGARD_EXPLICIT_LOD
),
460 /* TODO: we have native gradient.. */
464 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
466 /* Must lower fdot2 after tex is lowered */
467 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
469 /* T720 is broken. */
471 if (quirks
& MIDGARD_BROKEN_LOD
)
472 NIR_PASS_V(nir
, midgard_nir_lod_errata
);
474 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_early
);
477 NIR_PASS(progress
, nir
, nir_fuse_io_16
);
482 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
483 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
485 NIR_PASS(progress
, nir
, nir_copy_prop
);
486 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
487 NIR_PASS(progress
, nir
, nir_opt_dce
);
488 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
489 NIR_PASS(progress
, nir
, nir_opt_cse
);
490 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
491 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
492 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
494 if (lower_flrp
!= 0) {
495 bool lower_flrp_progress
= false;
496 NIR_PASS(lower_flrp_progress
,
500 false /* always_precise */,
501 nir
->options
->lower_ffma
);
502 if (lower_flrp_progress
) {
503 NIR_PASS(progress
, nir
,
504 nir_opt_constant_folding
);
508 /* Nothing should rematerialize any flrps, so we only
509 * need to do this lowering once.
514 NIR_PASS(progress
, nir
, nir_opt_undef
);
515 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
517 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
520 nir_var_function_temp
);
522 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
525 /* Must be run at the end to prevent creation of fsin/fcos ops */
526 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
531 NIR_PASS(progress
, nir
, nir_opt_dce
);
532 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
533 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
534 NIR_PASS(progress
, nir
, nir_copy_prop
);
537 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
538 NIR_PASS(progress
, nir
, nir_opt_algebraic_distribute_src_mods
);
540 /* We implement booleans as 32-bit 0/~0 */
541 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
543 /* Now that booleans are lowered, we can run out late opts */
544 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
545 NIR_PASS(progress
, nir
, midgard_nir_cancel_inot
);
547 NIR_PASS(progress
, nir
, nir_copy_prop
);
548 NIR_PASS(progress
, nir
, nir_opt_dce
);
550 /* Take us out of SSA */
551 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
552 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
554 /* We are a vector architecture; write combine where possible */
555 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
556 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
558 NIR_PASS(progress
, nir
, nir_opt_dce
);
561 /* Do not actually emit a load; instead, cache the constant for inlining */
564 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
566 nir_ssa_def def
= instr
->def
;
568 midgard_constants
*consts
= rzalloc(NULL
, midgard_constants
);
570 assert(instr
->def
.num_components
* instr
->def
.bit_size
<= sizeof(*consts
) * 8);
572 #define RAW_CONST_COPY(bits) \
573 nir_const_value_to_array(consts->u##bits, instr->value, \
574 instr->def.num_components, u##bits)
576 switch (instr
->def
.bit_size
) {
590 unreachable("Invalid bit_size for load_const instruction\n");
593 /* Shifted for SSA, +1 for off-by-one */
594 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (def
.index
<< 1) + 1, consts
);
597 /* Normally constants are embedded implicitly, but for I/O and such we have to
598 * explicitly emit a move with the constant source */
601 emit_explicit_constant(compiler_context
*ctx
, unsigned node
, unsigned to
)
603 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, node
+ 1);
605 if (constant_value
) {
606 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), to
);
607 attach_constants(ctx
, &ins
, constant_value
, node
+ 1);
608 emit_mir_instruction(ctx
, ins
);
613 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
615 unsigned comp
= src
->swizzle
[0];
617 for (unsigned c
= 1; c
< nr_components
; ++c
) {
618 if (src
->swizzle
[c
] != comp
)
625 #define ALU_CASE(nir, _op) \
627 op = midgard_alu_op_##_op; \
628 assert(src_bitsize == dst_bitsize); \
631 #define ALU_CASE_RTZ(nir, _op) \
633 op = midgard_alu_op_##_op; \
634 roundmode = MIDGARD_RTZ; \
637 #define ALU_CHECK_CMP(sext) \
638 assert(src_bitsize == 16 || src_bitsize == 32); \
639 assert(dst_bitsize == 16 || dst_bitsize == 32); \
641 #define ALU_CASE_BCAST(nir, _op, count) \
643 op = midgard_alu_op_##_op; \
644 broadcast_swizzle = count; \
645 ALU_CHECK_CMP(true); \
648 #define ALU_CASE_CMP(nir, _op, sext) \
650 op = midgard_alu_op_##_op; \
651 ALU_CHECK_CMP(sext); \
654 /* Analyze the sizes of the dest and inputs to determine reg mode. */
656 static midgard_reg_mode
657 reg_mode_for_nir(nir_alu_instr
*instr
)
659 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
660 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
661 unsigned max_bitsize
= MAX2(src_bitsize
, dst_bitsize
);
663 /* We don't have fp16 LUTs, so we'll want to emit code like:
665 * vlut.fsinr hr0, hr0
667 * where both input and output are 16-bit but the operation is carried
679 max_bitsize
= MAX2(max_bitsize
, 32);
682 /* These get lowered to moves */
683 case nir_op_pack_32_4x8
:
686 case nir_op_pack_32_2x16
:
694 switch (max_bitsize
) {
695 /* Use 16 pipe for 8 since we don't support vec16 yet */
698 return midgard_reg_mode_16
;
700 return midgard_reg_mode_32
;
702 return midgard_reg_mode_64
;
704 unreachable("Invalid bit size");
708 /* Compare mir_lower_invert */
710 nir_accepts_inot(nir_op op
, unsigned src
)
714 case nir_op_iand
: /* TODO: b2f16 */
718 /* Only the condition */
726 mir_accept_dest_mod(compiler_context
*ctx
, nir_dest
**dest
, nir_op op
)
728 if (pan_has_dest_mod(dest
, op
)) {
729 assert((*dest
)->is_ssa
);
730 BITSET_SET(ctx
->already_emitted
, (*dest
)->ssa
.index
);
738 mir_copy_src(midgard_instruction
*ins
, nir_alu_instr
*instr
, unsigned i
, unsigned to
, bool *abs
, bool *neg
, bool *not, enum midgard_roundmode
*roundmode
, bool is_int
, unsigned bcast_count
)
740 nir_alu_src src
= instr
->src
[i
];
743 if (pan_has_source_mod(&src
, nir_op_fneg
))
746 if (pan_has_source_mod(&src
, nir_op_fabs
))
750 if (nir_accepts_inot(instr
->op
, i
) && pan_has_source_mod(&src
, nir_op_inot
))
754 if (pan_has_source_mod(&src
, nir_op_fround_even
))
755 *roundmode
= MIDGARD_RTE
;
757 if (pan_has_source_mod(&src
, nir_op_ftrunc
))
758 *roundmode
= MIDGARD_RTZ
;
760 if (pan_has_source_mod(&src
, nir_op_ffloor
))
761 *roundmode
= MIDGARD_RTN
;
763 if (pan_has_source_mod(&src
, nir_op_fceil
))
764 *roundmode
= MIDGARD_RTP
;
767 unsigned bits
= nir_src_bit_size(src
.src
);
769 ins
->src
[to
] = nir_src_index(NULL
, &src
.src
);
770 ins
->src_types
[to
] = nir_op_infos
[instr
->op
].input_types
[i
] | bits
;
772 for (unsigned c
= 0; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
773 ins
->swizzle
[to
][c
] = src
.swizzle
[
774 (!bcast_count
|| c
< bcast_count
) ? c
:
779 /* Midgard features both fcsel and icsel, depending on whether you want int or
780 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
781 * we should emit an int or float csel depending on what modifiers could be
782 * placed. In the absense of modifiers, this is probably arbitrary. */
785 mir_is_bcsel_float(nir_alu_instr
*instr
)
788 nir_op_i2i8
, nir_op_i2i16
,
789 nir_op_i2i32
, nir_op_i2i64
792 nir_op floatmods
[] = {
793 nir_op_fabs
, nir_op_fneg
,
794 nir_op_f2f16
, nir_op_f2f32
,
798 nir_op floatdestmods
[] = {
799 nir_op_fsat
, nir_op_fsat_signed
, nir_op_fclamp_pos
,
800 nir_op_f2f16
, nir_op_f2f32
805 for (unsigned i
= 1; i
< 3; ++i
) {
806 nir_alu_src s
= instr
->src
[i
];
807 for (unsigned q
= 0; q
< ARRAY_SIZE(intmods
); ++q
) {
808 if (pan_has_source_mod(&s
, intmods
[q
]))
813 for (unsigned i
= 1; i
< 3; ++i
) {
814 nir_alu_src s
= instr
->src
[i
];
815 for (unsigned q
= 0; q
< ARRAY_SIZE(floatmods
); ++q
) {
816 if (pan_has_source_mod(&s
, floatmods
[q
]))
821 for (unsigned q
= 0; q
< ARRAY_SIZE(floatdestmods
); ++q
) {
822 nir_dest
*dest
= &instr
->dest
.dest
;
823 if (pan_has_dest_mod(&dest
, floatdestmods
[q
]))
831 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
833 nir_dest
*dest
= &instr
->dest
.dest
;
835 if (dest
->is_ssa
&& BITSET_TEST(ctx
->already_emitted
, dest
->ssa
.index
))
838 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
839 * is handled elsewhere */
841 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddy
) {
842 midgard_emit_derivatives(ctx
, instr
);
846 bool is_ssa
= dest
->is_ssa
;
848 unsigned nr_components
= nir_dest_num_components(*dest
);
849 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
852 /* Number of components valid to check for the instruction (the rest
853 * will be forced to the last), or 0 to use as-is. Relevant as
854 * ball-type instructions have a channel count in NIR but are all vec4
857 unsigned broadcast_swizzle
= 0;
859 /* What register mode should we operate in? */
860 midgard_reg_mode reg_mode
=
861 reg_mode_for_nir(instr
);
863 /* Should we swap arguments? */
864 bool flip_src12
= false;
866 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
867 unsigned dst_bitsize
= nir_dest_bit_size(*dest
);
869 enum midgard_roundmode roundmode
= MIDGARD_RTE
;
872 ALU_CASE(fadd
, fadd
);
873 ALU_CASE(fmul
, fmul
);
874 ALU_CASE(fmin
, fmin
);
875 ALU_CASE(fmax
, fmax
);
876 ALU_CASE(imin
, imin
);
877 ALU_CASE(imax
, imax
);
878 ALU_CASE(umin
, umin
);
879 ALU_CASE(umax
, umax
);
880 ALU_CASE(ffloor
, ffloor
);
881 ALU_CASE(fround_even
, froundeven
);
882 ALU_CASE(ftrunc
, ftrunc
);
883 ALU_CASE(fceil
, fceil
);
884 ALU_CASE(fdot3
, fdot3
);
885 ALU_CASE(fdot4
, fdot4
);
886 ALU_CASE(iadd
, iadd
);
887 ALU_CASE(isub
, isub
);
888 ALU_CASE(imul
, imul
);
890 /* Zero shoved as second-arg */
891 ALU_CASE(iabs
, iabsdiff
);
895 ALU_CASE_CMP(feq32
, feq
, false);
896 ALU_CASE_CMP(fne32
, fne
, false);
897 ALU_CASE_CMP(flt32
, flt
, false);
898 ALU_CASE_CMP(ieq32
, ieq
, true);
899 ALU_CASE_CMP(ine32
, ine
, true);
900 ALU_CASE_CMP(ilt32
, ilt
, true);
901 ALU_CASE_CMP(ult32
, ult
, false);
903 /* We don't have a native b2f32 instruction. Instead, like many
904 * GPUs, we exploit booleans as 0/~0 for false/true, and
905 * correspondingly AND
906 * by 1.0 to do the type conversion. For the moment, prime us
909 * iand [whatever], #0
911 * At the end of emit_alu (as MIR), we'll fix-up the constant
914 ALU_CASE_CMP(b2f32
, iand
, true);
915 ALU_CASE_CMP(b2f16
, iand
, true);
916 ALU_CASE_CMP(b2i32
, iand
, true);
918 /* Likewise, we don't have a dedicated f2b32 instruction, but
919 * we can do a "not equal to 0.0" test. */
921 ALU_CASE_CMP(f2b32
, fne
, false);
922 ALU_CASE_CMP(i2b32
, ine
, true);
924 ALU_CASE(frcp
, frcp
);
925 ALU_CASE(frsq
, frsqrt
);
926 ALU_CASE(fsqrt
, fsqrt
);
927 ALU_CASE(fexp2
, fexp2
);
928 ALU_CASE(flog2
, flog2
);
930 ALU_CASE_RTZ(f2i64
, f2i_rte
);
931 ALU_CASE_RTZ(f2u64
, f2u_rte
);
932 ALU_CASE_RTZ(i2f64
, i2f_rte
);
933 ALU_CASE_RTZ(u2f64
, u2f_rte
);
935 ALU_CASE_RTZ(f2i32
, f2i_rte
);
936 ALU_CASE_RTZ(f2u32
, f2u_rte
);
937 ALU_CASE_RTZ(i2f32
, i2f_rte
);
938 ALU_CASE_RTZ(u2f32
, u2f_rte
);
940 ALU_CASE_RTZ(f2i8
, f2i_rte
);
941 ALU_CASE_RTZ(f2u8
, f2u_rte
);
943 ALU_CASE_RTZ(f2i16
, f2i_rte
);
944 ALU_CASE_RTZ(f2u16
, f2u_rte
);
945 ALU_CASE_RTZ(i2f16
, i2f_rte
);
946 ALU_CASE_RTZ(u2f16
, u2f_rte
);
948 ALU_CASE(fsin
, fsin
);
949 ALU_CASE(fcos
, fcos
);
951 /* We'll get 0 in the second arg, so:
952 * ~a = ~(a | 0) = nor(a, 0) */
953 ALU_CASE(inot
, inor
);
954 ALU_CASE(iand
, iand
);
956 ALU_CASE(ixor
, ixor
);
957 ALU_CASE(ishl
, ishl
);
958 ALU_CASE(ishr
, iasr
);
959 ALU_CASE(ushr
, ilsr
);
961 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
962 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
963 ALU_CASE_CMP(b32all_fequal4
, fball_eq
, true);
965 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
966 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
967 ALU_CASE_CMP(b32any_fnequal4
, fbany_neq
, true);
969 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
970 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
971 ALU_CASE_CMP(b32all_iequal4
, iball_eq
, true);
973 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
974 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
975 ALU_CASE_CMP(b32any_inequal4
, ibany_neq
, true);
977 /* Source mods will be shoved in later */
978 ALU_CASE(fabs
, fmov
);
979 ALU_CASE(fneg
, fmov
);
980 ALU_CASE(fsat
, fmov
);
981 ALU_CASE(fsat_signed
, fmov
);
982 ALU_CASE(fclamp_pos
, fmov
);
984 /* For size conversion, we use a move. Ideally though we would squash
985 * these ops together; maybe that has to happen after in NIR as part of
986 * propagation...? An earlier algebraic pass ensured we step down by
987 * only / exactly one size. If stepping down, we use a dest override to
988 * reduce the size; if stepping up, we use a larger-sized move with a
989 * half source and a sign/zero-extension modifier */
1001 case nir_op_f2f64
: {
1002 if (instr
->op
== nir_op_f2f16
|| instr
->op
== nir_op_f2f32
||
1003 instr
->op
== nir_op_f2f64
)
1004 op
= midgard_alu_op_fmov
;
1006 op
= midgard_alu_op_imov
;
1011 /* For greater-or-equal, we lower to less-or-equal and flip the
1017 case nir_op_uge32
: {
1019 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
1020 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
1021 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
1022 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
1026 ALU_CHECK_CMP(false);
1030 case nir_op_b32csel
: {
1031 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
1032 bool is_float
= mir_is_bcsel_float(instr
);
1034 (mixed
? midgard_alu_op_fcsel_v
: midgard_alu_op_fcsel
) :
1035 (mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
);
1040 case nir_op_unpack_32_2x16
:
1041 case nir_op_unpack_32_4x8
:
1042 case nir_op_pack_32_2x16
:
1043 case nir_op_pack_32_4x8
: {
1044 op
= midgard_alu_op_imov
;
1049 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1054 /* Promote imov to fmov if it might help inline a constant */
1055 if (op
== midgard_alu_op_imov
&& nir_src_is_const(instr
->src
[0].src
)
1056 && nir_src_bit_size(instr
->src
[0].src
) == 32
1057 && nir_is_same_comp_swizzle(instr
->src
[0].swizzle
,
1058 nir_src_num_components(instr
->src
[0].src
))) {
1059 op
= midgard_alu_op_fmov
;
1062 /* Midgard can perform certain modifiers on output of an ALU op */
1064 unsigned outmod
= 0;
1065 bool is_int
= midgard_is_integer_op(op
);
1067 if (midgard_is_integer_out_op(op
)) {
1068 outmod
= midgard_outmod_int_wrap
;
1069 } else if (instr
->op
== nir_op_fsat
) {
1070 outmod
= midgard_outmod_sat
;
1071 } else if (instr
->op
== nir_op_fsat_signed
) {
1072 outmod
= midgard_outmod_sat_signed
;
1073 } else if (instr
->op
== nir_op_fclamp_pos
) {
1074 outmod
= midgard_outmod_pos
;
1077 /* Fetch unit, quirks, etc information */
1078 unsigned opcode_props
= alu_opcode_props
[op
].props
;
1079 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1081 /* Look for floating point mods. We have the mods fsat, fsat_signed,
1082 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
1084 * fsat_signed(fpos(x)) = fsat(x)
1085 * fsat_signed(fsat(x)) = fsat(x)
1086 * fpos(fsat_signed(x)) = fsat(x)
1087 * fpos(fsat(x)) = fsat(x)
1088 * fsat(fsat_signed(x)) = fsat(x)
1089 * fsat(fpos(x)) = fsat(x)
1091 * So by cases any composition of output modifiers is equivalent to
1095 if (!is_int
&& !(opcode_props
& OP_TYPE_CONVERT
)) {
1096 bool fpos
= mir_accept_dest_mod(ctx
, &dest
, nir_op_fclamp_pos
);
1097 bool fsat
= mir_accept_dest_mod(ctx
, &dest
, nir_op_fsat
);
1098 bool ssat
= mir_accept_dest_mod(ctx
, &dest
, nir_op_fsat_signed
);
1099 bool prior
= (outmod
!= midgard_outmod_none
);
1100 int count
= (int) prior
+ (int) fpos
+ (int) ssat
+ (int) fsat
;
1102 outmod
= ((count
> 1) || fsat
) ? midgard_outmod_sat
:
1103 fpos
? midgard_outmod_pos
:
1104 ssat
? midgard_outmod_sat_signed
:
1108 midgard_instruction ins
= {
1110 .dest
= nir_dest_index(dest
),
1111 .dest_type
= nir_op_infos
[instr
->op
].output_type
1112 | nir_dest_bit_size(*dest
),
1113 .roundmode
= roundmode
,
1116 enum midgard_roundmode
*roundptr
= (opcode_props
& MIDGARD_ROUNDS
) ?
1117 &ins
.roundmode
: NULL
;
1119 for (unsigned i
= nr_inputs
; i
< ARRAY_SIZE(ins
.src
); ++i
)
1122 if (quirk_flipped_r24
) {
1124 mir_copy_src(&ins
, instr
, 0, 1, &ins
.src_abs
[1], &ins
.src_neg
[1], &ins
.src_invert
[1], roundptr
, is_int
, broadcast_swizzle
);
1126 for (unsigned i
= 0; i
< nr_inputs
; ++i
) {
1129 if (instr
->op
== nir_op_b32csel
) {
1130 /* The condition is the first argument; move
1131 * the other arguments up one to be a binary
1132 * instruction for Midgard with the condition
1137 else if (flip_src12
)
1141 } else if (flip_src12
) {
1145 mir_copy_src(&ins
, instr
, i
, to
, &ins
.src_abs
[to
], &ins
.src_neg
[to
], &ins
.src_invert
[to
], roundptr
, is_int
, broadcast_swizzle
);
1147 /* (!c) ? a : b = c ? b : a */
1148 if (instr
->op
== nir_op_b32csel
&& ins
.src_invert
[2]) {
1149 ins
.src_invert
[2] = false;
1155 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
1156 /* Lowered to move */
1157 if (instr
->op
== nir_op_fneg
)
1158 ins
.src_neg
[1] ^= true;
1160 if (instr
->op
== nir_op_fabs
)
1161 ins
.src_abs
[1] = true;
1164 ins
.mask
= mask_of(nr_components
);
1166 midgard_vector_alu alu
= {
1168 .reg_mode
= reg_mode
,
1172 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1173 * components that don't exist. Note modifier => SSA => !reg => no
1174 * writemask, so we don't have to worry about writemasks here.*/
1177 ins
.mask
&= instr
->dest
.write_mask
;
1181 /* Late fixup for emulated instructions */
1183 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1184 /* Presently, our second argument is an inline #0 constant.
1185 * Switch over to an embedded 1.0 constant (that can't fit
1186 * inline, since we're 32-bit, not 16-bit like the inline
1189 ins
.has_inline_constant
= false;
1190 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1191 ins
.src_types
[1] = nir_type_float32
;
1192 ins
.has_constants
= true;
1194 if (instr
->op
== nir_op_b2f32
)
1195 ins
.constants
.f32
[0] = 1.0f
;
1197 ins
.constants
.i32
[0] = 1;
1199 for (unsigned c
= 0; c
< 16; ++c
)
1200 ins
.swizzle
[1][c
] = 0;
1201 } else if (instr
->op
== nir_op_b2f16
) {
1202 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1203 ins
.src_types
[1] = nir_type_float16
;
1204 ins
.has_constants
= true;
1205 ins
.constants
.i16
[0] = _mesa_float_to_half(1.0);
1207 for (unsigned c
= 0; c
< 16; ++c
)
1208 ins
.swizzle
[1][c
] = 0;
1209 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1210 /* Lots of instructions need a 0 plonked in */
1211 ins
.has_inline_constant
= false;
1212 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1213 ins
.src_types
[1] = nir_type_uint32
;
1214 ins
.has_constants
= true;
1215 ins
.constants
.u32
[0] = 0;
1217 for (unsigned c
= 0; c
< 16; ++c
)
1218 ins
.swizzle
[1][c
] = 0;
1219 } else if (instr
->op
== nir_op_pack_32_2x16
) {
1220 ins
.dest_type
= nir_type_uint16
;
1221 ins
.mask
= mask_of(nr_components
* 2);
1223 } else if (instr
->op
== nir_op_pack_32_4x8
) {
1224 ins
.dest_type
= nir_type_uint8
;
1225 ins
.mask
= mask_of(nr_components
* 4);
1227 } else if (instr
->op
== nir_op_unpack_32_2x16
) {
1228 ins
.dest_type
= nir_type_uint32
;
1229 ins
.mask
= mask_of(nr_components
>> 1);
1231 } else if (instr
->op
== nir_op_unpack_32_4x8
) {
1232 ins
.dest_type
= nir_type_uint32
;
1233 ins
.mask
= mask_of(nr_components
>> 2);
1237 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1238 /* To avoid duplicating the lookup tables (probably), true LUT
1239 * instructions can only operate as if they were scalars. Lower
1240 * them here by changing the component. */
1242 unsigned orig_mask
= ins
.mask
;
1244 unsigned swizzle_back
[MIR_VEC_COMPONENTS
];
1245 memcpy(&swizzle_back
, ins
.swizzle
[0], sizeof(swizzle_back
));
1247 for (int i
= 0; i
< nr_components
; ++i
) {
1248 /* Mask the associated component, dropping the
1249 * instruction if needed */
1252 ins
.mask
&= orig_mask
;
1257 for (unsigned j
= 0; j
< MIR_VEC_COMPONENTS
; ++j
)
1258 ins
.swizzle
[0][j
] = swizzle_back
[i
]; /* Pull from the correct component */
1260 emit_mir_instruction(ctx
, ins
);
1263 emit_mir_instruction(ctx
, ins
);
1270 mir_set_intr_mask(nir_instr
*instr
, midgard_instruction
*ins
, bool is_read
)
1272 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
1273 unsigned nir_mask
= 0;
1277 nir_mask
= mask_of(nir_intrinsic_dest_components(intr
));
1278 dsize
= nir_dest_bit_size(intr
->dest
);
1280 nir_mask
= nir_intrinsic_write_mask(intr
);
1284 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1285 unsigned bytemask
= pan_to_bytemask(dsize
, nir_mask
);
1286 mir_set_bytemask(ins
, bytemask
);
1287 ins
->dest_type
= nir_type_uint
| dsize
;
1290 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1291 * optimized) versions of UBO #0 */
1293 static midgard_instruction
*
1295 compiler_context
*ctx
,
1299 nir_src
*indirect_offset
,
1300 unsigned indirect_shift
,
1303 /* TODO: half-floats */
1305 midgard_instruction ins
= m_ld_ubo_int4(dest
, 0);
1306 ins
.constants
.u32
[0] = offset
;
1308 if (instr
->type
== nir_instr_type_intrinsic
)
1309 mir_set_intr_mask(instr
, &ins
, true);
1311 if (indirect_offset
) {
1312 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1313 ins
.src_types
[2] = nir_type_uint32
;
1314 ins
.load_store
.arg_2
= (indirect_shift
<< 5);
1316 ins
.load_store
.arg_2
= 0x1E;
1319 ins
.load_store
.arg_1
= index
;
1321 return emit_mir_instruction(ctx
, ins
);
1324 /* Globals are like UBOs if you squint. And shared memory is like globals if
1325 * you squint even harder */
1329 compiler_context
*ctx
,
1338 midgard_instruction ins
;
1341 ins
= m_ld_int4(srcdest
, 0);
1343 ins
= m_st_int4(srcdest
, 0);
1345 mir_set_offset(ctx
, &ins
, offset
, is_shared
);
1346 mir_set_intr_mask(instr
, &ins
, is_read
);
1348 emit_mir_instruction(ctx
, ins
);
1353 compiler_context
*ctx
,
1354 unsigned dest
, unsigned offset
,
1355 unsigned nr_comp
, unsigned component
,
1356 nir_src
*indirect_offset
, nir_alu_type type
, bool flat
)
1358 /* XXX: Half-floats? */
1359 /* TODO: swizzle, mask */
1361 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1362 ins
.mask
= mask_of(nr_comp
);
1363 ins
.dest_type
= type
;
1365 if (type
== nir_type_float16
) {
1366 /* Ensure we are aligned so we can pack it later */
1367 ins
.mask
= mask_of(ALIGN_POT(nr_comp
, 2));
1370 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
.swizzle
[0]); ++i
)
1371 ins
.swizzle
[0][i
] = MIN2(i
+ component
, COMPONENT_W
);
1373 midgard_varying_parameter p
= {
1375 .interpolation
= midgard_interp_default
,
1380 memcpy(&u
, &p
, sizeof(p
));
1381 ins
.load_store
.varying_parameters
= u
;
1383 if (indirect_offset
) {
1384 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1385 ins
.src_types
[2] = nir_type_uint32
;
1387 ins
.load_store
.arg_2
= 0x1E;
1389 ins
.load_store
.arg_1
= 0x9E;
1391 /* Use the type appropriate load */
1393 case nir_type_uint32
:
1394 case nir_type_bool32
:
1395 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1397 case nir_type_int32
:
1398 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1400 case nir_type_float32
:
1401 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1403 case nir_type_float16
:
1404 ins
.load_store
.op
= midgard_op_ld_vary_16
;
1407 unreachable("Attempted to load unknown type");
1411 emit_mir_instruction(ctx
, ins
);
1416 compiler_context
*ctx
,
1417 unsigned dest
, unsigned offset
,
1418 unsigned nr_comp
, nir_alu_type t
)
1420 midgard_instruction ins
= m_ld_attr_32(dest
, offset
);
1421 ins
.load_store
.arg_1
= 0x1E;
1422 ins
.load_store
.arg_2
= 0x1E;
1423 ins
.mask
= mask_of(nr_comp
);
1425 /* Use the type appropriate load */
1429 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1432 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1434 case nir_type_float
:
1435 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1438 unreachable("Attempted to load unknown type");
1442 emit_mir_instruction(ctx
, ins
);
1446 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
,
1447 unsigned nr_components
, unsigned offset
)
1451 /* Figure out which uniform this is */
1452 int sysval
= panfrost_sysval_for_instr(instr
, &nir_dest
);
1453 void *val
= _mesa_hash_table_u64_search(ctx
->sysvals
.sysval_to_id
, sysval
);
1455 unsigned dest
= nir_dest_index(&nir_dest
);
1457 /* Sysvals are prefix uniforms */
1458 unsigned uniform
= ((uintptr_t) val
) - 1;
1460 /* Emit the read itself -- this is never indirect */
1461 midgard_instruction
*ins
=
1462 emit_ubo_read(ctx
, instr
, dest
, (uniform
* 16) + offset
, NULL
, 0, 0);
1464 ins
->mask
= mask_of(nr_components
);
1468 compute_builtin_arg(nir_op op
)
1471 case nir_intrinsic_load_work_group_id
:
1473 case nir_intrinsic_load_local_invocation_id
:
1476 unreachable("Invalid compute paramater loaded");
1481 emit_fragment_store(compiler_context
*ctx
, unsigned src
, unsigned src_z
, unsigned src_s
, enum midgard_rt_id rt
)
1483 assert(rt
< ARRAY_SIZE(ctx
->writeout_branch
));
1485 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
1489 emit_explicit_constant(ctx
, src
, src
);
1491 struct midgard_instruction ins
=
1492 v_branch(false, false);
1494 bool depth_only
= (rt
== MIDGARD_ZS_RT
);
1496 ins
.writeout
= depth_only
? 0 : PAN_WRITEOUT_C
;
1498 /* Add dependencies */
1500 ins
.src_types
[0] = nir_type_uint32
;
1501 ins
.constants
.u32
[0] = depth_only
? 0xFF : (rt
- MIDGARD_COLOR_RT0
) * 0x100;
1502 for (int i
= 0; i
< 4; ++i
)
1503 ins
.swizzle
[0][i
] = i
;
1506 emit_explicit_constant(ctx
, src_z
, src_z
);
1508 ins
.src_types
[2] = nir_type_uint32
;
1509 ins
.writeout
|= PAN_WRITEOUT_Z
;
1512 emit_explicit_constant(ctx
, src_s
, src_s
);
1514 ins
.src_types
[3] = nir_type_uint32
;
1515 ins
.writeout
|= PAN_WRITEOUT_S
;
1518 /* Emit the branch */
1519 br
= emit_mir_instruction(ctx
, ins
);
1520 schedule_barrier(ctx
);
1521 ctx
->writeout_branch
[rt
] = br
;
1523 /* Push our current location = current block count - 1 = where we'll
1524 * jump to. Maybe a bit too clever for my own good */
1526 br
->branch
.target_block
= ctx
->block_count
- 1;
1530 emit_compute_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1532 unsigned reg
= nir_dest_index(&instr
->dest
);
1533 midgard_instruction ins
= m_ld_compute_id(reg
, 0);
1534 ins
.mask
= mask_of(3);
1535 ins
.swizzle
[0][3] = COMPONENT_X
; /* xyzx */
1536 ins
.load_store
.arg_1
= compute_builtin_arg(instr
->intrinsic
);
1537 emit_mir_instruction(ctx
, ins
);
1541 vertex_builtin_arg(nir_op op
)
1544 case nir_intrinsic_load_vertex_id
:
1545 return PAN_VERTEX_ID
;
1546 case nir_intrinsic_load_instance_id
:
1547 return PAN_INSTANCE_ID
;
1549 unreachable("Invalid vertex builtin");
1554 emit_vertex_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1556 unsigned reg
= nir_dest_index(&instr
->dest
);
1557 emit_attr_read(ctx
, reg
, vertex_builtin_arg(instr
->intrinsic
), 1, nir_type_int
);
1561 emit_control_barrier(compiler_context
*ctx
)
1563 midgard_instruction ins
= {
1564 .type
= TAG_TEXTURE_4
,
1566 .src
= { ~0, ~0, ~0, ~0 },
1568 .op
= TEXTURE_OP_BARRIER
,
1570 /* TODO: optimize */
1571 .out_of_order
= MIDGARD_BARRIER_BUFFER
|
1572 MIDGARD_BARRIER_SHARED
,
1576 emit_mir_instruction(ctx
, ins
);
1580 mir_get_branch_cond(nir_src
*src
, bool *invert
)
1582 /* Wrap it. No swizzle since it's a scalar */
1588 *invert
= pan_has_source_mod(&alu
, nir_op_inot
);
1589 return nir_src_index(NULL
, &alu
.src
);
1593 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1595 unsigned offset
= 0, reg
;
1597 switch (instr
->intrinsic
) {
1598 case nir_intrinsic_discard_if
:
1599 case nir_intrinsic_discard
: {
1600 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1601 struct midgard_instruction discard
= v_branch(conditional
, false);
1602 discard
.branch
.target_type
= TARGET_DISCARD
;
1605 discard
.src
[0] = mir_get_branch_cond(&instr
->src
[0],
1606 &discard
.branch
.invert_conditional
);
1607 discard
.src_types
[0] = nir_type_uint32
;
1610 emit_mir_instruction(ctx
, discard
);
1611 schedule_barrier(ctx
);
1616 case nir_intrinsic_load_uniform
:
1617 case nir_intrinsic_load_ubo
:
1618 case nir_intrinsic_load_global
:
1619 case nir_intrinsic_load_shared
:
1620 case nir_intrinsic_load_input
:
1621 case nir_intrinsic_load_interpolated_input
: {
1622 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1623 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1624 bool is_global
= instr
->intrinsic
== nir_intrinsic_load_global
;
1625 bool is_shared
= instr
->intrinsic
== nir_intrinsic_load_shared
;
1626 bool is_flat
= instr
->intrinsic
== nir_intrinsic_load_input
;
1627 bool is_interp
= instr
->intrinsic
== nir_intrinsic_load_interpolated_input
;
1629 /* Get the base type of the intrinsic */
1630 /* TODO: Infer type? Does it matter? */
1632 (is_ubo
|| is_global
|| is_shared
) ? nir_type_uint
:
1633 (is_interp
) ? nir_type_float
:
1634 nir_intrinsic_type(instr
);
1636 t
= nir_alu_type_get_base_type(t
);
1638 if (!(is_ubo
|| is_global
)) {
1639 offset
= nir_intrinsic_base(instr
);
1642 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1644 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1646 bool direct
= nir_src_is_const(*src_offset
);
1647 nir_src
*indirect_offset
= direct
? NULL
: src_offset
;
1650 offset
+= nir_src_as_uint(*src_offset
);
1652 /* We may need to apply a fractional offset */
1653 int component
= (is_flat
|| is_interp
) ?
1654 nir_intrinsic_component(instr
) : 0;
1655 reg
= nir_dest_index(&instr
->dest
);
1657 if (is_uniform
&& !ctx
->is_blend
) {
1658 emit_ubo_read(ctx
, &instr
->instr
, reg
, (ctx
->sysvals
.sysval_count
+ offset
) * 16, indirect_offset
, 4, 0);
1659 } else if (is_ubo
) {
1660 nir_src index
= instr
->src
[0];
1662 /* TODO: Is indirect block number possible? */
1663 assert(nir_src_is_const(index
));
1665 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1666 emit_ubo_read(ctx
, &instr
->instr
, reg
, offset
, indirect_offset
, 0, uindex
);
1667 } else if (is_global
|| is_shared
) {
1668 emit_global(ctx
, &instr
->instr
, true, reg
, src_offset
, is_shared
);
1669 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1670 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, indirect_offset
, t
| nir_dest_bit_size(instr
->dest
), is_flat
);
1671 } else if (ctx
->is_blend
) {
1672 /* ctx->blend_input will be precoloured to r0, where
1673 * the input is preloaded */
1675 if (ctx
->blend_input
== ~0)
1676 ctx
->blend_input
= reg
;
1678 emit_mir_instruction(ctx
, v_mov(ctx
->blend_input
, reg
));
1679 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1680 emit_attr_read(ctx
, reg
, offset
, nr_comp
, t
);
1682 DBG("Unknown load\n");
1689 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1690 case nir_intrinsic_load_barycentric_pixel
:
1691 case nir_intrinsic_load_barycentric_centroid
:
1694 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1696 case nir_intrinsic_load_raw_output_pan
: {
1697 reg
= nir_dest_index(&instr
->dest
);
1698 assert(ctx
->is_blend
);
1700 /* T720 and below use different blend opcodes with slightly
1701 * different semantics than T760 and up */
1703 midgard_instruction ld
= m_ld_color_buffer_32u(reg
, 0);
1705 if (ctx
->quirks
& MIDGARD_OLD_BLEND
) {
1706 ld
.load_store
.op
= midgard_op_ld_color_buffer_32u_old
;
1707 ld
.load_store
.address
= 16;
1708 ld
.load_store
.arg_2
= 0x1E;
1711 emit_mir_instruction(ctx
, ld
);
1715 case nir_intrinsic_load_output
: {
1716 reg
= nir_dest_index(&instr
->dest
);
1717 assert(ctx
->is_blend
);
1719 midgard_instruction ld
= m_ld_color_buffer_as_fp16(reg
, 0);
1721 for (unsigned c
= 4; c
< 16; ++c
)
1722 ld
.swizzle
[0][c
] = 0;
1724 if (ctx
->quirks
& MIDGARD_OLD_BLEND
) {
1725 ld
.load_store
.op
= midgard_op_ld_color_buffer_as_fp16_old
;
1726 ld
.load_store
.address
= 1;
1727 ld
.load_store
.arg_2
= 0x1E;
1730 emit_mir_instruction(ctx
, ld
);
1734 case nir_intrinsic_load_blend_const_color_rgba
: {
1735 assert(ctx
->is_blend
);
1736 reg
= nir_dest_index(&instr
->dest
);
1738 /* Blend constants are embedded directly in the shader and
1739 * patched in, so we use some magic routing */
1741 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), reg
);
1742 ins
.has_constants
= true;
1743 ins
.has_blend_constant
= true;
1744 emit_mir_instruction(ctx
, ins
);
1748 case nir_intrinsic_store_output
:
1749 case nir_intrinsic_store_combined_output_pan
:
1750 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1752 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1754 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1756 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1757 bool combined
= instr
->intrinsic
==
1758 nir_intrinsic_store_combined_output_pan
;
1760 const nir_variable
*var
;
1761 enum midgard_rt_id rt
;
1763 var
= search_var(&ctx
->nir
->outputs
,
1764 nir_intrinsic_base(instr
));
1766 if (var
->data
.location
== FRAG_RESULT_COLOR
)
1767 rt
= MIDGARD_COLOR_RT0
;
1768 else if (var
->data
.location
>= FRAG_RESULT_DATA0
)
1769 rt
= MIDGARD_COLOR_RT0
+ var
->data
.location
-
1776 unsigned reg_z
= ~0, reg_s
= ~0;
1778 unsigned writeout
= nir_intrinsic_component(instr
);
1779 if (writeout
& PAN_WRITEOUT_Z
)
1780 reg_z
= nir_src_index(ctx
, &instr
->src
[2]);
1781 if (writeout
& PAN_WRITEOUT_S
)
1782 reg_s
= nir_src_index(ctx
, &instr
->src
[3]);
1785 emit_fragment_store(ctx
, reg
, reg_z
, reg_s
, rt
);
1786 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1787 assert(instr
->intrinsic
== nir_intrinsic_store_output
);
1789 /* We should have been vectorized, though we don't
1790 * currently check that st_vary is emitted only once
1791 * per slot (this is relevant, since there's not a mask
1792 * parameter available on the store [set to 0 by the
1793 * blob]). We do respect the component by adjusting the
1794 * swizzle. If this is a constant source, we'll need to
1795 * emit that explicitly. */
1797 emit_explicit_constant(ctx
, reg
, reg
);
1799 unsigned dst_component
= nir_intrinsic_component(instr
);
1800 unsigned nr_comp
= nir_src_num_components(instr
->src
[0]);
1802 midgard_instruction st
= m_st_vary_32(reg
, offset
);
1803 st
.load_store
.arg_1
= 0x9E;
1804 st
.load_store
.arg_2
= 0x1E;
1806 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr
))) {
1809 st
.load_store
.op
= midgard_op_st_vary_32u
;
1812 st
.load_store
.op
= midgard_op_st_vary_32i
;
1814 case nir_type_float
:
1815 st
.load_store
.op
= midgard_op_st_vary_32
;
1818 unreachable("Attempted to store unknown type");
1822 /* nir_intrinsic_component(store_intr) encodes the
1823 * destination component start. Source component offset
1824 * adjustment is taken care of in
1825 * install_registers_instr(), when offset_swizzle() is
1828 unsigned src_component
= COMPONENT_X
;
1830 assert(nr_comp
> 0);
1831 for (unsigned i
= 0; i
< ARRAY_SIZE(st
.swizzle
); ++i
) {
1832 st
.swizzle
[0][i
] = src_component
;
1833 if (i
>= dst_component
&& i
< dst_component
+ nr_comp
- 1)
1837 emit_mir_instruction(ctx
, st
);
1839 DBG("Unknown store\n");
1845 /* Special case of store_output for lowered blend shaders */
1846 case nir_intrinsic_store_raw_output_pan
:
1847 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1848 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1849 emit_fragment_store(ctx
, reg
, ~0, ~0, ctx
->blend_rt
);
1852 case nir_intrinsic_store_global
:
1853 case nir_intrinsic_store_shared
:
1854 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1855 emit_explicit_constant(ctx
, reg
, reg
);
1857 emit_global(ctx
, &instr
->instr
, false, reg
, &instr
->src
[1], instr
->intrinsic
== nir_intrinsic_store_shared
);
1860 case nir_intrinsic_load_ssbo_address
:
1861 emit_sysval_read(ctx
, &instr
->instr
, 1, 0);
1864 case nir_intrinsic_get_buffer_size
:
1865 emit_sysval_read(ctx
, &instr
->instr
, 1, 8);
1868 case nir_intrinsic_load_viewport_scale
:
1869 case nir_intrinsic_load_viewport_offset
:
1870 case nir_intrinsic_load_num_work_groups
:
1871 case nir_intrinsic_load_sampler_lod_parameters_pan
:
1872 emit_sysval_read(ctx
, &instr
->instr
, 3, 0);
1875 case nir_intrinsic_load_work_group_id
:
1876 case nir_intrinsic_load_local_invocation_id
:
1877 emit_compute_builtin(ctx
, instr
);
1880 case nir_intrinsic_load_vertex_id
:
1881 case nir_intrinsic_load_instance_id
:
1882 emit_vertex_builtin(ctx
, instr
);
1885 case nir_intrinsic_memory_barrier_buffer
:
1886 case nir_intrinsic_memory_barrier_shared
:
1889 case nir_intrinsic_control_barrier
:
1890 schedule_barrier(ctx
);
1891 emit_control_barrier(ctx
);
1892 schedule_barrier(ctx
);
1896 fprintf(stderr
, "Unhandled intrinsic %s\n", nir_intrinsic_infos
[instr
->intrinsic
].name
);
1903 midgard_tex_format(enum glsl_sampler_dim dim
)
1906 case GLSL_SAMPLER_DIM_1D
:
1907 case GLSL_SAMPLER_DIM_BUF
:
1910 case GLSL_SAMPLER_DIM_2D
:
1911 case GLSL_SAMPLER_DIM_EXTERNAL
:
1912 case GLSL_SAMPLER_DIM_RECT
:
1915 case GLSL_SAMPLER_DIM_3D
:
1918 case GLSL_SAMPLER_DIM_CUBE
:
1919 return MALI_TEX_CUBE
;
1922 DBG("Unknown sampler dim type\n");
1928 /* Tries to attach an explicit LOD or bias as a constant. Returns whether this
1932 pan_attach_constant_bias(
1933 compiler_context
*ctx
,
1935 midgard_texture_word
*word
)
1937 /* To attach as constant, it has to *be* constant */
1939 if (!nir_src_is_const(lod
))
1942 float f
= nir_src_as_float(lod
);
1944 /* Break into fixed-point */
1946 float lod_frac
= f
- lod_int
;
1948 /* Carry over negative fractions */
1949 if (lod_frac
< 0.0) {
1955 word
->bias
= float_to_ubyte(lod_frac
);
1956 word
->bias_int
= lod_int
;
1962 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1963 unsigned midgard_texop
)
1966 //assert (!instr->sampler);
1968 int texture_index
= instr
->texture_index
;
1969 int sampler_index
= texture_index
;
1971 nir_alu_type dest_base
= nir_alu_type_get_base_type(instr
->dest_type
);
1972 nir_alu_type dest_type
= dest_base
| nir_dest_bit_size(instr
->dest
);
1974 midgard_instruction ins
= {
1975 .type
= TAG_TEXTURE_4
,
1977 .dest
= nir_dest_index(&instr
->dest
),
1978 .src
= { ~0, ~0, ~0, ~0 },
1979 .dest_type
= dest_type
,
1980 .swizzle
= SWIZZLE_IDENTITY_4
,
1982 .op
= midgard_texop
,
1983 .format
= midgard_tex_format(instr
->sampler_dim
),
1984 .texture_handle
= texture_index
,
1985 .sampler_handle
= sampler_index
,
1986 .shadow
= instr
->is_shadow
,
1990 if (instr
->is_shadow
&& !instr
->is_new_style_shadow
)
1991 for (int i
= 0; i
< 4; ++i
)
1992 ins
.swizzle
[0][i
] = COMPONENT_X
;
1994 /* We may need a temporary for the coordinate */
1996 bool needs_temp_coord
=
1997 (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) ||
1998 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) ||
2001 unsigned coords
= needs_temp_coord
? make_compiler_temp_reg(ctx
) : 0;
2003 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
2004 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
2005 unsigned nr_components
= nir_src_num_components(instr
->src
[i
].src
);
2006 unsigned sz
= nir_src_bit_size(instr
->src
[i
].src
);
2007 nir_alu_type T
= nir_tex_instr_src_type(instr
, i
) | sz
;
2009 switch (instr
->src
[i
].src_type
) {
2010 case nir_tex_src_coord
: {
2011 emit_explicit_constant(ctx
, index
, index
);
2013 unsigned coord_mask
= mask_of(instr
->coord_components
);
2015 bool flip_zw
= (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) && (coord_mask
& (1 << COMPONENT_Z
));
2018 coord_mask
^= ((1 << COMPONENT_Z
) | (1 << COMPONENT_W
));
2020 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2021 /* texelFetch is undefined on samplerCube */
2022 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
2024 /* For cubemaps, we use a special ld/st op to
2025 * select the face and copy the xy into the
2026 * texture register */
2028 midgard_instruction ld
= m_ld_cubemap_coords(coords
, 0);
2030 ld
.src_types
[1] = T
;
2031 ld
.mask
= 0x3; /* xy */
2032 ld
.load_store
.arg_1
= 0x20;
2033 ld
.swizzle
[1][3] = COMPONENT_X
;
2034 emit_mir_instruction(ctx
, ld
);
2037 ins
.swizzle
[1][2] = instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
2038 ins
.swizzle
[1][3] = COMPONENT_X
;
2039 } else if (needs_temp_coord
) {
2040 /* mov coord_temp, coords */
2041 midgard_instruction mov
= v_mov(index
, coords
);
2042 mov
.mask
= coord_mask
;
2045 mov
.swizzle
[1][COMPONENT_W
] = COMPONENT_Z
;
2047 emit_mir_instruction(ctx
, mov
);
2052 ins
.src
[1] = coords
;
2053 ins
.src_types
[1] = T
;
2055 /* Texelfetch coordinates uses all four elements
2056 * (xyz/index) regardless of texture dimensionality,
2057 * which means it's necessary to zero the unused
2058 * components to keep everything happy */
2060 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
2061 /* mov index.zw, #0, or generalized */
2062 midgard_instruction mov
=
2063 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), coords
);
2064 mov
.has_constants
= true;
2065 mov
.mask
= coord_mask
^ 0xF;
2066 emit_mir_instruction(ctx
, mov
);
2069 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) {
2070 /* Array component in w but NIR wants it in z,
2071 * but if we have a temp coord we already fixed
2074 if (nr_components
== 3) {
2075 ins
.swizzle
[1][2] = COMPONENT_Z
;
2076 ins
.swizzle
[1][3] = needs_temp_coord
? COMPONENT_W
: COMPONENT_Z
;
2077 } else if (nr_components
== 2) {
2079 instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
2080 ins
.swizzle
[1][3] = COMPONENT_X
;
2082 unreachable("Invalid texture 2D components");
2085 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
2087 ins
.swizzle
[1][2] = COMPONENT_Z
;
2088 ins
.swizzle
[1][3] = COMPONENT_W
;
2094 case nir_tex_src_bias
:
2095 case nir_tex_src_lod
: {
2096 /* Try as a constant if we can */
2098 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
2099 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
2102 ins
.texture
.lod_register
= true;
2104 ins
.src_types
[2] = T
;
2106 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
2107 ins
.swizzle
[2][c
] = COMPONENT_X
;
2109 emit_explicit_constant(ctx
, index
, index
);
2114 case nir_tex_src_offset
: {
2115 ins
.texture
.offset_register
= true;
2117 ins
.src_types
[3] = T
;
2119 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
2120 ins
.swizzle
[3][c
] = (c
> COMPONENT_Z
) ? 0 : c
;
2122 emit_explicit_constant(ctx
, index
, index
);
2126 case nir_tex_src_comparator
: {
2127 unsigned comp
= COMPONENT_Z
;
2129 /* mov coord_temp.foo, coords */
2130 midgard_instruction mov
= v_mov(index
, coords
);
2131 mov
.mask
= 1 << comp
;
2133 for (unsigned i
= 0; i
< MIR_VEC_COMPONENTS
; ++i
)
2134 mov
.swizzle
[1][i
] = COMPONENT_X
;
2136 emit_mir_instruction(ctx
, mov
);
2141 fprintf(stderr
, "Unknown texture source type: %d\n", instr
->src
[i
].src_type
);
2147 emit_mir_instruction(ctx
, ins
);
2151 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
2153 switch (instr
->op
) {
2156 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
2159 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
2162 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
2165 emit_sysval_read(ctx
, &instr
->instr
, 4, 0);
2168 fprintf(stderr
, "Unhandled texture op: %d\n", instr
->op
);
2175 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
2177 switch (instr
->type
) {
2178 case nir_jump_break
: {
2179 /* Emit a branch out of the loop */
2180 struct midgard_instruction br
= v_branch(false, false);
2181 br
.branch
.target_type
= TARGET_BREAK
;
2182 br
.branch
.target_break
= ctx
->current_loop_depth
;
2183 emit_mir_instruction(ctx
, br
);
2188 DBG("Unknown jump type %d\n", instr
->type
);
2194 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
2196 switch (instr
->type
) {
2197 case nir_instr_type_load_const
:
2198 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2201 case nir_instr_type_intrinsic
:
2202 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2205 case nir_instr_type_alu
:
2206 emit_alu(ctx
, nir_instr_as_alu(instr
));
2209 case nir_instr_type_tex
:
2210 emit_tex(ctx
, nir_instr_as_tex(instr
));
2213 case nir_instr_type_jump
:
2214 emit_jump(ctx
, nir_instr_as_jump(instr
));
2217 case nir_instr_type_ssa_undef
:
2222 DBG("Unhandled instruction type\n");
2228 /* ALU instructions can inline or embed constants, which decreases register
2229 * pressure and saves space. */
2231 #define CONDITIONAL_ATTACH(idx) { \
2232 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2235 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2236 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2241 inline_alu_constants(compiler_context
*ctx
, midgard_block
*block
)
2243 mir_foreach_instr_in_block(block
, alu
) {
2244 /* Other instructions cannot inline constants */
2245 if (alu
->type
!= TAG_ALU_4
) continue;
2246 if (alu
->compact_branch
) continue;
2248 /* If there is already a constant here, we can do nothing */
2249 if (alu
->has_constants
) continue;
2251 CONDITIONAL_ATTACH(0);
2253 if (!alu
->has_constants
) {
2254 CONDITIONAL_ATTACH(1)
2255 } else if (!alu
->inline_constant
) {
2256 /* Corner case: _two_ vec4 constants, for instance with a
2257 * csel. For this case, we can only use a constant
2258 * register for one, we'll have to emit a move for the
2261 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->src
[1] + 1);
2262 unsigned scratch
= make_compiler_temp(ctx
);
2265 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), scratch
);
2266 attach_constants(ctx
, &ins
, entry
, alu
->src
[1] + 1);
2268 /* Set the source */
2269 alu
->src
[1] = scratch
;
2271 /* Inject us -before- the last instruction which set r31 */
2272 mir_insert_instruction_before(ctx
, mir_prev_op(alu
), ins
);
2278 /* Midgard supports two types of constants, embedded constants (128-bit) and
2279 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2280 * constants can be demoted to inline constants, for space savings and
2281 * sometimes a performance boost */
2284 embedded_to_inline_constant(compiler_context
*ctx
, midgard_block
*block
)
2286 mir_foreach_instr_in_block(block
, ins
) {
2287 if (!ins
->has_constants
) continue;
2288 if (ins
->has_inline_constant
) continue;
2290 /* Blend constants must not be inlined by definition */
2291 if (ins
->has_blend_constant
) continue;
2293 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2294 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
2295 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
2297 if (!(is_16
|| is_32
))
2300 /* src1 cannot be an inline constant due to encoding
2301 * restrictions. So, if possible we try to flip the arguments
2304 int op
= ins
->alu
.op
;
2306 if (ins
->src
[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
) &&
2307 alu_opcode_props
[op
].props
& OP_COMMUTES
) {
2311 if (ins
->src
[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2312 /* Component is from the swizzle. Take a nonzero component */
2314 unsigned first_comp
= ffs(ins
->mask
) - 1;
2315 unsigned component
= ins
->swizzle
[1][first_comp
];
2317 /* Scale constant appropriately, if we can legally */
2318 int16_t scaled_constant
= 0;
2321 scaled_constant
= ins
->constants
.u16
[component
];
2322 } else if (midgard_is_integer_op(op
)) {
2323 scaled_constant
= ins
->constants
.u32
[component
];
2325 /* Constant overflow after resize */
2326 if (scaled_constant
!= ins
->constants
.u32
[component
])
2329 float original
= ins
->constants
.f32
[component
];
2330 scaled_constant
= _mesa_float_to_half(original
);
2332 /* Check for loss of precision. If this is
2333 * mediump, we don't care, but for a highp
2334 * shader, we need to pay attention. NIR
2335 * doesn't yet tell us which mode we're in!
2336 * Practically this prevents most constants
2337 * from being inlined, sadly. */
2339 float fp32
= _mesa_half_to_float(scaled_constant
);
2341 if (fp32
!= original
)
2345 /* Should've been const folded */
2346 if (ins
->src_abs
[1] || ins
->src_neg
[1])
2349 /* Make sure that the constant is not itself a vector
2350 * by checking if all accessed values are the same. */
2352 const midgard_constants
*cons
= &ins
->constants
;
2353 uint32_t value
= is_16
? cons
->u16
[component
] : cons
->u32
[component
];
2355 bool is_vector
= false;
2356 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
2358 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
) {
2359 /* We only care if this component is actually used */
2360 if (!(mask
& (1 << c
)))
2363 uint32_t test
= is_16
?
2364 cons
->u16
[ins
->swizzle
[1][c
]] :
2365 cons
->u32
[ins
->swizzle
[1][c
]];
2367 if (test
!= value
) {
2376 /* Get rid of the embedded constant */
2377 ins
->has_constants
= false;
2379 ins
->has_inline_constant
= true;
2380 ins
->inline_constant
= scaled_constant
;
2385 /* Dead code elimination for branches at the end of a block - only one branch
2386 * per block is legal semantically */
2389 midgard_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
2391 bool branched
= false;
2393 mir_foreach_instr_in_block_safe(block
, ins
) {
2394 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2397 mir_remove_instruction(ins
);
2403 /* We want to force the invert on AND/OR to the second slot to legalize into
2404 * iandnot/iornot. The relevant patterns are for AND (and OR respectively)
2406 * ~a & #b = ~a & ~(#~b)
2411 midgard_legalize_invert(compiler_context
*ctx
, midgard_block
*block
)
2413 mir_foreach_instr_in_block(block
, ins
) {
2414 if (ins
->type
!= TAG_ALU_4
) continue;
2416 if (ins
->alu
.op
!= midgard_alu_op_iand
&&
2417 ins
->alu
.op
!= midgard_alu_op_ior
) continue;
2419 if (ins
->src_invert
[1] || !ins
->src_invert
[0]) continue;
2421 if (ins
->has_inline_constant
) {
2422 /* ~(#~a) = ~(~#a) = a, so valid, and forces both
2424 ins
->inline_constant
= ~ins
->inline_constant
;
2425 ins
->src_invert
[1] = true;
2427 /* Flip to the right invert order. Note
2428 * has_inline_constant false by assumption on the
2429 * branch, so flipping makes sense. */
2436 emit_fragment_epilogue(compiler_context
*ctx
, unsigned rt
)
2438 /* Loop to ourselves */
2439 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
2440 struct midgard_instruction ins
= v_branch(false, false);
2441 ins
.writeout
= br
->writeout
;
2442 ins
.branch
.target_block
= ctx
->block_count
- 1;
2443 ins
.constants
.u32
[0] = br
->constants
.u32
[0];
2444 memcpy(&ins
.src_types
, &br
->src_types
, sizeof(ins
.src_types
));
2445 emit_mir_instruction(ctx
, ins
);
2447 ctx
->current_block
->epilogue
= true;
2448 schedule_barrier(ctx
);
2449 return ins
.branch
.target_block
;
2452 static midgard_block
*
2453 emit_block(compiler_context
*ctx
, nir_block
*block
)
2455 midgard_block
*this_block
= ctx
->after_block
;
2456 ctx
->after_block
= NULL
;
2459 this_block
= create_empty_block(ctx
);
2461 list_addtail(&this_block
->base
.link
, &ctx
->blocks
);
2463 this_block
->scheduled
= false;
2466 /* Set up current block */
2467 list_inithead(&this_block
->base
.instructions
);
2468 ctx
->current_block
= this_block
;
2470 nir_foreach_instr(instr
, block
) {
2471 emit_instr(ctx
, instr
);
2472 ++ctx
->instruction_count
;
2478 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2481 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2483 midgard_block
*before_block
= ctx
->current_block
;
2485 /* Speculatively emit the branch, but we can't fill it in until later */
2487 EMIT(branch
, true, true);
2488 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2489 then_branch
->src
[0] = mir_get_branch_cond(&nif
->condition
, &inv
);
2490 then_branch
->src_types
[0] = nir_type_uint32
;
2491 then_branch
->branch
.invert_conditional
= !inv
;
2493 /* Emit the two subblocks. */
2494 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2495 midgard_block
*end_then_block
= ctx
->current_block
;
2497 /* Emit a jump from the end of the then block to the end of the else */
2498 EMIT(branch
, false, false);
2499 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2501 /* Emit second block, and check if it's empty */
2503 int else_idx
= ctx
->block_count
;
2504 int count_in
= ctx
->instruction_count
;
2505 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2506 midgard_block
*end_else_block
= ctx
->current_block
;
2507 int after_else_idx
= ctx
->block_count
;
2509 /* Now that we have the subblocks emitted, fix up the branches */
2514 if (ctx
->instruction_count
== count_in
) {
2515 /* The else block is empty, so don't emit an exit jump */
2516 mir_remove_instruction(then_exit
);
2517 then_branch
->branch
.target_block
= after_else_idx
;
2519 then_branch
->branch
.target_block
= else_idx
;
2520 then_exit
->branch
.target_block
= after_else_idx
;
2523 /* Wire up the successors */
2525 ctx
->after_block
= create_empty_block(ctx
);
2527 pan_block_add_successor(&before_block
->base
, &then_block
->base
);
2528 pan_block_add_successor(&before_block
->base
, &else_block
->base
);
2530 pan_block_add_successor(&end_then_block
->base
, &ctx
->after_block
->base
);
2531 pan_block_add_successor(&end_else_block
->base
, &ctx
->after_block
->base
);
2535 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2537 /* Remember where we are */
2538 midgard_block
*start_block
= ctx
->current_block
;
2540 /* Allocate a loop number, growing the current inner loop depth */
2541 int loop_idx
= ++ctx
->current_loop_depth
;
2543 /* Get index from before the body so we can loop back later */
2544 int start_idx
= ctx
->block_count
;
2546 /* Emit the body itself */
2547 midgard_block
*loop_block
= emit_cf_list(ctx
, &nloop
->body
);
2549 /* Branch back to loop back */
2550 struct midgard_instruction br_back
= v_branch(false, false);
2551 br_back
.branch
.target_block
= start_idx
;
2552 emit_mir_instruction(ctx
, br_back
);
2554 /* Mark down that branch in the graph. */
2555 pan_block_add_successor(&start_block
->base
, &loop_block
->base
);
2556 pan_block_add_successor(&ctx
->current_block
->base
, &loop_block
->base
);
2558 /* Find the index of the block about to follow us (note: we don't add
2559 * one; blocks are 0-indexed so we get a fencepost problem) */
2560 int break_block_idx
= ctx
->block_count
;
2562 /* Fix up the break statements we emitted to point to the right place,
2563 * now that we can allocate a block number for them */
2564 ctx
->after_block
= create_empty_block(ctx
);
2566 mir_foreach_block_from(ctx
, start_block
, _block
) {
2567 mir_foreach_instr_in_block(((midgard_block
*) _block
), ins
) {
2568 if (ins
->type
!= TAG_ALU_4
) continue;
2569 if (!ins
->compact_branch
) continue;
2571 /* We found a branch -- check the type to see if we need to do anything */
2572 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2574 /* It's a break! Check if it's our break */
2575 if (ins
->branch
.target_break
!= loop_idx
) continue;
2577 /* Okay, cool, we're breaking out of this loop.
2578 * Rewrite from a break to a goto */
2580 ins
->branch
.target_type
= TARGET_GOTO
;
2581 ins
->branch
.target_block
= break_block_idx
;
2583 pan_block_add_successor(_block
, &ctx
->after_block
->base
);
2587 /* Now that we've finished emitting the loop, free up the depth again
2588 * so we play nice with recursion amid nested loops */
2589 --ctx
->current_loop_depth
;
2591 /* Dump loop stats */
2595 static midgard_block
*
2596 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2598 midgard_block
*start_block
= NULL
;
2600 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2601 switch (node
->type
) {
2602 case nir_cf_node_block
: {
2603 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2606 start_block
= block
;
2611 case nir_cf_node_if
:
2612 emit_if(ctx
, nir_cf_node_as_if(node
));
2615 case nir_cf_node_loop
:
2616 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2619 case nir_cf_node_function
:
2628 /* Due to lookahead, we need to report the first tag executed in the command
2629 * stream and in branch targets. An initial block might be empty, so iterate
2630 * until we find one that 'works' */
2633 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2635 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2637 mir_foreach_block_from(ctx
, initial_block
, _v
) {
2638 midgard_block
*v
= (midgard_block
*) _v
;
2639 if (v
->quadword_count
) {
2640 midgard_bundle
*initial_bundle
=
2641 util_dynarray_element(&v
->bundles
, midgard_bundle
, 0);
2643 return initial_bundle
->tag
;
2647 /* Default to a tag 1 which will break from the shader, in case we jump
2648 * to the exit block (i.e. `return` in a compute shader) */
2653 /* For each fragment writeout instruction, generate a writeout loop to
2654 * associate with it */
2657 mir_add_writeout_loops(compiler_context
*ctx
)
2659 for (unsigned rt
= 0; rt
< ARRAY_SIZE(ctx
->writeout_branch
); ++rt
) {
2660 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
2663 unsigned popped
= br
->branch
.target_block
;
2664 pan_block_add_successor(&(mir_get_block(ctx
, popped
- 1)->base
), &ctx
->current_block
->base
);
2665 br
->branch
.target_block
= emit_fragment_epilogue(ctx
, rt
);
2666 br
->branch
.target_type
= TARGET_GOTO
;
2668 /* If we have more RTs, we'll need to restore back after our
2669 * loop terminates */
2671 if ((rt
+ 1) < ARRAY_SIZE(ctx
->writeout_branch
) && ctx
->writeout_branch
[rt
+ 1]) {
2672 midgard_instruction uncond
= v_branch(false, false);
2673 uncond
.branch
.target_block
= popped
;
2674 uncond
.branch
.target_type
= TARGET_GOTO
;
2675 emit_mir_instruction(ctx
, uncond
);
2676 pan_block_add_successor(&ctx
->current_block
->base
, &(mir_get_block(ctx
, popped
)->base
));
2677 schedule_barrier(ctx
);
2679 /* We're last, so we can terminate here */
2680 br
->last_writeout
= true;
2686 midgard_compile_shader_nir(nir_shader
*nir
, panfrost_program
*program
, bool is_blend
, unsigned blend_rt
, unsigned gpu_id
, bool shaderdb
)
2688 struct util_dynarray
*compiled
= &program
->compiled
;
2690 midgard_debug
= debug_get_option_midgard_debug();
2692 /* TODO: Bound against what? */
2693 compiler_context
*ctx
= rzalloc(NULL
, compiler_context
);
2696 ctx
->stage
= nir
->info
.stage
;
2697 ctx
->is_blend
= is_blend
;
2698 ctx
->alpha_ref
= program
->alpha_ref
;
2699 ctx
->blend_rt
= MIDGARD_COLOR_RT0
+ blend_rt
;
2700 ctx
->blend_input
= ~0;
2701 ctx
->quirks
= midgard_get_quirks(gpu_id
);
2703 /* Start off with a safe cutoff, allowing usage of all 16 work
2704 * registers. Later, we'll promote uniform reads to uniform registers
2705 * if we determine it is beneficial to do so */
2706 ctx
->uniform_cutoff
= 8;
2708 /* Initialize at a global (not block) level hash tables */
2710 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2711 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2713 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2714 * (so we don't accidentally duplicate the epilogue since mesa/st has
2715 * messed with our I/O quite a bit already) */
2717 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2719 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2720 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2721 NIR_PASS_V(nir
, nir_lower_point_size
, 1.0, 1024.0);
2724 NIR_PASS_V(nir
, nir_lower_var_copies
);
2725 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2726 NIR_PASS_V(nir
, nir_split_var_copies
);
2727 NIR_PASS_V(nir
, nir_lower_var_copies
);
2728 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2729 NIR_PASS_V(nir
, nir_lower_var_copies
);
2730 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2732 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2733 NIR_PASS_V(nir
, nir_lower_ssbo
);
2734 NIR_PASS_V(nir
, midgard_nir_lower_zs_store
);
2736 /* Optimisation passes */
2738 optimise_nir(nir
, ctx
->quirks
, is_blend
);
2740 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2741 nir_print_shader(nir
, stdout
);
2744 /* Assign sysvals and counts, now that we're sure
2745 * (post-optimisation) */
2747 panfrost_nir_assign_sysvals(&ctx
->sysvals
, nir
);
2748 program
->sysval_count
= ctx
->sysvals
.sysval_count
;
2749 memcpy(program
->sysvals
, ctx
->sysvals
.sysvals
, sizeof(ctx
->sysvals
.sysvals
[0]) * ctx
->sysvals
.sysval_count
);
2751 nir_foreach_function(func
, nir
) {
2755 list_inithead(&ctx
->blocks
);
2756 ctx
->block_count
= 0;
2758 ctx
->already_emitted
= calloc(BITSET_WORDS(func
->impl
->ssa_alloc
), sizeof(BITSET_WORD
));
2760 emit_cf_list(ctx
, &func
->impl
->body
);
2761 free(ctx
->already_emitted
);
2762 break; /* TODO: Multi-function shaders */
2765 util_dynarray_init(compiled
, NULL
);
2767 /* Per-block lowering before opts */
2769 mir_foreach_block(ctx
, _block
) {
2770 midgard_block
*block
= (midgard_block
*) _block
;
2771 inline_alu_constants(ctx
, block
);
2772 embedded_to_inline_constant(ctx
, block
);
2774 /* MIR-level optimizations */
2776 bool progress
= false;
2780 progress
|= midgard_opt_dead_code_eliminate(ctx
);
2782 mir_foreach_block(ctx
, _block
) {
2783 midgard_block
*block
= (midgard_block
*) _block
;
2784 progress
|= midgard_opt_copy_prop(ctx
, block
);
2785 progress
|= midgard_opt_combine_projection(ctx
, block
);
2786 progress
|= midgard_opt_varying_projection(ctx
, block
);
2790 mir_foreach_block(ctx
, _block
) {
2791 midgard_block
*block
= (midgard_block
*) _block
;
2792 midgard_lower_derivatives(ctx
, block
);
2793 midgard_legalize_invert(ctx
, block
);
2794 midgard_cull_dead_branch(ctx
, block
);
2797 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
2798 mir_add_writeout_loops(ctx
);
2800 /* Analyze now that the code is known but before scheduling creates
2801 * pipeline registers which are harder to track */
2802 mir_analyze_helper_terminate(ctx
);
2803 mir_analyze_helper_requirements(ctx
);
2806 midgard_schedule_program(ctx
);
2809 /* Now that all the bundles are scheduled and we can calculate block
2810 * sizes, emit actual branch instructions rather than placeholders */
2812 int br_block_idx
= 0;
2814 mir_foreach_block(ctx
, _block
) {
2815 midgard_block
*block
= (midgard_block
*) _block
;
2816 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2817 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2818 midgard_instruction
*ins
= bundle
->instructions
[c
];
2820 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2822 /* Parse some basic branch info */
2823 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2824 bool is_conditional
= ins
->branch
.conditional
;
2825 bool is_inverted
= ins
->branch
.invert_conditional
;
2826 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2827 bool is_writeout
= ins
->writeout
;
2829 /* Determine the block we're jumping to */
2830 int target_number
= ins
->branch
.target_block
;
2832 /* Report the destination tag */
2833 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2835 /* Count up the number of quadwords we're
2836 * jumping over = number of quadwords until
2837 * (br_block_idx, target_number) */
2839 int quadword_offset
= 0;
2843 } else if (target_number
> br_block_idx
) {
2846 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2847 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2850 quadword_offset
+= blk
->quadword_count
;
2853 /* Jump backwards */
2855 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2856 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2859 quadword_offset
-= blk
->quadword_count
;
2863 /* Unconditional extended branches (far jumps)
2864 * have issues, so we always use a conditional
2865 * branch, setting the condition to always for
2866 * unconditional. For compact unconditional
2867 * branches, cond isn't used so it doesn't
2868 * matter what we pick. */
2870 midgard_condition cond
=
2871 !is_conditional
? midgard_condition_always
:
2872 is_inverted
? midgard_condition_false
:
2873 midgard_condition_true
;
2875 midgard_jmp_writeout_op op
=
2876 is_discard
? midgard_jmp_writeout_op_discard
:
2877 is_writeout
? midgard_jmp_writeout_op_writeout
:
2878 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2879 midgard_jmp_writeout_op_branch_cond
;
2882 midgard_branch_extended branch
=
2883 midgard_create_branch_extended(
2888 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2889 } else if (is_conditional
|| is_discard
) {
2890 midgard_branch_cond branch
= {
2892 .dest_tag
= dest_tag
,
2893 .offset
= quadword_offset
,
2897 assert(branch
.offset
== quadword_offset
);
2899 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2901 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2903 midgard_branch_uncond branch
= {
2905 .dest_tag
= dest_tag
,
2906 .offset
= quadword_offset
,
2910 assert(branch
.offset
== quadword_offset
);
2912 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2920 /* Emit flat binary from the instruction arrays. Iterate each block in
2921 * sequence. Save instruction boundaries such that lookahead tags can
2922 * be assigned easily */
2924 /* Cache _all_ bundles in source order for lookahead across failed branches */
2926 int bundle_count
= 0;
2927 mir_foreach_block(ctx
, _block
) {
2928 midgard_block
*block
= (midgard_block
*) _block
;
2929 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2931 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2933 mir_foreach_block(ctx
, _block
) {
2934 midgard_block
*block
= (midgard_block
*) _block
;
2935 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2936 source_order_bundles
[bundle_idx
++] = bundle
;
2940 int current_bundle
= 0;
2942 /* Midgard prefetches instruction types, so during emission we
2943 * need to lookahead. Unless this is the last instruction, in
2944 * which we return 1. */
2946 mir_foreach_block(ctx
, _block
) {
2947 midgard_block
*block
= (midgard_block
*) _block
;
2948 mir_foreach_bundle_in_block(block
, bundle
) {
2951 if (!bundle
->last_writeout
&& (current_bundle
+ 1 < bundle_count
))
2952 lookahead
= source_order_bundles
[current_bundle
+ 1]->tag
;
2954 emit_binary_bundle(ctx
, block
, bundle
, compiled
, lookahead
);
2958 /* TODO: Free deeper */
2959 //util_dynarray_fini(&block->instructions);
2962 free(source_order_bundles
);
2964 /* Report the very first tag executed */
2965 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2967 /* Deal with off-by-one related to the fencepost problem */
2968 program
->work_register_count
= ctx
->work_registers
+ 1;
2969 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2971 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2972 program
->tls_size
= ctx
->tls_size
;
2974 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2975 disassemble_midgard(stdout
, program
->compiled
.data
, program
->compiled
.size
, gpu_id
, ctx
->stage
);
2977 if (midgard_debug
& MIDGARD_DBG_SHADERDB
|| shaderdb
) {
2978 unsigned nr_bundles
= 0, nr_ins
= 0;
2980 /* Count instructions and bundles */
2982 mir_foreach_block(ctx
, _block
) {
2983 midgard_block
*block
= (midgard_block
*) _block
;
2984 nr_bundles
+= util_dynarray_num_elements(
2985 &block
->bundles
, midgard_bundle
);
2987 mir_foreach_bundle_in_block(block
, bun
)
2988 nr_ins
+= bun
->instruction_count
;
2991 /* Calculate thread count. There are certain cutoffs by
2992 * register count for thread count */
2994 unsigned nr_registers
= program
->work_register_count
;
2996 unsigned nr_threads
=
2997 (nr_registers
<= 4) ? 4 :
2998 (nr_registers
<= 8) ? 2 :
3003 fprintf(stderr
, "shader%d - %s shader: "
3004 "%u inst, %u bundles, %u quadwords, "
3005 "%u registers, %u threads, %u loops, "
3006 "%u:%u spills:fills\n",
3008 ctx
->is_blend
? "PAN_SHADER_BLEND" :
3009 gl_shader_stage_name(ctx
->stage
),
3010 nr_ins
, nr_bundles
, ctx
->quadword_count
,
3011 nr_registers
, nr_threads
,
3013 ctx
->spills
, ctx
->fills
);