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pan/mdg: Don't generate conversions for fp16 LUTs
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 i.dest_type = T; \
121 } else { \
122 i.dest = ssa; \
123 i.dest_type = T; \
124 } \
125 return i; \
126 }
127
128 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
129 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
130
131 M_LOAD(ld_attr_32, nir_type_uint32);
132 M_LOAD(ld_vary_32, nir_type_uint32);
133 M_LOAD(ld_ubo_int4, nir_type_uint32);
134 M_LOAD(ld_int4, nir_type_uint32);
135 M_STORE(st_int4, nir_type_uint32);
136 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
137 M_STORE(st_vary_32, nir_type_uint32);
138 M_LOAD(ld_cubemap_coords, nir_type_uint32);
139 M_LOAD(ld_compute_id, nir_type_uint32);
140
141 static midgard_instruction
142 v_branch(bool conditional, bool invert)
143 {
144 midgard_instruction ins = {
145 .type = TAG_ALU_4,
146 .unit = ALU_ENAB_BRANCH,
147 .compact_branch = true,
148 .branch = {
149 .conditional = conditional,
150 .invert_conditional = invert
151 },
152 .dest = ~0,
153 .src = { ~0, ~0, ~0, ~0 },
154 };
155
156 return ins;
157 }
158
159 static midgard_branch_extended
160 midgard_create_branch_extended( midgard_condition cond,
161 midgard_jmp_writeout_op op,
162 unsigned dest_tag,
163 signed quadword_offset)
164 {
165 /* The condition code is actually a LUT describing a function to
166 * combine multiple condition codes. However, we only support a single
167 * condition code at the moment, so we just duplicate over a bunch of
168 * times. */
169
170 uint16_t duplicated_cond =
171 (cond << 14) |
172 (cond << 12) |
173 (cond << 10) |
174 (cond << 8) |
175 (cond << 6) |
176 (cond << 4) |
177 (cond << 2) |
178 (cond << 0);
179
180 midgard_branch_extended branch = {
181 .op = op,
182 .dest_tag = dest_tag,
183 .offset = quadword_offset,
184 .cond = duplicated_cond
185 };
186
187 return branch;
188 }
189
190 static void
191 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
192 {
193 ins->has_constants = true;
194 memcpy(&ins->constants, constants, 16);
195 }
196
197 static int
198 glsl_type_size(const struct glsl_type *type, bool bindless)
199 {
200 return glsl_count_attribute_slots(type, false);
201 }
202
203 /* Lower fdot2 to a vector multiplication followed by channel addition */
204 static void
205 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
206 {
207 if (alu->op != nir_op_fdot2)
208 return;
209
210 b->cursor = nir_before_instr(&alu->instr);
211
212 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
213 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
214
215 nir_ssa_def *product = nir_fmul(b, src0, src1);
216
217 nir_ssa_def *sum = nir_fadd(b,
218 nir_channel(b, product, 0),
219 nir_channel(b, product, 1));
220
221 /* Replace the fdot2 with this sum */
222 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
223 }
224
225 static bool
226 midgard_nir_lower_fdot2(nir_shader *shader)
227 {
228 bool progress = false;
229
230 nir_foreach_function(function, shader) {
231 if (!function->impl) continue;
232
233 nir_builder _b;
234 nir_builder *b = &_b;
235 nir_builder_init(b, function->impl);
236
237 nir_foreach_block(block, function->impl) {
238 nir_foreach_instr_safe(instr, block) {
239 if (instr->type != nir_instr_type_alu) continue;
240
241 nir_alu_instr *alu = nir_instr_as_alu(instr);
242 midgard_nir_lower_fdot2_body(b, alu);
243
244 progress |= true;
245 }
246 }
247
248 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
249
250 }
251
252 return progress;
253 }
254
255 /* Midgard can't write depth and stencil separately. It has to happen in a
256 * single store operation containing both. Let's add a panfrost specific
257 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
258 * one.
259 */
260 static bool
261 midgard_nir_lower_zs_store(nir_shader *nir)
262 {
263 if (nir->info.stage != MESA_SHADER_FRAGMENT)
264 return false;
265
266 nir_variable *z_var = NULL, *s_var = NULL;
267
268 nir_foreach_variable(var, &nir->outputs) {
269 if (var->data.location == FRAG_RESULT_DEPTH)
270 z_var = var;
271 else if (var->data.location == FRAG_RESULT_STENCIL)
272 s_var = var;
273 }
274
275 if (!z_var && !s_var)
276 return false;
277
278 bool progress = false;
279
280 nir_foreach_function(function, nir) {
281 if (!function->impl) continue;
282
283 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
284
285 nir_foreach_block(block, function->impl) {
286 nir_foreach_instr_safe(instr, block) {
287 if (instr->type != nir_instr_type_intrinsic)
288 continue;
289
290 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
291 if (intr->intrinsic != nir_intrinsic_store_output)
292 continue;
293
294 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
295 assert(!z_store);
296 z_store = intr;
297 last_store = intr;
298 }
299
300 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
301 assert(!s_store);
302 s_store = intr;
303 last_store = intr;
304 }
305 }
306 }
307
308 if (!z_store && !s_store) continue;
309
310 nir_builder b;
311 nir_builder_init(&b, function->impl);
312
313 b.cursor = nir_before_instr(&last_store->instr);
314
315 nir_ssa_def *zs_store_src;
316
317 if (z_store && s_store) {
318 nir_ssa_def *srcs[2] = {
319 nir_ssa_for_src(&b, z_store->src[0], 1),
320 nir_ssa_for_src(&b, s_store->src[0], 1),
321 };
322
323 zs_store_src = nir_vec(&b, srcs, 2);
324 } else {
325 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
326 }
327
328 nir_intrinsic_instr *zs_store;
329
330 zs_store = nir_intrinsic_instr_create(b.shader,
331 nir_intrinsic_store_zs_output_pan);
332 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
333 zs_store->num_components = z_store && s_store ? 2 : 1;
334 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
335
336 /* Replace the Z and S store by a ZS store */
337 nir_builder_instr_insert(&b, &zs_store->instr);
338
339 if (z_store)
340 nir_instr_remove(&z_store->instr);
341
342 if (s_store)
343 nir_instr_remove(&s_store->instr);
344
345 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
346 progress = true;
347 }
348
349 return progress;
350 }
351
352 /* Flushes undefined values to zero */
353
354 static void
355 optimise_nir(nir_shader *nir, unsigned quirks)
356 {
357 bool progress;
358 unsigned lower_flrp =
359 (nir->options->lower_flrp16 ? 16 : 0) |
360 (nir->options->lower_flrp32 ? 32 : 0) |
361 (nir->options->lower_flrp64 ? 64 : 0);
362
363 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
364 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
365
366 nir_lower_tex_options lower_tex_options = {
367 .lower_txs_lod = true,
368 .lower_txp = ~0,
369 .lower_tex_without_implicit_lod =
370 (quirks & MIDGARD_EXPLICIT_LOD),
371
372 /* TODO: we have native gradient.. */
373 .lower_txd = true,
374 };
375
376 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
377
378 /* Must lower fdot2 after tex is lowered */
379 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
380
381 /* T720 is broken. */
382
383 if (quirks & MIDGARD_BROKEN_LOD)
384 NIR_PASS_V(nir, midgard_nir_lod_errata);
385
386 do {
387 progress = false;
388
389 NIR_PASS(progress, nir, nir_lower_var_copies);
390 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
391
392 NIR_PASS(progress, nir, nir_copy_prop);
393 NIR_PASS(progress, nir, nir_opt_remove_phis);
394 NIR_PASS(progress, nir, nir_opt_dce);
395 NIR_PASS(progress, nir, nir_opt_dead_cf);
396 NIR_PASS(progress, nir, nir_opt_cse);
397 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
398 NIR_PASS(progress, nir, nir_opt_algebraic);
399 NIR_PASS(progress, nir, nir_opt_constant_folding);
400
401 if (lower_flrp != 0) {
402 bool lower_flrp_progress = false;
403 NIR_PASS(lower_flrp_progress,
404 nir,
405 nir_lower_flrp,
406 lower_flrp,
407 false /* always_precise */,
408 nir->options->lower_ffma);
409 if (lower_flrp_progress) {
410 NIR_PASS(progress, nir,
411 nir_opt_constant_folding);
412 progress = true;
413 }
414
415 /* Nothing should rematerialize any flrps, so we only
416 * need to do this lowering once.
417 */
418 lower_flrp = 0;
419 }
420
421 NIR_PASS(progress, nir, nir_opt_undef);
422 NIR_PASS(progress, nir, nir_undef_to_zero);
423
424 NIR_PASS(progress, nir, nir_opt_loop_unroll,
425 nir_var_shader_in |
426 nir_var_shader_out |
427 nir_var_function_temp);
428
429 NIR_PASS(progress, nir, nir_opt_vectorize);
430 } while (progress);
431
432 /* Must be run at the end to prevent creation of fsin/fcos ops */
433 NIR_PASS(progress, nir, midgard_nir_scale_trig);
434
435 do {
436 progress = false;
437
438 NIR_PASS(progress, nir, nir_opt_dce);
439 NIR_PASS(progress, nir, nir_opt_algebraic);
440 NIR_PASS(progress, nir, nir_opt_constant_folding);
441 NIR_PASS(progress, nir, nir_copy_prop);
442 } while (progress);
443
444 NIR_PASS(progress, nir, nir_opt_algebraic_late);
445 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
446
447 /* We implement booleans as 32-bit 0/~0 */
448 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
449
450 /* Now that booleans are lowered, we can run out late opts */
451 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
452 NIR_PASS(progress, nir, midgard_nir_cancel_inot);
453
454 NIR_PASS(progress, nir, nir_copy_prop);
455 NIR_PASS(progress, nir, nir_opt_dce);
456
457 /* Take us out of SSA */
458 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
459 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
460
461 /* We are a vector architecture; write combine where possible */
462 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
463 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
464
465 NIR_PASS(progress, nir, nir_opt_dce);
466 }
467
468 /* Do not actually emit a load; instead, cache the constant for inlining */
469
470 static void
471 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
472 {
473 nir_ssa_def def = instr->def;
474
475 midgard_constants *consts = rzalloc(NULL, midgard_constants);
476
477 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
478
479 #define RAW_CONST_COPY(bits) \
480 nir_const_value_to_array(consts->u##bits, instr->value, \
481 instr->def.num_components, u##bits)
482
483 switch (instr->def.bit_size) {
484 case 64:
485 RAW_CONST_COPY(64);
486 break;
487 case 32:
488 RAW_CONST_COPY(32);
489 break;
490 case 16:
491 RAW_CONST_COPY(16);
492 break;
493 case 8:
494 RAW_CONST_COPY(8);
495 break;
496 default:
497 unreachable("Invalid bit_size for load_const instruction\n");
498 }
499
500 /* Shifted for SSA, +1 for off-by-one */
501 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
502 }
503
504 /* Normally constants are embedded implicitly, but for I/O and such we have to
505 * explicitly emit a move with the constant source */
506
507 static void
508 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
509 {
510 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
511
512 if (constant_value) {
513 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
514 attach_constants(ctx, &ins, constant_value, node + 1);
515 emit_mir_instruction(ctx, ins);
516 }
517 }
518
519 static bool
520 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
521 {
522 unsigned comp = src->swizzle[0];
523
524 for (unsigned c = 1; c < nr_components; ++c) {
525 if (src->swizzle[c] != comp)
526 return true;
527 }
528
529 return false;
530 }
531
532 #define ALU_CASE(nir, _op) \
533 case nir_op_##nir: \
534 op = midgard_alu_op_##_op; \
535 assert(src_bitsize == dst_bitsize); \
536 break;
537
538 #define ALU_CHECK_CMP(sext) \
539 assert(src_bitsize == 16 || src_bitsize == 32); \
540 assert(dst_bitsize == 16 || dst_bitsize == 32); \
541
542 #define ALU_CASE_BCAST(nir, _op, count) \
543 case nir_op_##nir: \
544 op = midgard_alu_op_##_op; \
545 broadcast_swizzle = count; \
546 ALU_CHECK_CMP(true); \
547 break;
548
549 #define ALU_CASE_CMP(nir, _op, sext) \
550 case nir_op_##nir: \
551 op = midgard_alu_op_##_op; \
552 ALU_CHECK_CMP(sext); \
553 break;
554
555 /* Analyze the sizes of the dest and inputs to determine reg mode. */
556
557 static midgard_reg_mode
558 reg_mode_for_nir(nir_alu_instr *instr)
559 {
560 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
561 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
562 unsigned max_bitsize = MAX2(src_bitsize, dst_bitsize);
563
564 /* We don't have fp16 LUTs, so we'll want to emit code like:
565 *
566 * vlut.fsinr hr0, hr0
567 *
568 * where both input and output are 16-bit but the operation is carried
569 * out in 32-bit
570 */
571
572 switch (instr->op) {
573 case nir_op_fsqrt:
574 case nir_op_frcp:
575 case nir_op_frsq:
576 case nir_op_fsin:
577 case nir_op_fcos:
578 case nir_op_fexp2:
579 case nir_op_flog2:
580 max_bitsize = MAX2(max_bitsize, 32);
581 default:
582 break;
583 }
584
585 switch (max_bitsize) {
586 case 8:
587 return midgard_reg_mode_8;
588 case 16:
589 return midgard_reg_mode_16;
590 case 32:
591 return midgard_reg_mode_32;
592 case 64:
593 return midgard_reg_mode_64;
594 default:
595 unreachable("Invalid bit size");
596 }
597 }
598
599 /* Compare mir_lower_invert */
600 static bool
601 nir_accepts_inot(nir_op op, unsigned src)
602 {
603 switch (op) {
604 case nir_op_ior:
605 case nir_op_iand: /* TODO: b2f16 */
606 case nir_op_ixor:
607 return true;
608 case nir_op_b32csel:
609 /* Only the condition */
610 return (src == 0);
611 default:
612 return false;
613 }
614 }
615
616 static bool
617 mir_accept_dest_mod(compiler_context *ctx, nir_dest **dest, nir_op op)
618 {
619 if (pan_has_dest_mod(dest, op)) {
620 assert((*dest)->is_ssa);
621 BITSET_SET(ctx->already_emitted, (*dest)->ssa.index);
622 return true;
623 }
624
625 return false;
626 }
627
628 static void
629 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool *not, bool is_int, unsigned bcast_count)
630 {
631 nir_alu_src src = instr->src[i];
632
633 if (!is_int) {
634 if (pan_has_source_mod(&src, nir_op_fneg))
635 *neg = !(*neg);
636
637 if (pan_has_source_mod(&src, nir_op_fabs))
638 *abs = true;
639 }
640
641 if (nir_accepts_inot(instr->op, i) && pan_has_source_mod(&src, nir_op_inot))
642 *not = true;
643
644 unsigned bits = nir_src_bit_size(src.src);
645
646 ins->src[to] = nir_src_index(NULL, &src.src);
647 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
648
649 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
650 ins->swizzle[to][c] = src.swizzle[
651 (!bcast_count || c < bcast_count) ? c :
652 (bcast_count - 1)];
653 }
654 }
655
656 /* Midgard features both fcsel and icsel, depending on whether you want int or
657 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
658 * we should emit an int or float csel depending on what modifiers could be
659 * placed. In the absense of modifiers, this is probably arbitrary. */
660
661 static bool
662 mir_is_bcsel_float(nir_alu_instr *instr)
663 {
664 nir_op intmods[] = {
665 nir_op_i2i8, nir_op_i2i16,
666 nir_op_i2i32, nir_op_i2i64
667 };
668
669 nir_op floatmods[] = {
670 nir_op_fabs, nir_op_fneg,
671 nir_op_f2f16, nir_op_f2f32,
672 nir_op_f2f64
673 };
674
675 nir_op floatdestmods[] = {
676 nir_op_fsat, nir_op_fsat_signed, nir_op_fclamp_pos,
677 nir_op_f2f16, nir_op_f2f32
678 };
679
680 signed score = 0;
681
682 for (unsigned i = 1; i < 3; ++i) {
683 nir_alu_src s = instr->src[i];
684 for (unsigned q = 0; q < ARRAY_SIZE(intmods); ++q) {
685 if (pan_has_source_mod(&s, intmods[q]))
686 score--;
687 }
688 }
689
690 for (unsigned i = 1; i < 3; ++i) {
691 nir_alu_src s = instr->src[i];
692 for (unsigned q = 0; q < ARRAY_SIZE(floatmods); ++q) {
693 if (pan_has_source_mod(&s, floatmods[q]))
694 score++;
695 }
696 }
697
698 for (unsigned q = 0; q < ARRAY_SIZE(floatdestmods); ++q) {
699 nir_dest *dest = &instr->dest.dest;
700 if (pan_has_dest_mod(&dest, floatdestmods[q]))
701 score++;
702 }
703
704 return (score > 0);
705 }
706
707 static void
708 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
709 {
710 nir_dest *dest = &instr->dest.dest;
711
712 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index))
713 return;
714
715 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
716 * is handled elsewhere */
717
718 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
719 midgard_emit_derivatives(ctx, instr);
720 return;
721 }
722
723 bool is_ssa = dest->is_ssa;
724
725 unsigned nr_components = nir_dest_num_components(*dest);
726 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
727 unsigned op = 0;
728
729 /* Number of components valid to check for the instruction (the rest
730 * will be forced to the last), or 0 to use as-is. Relevant as
731 * ball-type instructions have a channel count in NIR but are all vec4
732 * in Midgard */
733
734 unsigned broadcast_swizzle = 0;
735
736 /* What register mode should we operate in? */
737 midgard_reg_mode reg_mode =
738 reg_mode_for_nir(instr);
739
740 /* Should we swap arguments? */
741 bool flip_src12 = false;
742
743 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
744 unsigned dst_bitsize = nir_dest_bit_size(*dest);
745
746 switch (instr->op) {
747 ALU_CASE(fadd, fadd);
748 ALU_CASE(fmul, fmul);
749 ALU_CASE(fmin, fmin);
750 ALU_CASE(fmax, fmax);
751 ALU_CASE(imin, imin);
752 ALU_CASE(imax, imax);
753 ALU_CASE(umin, umin);
754 ALU_CASE(umax, umax);
755 ALU_CASE(ffloor, ffloor);
756 ALU_CASE(fround_even, froundeven);
757 ALU_CASE(ftrunc, ftrunc);
758 ALU_CASE(fceil, fceil);
759 ALU_CASE(fdot3, fdot3);
760 ALU_CASE(fdot4, fdot4);
761 ALU_CASE(iadd, iadd);
762 ALU_CASE(isub, isub);
763 ALU_CASE(imul, imul);
764
765 /* Zero shoved as second-arg */
766 ALU_CASE(iabs, iabsdiff);
767
768 ALU_CASE(mov, imov);
769
770 ALU_CASE_CMP(feq32, feq, false);
771 ALU_CASE_CMP(fne32, fne, false);
772 ALU_CASE_CMP(flt32, flt, false);
773 ALU_CASE_CMP(ieq32, ieq, true);
774 ALU_CASE_CMP(ine32, ine, true);
775 ALU_CASE_CMP(ilt32, ilt, true);
776 ALU_CASE_CMP(ult32, ult, false);
777
778 /* We don't have a native b2f32 instruction. Instead, like many
779 * GPUs, we exploit booleans as 0/~0 for false/true, and
780 * correspondingly AND
781 * by 1.0 to do the type conversion. For the moment, prime us
782 * to emit:
783 *
784 * iand [whatever], #0
785 *
786 * At the end of emit_alu (as MIR), we'll fix-up the constant
787 */
788
789 ALU_CASE_CMP(b2f32, iand, true);
790 ALU_CASE_CMP(b2f16, iand, true);
791 ALU_CASE_CMP(b2i32, iand, true);
792
793 /* Likewise, we don't have a dedicated f2b32 instruction, but
794 * we can do a "not equal to 0.0" test. */
795
796 ALU_CASE_CMP(f2b32, fne, false);
797 ALU_CASE_CMP(i2b32, ine, true);
798
799 ALU_CASE(frcp, frcp);
800 ALU_CASE(frsq, frsqrt);
801 ALU_CASE(fsqrt, fsqrt);
802 ALU_CASE(fexp2, fexp2);
803 ALU_CASE(flog2, flog2);
804
805 ALU_CASE(f2i64, f2i_rtz);
806 ALU_CASE(f2u64, f2u_rtz);
807 ALU_CASE(i2f64, i2f_rtz);
808 ALU_CASE(u2f64, u2f_rtz);
809
810 ALU_CASE(f2i32, f2i_rtz);
811 ALU_CASE(f2u32, f2u_rtz);
812 ALU_CASE(i2f32, i2f_rtz);
813 ALU_CASE(u2f32, u2f_rtz);
814
815 ALU_CASE(f2i16, f2i_rtz);
816 ALU_CASE(f2u16, f2u_rtz);
817 ALU_CASE(i2f16, i2f_rtz);
818 ALU_CASE(u2f16, u2f_rtz);
819
820 ALU_CASE(fsin, fsin);
821 ALU_CASE(fcos, fcos);
822
823 /* We'll get 0 in the second arg, so:
824 * ~a = ~(a | 0) = nor(a, 0) */
825 ALU_CASE(inot, inor);
826 ALU_CASE(iand, iand);
827 ALU_CASE(ior, ior);
828 ALU_CASE(ixor, ixor);
829 ALU_CASE(ishl, ishl);
830 ALU_CASE(ishr, iasr);
831 ALU_CASE(ushr, ilsr);
832
833 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
834 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
835 ALU_CASE_CMP(b32all_fequal4, fball_eq, true);
836
837 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
838 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
839 ALU_CASE_CMP(b32any_fnequal4, fbany_neq, true);
840
841 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
842 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
843 ALU_CASE_CMP(b32all_iequal4, iball_eq, true);
844
845 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
846 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
847 ALU_CASE_CMP(b32any_inequal4, ibany_neq, true);
848
849 /* Source mods will be shoved in later */
850 ALU_CASE(fabs, fmov);
851 ALU_CASE(fneg, fmov);
852 ALU_CASE(fsat, fmov);
853 ALU_CASE(fsat_signed, fmov);
854 ALU_CASE(fclamp_pos, fmov);
855
856 /* For size conversion, we use a move. Ideally though we would squash
857 * these ops together; maybe that has to happen after in NIR as part of
858 * propagation...? An earlier algebraic pass ensured we step down by
859 * only / exactly one size. If stepping down, we use a dest override to
860 * reduce the size; if stepping up, we use a larger-sized move with a
861 * half source and a sign/zero-extension modifier */
862
863 case nir_op_i2i8:
864 case nir_op_i2i16:
865 case nir_op_i2i32:
866 case nir_op_i2i64:
867 case nir_op_u2u8:
868 case nir_op_u2u16:
869 case nir_op_u2u32:
870 case nir_op_u2u64:
871 case nir_op_f2f16:
872 case nir_op_f2f32:
873 case nir_op_f2f64: {
874 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
875 instr->op == nir_op_f2f64)
876 op = midgard_alu_op_fmov;
877 else
878 op = midgard_alu_op_imov;
879
880 break;
881 }
882
883 /* For greater-or-equal, we lower to less-or-equal and flip the
884 * arguments */
885
886 case nir_op_fge:
887 case nir_op_fge32:
888 case nir_op_ige32:
889 case nir_op_uge32: {
890 op =
891 instr->op == nir_op_fge ? midgard_alu_op_fle :
892 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
893 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
894 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
895 0;
896
897 flip_src12 = true;
898 ALU_CHECK_CMP(false);
899 break;
900 }
901
902 case nir_op_b32csel: {
903 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
904 bool is_float = mir_is_bcsel_float(instr);
905 op = is_float ?
906 (mixed ? midgard_alu_op_fcsel_v : midgard_alu_op_fcsel) :
907 (mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel);
908
909 break;
910 }
911
912 default:
913 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
914 assert(0);
915 return;
916 }
917
918 /* Promote imov to fmov if it might help inline a constant */
919 if (op == midgard_alu_op_imov && nir_src_is_const(instr->src[0].src)
920 && nir_src_bit_size(instr->src[0].src) == 32
921 && nir_is_same_comp_swizzle(instr->src[0].swizzle,
922 nir_src_num_components(instr->src[0].src))) {
923 op = midgard_alu_op_fmov;
924 }
925
926 /* Midgard can perform certain modifiers on output of an ALU op */
927
928 unsigned outmod = 0;
929 bool is_int = midgard_is_integer_op(op);
930
931 if (midgard_is_integer_out_op(op)) {
932 outmod = midgard_outmod_int_wrap;
933 } else if (instr->op == nir_op_fsat) {
934 outmod = midgard_outmod_sat;
935 } else if (instr->op == nir_op_fsat_signed) {
936 outmod = midgard_outmod_sat_signed;
937 } else if (instr->op == nir_op_fclamp_pos) {
938 outmod = midgard_outmod_pos;
939 }
940
941 /* Fetch unit, quirks, etc information */
942 unsigned opcode_props = alu_opcode_props[op].props;
943 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
944
945 /* Look for floating point mods. We have the mods fsat, fsat_signed,
946 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
947 *
948 * fsat_signed(fpos(x)) = fsat(x)
949 * fsat_signed(fsat(x)) = fsat(x)
950 * fpos(fsat_signed(x)) = fsat(x)
951 * fpos(fsat(x)) = fsat(x)
952 * fsat(fsat_signed(x)) = fsat(x)
953 * fsat(fpos(x)) = fsat(x)
954 *
955 * So by cases any composition of output modifiers is equivalent to
956 * fsat alone.
957 */
958
959 if (!is_int && !(opcode_props & OP_TYPE_CONVERT)) {
960 bool fpos = mir_accept_dest_mod(ctx, &dest, nir_op_fclamp_pos);
961 bool fsat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat);
962 bool ssat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat_signed);
963 bool prior = (outmod != midgard_outmod_none);
964 int count = (int) prior + (int) fpos + (int) ssat + (int) fsat;
965
966 outmod = ((count > 1) || fsat) ? midgard_outmod_sat :
967 fpos ? midgard_outmod_pos :
968 ssat ? midgard_outmod_sat_signed :
969 outmod;
970 }
971
972 midgard_instruction ins = {
973 .type = TAG_ALU_4,
974 .dest = nir_dest_index(dest),
975 .dest_type = nir_op_infos[instr->op].output_type
976 | nir_dest_bit_size(*dest),
977 };
978
979 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
980 ins.src[i] = ~0;
981
982 if (quirk_flipped_r24) {
983 ins.src[0] = ~0;
984 mir_copy_src(&ins, instr, 0, 1, &ins.src_abs[1], &ins.src_neg[1], &ins.src_invert[1], is_int, broadcast_swizzle);
985 } else {
986 for (unsigned i = 0; i < nr_inputs; ++i) {
987 unsigned to = i;
988
989 if (instr->op == nir_op_b32csel) {
990 /* The condition is the first argument; move
991 * the other arguments up one to be a binary
992 * instruction for Midgard with the condition
993 * last */
994
995 if (i == 0)
996 to = 2;
997 else if (flip_src12)
998 to = 2 - i;
999 else
1000 to = i - 1;
1001 } else if (flip_src12) {
1002 to = 1 - to;
1003 }
1004
1005 mir_copy_src(&ins, instr, i, to, &ins.src_abs[to], &ins.src_neg[to], &ins.src_invert[to], is_int, broadcast_swizzle);
1006
1007 /* (!c) ? a : b = c ? b : a */
1008 if (instr->op == nir_op_b32csel && ins.src_invert[2]) {
1009 ins.src_invert[2] = false;
1010 flip_src12 ^= true;
1011 }
1012 }
1013 }
1014
1015 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
1016 /* Lowered to move */
1017 if (instr->op == nir_op_fneg)
1018 ins.src_neg[1] ^= true;
1019
1020 if (instr->op == nir_op_fabs)
1021 ins.src_abs[1] = true;
1022 }
1023
1024 ins.mask = mask_of(nr_components);
1025
1026 midgard_vector_alu alu = {
1027 .op = op,
1028 .reg_mode = reg_mode,
1029 .outmod = outmod,
1030 };
1031
1032 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1033 * components that don't exist. Note modifier => SSA => !reg => no
1034 * writemask, so we don't have to worry about writemasks here.*/
1035
1036 if (!is_ssa)
1037 ins.mask &= instr->dest.write_mask;
1038
1039 ins.alu = alu;
1040
1041 /* Late fixup for emulated instructions */
1042
1043 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1044 /* Presently, our second argument is an inline #0 constant.
1045 * Switch over to an embedded 1.0 constant (that can't fit
1046 * inline, since we're 32-bit, not 16-bit like the inline
1047 * constants) */
1048
1049 ins.has_inline_constant = false;
1050 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1051 ins.src_types[1] = nir_type_float32;
1052 ins.has_constants = true;
1053
1054 if (instr->op == nir_op_b2f32)
1055 ins.constants.f32[0] = 1.0f;
1056 else
1057 ins.constants.i32[0] = 1;
1058
1059 for (unsigned c = 0; c < 16; ++c)
1060 ins.swizzle[1][c] = 0;
1061 } else if (instr->op == nir_op_b2f16) {
1062 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1063 ins.src_types[1] = nir_type_float16;
1064 ins.has_constants = true;
1065 ins.constants.i16[0] = _mesa_float_to_half(1.0);
1066
1067 for (unsigned c = 0; c < 16; ++c)
1068 ins.swizzle[1][c] = 0;
1069 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1070 /* Lots of instructions need a 0 plonked in */
1071 ins.has_inline_constant = false;
1072 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1073 ins.src_types[1] = nir_type_uint32;
1074 ins.has_constants = true;
1075 ins.constants.u32[0] = 0;
1076
1077 for (unsigned c = 0; c < 16; ++c)
1078 ins.swizzle[1][c] = 0;
1079 }
1080
1081 /* Arrange for creation of iandnot/iornot */
1082 if (ins.src_invert[0] && !ins.src_invert[1]) {
1083 mir_flip(&ins);
1084 ins.src_invert[0] = false;
1085 ins.src_invert[1] = true;
1086 }
1087
1088 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1089 /* To avoid duplicating the lookup tables (probably), true LUT
1090 * instructions can only operate as if they were scalars. Lower
1091 * them here by changing the component. */
1092
1093 unsigned orig_mask = ins.mask;
1094
1095 unsigned swizzle_back[MIR_VEC_COMPONENTS];
1096 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
1097
1098 for (int i = 0; i < nr_components; ++i) {
1099 /* Mask the associated component, dropping the
1100 * instruction if needed */
1101
1102 ins.mask = 1 << i;
1103 ins.mask &= orig_mask;
1104
1105 if (!ins.mask)
1106 continue;
1107
1108 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1109 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1110
1111 emit_mir_instruction(ctx, ins);
1112 }
1113 } else {
1114 emit_mir_instruction(ctx, ins);
1115 }
1116 }
1117
1118 #undef ALU_CASE
1119
1120 static void
1121 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1122 {
1123 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1124 unsigned nir_mask = 0;
1125 unsigned dsize = 0;
1126
1127 if (is_read) {
1128 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1129 dsize = nir_dest_bit_size(intr->dest);
1130 } else {
1131 nir_mask = nir_intrinsic_write_mask(intr);
1132 dsize = 32;
1133 }
1134
1135 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1136 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1137 mir_set_bytemask(ins, bytemask);
1138
1139 if (dsize == 64)
1140 ins->load_64 = true;
1141 }
1142
1143 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1144 * optimized) versions of UBO #0 */
1145
1146 static midgard_instruction *
1147 emit_ubo_read(
1148 compiler_context *ctx,
1149 nir_instr *instr,
1150 unsigned dest,
1151 unsigned offset,
1152 nir_src *indirect_offset,
1153 unsigned indirect_shift,
1154 unsigned index)
1155 {
1156 /* TODO: half-floats */
1157
1158 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1159 ins.constants.u32[0] = offset;
1160
1161 if (instr->type == nir_instr_type_intrinsic)
1162 mir_set_intr_mask(instr, &ins, true);
1163
1164 if (indirect_offset) {
1165 ins.src[2] = nir_src_index(ctx, indirect_offset);
1166 ins.src_types[2] = nir_type_uint32;
1167 ins.load_store.arg_2 = (indirect_shift << 5);
1168 } else {
1169 ins.load_store.arg_2 = 0x1E;
1170 }
1171
1172 ins.load_store.arg_1 = index;
1173
1174 return emit_mir_instruction(ctx, ins);
1175 }
1176
1177 /* Globals are like UBOs if you squint. And shared memory is like globals if
1178 * you squint even harder */
1179
1180 static void
1181 emit_global(
1182 compiler_context *ctx,
1183 nir_instr *instr,
1184 bool is_read,
1185 unsigned srcdest,
1186 nir_src *offset,
1187 bool is_shared)
1188 {
1189 /* TODO: types */
1190
1191 midgard_instruction ins;
1192
1193 if (is_read)
1194 ins = m_ld_int4(srcdest, 0);
1195 else
1196 ins = m_st_int4(srcdest, 0);
1197
1198 mir_set_offset(ctx, &ins, offset, is_shared);
1199 mir_set_intr_mask(instr, &ins, is_read);
1200
1201 emit_mir_instruction(ctx, ins);
1202 }
1203
1204 static void
1205 emit_varying_read(
1206 compiler_context *ctx,
1207 unsigned dest, unsigned offset,
1208 unsigned nr_comp, unsigned component,
1209 nir_src *indirect_offset, nir_alu_type type, bool flat)
1210 {
1211 /* XXX: Half-floats? */
1212 /* TODO: swizzle, mask */
1213
1214 midgard_instruction ins = m_ld_vary_32(dest, offset);
1215 ins.mask = mask_of(nr_comp);
1216
1217 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1218 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1219
1220 midgard_varying_parameter p = {
1221 .is_varying = 1,
1222 .interpolation = midgard_interp_default,
1223 .flat = flat,
1224 };
1225
1226 unsigned u;
1227 memcpy(&u, &p, sizeof(p));
1228 ins.load_store.varying_parameters = u;
1229
1230 if (indirect_offset) {
1231 ins.src[2] = nir_src_index(ctx, indirect_offset);
1232 ins.src_types[2] = nir_type_uint32;
1233 } else
1234 ins.load_store.arg_2 = 0x1E;
1235
1236 ins.load_store.arg_1 = 0x9E;
1237
1238 /* Use the type appropriate load */
1239 switch (type) {
1240 case nir_type_uint:
1241 case nir_type_bool:
1242 ins.load_store.op = midgard_op_ld_vary_32u;
1243 break;
1244 case nir_type_int:
1245 ins.load_store.op = midgard_op_ld_vary_32i;
1246 break;
1247 case nir_type_float:
1248 ins.load_store.op = midgard_op_ld_vary_32;
1249 break;
1250 default:
1251 unreachable("Attempted to load unknown type");
1252 break;
1253 }
1254
1255 emit_mir_instruction(ctx, ins);
1256 }
1257
1258 static void
1259 emit_attr_read(
1260 compiler_context *ctx,
1261 unsigned dest, unsigned offset,
1262 unsigned nr_comp, nir_alu_type t)
1263 {
1264 midgard_instruction ins = m_ld_attr_32(dest, offset);
1265 ins.load_store.arg_1 = 0x1E;
1266 ins.load_store.arg_2 = 0x1E;
1267 ins.mask = mask_of(nr_comp);
1268
1269 /* Use the type appropriate load */
1270 switch (t) {
1271 case nir_type_uint:
1272 case nir_type_bool:
1273 ins.load_store.op = midgard_op_ld_attr_32u;
1274 break;
1275 case nir_type_int:
1276 ins.load_store.op = midgard_op_ld_attr_32i;
1277 break;
1278 case nir_type_float:
1279 ins.load_store.op = midgard_op_ld_attr_32;
1280 break;
1281 default:
1282 unreachable("Attempted to load unknown type");
1283 break;
1284 }
1285
1286 emit_mir_instruction(ctx, ins);
1287 }
1288
1289 static void
1290 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1291 unsigned nr_components, unsigned offset)
1292 {
1293 nir_dest nir_dest;
1294
1295 /* Figure out which uniform this is */
1296 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1297 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1298
1299 unsigned dest = nir_dest_index(&nir_dest);
1300
1301 /* Sysvals are prefix uniforms */
1302 unsigned uniform = ((uintptr_t) val) - 1;
1303
1304 /* Emit the read itself -- this is never indirect */
1305 midgard_instruction *ins =
1306 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1307
1308 ins->mask = mask_of(nr_components);
1309 }
1310
1311 static unsigned
1312 compute_builtin_arg(nir_op op)
1313 {
1314 switch (op) {
1315 case nir_intrinsic_load_work_group_id:
1316 return 0x14;
1317 case nir_intrinsic_load_local_invocation_id:
1318 return 0x10;
1319 default:
1320 unreachable("Invalid compute paramater loaded");
1321 }
1322 }
1323
1324 static void
1325 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1326 {
1327 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1328
1329 midgard_instruction *br = ctx->writeout_branch[rt];
1330
1331 assert(!br);
1332
1333 emit_explicit_constant(ctx, src, src);
1334
1335 struct midgard_instruction ins =
1336 v_branch(false, false);
1337
1338 ins.writeout = true;
1339
1340 /* Add dependencies */
1341 ins.src[0] = src;
1342 ins.src_types[0] = nir_type_uint32;
1343 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1344 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1345
1346 /* Emit the branch */
1347 br = emit_mir_instruction(ctx, ins);
1348 schedule_barrier(ctx);
1349 ctx->writeout_branch[rt] = br;
1350
1351 /* Push our current location = current block count - 1 = where we'll
1352 * jump to. Maybe a bit too clever for my own good */
1353
1354 br->branch.target_block = ctx->block_count - 1;
1355 }
1356
1357 static void
1358 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1359 {
1360 unsigned reg = nir_dest_index(&instr->dest);
1361 midgard_instruction ins = m_ld_compute_id(reg, 0);
1362 ins.mask = mask_of(3);
1363 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1364 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1365 emit_mir_instruction(ctx, ins);
1366 }
1367
1368 static unsigned
1369 vertex_builtin_arg(nir_op op)
1370 {
1371 switch (op) {
1372 case nir_intrinsic_load_vertex_id:
1373 return PAN_VERTEX_ID;
1374 case nir_intrinsic_load_instance_id:
1375 return PAN_INSTANCE_ID;
1376 default:
1377 unreachable("Invalid vertex builtin");
1378 }
1379 }
1380
1381 static void
1382 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1383 {
1384 unsigned reg = nir_dest_index(&instr->dest);
1385 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1386 }
1387
1388 static void
1389 emit_control_barrier(compiler_context *ctx)
1390 {
1391 midgard_instruction ins = {
1392 .type = TAG_TEXTURE_4,
1393 .src = { ~0, ~0, ~0, ~0 },
1394 .texture = {
1395 .op = TEXTURE_OP_BARRIER,
1396
1397 /* TODO: optimize */
1398 .barrier_buffer = 1,
1399 .barrier_shared = 1
1400 }
1401 };
1402
1403 emit_mir_instruction(ctx, ins);
1404 }
1405
1406 static const nir_variable *
1407 search_var(struct exec_list *vars, unsigned driver_loc)
1408 {
1409 nir_foreach_variable(var, vars) {
1410 if (var->data.driver_location == driver_loc)
1411 return var;
1412 }
1413
1414 return NULL;
1415 }
1416
1417 static unsigned
1418 mir_get_branch_cond(nir_src *src, bool *invert)
1419 {
1420 /* Wrap it. No swizzle since it's a scalar */
1421
1422 nir_alu_src alu = {
1423 .src = *src
1424 };
1425
1426 *invert = pan_has_source_mod(&alu, nir_op_inot);
1427 return nir_src_index(NULL, &alu.src);
1428 }
1429
1430 static void
1431 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1432 {
1433 unsigned offset = 0, reg;
1434
1435 switch (instr->intrinsic) {
1436 case nir_intrinsic_discard_if:
1437 case nir_intrinsic_discard: {
1438 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1439 struct midgard_instruction discard = v_branch(conditional, false);
1440 discard.branch.target_type = TARGET_DISCARD;
1441
1442 if (conditional) {
1443 discard.src[0] = mir_get_branch_cond(&instr->src[0],
1444 &discard.branch.invert_conditional);
1445 discard.src_types[0] = nir_type_uint32;
1446 }
1447
1448 emit_mir_instruction(ctx, discard);
1449 schedule_barrier(ctx);
1450
1451 break;
1452 }
1453
1454 case nir_intrinsic_load_uniform:
1455 case nir_intrinsic_load_ubo:
1456 case nir_intrinsic_load_global:
1457 case nir_intrinsic_load_shared:
1458 case nir_intrinsic_load_input:
1459 case nir_intrinsic_load_interpolated_input: {
1460 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1461 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1462 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1463 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1464 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1465 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1466
1467 /* Get the base type of the intrinsic */
1468 /* TODO: Infer type? Does it matter? */
1469 nir_alu_type t =
1470 (is_ubo || is_global || is_shared) ? nir_type_uint :
1471 (is_interp) ? nir_type_float :
1472 nir_intrinsic_type(instr);
1473
1474 t = nir_alu_type_get_base_type(t);
1475
1476 if (!(is_ubo || is_global)) {
1477 offset = nir_intrinsic_base(instr);
1478 }
1479
1480 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1481
1482 nir_src *src_offset = nir_get_io_offset_src(instr);
1483
1484 bool direct = nir_src_is_const(*src_offset);
1485 nir_src *indirect_offset = direct ? NULL : src_offset;
1486
1487 if (direct)
1488 offset += nir_src_as_uint(*src_offset);
1489
1490 /* We may need to apply a fractional offset */
1491 int component = (is_flat || is_interp) ?
1492 nir_intrinsic_component(instr) : 0;
1493 reg = nir_dest_index(&instr->dest);
1494
1495 if (is_uniform && !ctx->is_blend) {
1496 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1497 } else if (is_ubo) {
1498 nir_src index = instr->src[0];
1499
1500 /* TODO: Is indirect block number possible? */
1501 assert(nir_src_is_const(index));
1502
1503 uint32_t uindex = nir_src_as_uint(index) + 1;
1504 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1505 } else if (is_global || is_shared) {
1506 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1507 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1508 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1509 } else if (ctx->is_blend) {
1510 /* For blend shaders, load the input color, which is
1511 * preloaded to r0 */
1512
1513 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1514 emit_mir_instruction(ctx, move);
1515 schedule_barrier(ctx);
1516 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1517 emit_attr_read(ctx, reg, offset, nr_comp, t);
1518 } else {
1519 DBG("Unknown load\n");
1520 assert(0);
1521 }
1522
1523 break;
1524 }
1525
1526 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1527 case nir_intrinsic_load_barycentric_pixel:
1528 case nir_intrinsic_load_barycentric_centroid:
1529 break;
1530
1531 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1532
1533 case nir_intrinsic_load_raw_output_pan:
1534 case nir_intrinsic_load_output_u8_as_fp16_pan:
1535 reg = nir_dest_index(&instr->dest);
1536 assert(ctx->is_blend);
1537
1538 /* T720 and below use different blend opcodes with slightly
1539 * different semantics than T760 and up */
1540
1541 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1542 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1543
1544 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1545 ld.load_store.op = old_blend ?
1546 midgard_op_ld_color_buffer_u8_as_fp16_old :
1547 midgard_op_ld_color_buffer_u8_as_fp16;
1548
1549 if (old_blend) {
1550 ld.load_store.address = 1;
1551 ld.load_store.arg_2 = 0x1E;
1552 }
1553
1554 for (unsigned c = 4; c < 16; ++c)
1555 ld.swizzle[0][c] = 0;
1556
1557 ld.dest_type = nir_type_float16;
1558 }
1559
1560 emit_mir_instruction(ctx, ld);
1561 break;
1562
1563 case nir_intrinsic_load_blend_const_color_rgba: {
1564 assert(ctx->is_blend);
1565 reg = nir_dest_index(&instr->dest);
1566
1567 /* Blend constants are embedded directly in the shader and
1568 * patched in, so we use some magic routing */
1569
1570 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1571 ins.has_constants = true;
1572 ins.has_blend_constant = true;
1573 emit_mir_instruction(ctx, ins);
1574 break;
1575 }
1576
1577 case nir_intrinsic_store_zs_output_pan: {
1578 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1579 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1580 MIDGARD_ZS_RT);
1581
1582 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1583
1584 if (!nir_intrinsic_component(instr))
1585 br->writeout_depth = true;
1586 if (nir_intrinsic_component(instr) ||
1587 instr->num_components)
1588 br->writeout_stencil = true;
1589 assert(br->writeout_depth | br->writeout_stencil);
1590 break;
1591 }
1592
1593 case nir_intrinsic_store_output:
1594 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1595
1596 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1597
1598 reg = nir_src_index(ctx, &instr->src[0]);
1599
1600 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1601 const nir_variable *var;
1602 enum midgard_rt_id rt;
1603
1604 var = search_var(&ctx->nir->outputs,
1605 nir_intrinsic_base(instr));
1606 assert(var);
1607 if (var->data.location == FRAG_RESULT_COLOR)
1608 rt = MIDGARD_COLOR_RT0;
1609 else if (var->data.location >= FRAG_RESULT_DATA0)
1610 rt = MIDGARD_COLOR_RT0 + var->data.location -
1611 FRAG_RESULT_DATA0;
1612 else
1613 assert(0);
1614
1615 emit_fragment_store(ctx, reg, rt);
1616 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1617 /* We should have been vectorized, though we don't
1618 * currently check that st_vary is emitted only once
1619 * per slot (this is relevant, since there's not a mask
1620 * parameter available on the store [set to 0 by the
1621 * blob]). We do respect the component by adjusting the
1622 * swizzle. If this is a constant source, we'll need to
1623 * emit that explicitly. */
1624
1625 emit_explicit_constant(ctx, reg, reg);
1626
1627 unsigned dst_component = nir_intrinsic_component(instr);
1628 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1629
1630 midgard_instruction st = m_st_vary_32(reg, offset);
1631 st.load_store.arg_1 = 0x9E;
1632 st.load_store.arg_2 = 0x1E;
1633
1634 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1635 case nir_type_uint:
1636 case nir_type_bool:
1637 st.load_store.op = midgard_op_st_vary_32u;
1638 break;
1639 case nir_type_int:
1640 st.load_store.op = midgard_op_st_vary_32i;
1641 break;
1642 case nir_type_float:
1643 st.load_store.op = midgard_op_st_vary_32;
1644 break;
1645 default:
1646 unreachable("Attempted to store unknown type");
1647 break;
1648 }
1649
1650 /* nir_intrinsic_component(store_intr) encodes the
1651 * destination component start. Source component offset
1652 * adjustment is taken care of in
1653 * install_registers_instr(), when offset_swizzle() is
1654 * called.
1655 */
1656 unsigned src_component = COMPONENT_X;
1657
1658 assert(nr_comp > 0);
1659 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1660 st.swizzle[0][i] = src_component;
1661 if (i >= dst_component && i < dst_component + nr_comp - 1)
1662 src_component++;
1663 }
1664
1665 emit_mir_instruction(ctx, st);
1666 } else {
1667 DBG("Unknown store\n");
1668 assert(0);
1669 }
1670
1671 break;
1672
1673 /* Special case of store_output for lowered blend shaders */
1674 case nir_intrinsic_store_raw_output_pan:
1675 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1676 reg = nir_src_index(ctx, &instr->src[0]);
1677
1678 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1679 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1680 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1681 * of:
1682 *
1683 * imov r0.xyzw, r0.xxxx
1684 */
1685
1686 unsigned expanded = make_compiler_temp(ctx);
1687
1688 midgard_instruction splatter = v_mov(reg, expanded);
1689
1690 for (unsigned c = 0; c < 16; ++c)
1691 splatter.swizzle[1][c] = 0;
1692
1693 emit_mir_instruction(ctx, splatter);
1694 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1695 } else
1696 emit_fragment_store(ctx, reg, ctx->blend_rt);
1697
1698 break;
1699
1700 case nir_intrinsic_store_global:
1701 case nir_intrinsic_store_shared:
1702 reg = nir_src_index(ctx, &instr->src[0]);
1703 emit_explicit_constant(ctx, reg, reg);
1704
1705 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1706 break;
1707
1708 case nir_intrinsic_load_ssbo_address:
1709 emit_sysval_read(ctx, &instr->instr, 1, 0);
1710 break;
1711
1712 case nir_intrinsic_get_buffer_size:
1713 emit_sysval_read(ctx, &instr->instr, 1, 8);
1714 break;
1715
1716 case nir_intrinsic_load_viewport_scale:
1717 case nir_intrinsic_load_viewport_offset:
1718 case nir_intrinsic_load_num_work_groups:
1719 case nir_intrinsic_load_sampler_lod_parameters_pan:
1720 emit_sysval_read(ctx, &instr->instr, 3, 0);
1721 break;
1722
1723 case nir_intrinsic_load_work_group_id:
1724 case nir_intrinsic_load_local_invocation_id:
1725 emit_compute_builtin(ctx, instr);
1726 break;
1727
1728 case nir_intrinsic_load_vertex_id:
1729 case nir_intrinsic_load_instance_id:
1730 emit_vertex_builtin(ctx, instr);
1731 break;
1732
1733 case nir_intrinsic_memory_barrier_buffer:
1734 case nir_intrinsic_memory_barrier_shared:
1735 break;
1736
1737 case nir_intrinsic_control_barrier:
1738 schedule_barrier(ctx);
1739 emit_control_barrier(ctx);
1740 schedule_barrier(ctx);
1741 break;
1742
1743 default:
1744 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1745 assert(0);
1746 break;
1747 }
1748 }
1749
1750 static unsigned
1751 midgard_tex_format(enum glsl_sampler_dim dim)
1752 {
1753 switch (dim) {
1754 case GLSL_SAMPLER_DIM_1D:
1755 case GLSL_SAMPLER_DIM_BUF:
1756 return MALI_TEX_1D;
1757
1758 case GLSL_SAMPLER_DIM_2D:
1759 case GLSL_SAMPLER_DIM_EXTERNAL:
1760 case GLSL_SAMPLER_DIM_RECT:
1761 return MALI_TEX_2D;
1762
1763 case GLSL_SAMPLER_DIM_3D:
1764 return MALI_TEX_3D;
1765
1766 case GLSL_SAMPLER_DIM_CUBE:
1767 return MALI_TEX_CUBE;
1768
1769 default:
1770 DBG("Unknown sampler dim type\n");
1771 assert(0);
1772 return 0;
1773 }
1774 }
1775
1776 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1777 * was successful */
1778
1779 static bool
1780 pan_attach_constant_bias(
1781 compiler_context *ctx,
1782 nir_src lod,
1783 midgard_texture_word *word)
1784 {
1785 /* To attach as constant, it has to *be* constant */
1786
1787 if (!nir_src_is_const(lod))
1788 return false;
1789
1790 float f = nir_src_as_float(lod);
1791
1792 /* Break into fixed-point */
1793 signed lod_int = f;
1794 float lod_frac = f - lod_int;
1795
1796 /* Carry over negative fractions */
1797 if (lod_frac < 0.0) {
1798 lod_int--;
1799 lod_frac += 1.0;
1800 }
1801
1802 /* Encode */
1803 word->bias = float_to_ubyte(lod_frac);
1804 word->bias_int = lod_int;
1805
1806 return true;
1807 }
1808
1809 static void
1810 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1811 unsigned midgard_texop)
1812 {
1813 /* TODO */
1814 //assert (!instr->sampler);
1815
1816 int texture_index = instr->texture_index;
1817 int sampler_index = texture_index;
1818
1819 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1820 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1821
1822 midgard_instruction ins = {
1823 .type = TAG_TEXTURE_4,
1824 .mask = 0xF,
1825 .dest = nir_dest_index(&instr->dest),
1826 .src = { ~0, ~0, ~0, ~0 },
1827 .dest_type = dest_type,
1828 .swizzle = SWIZZLE_IDENTITY_4,
1829 .texture = {
1830 .op = midgard_texop,
1831 .format = midgard_tex_format(instr->sampler_dim),
1832 .texture_handle = texture_index,
1833 .sampler_handle = sampler_index,
1834 .shadow = instr->is_shadow,
1835 }
1836 };
1837
1838 if (instr->is_shadow && !instr->is_new_style_shadow)
1839 for (int i = 0; i < 4; ++i)
1840 ins.swizzle[0][i] = COMPONENT_X;
1841
1842 /* We may need a temporary for the coordinate */
1843
1844 bool needs_temp_coord =
1845 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1846 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1847 (instr->is_shadow);
1848
1849 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1850
1851 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1852 int index = nir_src_index(ctx, &instr->src[i].src);
1853 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1854 unsigned sz = nir_src_bit_size(instr->src[i].src);
1855 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1856
1857 switch (instr->src[i].src_type) {
1858 case nir_tex_src_coord: {
1859 emit_explicit_constant(ctx, index, index);
1860
1861 unsigned coord_mask = mask_of(instr->coord_components);
1862
1863 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1864
1865 if (flip_zw)
1866 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1867
1868 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1869 /* texelFetch is undefined on samplerCube */
1870 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1871
1872 /* For cubemaps, we use a special ld/st op to
1873 * select the face and copy the xy into the
1874 * texture register */
1875
1876 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1877 ld.src[1] = index;
1878 ld.src_types[1] = T;
1879 ld.mask = 0x3; /* xy */
1880 ld.load_store.arg_1 = 0x20;
1881 ld.swizzle[1][3] = COMPONENT_X;
1882 emit_mir_instruction(ctx, ld);
1883
1884 /* xyzw -> xyxx */
1885 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1886 ins.swizzle[1][3] = COMPONENT_X;
1887 } else if (needs_temp_coord) {
1888 /* mov coord_temp, coords */
1889 midgard_instruction mov = v_mov(index, coords);
1890 mov.mask = coord_mask;
1891
1892 if (flip_zw)
1893 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1894
1895 emit_mir_instruction(ctx, mov);
1896 } else {
1897 coords = index;
1898 }
1899
1900 ins.src[1] = coords;
1901 ins.src_types[1] = T;
1902
1903 /* Texelfetch coordinates uses all four elements
1904 * (xyz/index) regardless of texture dimensionality,
1905 * which means it's necessary to zero the unused
1906 * components to keep everything happy */
1907
1908 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1909 /* mov index.zw, #0, or generalized */
1910 midgard_instruction mov =
1911 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1912 mov.has_constants = true;
1913 mov.mask = coord_mask ^ 0xF;
1914 emit_mir_instruction(ctx, mov);
1915 }
1916
1917 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1918 /* Array component in w but NIR wants it in z,
1919 * but if we have a temp coord we already fixed
1920 * that up */
1921
1922 if (nr_components == 3) {
1923 ins.swizzle[1][2] = COMPONENT_Z;
1924 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1925 } else if (nr_components == 2) {
1926 ins.swizzle[1][2] =
1927 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1928 ins.swizzle[1][3] = COMPONENT_X;
1929 } else
1930 unreachable("Invalid texture 2D components");
1931 }
1932
1933 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1934 /* We zeroed */
1935 ins.swizzle[1][2] = COMPONENT_Z;
1936 ins.swizzle[1][3] = COMPONENT_W;
1937 }
1938
1939 break;
1940 }
1941
1942 case nir_tex_src_bias:
1943 case nir_tex_src_lod: {
1944 /* Try as a constant if we can */
1945
1946 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1947 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1948 break;
1949
1950 ins.texture.lod_register = true;
1951 ins.src[2] = index;
1952 ins.src_types[2] = T;
1953
1954 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1955 ins.swizzle[2][c] = COMPONENT_X;
1956
1957 emit_explicit_constant(ctx, index, index);
1958
1959 break;
1960 };
1961
1962 case nir_tex_src_offset: {
1963 ins.texture.offset_register = true;
1964 ins.src[3] = index;
1965 ins.src_types[3] = T;
1966
1967 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1968 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
1969
1970 emit_explicit_constant(ctx, index, index);
1971 break;
1972 };
1973
1974 case nir_tex_src_comparator: {
1975 unsigned comp = COMPONENT_Z;
1976
1977 /* mov coord_temp.foo, coords */
1978 midgard_instruction mov = v_mov(index, coords);
1979 mov.mask = 1 << comp;
1980
1981 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
1982 mov.swizzle[1][i] = COMPONENT_X;
1983
1984 emit_mir_instruction(ctx, mov);
1985 break;
1986 }
1987
1988 default: {
1989 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
1990 assert(0);
1991 }
1992 }
1993 }
1994
1995 emit_mir_instruction(ctx, ins);
1996 }
1997
1998 static void
1999 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
2000 {
2001 switch (instr->op) {
2002 case nir_texop_tex:
2003 case nir_texop_txb:
2004 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
2005 break;
2006 case nir_texop_txl:
2007 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
2008 break;
2009 case nir_texop_txf:
2010 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
2011 break;
2012 case nir_texop_txs:
2013 emit_sysval_read(ctx, &instr->instr, 4, 0);
2014 break;
2015 default: {
2016 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
2017 assert(0);
2018 }
2019 }
2020 }
2021
2022 static void
2023 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
2024 {
2025 switch (instr->type) {
2026 case nir_jump_break: {
2027 /* Emit a branch out of the loop */
2028 struct midgard_instruction br = v_branch(false, false);
2029 br.branch.target_type = TARGET_BREAK;
2030 br.branch.target_break = ctx->current_loop_depth;
2031 emit_mir_instruction(ctx, br);
2032 break;
2033 }
2034
2035 default:
2036 DBG("Unknown jump type %d\n", instr->type);
2037 break;
2038 }
2039 }
2040
2041 static void
2042 emit_instr(compiler_context *ctx, struct nir_instr *instr)
2043 {
2044 switch (instr->type) {
2045 case nir_instr_type_load_const:
2046 emit_load_const(ctx, nir_instr_as_load_const(instr));
2047 break;
2048
2049 case nir_instr_type_intrinsic:
2050 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2051 break;
2052
2053 case nir_instr_type_alu:
2054 emit_alu(ctx, nir_instr_as_alu(instr));
2055 break;
2056
2057 case nir_instr_type_tex:
2058 emit_tex(ctx, nir_instr_as_tex(instr));
2059 break;
2060
2061 case nir_instr_type_jump:
2062 emit_jump(ctx, nir_instr_as_jump(instr));
2063 break;
2064
2065 case nir_instr_type_ssa_undef:
2066 /* Spurious */
2067 break;
2068
2069 default:
2070 DBG("Unhandled instruction type\n");
2071 break;
2072 }
2073 }
2074
2075
2076 /* ALU instructions can inline or embed constants, which decreases register
2077 * pressure and saves space. */
2078
2079 #define CONDITIONAL_ATTACH(idx) { \
2080 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2081 \
2082 if (entry) { \
2083 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2084 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2085 } \
2086 }
2087
2088 static void
2089 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2090 {
2091 mir_foreach_instr_in_block(block, alu) {
2092 /* Other instructions cannot inline constants */
2093 if (alu->type != TAG_ALU_4) continue;
2094 if (alu->compact_branch) continue;
2095
2096 /* If there is already a constant here, we can do nothing */
2097 if (alu->has_constants) continue;
2098
2099 CONDITIONAL_ATTACH(0);
2100
2101 if (!alu->has_constants) {
2102 CONDITIONAL_ATTACH(1)
2103 } else if (!alu->inline_constant) {
2104 /* Corner case: _two_ vec4 constants, for instance with a
2105 * csel. For this case, we can only use a constant
2106 * register for one, we'll have to emit a move for the
2107 * other. */
2108
2109 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2110 unsigned scratch = make_compiler_temp(ctx);
2111
2112 if (entry) {
2113 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2114 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2115
2116 /* Set the source */
2117 alu->src[1] = scratch;
2118
2119 /* Inject us -before- the last instruction which set r31 */
2120 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2121 }
2122 }
2123 }
2124 }
2125
2126 /* Midgard supports two types of constants, embedded constants (128-bit) and
2127 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2128 * constants can be demoted to inline constants, for space savings and
2129 * sometimes a performance boost */
2130
2131 static void
2132 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2133 {
2134 mir_foreach_instr_in_block(block, ins) {
2135 if (!ins->has_constants) continue;
2136 if (ins->has_inline_constant) continue;
2137
2138 /* Blend constants must not be inlined by definition */
2139 if (ins->has_blend_constant) continue;
2140
2141 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2142 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2143 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2144
2145 if (!(is_16 || is_32))
2146 continue;
2147
2148 /* src1 cannot be an inline constant due to encoding
2149 * restrictions. So, if possible we try to flip the arguments
2150 * in that case */
2151
2152 int op = ins->alu.op;
2153
2154 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2155 alu_opcode_props[op].props & OP_COMMUTES) {
2156 mir_flip(ins);
2157 }
2158
2159 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2160 /* Component is from the swizzle. Take a nonzero component */
2161 assert(ins->mask);
2162 unsigned first_comp = ffs(ins->mask) - 1;
2163 unsigned component = ins->swizzle[1][first_comp];
2164
2165 /* Scale constant appropriately, if we can legally */
2166 uint16_t scaled_constant = 0;
2167
2168 if (is_16) {
2169 scaled_constant = ins->constants.u16[component];
2170 } else if (midgard_is_integer_op(op)) {
2171 scaled_constant = ins->constants.u32[component];
2172
2173 /* Constant overflow after resize */
2174 if (scaled_constant != ins->constants.u32[component])
2175 continue;
2176 } else {
2177 float original = ins->constants.f32[component];
2178 scaled_constant = _mesa_float_to_half(original);
2179
2180 /* Check for loss of precision. If this is
2181 * mediump, we don't care, but for a highp
2182 * shader, we need to pay attention. NIR
2183 * doesn't yet tell us which mode we're in!
2184 * Practically this prevents most constants
2185 * from being inlined, sadly. */
2186
2187 float fp32 = _mesa_half_to_float(scaled_constant);
2188
2189 if (fp32 != original)
2190 continue;
2191 }
2192
2193 /* Should've been const folded */
2194 if (ins->src_abs[1] || ins->src_neg[1])
2195 continue;
2196
2197 /* Make sure that the constant is not itself a vector
2198 * by checking if all accessed values are the same. */
2199
2200 const midgard_constants *cons = &ins->constants;
2201 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2202
2203 bool is_vector = false;
2204 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2205
2206 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2207 /* We only care if this component is actually used */
2208 if (!(mask & (1 << c)))
2209 continue;
2210
2211 uint32_t test = is_16 ?
2212 cons->u16[ins->swizzle[1][c]] :
2213 cons->u32[ins->swizzle[1][c]];
2214
2215 if (test != value) {
2216 is_vector = true;
2217 break;
2218 }
2219 }
2220
2221 if (is_vector)
2222 continue;
2223
2224 /* Get rid of the embedded constant */
2225 ins->has_constants = false;
2226 ins->src[1] = ~0;
2227 ins->has_inline_constant = true;
2228 ins->inline_constant = scaled_constant;
2229 }
2230 }
2231 }
2232
2233 /* Dead code elimination for branches at the end of a block - only one branch
2234 * per block is legal semantically */
2235
2236 static void
2237 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2238 {
2239 bool branched = false;
2240
2241 mir_foreach_instr_in_block_safe(block, ins) {
2242 if (!midgard_is_branch_unit(ins->unit)) continue;
2243
2244 if (branched)
2245 mir_remove_instruction(ins);
2246
2247 branched = true;
2248 }
2249 }
2250
2251 static unsigned
2252 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2253 {
2254 /* Loop to ourselves */
2255 midgard_instruction *br = ctx->writeout_branch[rt];
2256 struct midgard_instruction ins = v_branch(false, false);
2257 ins.writeout = true;
2258 ins.writeout_depth = br->writeout_depth;
2259 ins.writeout_stencil = br->writeout_stencil;
2260 ins.branch.target_block = ctx->block_count - 1;
2261 ins.constants.u32[0] = br->constants.u32[0];
2262 emit_mir_instruction(ctx, ins);
2263
2264 ctx->current_block->epilogue = true;
2265 schedule_barrier(ctx);
2266 return ins.branch.target_block;
2267 }
2268
2269 static midgard_block *
2270 emit_block(compiler_context *ctx, nir_block *block)
2271 {
2272 midgard_block *this_block = ctx->after_block;
2273 ctx->after_block = NULL;
2274
2275 if (!this_block)
2276 this_block = create_empty_block(ctx);
2277
2278 list_addtail(&this_block->base.link, &ctx->blocks);
2279
2280 this_block->scheduled = false;
2281 ++ctx->block_count;
2282
2283 /* Set up current block */
2284 list_inithead(&this_block->base.instructions);
2285 ctx->current_block = this_block;
2286
2287 nir_foreach_instr(instr, block) {
2288 emit_instr(ctx, instr);
2289 ++ctx->instruction_count;
2290 }
2291
2292 return this_block;
2293 }
2294
2295 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2296
2297 static void
2298 emit_if(struct compiler_context *ctx, nir_if *nif)
2299 {
2300 midgard_block *before_block = ctx->current_block;
2301
2302 /* Speculatively emit the branch, but we can't fill it in until later */
2303 bool inv = false;
2304 EMIT(branch, true, true);
2305 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2306 then_branch->src[0] = mir_get_branch_cond(&nif->condition, &inv);
2307 then_branch->src_types[0] = nir_type_uint32;
2308 then_branch->branch.invert_conditional = !inv;
2309
2310 /* Emit the two subblocks. */
2311 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2312 midgard_block *end_then_block = ctx->current_block;
2313
2314 /* Emit a jump from the end of the then block to the end of the else */
2315 EMIT(branch, false, false);
2316 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2317
2318 /* Emit second block, and check if it's empty */
2319
2320 int else_idx = ctx->block_count;
2321 int count_in = ctx->instruction_count;
2322 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2323 midgard_block *end_else_block = ctx->current_block;
2324 int after_else_idx = ctx->block_count;
2325
2326 /* Now that we have the subblocks emitted, fix up the branches */
2327
2328 assert(then_block);
2329 assert(else_block);
2330
2331 if (ctx->instruction_count == count_in) {
2332 /* The else block is empty, so don't emit an exit jump */
2333 mir_remove_instruction(then_exit);
2334 then_branch->branch.target_block = after_else_idx;
2335 } else {
2336 then_branch->branch.target_block = else_idx;
2337 then_exit->branch.target_block = after_else_idx;
2338 }
2339
2340 /* Wire up the successors */
2341
2342 ctx->after_block = create_empty_block(ctx);
2343
2344 pan_block_add_successor(&before_block->base, &then_block->base);
2345 pan_block_add_successor(&before_block->base, &else_block->base);
2346
2347 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2348 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2349 }
2350
2351 static void
2352 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2353 {
2354 /* Remember where we are */
2355 midgard_block *start_block = ctx->current_block;
2356
2357 /* Allocate a loop number, growing the current inner loop depth */
2358 int loop_idx = ++ctx->current_loop_depth;
2359
2360 /* Get index from before the body so we can loop back later */
2361 int start_idx = ctx->block_count;
2362
2363 /* Emit the body itself */
2364 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2365
2366 /* Branch back to loop back */
2367 struct midgard_instruction br_back = v_branch(false, false);
2368 br_back.branch.target_block = start_idx;
2369 emit_mir_instruction(ctx, br_back);
2370
2371 /* Mark down that branch in the graph. */
2372 pan_block_add_successor(&start_block->base, &loop_block->base);
2373 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2374
2375 /* Find the index of the block about to follow us (note: we don't add
2376 * one; blocks are 0-indexed so we get a fencepost problem) */
2377 int break_block_idx = ctx->block_count;
2378
2379 /* Fix up the break statements we emitted to point to the right place,
2380 * now that we can allocate a block number for them */
2381 ctx->after_block = create_empty_block(ctx);
2382
2383 mir_foreach_block_from(ctx, start_block, _block) {
2384 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2385 if (ins->type != TAG_ALU_4) continue;
2386 if (!ins->compact_branch) continue;
2387
2388 /* We found a branch -- check the type to see if we need to do anything */
2389 if (ins->branch.target_type != TARGET_BREAK) continue;
2390
2391 /* It's a break! Check if it's our break */
2392 if (ins->branch.target_break != loop_idx) continue;
2393
2394 /* Okay, cool, we're breaking out of this loop.
2395 * Rewrite from a break to a goto */
2396
2397 ins->branch.target_type = TARGET_GOTO;
2398 ins->branch.target_block = break_block_idx;
2399
2400 pan_block_add_successor(_block, &ctx->after_block->base);
2401 }
2402 }
2403
2404 /* Now that we've finished emitting the loop, free up the depth again
2405 * so we play nice with recursion amid nested loops */
2406 --ctx->current_loop_depth;
2407
2408 /* Dump loop stats */
2409 ++ctx->loop_count;
2410 }
2411
2412 static midgard_block *
2413 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2414 {
2415 midgard_block *start_block = NULL;
2416
2417 foreach_list_typed(nir_cf_node, node, node, list) {
2418 switch (node->type) {
2419 case nir_cf_node_block: {
2420 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2421
2422 if (!start_block)
2423 start_block = block;
2424
2425 break;
2426 }
2427
2428 case nir_cf_node_if:
2429 emit_if(ctx, nir_cf_node_as_if(node));
2430 break;
2431
2432 case nir_cf_node_loop:
2433 emit_loop(ctx, nir_cf_node_as_loop(node));
2434 break;
2435
2436 case nir_cf_node_function:
2437 assert(0);
2438 break;
2439 }
2440 }
2441
2442 return start_block;
2443 }
2444
2445 /* Due to lookahead, we need to report the first tag executed in the command
2446 * stream and in branch targets. An initial block might be empty, so iterate
2447 * until we find one that 'works' */
2448
2449 static unsigned
2450 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2451 {
2452 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2453
2454 mir_foreach_block_from(ctx, initial_block, _v) {
2455 midgard_block *v = (midgard_block *) _v;
2456 if (v->quadword_count) {
2457 midgard_bundle *initial_bundle =
2458 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2459
2460 return initial_bundle->tag;
2461 }
2462 }
2463
2464 /* Default to a tag 1 which will break from the shader, in case we jump
2465 * to the exit block (i.e. `return` in a compute shader) */
2466
2467 return 1;
2468 }
2469
2470 /* For each fragment writeout instruction, generate a writeout loop to
2471 * associate with it */
2472
2473 static void
2474 mir_add_writeout_loops(compiler_context *ctx)
2475 {
2476 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2477 midgard_instruction *br = ctx->writeout_branch[rt];
2478 if (!br) continue;
2479
2480 unsigned popped = br->branch.target_block;
2481 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2482 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2483 br->branch.target_type = TARGET_GOTO;
2484
2485 /* If we have more RTs, we'll need to restore back after our
2486 * loop terminates */
2487
2488 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2489 midgard_instruction uncond = v_branch(false, false);
2490 uncond.branch.target_block = popped;
2491 uncond.branch.target_type = TARGET_GOTO;
2492 emit_mir_instruction(ctx, uncond);
2493 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2494 schedule_barrier(ctx);
2495 } else {
2496 /* We're last, so we can terminate here */
2497 br->last_writeout = true;
2498 }
2499 }
2500 }
2501
2502 int
2503 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2504 {
2505 struct util_dynarray *compiled = &program->compiled;
2506
2507 midgard_debug = debug_get_option_midgard_debug();
2508
2509 /* TODO: Bound against what? */
2510 compiler_context *ctx = rzalloc(NULL, compiler_context);
2511
2512 ctx->nir = nir;
2513 ctx->stage = nir->info.stage;
2514 ctx->is_blend = is_blend;
2515 ctx->alpha_ref = program->alpha_ref;
2516 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2517 ctx->quirks = midgard_get_quirks(gpu_id);
2518
2519 /* Start off with a safe cutoff, allowing usage of all 16 work
2520 * registers. Later, we'll promote uniform reads to uniform registers
2521 * if we determine it is beneficial to do so */
2522 ctx->uniform_cutoff = 8;
2523
2524 /* Initialize at a global (not block) level hash tables */
2525
2526 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2527 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2528
2529 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2530 * (so we don't accidentally duplicate the epilogue since mesa/st has
2531 * messed with our I/O quite a bit already) */
2532
2533 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2534
2535 if (ctx->stage == MESA_SHADER_VERTEX) {
2536 NIR_PASS_V(nir, nir_lower_viewport_transform);
2537 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2538 }
2539
2540 NIR_PASS_V(nir, nir_lower_var_copies);
2541 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2542 NIR_PASS_V(nir, nir_split_var_copies);
2543 NIR_PASS_V(nir, nir_lower_var_copies);
2544 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2545 NIR_PASS_V(nir, nir_lower_var_copies);
2546 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2547
2548 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2549 NIR_PASS_V(nir, nir_lower_ssbo);
2550 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2551
2552 /* Optimisation passes */
2553
2554 optimise_nir(nir, ctx->quirks);
2555
2556 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2557 nir_print_shader(nir, stdout);
2558 }
2559
2560 /* Assign sysvals and counts, now that we're sure
2561 * (post-optimisation) */
2562
2563 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2564 program->sysval_count = ctx->sysvals.sysval_count;
2565 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2566
2567 nir_foreach_function(func, nir) {
2568 if (!func->impl)
2569 continue;
2570
2571 list_inithead(&ctx->blocks);
2572 ctx->block_count = 0;
2573 ctx->func = func;
2574 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
2575
2576 emit_cf_list(ctx, &func->impl->body);
2577 free(ctx->already_emitted);
2578 break; /* TODO: Multi-function shaders */
2579 }
2580
2581 util_dynarray_init(compiled, NULL);
2582
2583 /* Per-block lowering before opts */
2584
2585 mir_foreach_block(ctx, _block) {
2586 midgard_block *block = (midgard_block *) _block;
2587 inline_alu_constants(ctx, block);
2588 embedded_to_inline_constant(ctx, block);
2589 }
2590 /* MIR-level optimizations */
2591
2592 bool progress = false;
2593
2594 do {
2595 progress = false;
2596 progress |= midgard_opt_dead_code_eliminate(ctx);
2597
2598 mir_foreach_block(ctx, _block) {
2599 midgard_block *block = (midgard_block *) _block;
2600 progress |= midgard_opt_copy_prop(ctx, block);
2601 progress |= midgard_opt_combine_projection(ctx, block);
2602 progress |= midgard_opt_varying_projection(ctx, block);
2603 }
2604 } while (progress);
2605
2606 mir_foreach_block(ctx, _block) {
2607 midgard_block *block = (midgard_block *) _block;
2608 midgard_lower_derivatives(ctx, block);
2609 midgard_cull_dead_branch(ctx, block);
2610 }
2611
2612 if (ctx->stage == MESA_SHADER_FRAGMENT)
2613 mir_add_writeout_loops(ctx);
2614
2615 /* Analyze now that the code is known but before scheduling creates
2616 * pipeline registers which are harder to track */
2617 mir_analyze_helper_terminate(ctx);
2618 mir_analyze_helper_requirements(ctx);
2619
2620 /* Schedule! */
2621 midgard_schedule_program(ctx);
2622 mir_ra(ctx);
2623
2624 /* Now that all the bundles are scheduled and we can calculate block
2625 * sizes, emit actual branch instructions rather than placeholders */
2626
2627 int br_block_idx = 0;
2628
2629 mir_foreach_block(ctx, _block) {
2630 midgard_block *block = (midgard_block *) _block;
2631 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2632 for (int c = 0; c < bundle->instruction_count; ++c) {
2633 midgard_instruction *ins = bundle->instructions[c];
2634
2635 if (!midgard_is_branch_unit(ins->unit)) continue;
2636
2637 /* Parse some basic branch info */
2638 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2639 bool is_conditional = ins->branch.conditional;
2640 bool is_inverted = ins->branch.invert_conditional;
2641 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2642 bool is_writeout = ins->writeout;
2643
2644 /* Determine the block we're jumping to */
2645 int target_number = ins->branch.target_block;
2646
2647 /* Report the destination tag */
2648 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2649
2650 /* Count up the number of quadwords we're
2651 * jumping over = number of quadwords until
2652 * (br_block_idx, target_number) */
2653
2654 int quadword_offset = 0;
2655
2656 if (is_discard) {
2657 /* Ignored */
2658 } else if (target_number > br_block_idx) {
2659 /* Jump forward */
2660
2661 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2662 midgard_block *blk = mir_get_block(ctx, idx);
2663 assert(blk);
2664
2665 quadword_offset += blk->quadword_count;
2666 }
2667 } else {
2668 /* Jump backwards */
2669
2670 for (int idx = br_block_idx; idx >= target_number; --idx) {
2671 midgard_block *blk = mir_get_block(ctx, idx);
2672 assert(blk);
2673
2674 quadword_offset -= blk->quadword_count;
2675 }
2676 }
2677
2678 /* Unconditional extended branches (far jumps)
2679 * have issues, so we always use a conditional
2680 * branch, setting the condition to always for
2681 * unconditional. For compact unconditional
2682 * branches, cond isn't used so it doesn't
2683 * matter what we pick. */
2684
2685 midgard_condition cond =
2686 !is_conditional ? midgard_condition_always :
2687 is_inverted ? midgard_condition_false :
2688 midgard_condition_true;
2689
2690 midgard_jmp_writeout_op op =
2691 is_discard ? midgard_jmp_writeout_op_discard :
2692 is_writeout ? midgard_jmp_writeout_op_writeout :
2693 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2694 midgard_jmp_writeout_op_branch_cond;
2695
2696 if (!is_compact) {
2697 midgard_branch_extended branch =
2698 midgard_create_branch_extended(
2699 cond, op,
2700 dest_tag,
2701 quadword_offset);
2702
2703 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2704 } else if (is_conditional || is_discard) {
2705 midgard_branch_cond branch = {
2706 .op = op,
2707 .dest_tag = dest_tag,
2708 .offset = quadword_offset,
2709 .cond = cond
2710 };
2711
2712 assert(branch.offset == quadword_offset);
2713
2714 memcpy(&ins->br_compact, &branch, sizeof(branch));
2715 } else {
2716 assert(op == midgard_jmp_writeout_op_branch_uncond);
2717
2718 midgard_branch_uncond branch = {
2719 .op = op,
2720 .dest_tag = dest_tag,
2721 .offset = quadword_offset,
2722 .unknown = 1
2723 };
2724
2725 assert(branch.offset == quadword_offset);
2726
2727 memcpy(&ins->br_compact, &branch, sizeof(branch));
2728 }
2729 }
2730 }
2731
2732 ++br_block_idx;
2733 }
2734
2735 /* Emit flat binary from the instruction arrays. Iterate each block in
2736 * sequence. Save instruction boundaries such that lookahead tags can
2737 * be assigned easily */
2738
2739 /* Cache _all_ bundles in source order for lookahead across failed branches */
2740
2741 int bundle_count = 0;
2742 mir_foreach_block(ctx, _block) {
2743 midgard_block *block = (midgard_block *) _block;
2744 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2745 }
2746 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2747 int bundle_idx = 0;
2748 mir_foreach_block(ctx, _block) {
2749 midgard_block *block = (midgard_block *) _block;
2750 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2751 source_order_bundles[bundle_idx++] = bundle;
2752 }
2753 }
2754
2755 int current_bundle = 0;
2756
2757 /* Midgard prefetches instruction types, so during emission we
2758 * need to lookahead. Unless this is the last instruction, in
2759 * which we return 1. */
2760
2761 mir_foreach_block(ctx, _block) {
2762 midgard_block *block = (midgard_block *) _block;
2763 mir_foreach_bundle_in_block(block, bundle) {
2764 int lookahead = 1;
2765
2766 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2767 lookahead = source_order_bundles[current_bundle + 1]->tag;
2768
2769 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2770 ++current_bundle;
2771 }
2772
2773 /* TODO: Free deeper */
2774 //util_dynarray_fini(&block->instructions);
2775 }
2776
2777 free(source_order_bundles);
2778
2779 /* Report the very first tag executed */
2780 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2781
2782 /* Deal with off-by-one related to the fencepost problem */
2783 program->work_register_count = ctx->work_registers + 1;
2784 program->uniform_cutoff = ctx->uniform_cutoff;
2785
2786 program->blend_patch_offset = ctx->blend_constant_offset;
2787 program->tls_size = ctx->tls_size;
2788
2789 if (midgard_debug & MIDGARD_DBG_SHADERS)
2790 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2791
2792 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2793 unsigned nr_bundles = 0, nr_ins = 0;
2794
2795 /* Count instructions and bundles */
2796
2797 mir_foreach_block(ctx, _block) {
2798 midgard_block *block = (midgard_block *) _block;
2799 nr_bundles += util_dynarray_num_elements(
2800 &block->bundles, midgard_bundle);
2801
2802 mir_foreach_bundle_in_block(block, bun)
2803 nr_ins += bun->instruction_count;
2804 }
2805
2806 /* Calculate thread count. There are certain cutoffs by
2807 * register count for thread count */
2808
2809 unsigned nr_registers = program->work_register_count;
2810
2811 unsigned nr_threads =
2812 (nr_registers <= 4) ? 4 :
2813 (nr_registers <= 8) ? 2 :
2814 1;
2815
2816 /* Dump stats */
2817
2818 fprintf(stderr, "shader%d - %s shader: "
2819 "%u inst, %u bundles, %u quadwords, "
2820 "%u registers, %u threads, %u loops, "
2821 "%u:%u spills:fills\n",
2822 SHADER_DB_COUNT++,
2823 gl_shader_stage_name(ctx->stage),
2824 nr_ins, nr_bundles, ctx->quadword_count,
2825 nr_registers, nr_threads,
2826 ctx->loop_count,
2827 ctx->spills, ctx->fills);
2828 }
2829
2830 ralloc_free(ctx);
2831
2832 return 0;
2833 }