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pan/mdg: Remove invert optimizations
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 } else { \
121 i.dest = ssa; \
122 i.dest_type = T; \
123 } \
124 return i; \
125 }
126
127 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
128 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
129
130 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
131 * the corresponding Midgard source */
132
133 static midgard_vector_alu_src
134 vector_alu_modifiers(bool abs, bool neg, bool is_int,
135 bool half, bool sext)
136 {
137 /* Figure out how many components there are so we can adjust.
138 * Specifically we want to broadcast the last channel so things like
139 * ball2/3 work.
140 */
141
142 midgard_vector_alu_src alu_src = {
143 .rep_low = 0,
144 .rep_high = 0,
145 .half = half
146 };
147
148 if (is_int) {
149 alu_src.mod = midgard_int_normal;
150
151 /* Sign/zero-extend if needed */
152
153 if (half) {
154 alu_src.mod = sext ?
155 midgard_int_sign_extend
156 : midgard_int_zero_extend;
157 }
158
159 /* These should have been lowered away */
160 assert(!(abs || neg));
161 } else {
162 alu_src.mod = (abs << 0) | (neg << 1);
163 }
164
165 return alu_src;
166 }
167
168 M_LOAD(ld_attr_32, nir_type_uint32);
169 M_LOAD(ld_vary_32, nir_type_uint32);
170 M_LOAD(ld_ubo_int4, nir_type_uint32);
171 M_LOAD(ld_int4, nir_type_uint32);
172 M_STORE(st_int4, nir_type_uint32);
173 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
174 M_STORE(st_vary_32, nir_type_uint32);
175 M_LOAD(ld_cubemap_coords, nir_type_uint32);
176 M_LOAD(ld_compute_id, nir_type_uint32);
177
178 static midgard_instruction
179 v_branch(bool conditional, bool invert)
180 {
181 midgard_instruction ins = {
182 .type = TAG_ALU_4,
183 .unit = ALU_ENAB_BRANCH,
184 .compact_branch = true,
185 .branch = {
186 .conditional = conditional,
187 .invert_conditional = invert
188 },
189 .dest = ~0,
190 .src = { ~0, ~0, ~0, ~0 },
191 };
192
193 return ins;
194 }
195
196 static midgard_branch_extended
197 midgard_create_branch_extended( midgard_condition cond,
198 midgard_jmp_writeout_op op,
199 unsigned dest_tag,
200 signed quadword_offset)
201 {
202 /* The condition code is actually a LUT describing a function to
203 * combine multiple condition codes. However, we only support a single
204 * condition code at the moment, so we just duplicate over a bunch of
205 * times. */
206
207 uint16_t duplicated_cond =
208 (cond << 14) |
209 (cond << 12) |
210 (cond << 10) |
211 (cond << 8) |
212 (cond << 6) |
213 (cond << 4) |
214 (cond << 2) |
215 (cond << 0);
216
217 midgard_branch_extended branch = {
218 .op = op,
219 .dest_tag = dest_tag,
220 .offset = quadword_offset,
221 .cond = duplicated_cond
222 };
223
224 return branch;
225 }
226
227 static void
228 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
229 {
230 ins->has_constants = true;
231 memcpy(&ins->constants, constants, 16);
232 }
233
234 static int
235 glsl_type_size(const struct glsl_type *type, bool bindless)
236 {
237 return glsl_count_attribute_slots(type, false);
238 }
239
240 /* Lower fdot2 to a vector multiplication followed by channel addition */
241 static void
242 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
243 {
244 if (alu->op != nir_op_fdot2)
245 return;
246
247 b->cursor = nir_before_instr(&alu->instr);
248
249 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
250 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
251
252 nir_ssa_def *product = nir_fmul(b, src0, src1);
253
254 nir_ssa_def *sum = nir_fadd(b,
255 nir_channel(b, product, 0),
256 nir_channel(b, product, 1));
257
258 /* Replace the fdot2 with this sum */
259 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
260 }
261
262 static bool
263 midgard_nir_lower_fdot2(nir_shader *shader)
264 {
265 bool progress = false;
266
267 nir_foreach_function(function, shader) {
268 if (!function->impl) continue;
269
270 nir_builder _b;
271 nir_builder *b = &_b;
272 nir_builder_init(b, function->impl);
273
274 nir_foreach_block(block, function->impl) {
275 nir_foreach_instr_safe(instr, block) {
276 if (instr->type != nir_instr_type_alu) continue;
277
278 nir_alu_instr *alu = nir_instr_as_alu(instr);
279 midgard_nir_lower_fdot2_body(b, alu);
280
281 progress |= true;
282 }
283 }
284
285 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
286
287 }
288
289 return progress;
290 }
291
292 /* Midgard can't write depth and stencil separately. It has to happen in a
293 * single store operation containing both. Let's add a panfrost specific
294 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
295 * one.
296 */
297 static bool
298 midgard_nir_lower_zs_store(nir_shader *nir)
299 {
300 if (nir->info.stage != MESA_SHADER_FRAGMENT)
301 return false;
302
303 nir_variable *z_var = NULL, *s_var = NULL;
304
305 nir_foreach_variable(var, &nir->outputs) {
306 if (var->data.location == FRAG_RESULT_DEPTH)
307 z_var = var;
308 else if (var->data.location == FRAG_RESULT_STENCIL)
309 s_var = var;
310 }
311
312 if (!z_var && !s_var)
313 return false;
314
315 bool progress = false;
316
317 nir_foreach_function(function, nir) {
318 if (!function->impl) continue;
319
320 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
321
322 nir_foreach_block(block, function->impl) {
323 nir_foreach_instr_safe(instr, block) {
324 if (instr->type != nir_instr_type_intrinsic)
325 continue;
326
327 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
328 if (intr->intrinsic != nir_intrinsic_store_output)
329 continue;
330
331 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
332 assert(!z_store);
333 z_store = intr;
334 last_store = intr;
335 }
336
337 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
338 assert(!s_store);
339 s_store = intr;
340 last_store = intr;
341 }
342 }
343 }
344
345 if (!z_store && !s_store) continue;
346
347 nir_builder b;
348 nir_builder_init(&b, function->impl);
349
350 b.cursor = nir_before_instr(&last_store->instr);
351
352 nir_ssa_def *zs_store_src;
353
354 if (z_store && s_store) {
355 nir_ssa_def *srcs[2] = {
356 nir_ssa_for_src(&b, z_store->src[0], 1),
357 nir_ssa_for_src(&b, s_store->src[0], 1),
358 };
359
360 zs_store_src = nir_vec(&b, srcs, 2);
361 } else {
362 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
363 }
364
365 nir_intrinsic_instr *zs_store;
366
367 zs_store = nir_intrinsic_instr_create(b.shader,
368 nir_intrinsic_store_zs_output_pan);
369 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
370 zs_store->num_components = z_store && s_store ? 2 : 1;
371 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
372
373 /* Replace the Z and S store by a ZS store */
374 nir_builder_instr_insert(&b, &zs_store->instr);
375
376 if (z_store)
377 nir_instr_remove(&z_store->instr);
378
379 if (s_store)
380 nir_instr_remove(&s_store->instr);
381
382 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
383 progress = true;
384 }
385
386 return progress;
387 }
388
389 /* Flushes undefined values to zero */
390
391 static void
392 optimise_nir(nir_shader *nir, unsigned quirks)
393 {
394 bool progress;
395 unsigned lower_flrp =
396 (nir->options->lower_flrp16 ? 16 : 0) |
397 (nir->options->lower_flrp32 ? 32 : 0) |
398 (nir->options->lower_flrp64 ? 64 : 0);
399
400 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
401 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
402
403 nir_lower_tex_options lower_tex_options = {
404 .lower_txs_lod = true,
405 .lower_txp = ~0,
406 .lower_tex_without_implicit_lod =
407 (quirks & MIDGARD_EXPLICIT_LOD),
408
409 /* TODO: we have native gradient.. */
410 .lower_txd = true,
411 };
412
413 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
414
415 /* Must lower fdot2 after tex is lowered */
416 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
417
418 /* T720 is broken. */
419
420 if (quirks & MIDGARD_BROKEN_LOD)
421 NIR_PASS_V(nir, midgard_nir_lod_errata);
422
423 do {
424 progress = false;
425
426 NIR_PASS(progress, nir, nir_lower_var_copies);
427 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
428
429 NIR_PASS(progress, nir, nir_copy_prop);
430 NIR_PASS(progress, nir, nir_opt_remove_phis);
431 NIR_PASS(progress, nir, nir_opt_dce);
432 NIR_PASS(progress, nir, nir_opt_dead_cf);
433 NIR_PASS(progress, nir, nir_opt_cse);
434 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
435 NIR_PASS(progress, nir, nir_opt_algebraic);
436 NIR_PASS(progress, nir, nir_opt_constant_folding);
437
438 if (lower_flrp != 0) {
439 bool lower_flrp_progress = false;
440 NIR_PASS(lower_flrp_progress,
441 nir,
442 nir_lower_flrp,
443 lower_flrp,
444 false /* always_precise */,
445 nir->options->lower_ffma);
446 if (lower_flrp_progress) {
447 NIR_PASS(progress, nir,
448 nir_opt_constant_folding);
449 progress = true;
450 }
451
452 /* Nothing should rematerialize any flrps, so we only
453 * need to do this lowering once.
454 */
455 lower_flrp = 0;
456 }
457
458 NIR_PASS(progress, nir, nir_opt_undef);
459 NIR_PASS(progress, nir, nir_undef_to_zero);
460
461 NIR_PASS(progress, nir, nir_opt_loop_unroll,
462 nir_var_shader_in |
463 nir_var_shader_out |
464 nir_var_function_temp);
465
466 NIR_PASS(progress, nir, nir_opt_vectorize);
467 } while (progress);
468
469 /* Must be run at the end to prevent creation of fsin/fcos ops */
470 NIR_PASS(progress, nir, midgard_nir_scale_trig);
471
472 do {
473 progress = false;
474
475 NIR_PASS(progress, nir, nir_opt_dce);
476 NIR_PASS(progress, nir, nir_opt_algebraic);
477 NIR_PASS(progress, nir, nir_opt_constant_folding);
478 NIR_PASS(progress, nir, nir_copy_prop);
479 } while (progress);
480
481 NIR_PASS(progress, nir, nir_opt_algebraic_late);
482 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
483
484 /* We implement booleans as 32-bit 0/~0 */
485 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
486
487 /* Now that booleans are lowered, we can run out late opts */
488 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
489 NIR_PASS(progress, nir, midgard_nir_cancel_inot);
490
491 NIR_PASS(progress, nir, nir_copy_prop);
492 NIR_PASS(progress, nir, nir_opt_dce);
493
494 /* Take us out of SSA */
495 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
496 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
497
498 /* We are a vector architecture; write combine where possible */
499 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
500 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
501
502 NIR_PASS(progress, nir, nir_opt_dce);
503 }
504
505 /* Do not actually emit a load; instead, cache the constant for inlining */
506
507 static void
508 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
509 {
510 nir_ssa_def def = instr->def;
511
512 midgard_constants *consts = rzalloc(NULL, midgard_constants);
513
514 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
515
516 #define RAW_CONST_COPY(bits) \
517 nir_const_value_to_array(consts->u##bits, instr->value, \
518 instr->def.num_components, u##bits)
519
520 switch (instr->def.bit_size) {
521 case 64:
522 RAW_CONST_COPY(64);
523 break;
524 case 32:
525 RAW_CONST_COPY(32);
526 break;
527 case 16:
528 RAW_CONST_COPY(16);
529 break;
530 case 8:
531 RAW_CONST_COPY(8);
532 break;
533 default:
534 unreachable("Invalid bit_size for load_const instruction\n");
535 }
536
537 /* Shifted for SSA, +1 for off-by-one */
538 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
539 }
540
541 /* Normally constants are embedded implicitly, but for I/O and such we have to
542 * explicitly emit a move with the constant source */
543
544 static void
545 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
546 {
547 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
548
549 if (constant_value) {
550 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
551 attach_constants(ctx, &ins, constant_value, node + 1);
552 emit_mir_instruction(ctx, ins);
553 }
554 }
555
556 static bool
557 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
558 {
559 unsigned comp = src->swizzle[0];
560
561 for (unsigned c = 1; c < nr_components; ++c) {
562 if (src->swizzle[c] != comp)
563 return true;
564 }
565
566 return false;
567 }
568
569 #define ALU_CASE(nir, _op) \
570 case nir_op_##nir: \
571 op = midgard_alu_op_##_op; \
572 assert(src_bitsize == dst_bitsize); \
573 break;
574
575 #define ALU_CASE_BCAST(nir, _op, count) \
576 case nir_op_##nir: \
577 op = midgard_alu_op_##_op; \
578 broadcast_swizzle = count; \
579 assert(src_bitsize == dst_bitsize); \
580 break;
581 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
582 * special treatment override this anyway. */
583
584 static midgard_reg_mode
585 reg_mode_for_nir(nir_alu_instr *instr)
586 {
587 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
588
589 switch (src_bitsize) {
590 case 8:
591 return midgard_reg_mode_8;
592 case 16:
593 return midgard_reg_mode_16;
594 case 32:
595 return midgard_reg_mode_32;
596 case 64:
597 return midgard_reg_mode_64;
598 default:
599 unreachable("Invalid bit size");
600 }
601 }
602
603 /* Compare mir_lower_invert */
604 static bool
605 nir_accepts_inot(nir_op op, unsigned src)
606 {
607 switch (op) {
608 case nir_op_ior:
609 case nir_op_iand:
610 case nir_op_ixor:
611 return true;
612 case nir_op_b32csel:
613 /* Only the condition */
614 return (src == 0);
615 default:
616 return false;
617 }
618 }
619
620 static void
621 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool *not, bool is_int, unsigned bcast_count)
622 {
623 nir_alu_src src = instr->src[i];
624
625 if (!is_int) {
626 if (pan_has_source_mod(&src, nir_op_fneg))
627 *neg = !(*neg);
628
629 if (pan_has_source_mod(&src, nir_op_fabs))
630 *abs = true;
631 }
632
633 if (nir_accepts_inot(instr->op, i) && pan_has_source_mod(&src, nir_op_inot))
634 *not = true;
635
636 unsigned bits = nir_src_bit_size(src.src);
637
638 ins->src[to] = nir_src_index(NULL, &src.src);
639 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
640
641 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
642 ins->swizzle[to][c] = src.swizzle[
643 (!bcast_count || c < bcast_count) ? c :
644 (bcast_count - 1)];
645 }
646 }
647
648 static void
649 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
650 {
651 nir_dest *dest = &instr->dest.dest;
652
653 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index))
654 return;
655
656 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
657 * is handled elsewhere */
658
659 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
660 midgard_emit_derivatives(ctx, instr);
661 return;
662 }
663
664 bool is_ssa = dest->is_ssa;
665
666 unsigned nr_components = nir_dest_num_components(*dest);
667 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
668 unsigned op = 0;
669
670 /* Number of components valid to check for the instruction (the rest
671 * will be forced to the last), or 0 to use as-is. Relevant as
672 * ball-type instructions have a channel count in NIR but are all vec4
673 * in Midgard */
674
675 unsigned broadcast_swizzle = 0;
676
677 /* What register mode should we operate in? */
678 midgard_reg_mode reg_mode =
679 reg_mode_for_nir(instr);
680
681 /* Do we need a destination override? Used for inline
682 * type conversion */
683
684 midgard_dest_override dest_override =
685 midgard_dest_override_none;
686
687 /* Should we use a smaller respective source and sign-extend? */
688
689 bool half_1 = false, sext_1 = false;
690 bool half_2 = false, sext_2 = false;
691
692 /* Should we swap arguments? */
693 bool flip_src12 = false;
694
695 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
696 unsigned dst_bitsize = nir_dest_bit_size(*dest);
697
698 switch (instr->op) {
699 ALU_CASE(fadd, fadd);
700 ALU_CASE(fmul, fmul);
701 ALU_CASE(fmin, fmin);
702 ALU_CASE(fmax, fmax);
703 ALU_CASE(imin, imin);
704 ALU_CASE(imax, imax);
705 ALU_CASE(umin, umin);
706 ALU_CASE(umax, umax);
707 ALU_CASE(ffloor, ffloor);
708 ALU_CASE(fround_even, froundeven);
709 ALU_CASE(ftrunc, ftrunc);
710 ALU_CASE(fceil, fceil);
711 ALU_CASE(fdot3, fdot3);
712 ALU_CASE(fdot4, fdot4);
713 ALU_CASE(iadd, iadd);
714 ALU_CASE(isub, isub);
715 ALU_CASE(imul, imul);
716
717 /* Zero shoved as second-arg */
718 ALU_CASE(iabs, iabsdiff);
719
720 ALU_CASE(mov, imov);
721
722 ALU_CASE(feq32, feq);
723 ALU_CASE(fne32, fne);
724 ALU_CASE(flt32, flt);
725 ALU_CASE(ieq32, ieq);
726 ALU_CASE(ine32, ine);
727 ALU_CASE(ilt32, ilt);
728 ALU_CASE(ult32, ult);
729
730 /* We don't have a native b2f32 instruction. Instead, like many
731 * GPUs, we exploit booleans as 0/~0 for false/true, and
732 * correspondingly AND
733 * by 1.0 to do the type conversion. For the moment, prime us
734 * to emit:
735 *
736 * iand [whatever], #0
737 *
738 * At the end of emit_alu (as MIR), we'll fix-up the constant
739 */
740
741 ALU_CASE(b2f32, iand);
742 ALU_CASE(b2i32, iand);
743
744 /* Likewise, we don't have a dedicated f2b32 instruction, but
745 * we can do a "not equal to 0.0" test. */
746
747 ALU_CASE(f2b32, fne);
748 ALU_CASE(i2b32, ine);
749
750 ALU_CASE(frcp, frcp);
751 ALU_CASE(frsq, frsqrt);
752 ALU_CASE(fsqrt, fsqrt);
753 ALU_CASE(fexp2, fexp2);
754 ALU_CASE(flog2, flog2);
755
756 ALU_CASE(f2i64, f2i_rtz);
757 ALU_CASE(f2u64, f2u_rtz);
758 ALU_CASE(i2f64, i2f_rtz);
759 ALU_CASE(u2f64, u2f_rtz);
760
761 ALU_CASE(f2i32, f2i_rtz);
762 ALU_CASE(f2u32, f2u_rtz);
763 ALU_CASE(i2f32, i2f_rtz);
764 ALU_CASE(u2f32, u2f_rtz);
765
766 ALU_CASE(f2i16, f2i_rtz);
767 ALU_CASE(f2u16, f2u_rtz);
768 ALU_CASE(i2f16, i2f_rtz);
769 ALU_CASE(u2f16, u2f_rtz);
770
771 ALU_CASE(fsin, fsin);
772 ALU_CASE(fcos, fcos);
773
774 /* We'll get 0 in the second arg, so:
775 * ~a = ~(a | 0) = nor(a, 0) */
776 ALU_CASE(inot, inor);
777 ALU_CASE(iand, iand);
778 ALU_CASE(ior, ior);
779 ALU_CASE(ixor, ixor);
780 ALU_CASE(ishl, ishl);
781 ALU_CASE(ishr, iasr);
782 ALU_CASE(ushr, ilsr);
783
784 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
785 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
786 ALU_CASE(b32all_fequal4, fball_eq);
787
788 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
789 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
790 ALU_CASE(b32any_fnequal4, fbany_neq);
791
792 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
793 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
794 ALU_CASE(b32all_iequal4, iball_eq);
795
796 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
797 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
798 ALU_CASE(b32any_inequal4, ibany_neq);
799
800 /* Source mods will be shoved in later */
801 ALU_CASE(fabs, fmov);
802 ALU_CASE(fneg, fmov);
803 ALU_CASE(fsat, fmov);
804 ALU_CASE(fsat_signed, fmov);
805 ALU_CASE(fclamp_pos, fmov);
806
807 /* For size conversion, we use a move. Ideally though we would squash
808 * these ops together; maybe that has to happen after in NIR as part of
809 * propagation...? An earlier algebraic pass ensured we step down by
810 * only / exactly one size. If stepping down, we use a dest override to
811 * reduce the size; if stepping up, we use a larger-sized move with a
812 * half source and a sign/zero-extension modifier */
813
814 case nir_op_i2i8:
815 case nir_op_i2i16:
816 case nir_op_i2i32:
817 case nir_op_i2i64:
818 /* If we end up upscale, we'll need a sign-extend on the
819 * operand (the second argument) */
820
821 sext_2 = true;
822 /* fallthrough */
823 case nir_op_u2u8:
824 case nir_op_u2u16:
825 case nir_op_u2u32:
826 case nir_op_u2u64:
827 case nir_op_f2f16:
828 case nir_op_f2f32:
829 case nir_op_f2f64: {
830 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
831 instr->op == nir_op_f2f64)
832 op = midgard_alu_op_fmov;
833 else
834 op = midgard_alu_op_imov;
835
836 if (dst_bitsize == (src_bitsize * 2)) {
837 /* Converting up */
838 half_2 = true;
839
840 /* Use a greater register mode */
841 reg_mode++;
842 } else if (src_bitsize == (dst_bitsize * 2)) {
843 /* Converting down */
844 dest_override = midgard_dest_override_lower;
845 }
846
847 break;
848 }
849
850 /* For greater-or-equal, we lower to less-or-equal and flip the
851 * arguments */
852
853 case nir_op_fge:
854 case nir_op_fge32:
855 case nir_op_ige32:
856 case nir_op_uge32: {
857 op =
858 instr->op == nir_op_fge ? midgard_alu_op_fle :
859 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
860 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
861 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
862 0;
863
864 flip_src12 = true;
865 break;
866 }
867
868 case nir_op_b32csel: {
869 /* Midgard features both fcsel and icsel, depending on
870 * the type of the arguments/output. However, as long
871 * as we're careful we can _always_ use icsel and
872 * _never_ need fcsel, since the latter does additional
873 * floating-point-specific processing whereas the
874 * former just moves bits on the wire. It's not obvious
875 * why these are separate opcodes, save for the ability
876 * to do things like sat/pos/abs/neg for free */
877
878 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
879 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
880
881 break;
882 }
883
884 default:
885 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
886 assert(0);
887 return;
888 }
889
890 /* Midgard can perform certain modifiers on output of an ALU op */
891
892 unsigned outmod = 0;
893
894 bool abs[4] = { false };
895 bool neg[4] = { false };
896 bool is_int = midgard_is_integer_op(op);
897
898 if (midgard_is_integer_out_op(op)) {
899 outmod = midgard_outmod_int_wrap;
900 } else if (instr->op == nir_op_fsat) {
901 outmod = midgard_outmod_sat;
902 } else if (instr->op == nir_op_fsat_signed) {
903 outmod = midgard_outmod_sat_signed;
904 } else if (instr->op == nir_op_fclamp_pos) {
905 outmod = midgard_outmod_pos;
906 }
907
908 /* Fetch unit, quirks, etc information */
909 unsigned opcode_props = alu_opcode_props[op].props;
910 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
911
912 midgard_instruction ins = {
913 .type = TAG_ALU_4,
914 .dest = nir_dest_index(dest),
915 .dest_type = nir_op_infos[instr->op].output_type
916 | nir_dest_bit_size(*dest),
917 };
918
919 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
920 ins.src[i] = ~0;
921
922 if (quirk_flipped_r24) {
923 ins.src[0] = ~0;
924 mir_copy_src(&ins, instr, 0, 1, &abs[1], &neg[1], &ins.src_invert[1], is_int, broadcast_swizzle);
925 } else {
926 for (unsigned i = 0; i < nr_inputs; ++i) {
927 unsigned to = i;
928
929 if (instr->op == nir_op_b32csel) {
930 /* The condition is the first argument; move
931 * the other arguments up one to be a binary
932 * instruction for Midgard with the condition
933 * last */
934
935 if (i == 0)
936 to = 2;
937 else if (flip_src12)
938 to = 2 - i;
939 else
940 to = i - 1;
941 } else if (flip_src12) {
942 to = 1 - to;
943 }
944
945 mir_copy_src(&ins, instr, i, to, &abs[to], &neg[to], &ins.src_invert[to], is_int, broadcast_swizzle);
946
947 /* (!c) ? a : b = c ? b : a */
948 if (instr->op == nir_op_b32csel && ins.src_invert[2]) {
949 ins.src_invert[2] = false;
950 flip_src12 ^= true;
951 }
952 }
953 }
954
955 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
956 /* Lowered to move */
957 if (instr->op == nir_op_fneg)
958 neg[1] = !neg[1];
959
960 if (instr->op == nir_op_fabs)
961 abs[1] = true;
962 }
963
964 ins.mask = mask_of(nr_components);
965
966 midgard_vector_alu alu = {
967 .op = op,
968 .reg_mode = reg_mode,
969 .dest_override = dest_override,
970 .outmod = outmod,
971
972 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(abs[0], neg[0], is_int, half_1, sext_1)),
973 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(abs[1], neg[1], is_int, half_2, sext_2)),
974 };
975
976 /* Apply writemask if non-SSA, keeping in mind that we can't write to
977 * components that don't exist. Note modifier => SSA => !reg => no
978 * writemask, so we don't have to worry about writemasks here.*/
979
980 if (!is_ssa)
981 ins.mask &= instr->dest.write_mask;
982
983 ins.alu = alu;
984
985 /* Arrange for creation of iandnot/iornot */
986 if (ins.src_invert[0] && !ins.src_invert[1]) {
987 mir_flip(&ins);
988 ins.src_invert[0] = false;
989 ins.src_invert[1] = true;
990 }
991
992 /* Late fixup for emulated instructions */
993
994 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
995 /* Presently, our second argument is an inline #0 constant.
996 * Switch over to an embedded 1.0 constant (that can't fit
997 * inline, since we're 32-bit, not 16-bit like the inline
998 * constants) */
999
1000 ins.has_inline_constant = false;
1001 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1002 ins.src_types[1] = nir_type_float32;
1003 ins.has_constants = true;
1004
1005 if (instr->op == nir_op_b2f32)
1006 ins.constants.f32[0] = 1.0f;
1007 else
1008 ins.constants.i32[0] = 1;
1009
1010 for (unsigned c = 0; c < 16; ++c)
1011 ins.swizzle[1][c] = 0;
1012 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1013 /* Lots of instructions need a 0 plonked in */
1014 ins.has_inline_constant = false;
1015 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1016 ins.src_types[1] = nir_type_uint32;
1017 ins.has_constants = true;
1018 ins.constants.u32[0] = 0;
1019
1020 for (unsigned c = 0; c < 16; ++c)
1021 ins.swizzle[1][c] = 0;
1022 }
1023
1024 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1025 /* To avoid duplicating the lookup tables (probably), true LUT
1026 * instructions can only operate as if they were scalars. Lower
1027 * them here by changing the component. */
1028
1029 unsigned orig_mask = ins.mask;
1030
1031 unsigned swizzle_back[MIR_VEC_COMPONENTS];
1032 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
1033
1034 for (int i = 0; i < nr_components; ++i) {
1035 /* Mask the associated component, dropping the
1036 * instruction if needed */
1037
1038 ins.mask = 1 << i;
1039 ins.mask &= orig_mask;
1040
1041 if (!ins.mask)
1042 continue;
1043
1044 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1045 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1046
1047 emit_mir_instruction(ctx, ins);
1048 }
1049 } else {
1050 emit_mir_instruction(ctx, ins);
1051 }
1052 }
1053
1054 #undef ALU_CASE
1055
1056 static void
1057 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1058 {
1059 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1060 unsigned nir_mask = 0;
1061 unsigned dsize = 0;
1062
1063 if (is_read) {
1064 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1065 dsize = nir_dest_bit_size(intr->dest);
1066 } else {
1067 nir_mask = nir_intrinsic_write_mask(intr);
1068 dsize = 32;
1069 }
1070
1071 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1072 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1073 mir_set_bytemask(ins, bytemask);
1074
1075 if (dsize == 64)
1076 ins->load_64 = true;
1077 }
1078
1079 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1080 * optimized) versions of UBO #0 */
1081
1082 static midgard_instruction *
1083 emit_ubo_read(
1084 compiler_context *ctx,
1085 nir_instr *instr,
1086 unsigned dest,
1087 unsigned offset,
1088 nir_src *indirect_offset,
1089 unsigned indirect_shift,
1090 unsigned index)
1091 {
1092 /* TODO: half-floats */
1093
1094 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1095 ins.constants.u32[0] = offset;
1096
1097 if (instr->type == nir_instr_type_intrinsic)
1098 mir_set_intr_mask(instr, &ins, true);
1099
1100 if (indirect_offset) {
1101 ins.src[2] = nir_src_index(ctx, indirect_offset);
1102 ins.src_types[2] = nir_type_uint32;
1103 ins.load_store.arg_2 = (indirect_shift << 5);
1104 } else {
1105 ins.load_store.arg_2 = 0x1E;
1106 }
1107
1108 ins.load_store.arg_1 = index;
1109
1110 return emit_mir_instruction(ctx, ins);
1111 }
1112
1113 /* Globals are like UBOs if you squint. And shared memory is like globals if
1114 * you squint even harder */
1115
1116 static void
1117 emit_global(
1118 compiler_context *ctx,
1119 nir_instr *instr,
1120 bool is_read,
1121 unsigned srcdest,
1122 nir_src *offset,
1123 bool is_shared)
1124 {
1125 /* TODO: types */
1126
1127 midgard_instruction ins;
1128
1129 if (is_read)
1130 ins = m_ld_int4(srcdest, 0);
1131 else
1132 ins = m_st_int4(srcdest, 0);
1133
1134 mir_set_offset(ctx, &ins, offset, is_shared);
1135 mir_set_intr_mask(instr, &ins, is_read);
1136
1137 emit_mir_instruction(ctx, ins);
1138 }
1139
1140 static void
1141 emit_varying_read(
1142 compiler_context *ctx,
1143 unsigned dest, unsigned offset,
1144 unsigned nr_comp, unsigned component,
1145 nir_src *indirect_offset, nir_alu_type type, bool flat)
1146 {
1147 /* XXX: Half-floats? */
1148 /* TODO: swizzle, mask */
1149
1150 midgard_instruction ins = m_ld_vary_32(dest, offset);
1151 ins.mask = mask_of(nr_comp);
1152
1153 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1154 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1155
1156 midgard_varying_parameter p = {
1157 .is_varying = 1,
1158 .interpolation = midgard_interp_default,
1159 .flat = flat,
1160 };
1161
1162 unsigned u;
1163 memcpy(&u, &p, sizeof(p));
1164 ins.load_store.varying_parameters = u;
1165
1166 if (indirect_offset) {
1167 ins.src[2] = nir_src_index(ctx, indirect_offset);
1168 ins.src_types[2] = nir_type_uint32;
1169 } else
1170 ins.load_store.arg_2 = 0x1E;
1171
1172 ins.load_store.arg_1 = 0x9E;
1173
1174 /* Use the type appropriate load */
1175 switch (type) {
1176 case nir_type_uint:
1177 case nir_type_bool:
1178 ins.load_store.op = midgard_op_ld_vary_32u;
1179 break;
1180 case nir_type_int:
1181 ins.load_store.op = midgard_op_ld_vary_32i;
1182 break;
1183 case nir_type_float:
1184 ins.load_store.op = midgard_op_ld_vary_32;
1185 break;
1186 default:
1187 unreachable("Attempted to load unknown type");
1188 break;
1189 }
1190
1191 emit_mir_instruction(ctx, ins);
1192 }
1193
1194 static void
1195 emit_attr_read(
1196 compiler_context *ctx,
1197 unsigned dest, unsigned offset,
1198 unsigned nr_comp, nir_alu_type t)
1199 {
1200 midgard_instruction ins = m_ld_attr_32(dest, offset);
1201 ins.load_store.arg_1 = 0x1E;
1202 ins.load_store.arg_2 = 0x1E;
1203 ins.mask = mask_of(nr_comp);
1204
1205 /* Use the type appropriate load */
1206 switch (t) {
1207 case nir_type_uint:
1208 case nir_type_bool:
1209 ins.load_store.op = midgard_op_ld_attr_32u;
1210 break;
1211 case nir_type_int:
1212 ins.load_store.op = midgard_op_ld_attr_32i;
1213 break;
1214 case nir_type_float:
1215 ins.load_store.op = midgard_op_ld_attr_32;
1216 break;
1217 default:
1218 unreachable("Attempted to load unknown type");
1219 break;
1220 }
1221
1222 emit_mir_instruction(ctx, ins);
1223 }
1224
1225 static void
1226 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1227 unsigned nr_components, unsigned offset)
1228 {
1229 nir_dest nir_dest;
1230
1231 /* Figure out which uniform this is */
1232 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1233 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1234
1235 unsigned dest = nir_dest_index(&nir_dest);
1236
1237 /* Sysvals are prefix uniforms */
1238 unsigned uniform = ((uintptr_t) val) - 1;
1239
1240 /* Emit the read itself -- this is never indirect */
1241 midgard_instruction *ins =
1242 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1243
1244 ins->mask = mask_of(nr_components);
1245 }
1246
1247 static unsigned
1248 compute_builtin_arg(nir_op op)
1249 {
1250 switch (op) {
1251 case nir_intrinsic_load_work_group_id:
1252 return 0x14;
1253 case nir_intrinsic_load_local_invocation_id:
1254 return 0x10;
1255 default:
1256 unreachable("Invalid compute paramater loaded");
1257 }
1258 }
1259
1260 static void
1261 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1262 {
1263 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1264
1265 midgard_instruction *br = ctx->writeout_branch[rt];
1266
1267 assert(!br);
1268
1269 emit_explicit_constant(ctx, src, src);
1270
1271 struct midgard_instruction ins =
1272 v_branch(false, false);
1273
1274 ins.writeout = true;
1275
1276 /* Add dependencies */
1277 ins.src[0] = src;
1278 ins.src_types[0] = nir_type_uint32;
1279 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1280 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1281
1282 /* Emit the branch */
1283 br = emit_mir_instruction(ctx, ins);
1284 schedule_barrier(ctx);
1285 ctx->writeout_branch[rt] = br;
1286
1287 /* Push our current location = current block count - 1 = where we'll
1288 * jump to. Maybe a bit too clever for my own good */
1289
1290 br->branch.target_block = ctx->block_count - 1;
1291 }
1292
1293 static void
1294 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1295 {
1296 unsigned reg = nir_dest_index(&instr->dest);
1297 midgard_instruction ins = m_ld_compute_id(reg, 0);
1298 ins.mask = mask_of(3);
1299 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1300 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1301 emit_mir_instruction(ctx, ins);
1302 }
1303
1304 static unsigned
1305 vertex_builtin_arg(nir_op op)
1306 {
1307 switch (op) {
1308 case nir_intrinsic_load_vertex_id:
1309 return PAN_VERTEX_ID;
1310 case nir_intrinsic_load_instance_id:
1311 return PAN_INSTANCE_ID;
1312 default:
1313 unreachable("Invalid vertex builtin");
1314 }
1315 }
1316
1317 static void
1318 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1319 {
1320 unsigned reg = nir_dest_index(&instr->dest);
1321 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1322 }
1323
1324 static void
1325 emit_control_barrier(compiler_context *ctx)
1326 {
1327 midgard_instruction ins = {
1328 .type = TAG_TEXTURE_4,
1329 .src = { ~0, ~0, ~0, ~0 },
1330 .texture = {
1331 .op = TEXTURE_OP_BARRIER,
1332
1333 /* TODO: optimize */
1334 .barrier_buffer = 1,
1335 .barrier_shared = 1
1336 }
1337 };
1338
1339 emit_mir_instruction(ctx, ins);
1340 }
1341
1342 static const nir_variable *
1343 search_var(struct exec_list *vars, unsigned driver_loc)
1344 {
1345 nir_foreach_variable(var, vars) {
1346 if (var->data.driver_location == driver_loc)
1347 return var;
1348 }
1349
1350 return NULL;
1351 }
1352
1353 static void
1354 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1355 {
1356 unsigned offset = 0, reg;
1357
1358 switch (instr->intrinsic) {
1359 case nir_intrinsic_discard_if:
1360 case nir_intrinsic_discard: {
1361 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1362 struct midgard_instruction discard = v_branch(conditional, false);
1363 discard.branch.target_type = TARGET_DISCARD;
1364
1365 if (conditional) {
1366 discard.src[0] = nir_src_index(ctx, &instr->src[0]);
1367 discard.src_types[0] = nir_type_uint32;
1368 }
1369
1370 emit_mir_instruction(ctx, discard);
1371 schedule_barrier(ctx);
1372
1373 break;
1374 }
1375
1376 case nir_intrinsic_load_uniform:
1377 case nir_intrinsic_load_ubo:
1378 case nir_intrinsic_load_global:
1379 case nir_intrinsic_load_shared:
1380 case nir_intrinsic_load_input:
1381 case nir_intrinsic_load_interpolated_input: {
1382 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1383 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1384 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1385 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1386 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1387 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1388
1389 /* Get the base type of the intrinsic */
1390 /* TODO: Infer type? Does it matter? */
1391 nir_alu_type t =
1392 (is_ubo || is_global || is_shared) ? nir_type_uint :
1393 (is_interp) ? nir_type_float :
1394 nir_intrinsic_type(instr);
1395
1396 t = nir_alu_type_get_base_type(t);
1397
1398 if (!(is_ubo || is_global)) {
1399 offset = nir_intrinsic_base(instr);
1400 }
1401
1402 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1403
1404 nir_src *src_offset = nir_get_io_offset_src(instr);
1405
1406 bool direct = nir_src_is_const(*src_offset);
1407 nir_src *indirect_offset = direct ? NULL : src_offset;
1408
1409 if (direct)
1410 offset += nir_src_as_uint(*src_offset);
1411
1412 /* We may need to apply a fractional offset */
1413 int component = (is_flat || is_interp) ?
1414 nir_intrinsic_component(instr) : 0;
1415 reg = nir_dest_index(&instr->dest);
1416
1417 if (is_uniform && !ctx->is_blend) {
1418 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1419 } else if (is_ubo) {
1420 nir_src index = instr->src[0];
1421
1422 /* TODO: Is indirect block number possible? */
1423 assert(nir_src_is_const(index));
1424
1425 uint32_t uindex = nir_src_as_uint(index) + 1;
1426 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1427 } else if (is_global || is_shared) {
1428 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1429 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1430 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1431 } else if (ctx->is_blend) {
1432 /* For blend shaders, load the input color, which is
1433 * preloaded to r0 */
1434
1435 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1436 emit_mir_instruction(ctx, move);
1437 schedule_barrier(ctx);
1438 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1439 emit_attr_read(ctx, reg, offset, nr_comp, t);
1440 } else {
1441 DBG("Unknown load\n");
1442 assert(0);
1443 }
1444
1445 break;
1446 }
1447
1448 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1449 case nir_intrinsic_load_barycentric_pixel:
1450 case nir_intrinsic_load_barycentric_centroid:
1451 break;
1452
1453 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1454
1455 case nir_intrinsic_load_raw_output_pan:
1456 case nir_intrinsic_load_output_u8_as_fp16_pan:
1457 reg = nir_dest_index(&instr->dest);
1458 assert(ctx->is_blend);
1459
1460 /* T720 and below use different blend opcodes with slightly
1461 * different semantics than T760 and up */
1462
1463 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1464 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1465
1466 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1467 ld.load_store.op = old_blend ?
1468 midgard_op_ld_color_buffer_u8_as_fp16_old :
1469 midgard_op_ld_color_buffer_u8_as_fp16;
1470
1471 if (old_blend) {
1472 ld.load_store.address = 1;
1473 ld.load_store.arg_2 = 0x1E;
1474 }
1475
1476 for (unsigned c = 2; c < 16; ++c)
1477 ld.swizzle[0][c] = 0;
1478 }
1479
1480 emit_mir_instruction(ctx, ld);
1481 break;
1482
1483 case nir_intrinsic_load_blend_const_color_rgba: {
1484 assert(ctx->is_blend);
1485 reg = nir_dest_index(&instr->dest);
1486
1487 /* Blend constants are embedded directly in the shader and
1488 * patched in, so we use some magic routing */
1489
1490 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1491 ins.has_constants = true;
1492 ins.has_blend_constant = true;
1493 emit_mir_instruction(ctx, ins);
1494 break;
1495 }
1496
1497 case nir_intrinsic_store_zs_output_pan: {
1498 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1499 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1500 MIDGARD_ZS_RT);
1501
1502 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1503
1504 if (!nir_intrinsic_component(instr))
1505 br->writeout_depth = true;
1506 if (nir_intrinsic_component(instr) ||
1507 instr->num_components)
1508 br->writeout_stencil = true;
1509 assert(br->writeout_depth | br->writeout_stencil);
1510 break;
1511 }
1512
1513 case nir_intrinsic_store_output:
1514 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1515
1516 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1517
1518 reg = nir_src_index(ctx, &instr->src[0]);
1519
1520 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1521 const nir_variable *var;
1522 enum midgard_rt_id rt;
1523
1524 var = search_var(&ctx->nir->outputs,
1525 nir_intrinsic_base(instr));
1526 assert(var);
1527 if (var->data.location == FRAG_RESULT_COLOR)
1528 rt = MIDGARD_COLOR_RT0;
1529 else if (var->data.location >= FRAG_RESULT_DATA0)
1530 rt = MIDGARD_COLOR_RT0 + var->data.location -
1531 FRAG_RESULT_DATA0;
1532 else
1533 assert(0);
1534
1535 emit_fragment_store(ctx, reg, rt);
1536 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1537 /* We should have been vectorized, though we don't
1538 * currently check that st_vary is emitted only once
1539 * per slot (this is relevant, since there's not a mask
1540 * parameter available on the store [set to 0 by the
1541 * blob]). We do respect the component by adjusting the
1542 * swizzle. If this is a constant source, we'll need to
1543 * emit that explicitly. */
1544
1545 emit_explicit_constant(ctx, reg, reg);
1546
1547 unsigned dst_component = nir_intrinsic_component(instr);
1548 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1549
1550 midgard_instruction st = m_st_vary_32(reg, offset);
1551 st.load_store.arg_1 = 0x9E;
1552 st.load_store.arg_2 = 0x1E;
1553
1554 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1555 case nir_type_uint:
1556 case nir_type_bool:
1557 st.load_store.op = midgard_op_st_vary_32u;
1558 break;
1559 case nir_type_int:
1560 st.load_store.op = midgard_op_st_vary_32i;
1561 break;
1562 case nir_type_float:
1563 st.load_store.op = midgard_op_st_vary_32;
1564 break;
1565 default:
1566 unreachable("Attempted to store unknown type");
1567 break;
1568 }
1569
1570 /* nir_intrinsic_component(store_intr) encodes the
1571 * destination component start. Source component offset
1572 * adjustment is taken care of in
1573 * install_registers_instr(), when offset_swizzle() is
1574 * called.
1575 */
1576 unsigned src_component = COMPONENT_X;
1577
1578 assert(nr_comp > 0);
1579 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1580 st.swizzle[0][i] = src_component;
1581 if (i >= dst_component && i < dst_component + nr_comp - 1)
1582 src_component++;
1583 }
1584
1585 emit_mir_instruction(ctx, st);
1586 } else {
1587 DBG("Unknown store\n");
1588 assert(0);
1589 }
1590
1591 break;
1592
1593 /* Special case of store_output for lowered blend shaders */
1594 case nir_intrinsic_store_raw_output_pan:
1595 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1596 reg = nir_src_index(ctx, &instr->src[0]);
1597
1598 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1599 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1600 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1601 * of:
1602 *
1603 * imov r0.xyzw, r0.xxxx
1604 */
1605
1606 unsigned expanded = make_compiler_temp(ctx);
1607
1608 midgard_instruction splatter = v_mov(reg, expanded);
1609
1610 for (unsigned c = 0; c < 16; ++c)
1611 splatter.swizzle[1][c] = 0;
1612
1613 emit_mir_instruction(ctx, splatter);
1614 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1615 } else
1616 emit_fragment_store(ctx, reg, ctx->blend_rt);
1617
1618 break;
1619
1620 case nir_intrinsic_store_global:
1621 case nir_intrinsic_store_shared:
1622 reg = nir_src_index(ctx, &instr->src[0]);
1623 emit_explicit_constant(ctx, reg, reg);
1624
1625 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1626 break;
1627
1628 case nir_intrinsic_load_ssbo_address:
1629 emit_sysval_read(ctx, &instr->instr, 1, 0);
1630 break;
1631
1632 case nir_intrinsic_get_buffer_size:
1633 emit_sysval_read(ctx, &instr->instr, 1, 8);
1634 break;
1635
1636 case nir_intrinsic_load_viewport_scale:
1637 case nir_intrinsic_load_viewport_offset:
1638 case nir_intrinsic_load_num_work_groups:
1639 case nir_intrinsic_load_sampler_lod_parameters_pan:
1640 emit_sysval_read(ctx, &instr->instr, 3, 0);
1641 break;
1642
1643 case nir_intrinsic_load_work_group_id:
1644 case nir_intrinsic_load_local_invocation_id:
1645 emit_compute_builtin(ctx, instr);
1646 break;
1647
1648 case nir_intrinsic_load_vertex_id:
1649 case nir_intrinsic_load_instance_id:
1650 emit_vertex_builtin(ctx, instr);
1651 break;
1652
1653 case nir_intrinsic_memory_barrier_buffer:
1654 case nir_intrinsic_memory_barrier_shared:
1655 break;
1656
1657 case nir_intrinsic_control_barrier:
1658 schedule_barrier(ctx);
1659 emit_control_barrier(ctx);
1660 schedule_barrier(ctx);
1661 break;
1662
1663 default:
1664 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1665 assert(0);
1666 break;
1667 }
1668 }
1669
1670 static unsigned
1671 midgard_tex_format(enum glsl_sampler_dim dim)
1672 {
1673 switch (dim) {
1674 case GLSL_SAMPLER_DIM_1D:
1675 case GLSL_SAMPLER_DIM_BUF:
1676 return MALI_TEX_1D;
1677
1678 case GLSL_SAMPLER_DIM_2D:
1679 case GLSL_SAMPLER_DIM_EXTERNAL:
1680 case GLSL_SAMPLER_DIM_RECT:
1681 return MALI_TEX_2D;
1682
1683 case GLSL_SAMPLER_DIM_3D:
1684 return MALI_TEX_3D;
1685
1686 case GLSL_SAMPLER_DIM_CUBE:
1687 return MALI_TEX_CUBE;
1688
1689 default:
1690 DBG("Unknown sampler dim type\n");
1691 assert(0);
1692 return 0;
1693 }
1694 }
1695
1696 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1697 * was successful */
1698
1699 static bool
1700 pan_attach_constant_bias(
1701 compiler_context *ctx,
1702 nir_src lod,
1703 midgard_texture_word *word)
1704 {
1705 /* To attach as constant, it has to *be* constant */
1706
1707 if (!nir_src_is_const(lod))
1708 return false;
1709
1710 float f = nir_src_as_float(lod);
1711
1712 /* Break into fixed-point */
1713 signed lod_int = f;
1714 float lod_frac = f - lod_int;
1715
1716 /* Carry over negative fractions */
1717 if (lod_frac < 0.0) {
1718 lod_int--;
1719 lod_frac += 1.0;
1720 }
1721
1722 /* Encode */
1723 word->bias = float_to_ubyte(lod_frac);
1724 word->bias_int = lod_int;
1725
1726 return true;
1727 }
1728
1729 static void
1730 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1731 unsigned midgard_texop)
1732 {
1733 /* TODO */
1734 //assert (!instr->sampler);
1735
1736 int texture_index = instr->texture_index;
1737 int sampler_index = texture_index;
1738
1739 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1740 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1741
1742 midgard_instruction ins = {
1743 .type = TAG_TEXTURE_4,
1744 .mask = 0xF,
1745 .dest = nir_dest_index(&instr->dest),
1746 .src = { ~0, ~0, ~0, ~0 },
1747 .dest_type = dest_type,
1748 .swizzle = SWIZZLE_IDENTITY_4,
1749 .texture = {
1750 .op = midgard_texop,
1751 .format = midgard_tex_format(instr->sampler_dim),
1752 .texture_handle = texture_index,
1753 .sampler_handle = sampler_index,
1754 .shadow = instr->is_shadow,
1755 }
1756 };
1757
1758 if (instr->is_shadow && !instr->is_new_style_shadow)
1759 for (int i = 0; i < 4; ++i)
1760 ins.swizzle[0][i] = COMPONENT_X;
1761
1762 /* We may need a temporary for the coordinate */
1763
1764 bool needs_temp_coord =
1765 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1766 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1767 (instr->is_shadow);
1768
1769 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1770
1771 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1772 int index = nir_src_index(ctx, &instr->src[i].src);
1773 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1774 unsigned sz = nir_src_bit_size(instr->src[i].src);
1775 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1776
1777 switch (instr->src[i].src_type) {
1778 case nir_tex_src_coord: {
1779 emit_explicit_constant(ctx, index, index);
1780
1781 unsigned coord_mask = mask_of(instr->coord_components);
1782
1783 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1784
1785 if (flip_zw)
1786 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1787
1788 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1789 /* texelFetch is undefined on samplerCube */
1790 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1791
1792 /* For cubemaps, we use a special ld/st op to
1793 * select the face and copy the xy into the
1794 * texture register */
1795
1796 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1797 ld.src[1] = index;
1798 ld.src_types[1] = T;
1799 ld.mask = 0x3; /* xy */
1800 ld.load_store.arg_1 = 0x20;
1801 ld.swizzle[1][3] = COMPONENT_X;
1802 emit_mir_instruction(ctx, ld);
1803
1804 /* xyzw -> xyxx */
1805 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1806 ins.swizzle[1][3] = COMPONENT_X;
1807 } else if (needs_temp_coord) {
1808 /* mov coord_temp, coords */
1809 midgard_instruction mov = v_mov(index, coords);
1810 mov.mask = coord_mask;
1811
1812 if (flip_zw)
1813 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1814
1815 emit_mir_instruction(ctx, mov);
1816 } else {
1817 coords = index;
1818 }
1819
1820 ins.src[1] = coords;
1821 ins.src_types[1] = T;
1822
1823 /* Texelfetch coordinates uses all four elements
1824 * (xyz/index) regardless of texture dimensionality,
1825 * which means it's necessary to zero the unused
1826 * components to keep everything happy */
1827
1828 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1829 /* mov index.zw, #0, or generalized */
1830 midgard_instruction mov =
1831 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1832 mov.has_constants = true;
1833 mov.mask = coord_mask ^ 0xF;
1834 emit_mir_instruction(ctx, mov);
1835 }
1836
1837 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1838 /* Array component in w but NIR wants it in z,
1839 * but if we have a temp coord we already fixed
1840 * that up */
1841
1842 if (nr_components == 3) {
1843 ins.swizzle[1][2] = COMPONENT_Z;
1844 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1845 } else if (nr_components == 2) {
1846 ins.swizzle[1][2] =
1847 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1848 ins.swizzle[1][3] = COMPONENT_X;
1849 } else
1850 unreachable("Invalid texture 2D components");
1851 }
1852
1853 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1854 /* We zeroed */
1855 ins.swizzle[1][2] = COMPONENT_Z;
1856 ins.swizzle[1][3] = COMPONENT_W;
1857 }
1858
1859 break;
1860 }
1861
1862 case nir_tex_src_bias:
1863 case nir_tex_src_lod: {
1864 /* Try as a constant if we can */
1865
1866 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1867 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1868 break;
1869
1870 ins.texture.lod_register = true;
1871 ins.src[2] = index;
1872 ins.src_types[2] = T;
1873
1874 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1875 ins.swizzle[2][c] = COMPONENT_X;
1876
1877 emit_explicit_constant(ctx, index, index);
1878
1879 break;
1880 };
1881
1882 case nir_tex_src_offset: {
1883 ins.texture.offset_register = true;
1884 ins.src[3] = index;
1885 ins.src_types[3] = T;
1886
1887 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1888 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
1889
1890 emit_explicit_constant(ctx, index, index);
1891 break;
1892 };
1893
1894 case nir_tex_src_comparator: {
1895 unsigned comp = COMPONENT_Z;
1896
1897 /* mov coord_temp.foo, coords */
1898 midgard_instruction mov = v_mov(index, coords);
1899 mov.mask = 1 << comp;
1900
1901 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
1902 mov.swizzle[1][i] = COMPONENT_X;
1903
1904 emit_mir_instruction(ctx, mov);
1905 break;
1906 }
1907
1908 default: {
1909 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
1910 assert(0);
1911 }
1912 }
1913 }
1914
1915 emit_mir_instruction(ctx, ins);
1916 }
1917
1918 static void
1919 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1920 {
1921 switch (instr->op) {
1922 case nir_texop_tex:
1923 case nir_texop_txb:
1924 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
1925 break;
1926 case nir_texop_txl:
1927 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
1928 break;
1929 case nir_texop_txf:
1930 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
1931 break;
1932 case nir_texop_txs:
1933 emit_sysval_read(ctx, &instr->instr, 4, 0);
1934 break;
1935 default: {
1936 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
1937 assert(0);
1938 }
1939 }
1940 }
1941
1942 static void
1943 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1944 {
1945 switch (instr->type) {
1946 case nir_jump_break: {
1947 /* Emit a branch out of the loop */
1948 struct midgard_instruction br = v_branch(false, false);
1949 br.branch.target_type = TARGET_BREAK;
1950 br.branch.target_break = ctx->current_loop_depth;
1951 emit_mir_instruction(ctx, br);
1952 break;
1953 }
1954
1955 default:
1956 DBG("Unknown jump type %d\n", instr->type);
1957 break;
1958 }
1959 }
1960
1961 static void
1962 emit_instr(compiler_context *ctx, struct nir_instr *instr)
1963 {
1964 switch (instr->type) {
1965 case nir_instr_type_load_const:
1966 emit_load_const(ctx, nir_instr_as_load_const(instr));
1967 break;
1968
1969 case nir_instr_type_intrinsic:
1970 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1971 break;
1972
1973 case nir_instr_type_alu:
1974 emit_alu(ctx, nir_instr_as_alu(instr));
1975 break;
1976
1977 case nir_instr_type_tex:
1978 emit_tex(ctx, nir_instr_as_tex(instr));
1979 break;
1980
1981 case nir_instr_type_jump:
1982 emit_jump(ctx, nir_instr_as_jump(instr));
1983 break;
1984
1985 case nir_instr_type_ssa_undef:
1986 /* Spurious */
1987 break;
1988
1989 default:
1990 DBG("Unhandled instruction type\n");
1991 break;
1992 }
1993 }
1994
1995
1996 /* ALU instructions can inline or embed constants, which decreases register
1997 * pressure and saves space. */
1998
1999 #define CONDITIONAL_ATTACH(idx) { \
2000 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2001 \
2002 if (entry) { \
2003 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2004 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2005 } \
2006 }
2007
2008 static void
2009 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2010 {
2011 mir_foreach_instr_in_block(block, alu) {
2012 /* Other instructions cannot inline constants */
2013 if (alu->type != TAG_ALU_4) continue;
2014 if (alu->compact_branch) continue;
2015
2016 /* If there is already a constant here, we can do nothing */
2017 if (alu->has_constants) continue;
2018
2019 CONDITIONAL_ATTACH(0);
2020
2021 if (!alu->has_constants) {
2022 CONDITIONAL_ATTACH(1)
2023 } else if (!alu->inline_constant) {
2024 /* Corner case: _two_ vec4 constants, for instance with a
2025 * csel. For this case, we can only use a constant
2026 * register for one, we'll have to emit a move for the
2027 * other. */
2028
2029 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2030 unsigned scratch = make_compiler_temp(ctx);
2031
2032 if (entry) {
2033 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2034 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2035
2036 /* Set the source */
2037 alu->src[1] = scratch;
2038
2039 /* Inject us -before- the last instruction which set r31 */
2040 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2041 }
2042 }
2043 }
2044 }
2045
2046 /* Midgard supports two types of constants, embedded constants (128-bit) and
2047 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2048 * constants can be demoted to inline constants, for space savings and
2049 * sometimes a performance boost */
2050
2051 static void
2052 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2053 {
2054 mir_foreach_instr_in_block(block, ins) {
2055 if (!ins->has_constants) continue;
2056 if (ins->has_inline_constant) continue;
2057
2058 /* Blend constants must not be inlined by definition */
2059 if (ins->has_blend_constant) continue;
2060
2061 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2062 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2063 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2064
2065 if (!(is_16 || is_32))
2066 continue;
2067
2068 /* src1 cannot be an inline constant due to encoding
2069 * restrictions. So, if possible we try to flip the arguments
2070 * in that case */
2071
2072 int op = ins->alu.op;
2073
2074 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2075 alu_opcode_props[op].props & OP_COMMUTES) {
2076 mir_flip(ins);
2077 }
2078
2079 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2080 /* Extract the source information */
2081
2082 midgard_vector_alu_src *src;
2083 int q = ins->alu.src2;
2084 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
2085 src = m;
2086
2087 /* Component is from the swizzle. Take a nonzero component */
2088 assert(ins->mask);
2089 unsigned first_comp = ffs(ins->mask) - 1;
2090 unsigned component = ins->swizzle[1][first_comp];
2091
2092 /* Scale constant appropriately, if we can legally */
2093 uint16_t scaled_constant = 0;
2094
2095 if (is_16) {
2096 scaled_constant = ins->constants.u16[component];
2097 } else if (midgard_is_integer_op(op)) {
2098 scaled_constant = ins->constants.u32[component];
2099
2100 /* Constant overflow after resize */
2101 if (scaled_constant != ins->constants.u32[component])
2102 continue;
2103 } else {
2104 float original = ins->constants.f32[component];
2105 scaled_constant = _mesa_float_to_half(original);
2106
2107 /* Check for loss of precision. If this is
2108 * mediump, we don't care, but for a highp
2109 * shader, we need to pay attention. NIR
2110 * doesn't yet tell us which mode we're in!
2111 * Practically this prevents most constants
2112 * from being inlined, sadly. */
2113
2114 float fp32 = _mesa_half_to_float(scaled_constant);
2115
2116 if (fp32 != original)
2117 continue;
2118 }
2119
2120 /* We don't know how to handle these with a constant */
2121
2122 if (mir_nontrivial_source2_mod_simple(ins) || src->rep_low || src->rep_high) {
2123 DBG("Bailing inline constant...\n");
2124 continue;
2125 }
2126
2127 /* Make sure that the constant is not itself a vector
2128 * by checking if all accessed values are the same. */
2129
2130 const midgard_constants *cons = &ins->constants;
2131 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2132
2133 bool is_vector = false;
2134 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2135
2136 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2137 /* We only care if this component is actually used */
2138 if (!(mask & (1 << c)))
2139 continue;
2140
2141 uint32_t test = is_16 ?
2142 cons->u16[ins->swizzle[1][c]] :
2143 cons->u32[ins->swizzle[1][c]];
2144
2145 if (test != value) {
2146 is_vector = true;
2147 break;
2148 }
2149 }
2150
2151 if (is_vector)
2152 continue;
2153
2154 /* Get rid of the embedded constant */
2155 ins->has_constants = false;
2156 ins->src[1] = ~0;
2157 ins->has_inline_constant = true;
2158 ins->inline_constant = scaled_constant;
2159 }
2160 }
2161 }
2162
2163 /* Dead code elimination for branches at the end of a block - only one branch
2164 * per block is legal semantically */
2165
2166 static void
2167 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2168 {
2169 bool branched = false;
2170
2171 mir_foreach_instr_in_block_safe(block, ins) {
2172 if (!midgard_is_branch_unit(ins->unit)) continue;
2173
2174 if (branched)
2175 mir_remove_instruction(ins);
2176
2177 branched = true;
2178 }
2179 }
2180
2181 static unsigned
2182 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2183 {
2184 /* Loop to ourselves */
2185 midgard_instruction *br = ctx->writeout_branch[rt];
2186 struct midgard_instruction ins = v_branch(false, false);
2187 ins.writeout = true;
2188 ins.writeout_depth = br->writeout_depth;
2189 ins.writeout_stencil = br->writeout_stencil;
2190 ins.branch.target_block = ctx->block_count - 1;
2191 ins.constants.u32[0] = br->constants.u32[0];
2192 emit_mir_instruction(ctx, ins);
2193
2194 ctx->current_block->epilogue = true;
2195 schedule_barrier(ctx);
2196 return ins.branch.target_block;
2197 }
2198
2199 static midgard_block *
2200 emit_block(compiler_context *ctx, nir_block *block)
2201 {
2202 midgard_block *this_block = ctx->after_block;
2203 ctx->after_block = NULL;
2204
2205 if (!this_block)
2206 this_block = create_empty_block(ctx);
2207
2208 list_addtail(&this_block->base.link, &ctx->blocks);
2209
2210 this_block->scheduled = false;
2211 ++ctx->block_count;
2212
2213 /* Set up current block */
2214 list_inithead(&this_block->base.instructions);
2215 ctx->current_block = this_block;
2216
2217 nir_foreach_instr(instr, block) {
2218 emit_instr(ctx, instr);
2219 ++ctx->instruction_count;
2220 }
2221
2222 return this_block;
2223 }
2224
2225 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2226
2227 static void
2228 emit_if(struct compiler_context *ctx, nir_if *nif)
2229 {
2230 midgard_block *before_block = ctx->current_block;
2231
2232 /* Speculatively emit the branch, but we can't fill it in until later */
2233 EMIT(branch, true, true);
2234 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2235 then_branch->src[0] = nir_src_index(ctx, &nif->condition);
2236 then_branch->src_types[0] = nir_type_uint32;
2237
2238 /* Emit the two subblocks. */
2239 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2240 midgard_block *end_then_block = ctx->current_block;
2241
2242 /* Emit a jump from the end of the then block to the end of the else */
2243 EMIT(branch, false, false);
2244 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2245
2246 /* Emit second block, and check if it's empty */
2247
2248 int else_idx = ctx->block_count;
2249 int count_in = ctx->instruction_count;
2250 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2251 midgard_block *end_else_block = ctx->current_block;
2252 int after_else_idx = ctx->block_count;
2253
2254 /* Now that we have the subblocks emitted, fix up the branches */
2255
2256 assert(then_block);
2257 assert(else_block);
2258
2259 if (ctx->instruction_count == count_in) {
2260 /* The else block is empty, so don't emit an exit jump */
2261 mir_remove_instruction(then_exit);
2262 then_branch->branch.target_block = after_else_idx;
2263 } else {
2264 then_branch->branch.target_block = else_idx;
2265 then_exit->branch.target_block = after_else_idx;
2266 }
2267
2268 /* Wire up the successors */
2269
2270 ctx->after_block = create_empty_block(ctx);
2271
2272 pan_block_add_successor(&before_block->base, &then_block->base);
2273 pan_block_add_successor(&before_block->base, &else_block->base);
2274
2275 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2276 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2277 }
2278
2279 static void
2280 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2281 {
2282 /* Remember where we are */
2283 midgard_block *start_block = ctx->current_block;
2284
2285 /* Allocate a loop number, growing the current inner loop depth */
2286 int loop_idx = ++ctx->current_loop_depth;
2287
2288 /* Get index from before the body so we can loop back later */
2289 int start_idx = ctx->block_count;
2290
2291 /* Emit the body itself */
2292 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2293
2294 /* Branch back to loop back */
2295 struct midgard_instruction br_back = v_branch(false, false);
2296 br_back.branch.target_block = start_idx;
2297 emit_mir_instruction(ctx, br_back);
2298
2299 /* Mark down that branch in the graph. */
2300 pan_block_add_successor(&start_block->base, &loop_block->base);
2301 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2302
2303 /* Find the index of the block about to follow us (note: we don't add
2304 * one; blocks are 0-indexed so we get a fencepost problem) */
2305 int break_block_idx = ctx->block_count;
2306
2307 /* Fix up the break statements we emitted to point to the right place,
2308 * now that we can allocate a block number for them */
2309 ctx->after_block = create_empty_block(ctx);
2310
2311 mir_foreach_block_from(ctx, start_block, _block) {
2312 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2313 if (ins->type != TAG_ALU_4) continue;
2314 if (!ins->compact_branch) continue;
2315
2316 /* We found a branch -- check the type to see if we need to do anything */
2317 if (ins->branch.target_type != TARGET_BREAK) continue;
2318
2319 /* It's a break! Check if it's our break */
2320 if (ins->branch.target_break != loop_idx) continue;
2321
2322 /* Okay, cool, we're breaking out of this loop.
2323 * Rewrite from a break to a goto */
2324
2325 ins->branch.target_type = TARGET_GOTO;
2326 ins->branch.target_block = break_block_idx;
2327
2328 pan_block_add_successor(_block, &ctx->after_block->base);
2329 }
2330 }
2331
2332 /* Now that we've finished emitting the loop, free up the depth again
2333 * so we play nice with recursion amid nested loops */
2334 --ctx->current_loop_depth;
2335
2336 /* Dump loop stats */
2337 ++ctx->loop_count;
2338 }
2339
2340 static midgard_block *
2341 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2342 {
2343 midgard_block *start_block = NULL;
2344
2345 foreach_list_typed(nir_cf_node, node, node, list) {
2346 switch (node->type) {
2347 case nir_cf_node_block: {
2348 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2349
2350 if (!start_block)
2351 start_block = block;
2352
2353 break;
2354 }
2355
2356 case nir_cf_node_if:
2357 emit_if(ctx, nir_cf_node_as_if(node));
2358 break;
2359
2360 case nir_cf_node_loop:
2361 emit_loop(ctx, nir_cf_node_as_loop(node));
2362 break;
2363
2364 case nir_cf_node_function:
2365 assert(0);
2366 break;
2367 }
2368 }
2369
2370 return start_block;
2371 }
2372
2373 /* Due to lookahead, we need to report the first tag executed in the command
2374 * stream and in branch targets. An initial block might be empty, so iterate
2375 * until we find one that 'works' */
2376
2377 static unsigned
2378 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2379 {
2380 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2381
2382 mir_foreach_block_from(ctx, initial_block, _v) {
2383 midgard_block *v = (midgard_block *) _v;
2384 if (v->quadword_count) {
2385 midgard_bundle *initial_bundle =
2386 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2387
2388 return initial_bundle->tag;
2389 }
2390 }
2391
2392 /* Default to a tag 1 which will break from the shader, in case we jump
2393 * to the exit block (i.e. `return` in a compute shader) */
2394
2395 return 1;
2396 }
2397
2398 /* For each fragment writeout instruction, generate a writeout loop to
2399 * associate with it */
2400
2401 static void
2402 mir_add_writeout_loops(compiler_context *ctx)
2403 {
2404 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2405 midgard_instruction *br = ctx->writeout_branch[rt];
2406 if (!br) continue;
2407
2408 unsigned popped = br->branch.target_block;
2409 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2410 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2411 br->branch.target_type = TARGET_GOTO;
2412
2413 /* If we have more RTs, we'll need to restore back after our
2414 * loop terminates */
2415
2416 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2417 midgard_instruction uncond = v_branch(false, false);
2418 uncond.branch.target_block = popped;
2419 uncond.branch.target_type = TARGET_GOTO;
2420 emit_mir_instruction(ctx, uncond);
2421 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2422 schedule_barrier(ctx);
2423 } else {
2424 /* We're last, so we can terminate here */
2425 br->last_writeout = true;
2426 }
2427 }
2428 }
2429
2430 int
2431 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2432 {
2433 struct util_dynarray *compiled = &program->compiled;
2434
2435 midgard_debug = debug_get_option_midgard_debug();
2436
2437 /* TODO: Bound against what? */
2438 compiler_context *ctx = rzalloc(NULL, compiler_context);
2439
2440 ctx->nir = nir;
2441 ctx->stage = nir->info.stage;
2442 ctx->is_blend = is_blend;
2443 ctx->alpha_ref = program->alpha_ref;
2444 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2445 ctx->quirks = midgard_get_quirks(gpu_id);
2446
2447 /* Start off with a safe cutoff, allowing usage of all 16 work
2448 * registers. Later, we'll promote uniform reads to uniform registers
2449 * if we determine it is beneficial to do so */
2450 ctx->uniform_cutoff = 8;
2451
2452 /* Initialize at a global (not block) level hash tables */
2453
2454 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2455 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2456
2457 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2458 * (so we don't accidentally duplicate the epilogue since mesa/st has
2459 * messed with our I/O quite a bit already) */
2460
2461 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2462
2463 if (ctx->stage == MESA_SHADER_VERTEX) {
2464 NIR_PASS_V(nir, nir_lower_viewport_transform);
2465 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2466 }
2467
2468 NIR_PASS_V(nir, nir_lower_var_copies);
2469 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2470 NIR_PASS_V(nir, nir_split_var_copies);
2471 NIR_PASS_V(nir, nir_lower_var_copies);
2472 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2473 NIR_PASS_V(nir, nir_lower_var_copies);
2474 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2475
2476 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2477 NIR_PASS_V(nir, nir_lower_ssbo);
2478 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2479
2480 /* Optimisation passes */
2481
2482 optimise_nir(nir, ctx->quirks);
2483
2484 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2485 nir_print_shader(nir, stdout);
2486 }
2487
2488 /* Assign sysvals and counts, now that we're sure
2489 * (post-optimisation) */
2490
2491 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2492 program->sysval_count = ctx->sysvals.sysval_count;
2493 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2494
2495 nir_foreach_function(func, nir) {
2496 if (!func->impl)
2497 continue;
2498
2499 list_inithead(&ctx->blocks);
2500 ctx->block_count = 0;
2501 ctx->func = func;
2502 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
2503
2504 emit_cf_list(ctx, &func->impl->body);
2505 free(ctx->already_emitted);
2506 break; /* TODO: Multi-function shaders */
2507 }
2508
2509 util_dynarray_init(compiled, NULL);
2510
2511 /* Per-block lowering before opts */
2512
2513 mir_foreach_block(ctx, _block) {
2514 midgard_block *block = (midgard_block *) _block;
2515 inline_alu_constants(ctx, block);
2516 midgard_opt_promote_fmov(ctx, block);
2517 embedded_to_inline_constant(ctx, block);
2518 }
2519 /* MIR-level optimizations */
2520
2521 bool progress = false;
2522
2523 do {
2524 progress = false;
2525
2526 mir_foreach_block(ctx, _block) {
2527 midgard_block *block = (midgard_block *) _block;
2528 progress |= midgard_opt_copy_prop(ctx, block);
2529 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2530 progress |= midgard_opt_combine_projection(ctx, block);
2531 progress |= midgard_opt_varying_projection(ctx, block);
2532 }
2533 } while (progress);
2534
2535 mir_foreach_block(ctx, _block) {
2536 midgard_block *block = (midgard_block *) _block;
2537 midgard_lower_derivatives(ctx, block);
2538 midgard_cull_dead_branch(ctx, block);
2539 }
2540
2541 if (ctx->stage == MESA_SHADER_FRAGMENT)
2542 mir_add_writeout_loops(ctx);
2543
2544 /* Analyze now that the code is known but before scheduling creates
2545 * pipeline registers which are harder to track */
2546 mir_analyze_helper_terminate(ctx);
2547 mir_analyze_helper_requirements(ctx);
2548
2549 /* Schedule! */
2550 midgard_schedule_program(ctx);
2551 mir_ra(ctx);
2552
2553 /* Now that all the bundles are scheduled and we can calculate block
2554 * sizes, emit actual branch instructions rather than placeholders */
2555
2556 int br_block_idx = 0;
2557
2558 mir_foreach_block(ctx, _block) {
2559 midgard_block *block = (midgard_block *) _block;
2560 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2561 for (int c = 0; c < bundle->instruction_count; ++c) {
2562 midgard_instruction *ins = bundle->instructions[c];
2563
2564 if (!midgard_is_branch_unit(ins->unit)) continue;
2565
2566 /* Parse some basic branch info */
2567 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2568 bool is_conditional = ins->branch.conditional;
2569 bool is_inverted = ins->branch.invert_conditional;
2570 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2571 bool is_writeout = ins->writeout;
2572
2573 /* Determine the block we're jumping to */
2574 int target_number = ins->branch.target_block;
2575
2576 /* Report the destination tag */
2577 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2578
2579 /* Count up the number of quadwords we're
2580 * jumping over = number of quadwords until
2581 * (br_block_idx, target_number) */
2582
2583 int quadword_offset = 0;
2584
2585 if (is_discard) {
2586 /* Ignored */
2587 } else if (target_number > br_block_idx) {
2588 /* Jump forward */
2589
2590 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2591 midgard_block *blk = mir_get_block(ctx, idx);
2592 assert(blk);
2593
2594 quadword_offset += blk->quadword_count;
2595 }
2596 } else {
2597 /* Jump backwards */
2598
2599 for (int idx = br_block_idx; idx >= target_number; --idx) {
2600 midgard_block *blk = mir_get_block(ctx, idx);
2601 assert(blk);
2602
2603 quadword_offset -= blk->quadword_count;
2604 }
2605 }
2606
2607 /* Unconditional extended branches (far jumps)
2608 * have issues, so we always use a conditional
2609 * branch, setting the condition to always for
2610 * unconditional. For compact unconditional
2611 * branches, cond isn't used so it doesn't
2612 * matter what we pick. */
2613
2614 midgard_condition cond =
2615 !is_conditional ? midgard_condition_always :
2616 is_inverted ? midgard_condition_false :
2617 midgard_condition_true;
2618
2619 midgard_jmp_writeout_op op =
2620 is_discard ? midgard_jmp_writeout_op_discard :
2621 is_writeout ? midgard_jmp_writeout_op_writeout :
2622 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2623 midgard_jmp_writeout_op_branch_cond;
2624
2625 if (!is_compact) {
2626 midgard_branch_extended branch =
2627 midgard_create_branch_extended(
2628 cond, op,
2629 dest_tag,
2630 quadword_offset);
2631
2632 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2633 } else if (is_conditional || is_discard) {
2634 midgard_branch_cond branch = {
2635 .op = op,
2636 .dest_tag = dest_tag,
2637 .offset = quadword_offset,
2638 .cond = cond
2639 };
2640
2641 assert(branch.offset == quadword_offset);
2642
2643 memcpy(&ins->br_compact, &branch, sizeof(branch));
2644 } else {
2645 assert(op == midgard_jmp_writeout_op_branch_uncond);
2646
2647 midgard_branch_uncond branch = {
2648 .op = op,
2649 .dest_tag = dest_tag,
2650 .offset = quadword_offset,
2651 .unknown = 1
2652 };
2653
2654 assert(branch.offset == quadword_offset);
2655
2656 memcpy(&ins->br_compact, &branch, sizeof(branch));
2657 }
2658 }
2659 }
2660
2661 ++br_block_idx;
2662 }
2663
2664 /* Emit flat binary from the instruction arrays. Iterate each block in
2665 * sequence. Save instruction boundaries such that lookahead tags can
2666 * be assigned easily */
2667
2668 /* Cache _all_ bundles in source order for lookahead across failed branches */
2669
2670 int bundle_count = 0;
2671 mir_foreach_block(ctx, _block) {
2672 midgard_block *block = (midgard_block *) _block;
2673 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2674 }
2675 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2676 int bundle_idx = 0;
2677 mir_foreach_block(ctx, _block) {
2678 midgard_block *block = (midgard_block *) _block;
2679 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2680 source_order_bundles[bundle_idx++] = bundle;
2681 }
2682 }
2683
2684 int current_bundle = 0;
2685
2686 /* Midgard prefetches instruction types, so during emission we
2687 * need to lookahead. Unless this is the last instruction, in
2688 * which we return 1. */
2689
2690 mir_foreach_block(ctx, _block) {
2691 midgard_block *block = (midgard_block *) _block;
2692 mir_foreach_bundle_in_block(block, bundle) {
2693 int lookahead = 1;
2694
2695 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2696 lookahead = source_order_bundles[current_bundle + 1]->tag;
2697
2698 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2699 ++current_bundle;
2700 }
2701
2702 /* TODO: Free deeper */
2703 //util_dynarray_fini(&block->instructions);
2704 }
2705
2706 free(source_order_bundles);
2707
2708 /* Report the very first tag executed */
2709 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2710
2711 /* Deal with off-by-one related to the fencepost problem */
2712 program->work_register_count = ctx->work_registers + 1;
2713 program->uniform_cutoff = ctx->uniform_cutoff;
2714
2715 program->blend_patch_offset = ctx->blend_constant_offset;
2716 program->tls_size = ctx->tls_size;
2717
2718 if (midgard_debug & MIDGARD_DBG_SHADERS)
2719 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2720
2721 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2722 unsigned nr_bundles = 0, nr_ins = 0;
2723
2724 /* Count instructions and bundles */
2725
2726 mir_foreach_block(ctx, _block) {
2727 midgard_block *block = (midgard_block *) _block;
2728 nr_bundles += util_dynarray_num_elements(
2729 &block->bundles, midgard_bundle);
2730
2731 mir_foreach_bundle_in_block(block, bun)
2732 nr_ins += bun->instruction_count;
2733 }
2734
2735 /* Calculate thread count. There are certain cutoffs by
2736 * register count for thread count */
2737
2738 unsigned nr_registers = program->work_register_count;
2739
2740 unsigned nr_threads =
2741 (nr_registers <= 4) ? 4 :
2742 (nr_registers <= 8) ? 2 :
2743 1;
2744
2745 /* Dump stats */
2746
2747 fprintf(stderr, "shader%d - %s shader: "
2748 "%u inst, %u bundles, %u quadwords, "
2749 "%u registers, %u threads, %u loops, "
2750 "%u:%u spills:fills\n",
2751 SHADER_DB_COUNT++,
2752 gl_shader_stage_name(ctx->stage),
2753 nr_ins, nr_bundles, ctx->quadword_count,
2754 nr_registers, nr_threads,
2755 ctx->loop_count,
2756 ctx->spills, ctx->fills);
2757 }
2758
2759 ralloc_free(ctx);
2760
2761 return 0;
2762 }