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pan/mdg: Handle 16-bit ld_vary
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 i.dest_type = T; \
121 } else { \
122 i.dest = ssa; \
123 i.dest_type = T; \
124 } \
125 return i; \
126 }
127
128 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
129 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
130
131 M_LOAD(ld_attr_32, nir_type_uint32);
132 M_LOAD(ld_vary_32, nir_type_uint32);
133 M_LOAD(ld_ubo_int4, nir_type_uint32);
134 M_LOAD(ld_int4, nir_type_uint32);
135 M_STORE(st_int4, nir_type_uint32);
136 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
137 M_STORE(st_vary_32, nir_type_uint32);
138 M_LOAD(ld_cubemap_coords, nir_type_uint32);
139 M_LOAD(ld_compute_id, nir_type_uint32);
140
141 static midgard_instruction
142 v_branch(bool conditional, bool invert)
143 {
144 midgard_instruction ins = {
145 .type = TAG_ALU_4,
146 .unit = ALU_ENAB_BRANCH,
147 .compact_branch = true,
148 .branch = {
149 .conditional = conditional,
150 .invert_conditional = invert
151 },
152 .dest = ~0,
153 .src = { ~0, ~0, ~0, ~0 },
154 };
155
156 return ins;
157 }
158
159 static midgard_branch_extended
160 midgard_create_branch_extended( midgard_condition cond,
161 midgard_jmp_writeout_op op,
162 unsigned dest_tag,
163 signed quadword_offset)
164 {
165 /* The condition code is actually a LUT describing a function to
166 * combine multiple condition codes. However, we only support a single
167 * condition code at the moment, so we just duplicate over a bunch of
168 * times. */
169
170 uint16_t duplicated_cond =
171 (cond << 14) |
172 (cond << 12) |
173 (cond << 10) |
174 (cond << 8) |
175 (cond << 6) |
176 (cond << 4) |
177 (cond << 2) |
178 (cond << 0);
179
180 midgard_branch_extended branch = {
181 .op = op,
182 .dest_tag = dest_tag,
183 .offset = quadword_offset,
184 .cond = duplicated_cond
185 };
186
187 return branch;
188 }
189
190 static void
191 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
192 {
193 ins->has_constants = true;
194 memcpy(&ins->constants, constants, 16);
195 }
196
197 static int
198 glsl_type_size(const struct glsl_type *type, bool bindless)
199 {
200 return glsl_count_attribute_slots(type, false);
201 }
202
203 /* Lower fdot2 to a vector multiplication followed by channel addition */
204 static void
205 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
206 {
207 if (alu->op != nir_op_fdot2)
208 return;
209
210 b->cursor = nir_before_instr(&alu->instr);
211
212 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
213 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
214
215 nir_ssa_def *product = nir_fmul(b, src0, src1);
216
217 nir_ssa_def *sum = nir_fadd(b,
218 nir_channel(b, product, 0),
219 nir_channel(b, product, 1));
220
221 /* Replace the fdot2 with this sum */
222 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
223 }
224
225 static bool
226 midgard_nir_lower_fdot2(nir_shader *shader)
227 {
228 bool progress = false;
229
230 nir_foreach_function(function, shader) {
231 if (!function->impl) continue;
232
233 nir_builder _b;
234 nir_builder *b = &_b;
235 nir_builder_init(b, function->impl);
236
237 nir_foreach_block(block, function->impl) {
238 nir_foreach_instr_safe(instr, block) {
239 if (instr->type != nir_instr_type_alu) continue;
240
241 nir_alu_instr *alu = nir_instr_as_alu(instr);
242 midgard_nir_lower_fdot2_body(b, alu);
243
244 progress |= true;
245 }
246 }
247
248 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
249
250 }
251
252 return progress;
253 }
254
255 /* Midgard can't write depth and stencil separately. It has to happen in a
256 * single store operation containing both. Let's add a panfrost specific
257 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
258 * one.
259 */
260 static bool
261 midgard_nir_lower_zs_store(nir_shader *nir)
262 {
263 if (nir->info.stage != MESA_SHADER_FRAGMENT)
264 return false;
265
266 nir_variable *z_var = NULL, *s_var = NULL;
267
268 nir_foreach_variable(var, &nir->outputs) {
269 if (var->data.location == FRAG_RESULT_DEPTH)
270 z_var = var;
271 else if (var->data.location == FRAG_RESULT_STENCIL)
272 s_var = var;
273 }
274
275 if (!z_var && !s_var)
276 return false;
277
278 bool progress = false;
279
280 nir_foreach_function(function, nir) {
281 if (!function->impl) continue;
282
283 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
284
285 nir_foreach_block(block, function->impl) {
286 nir_foreach_instr_safe(instr, block) {
287 if (instr->type != nir_instr_type_intrinsic)
288 continue;
289
290 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
291 if (intr->intrinsic != nir_intrinsic_store_output)
292 continue;
293
294 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
295 assert(!z_store);
296 z_store = intr;
297 last_store = intr;
298 }
299
300 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
301 assert(!s_store);
302 s_store = intr;
303 last_store = intr;
304 }
305 }
306 }
307
308 if (!z_store && !s_store) continue;
309
310 nir_builder b;
311 nir_builder_init(&b, function->impl);
312
313 b.cursor = nir_before_instr(&last_store->instr);
314
315 nir_ssa_def *zs_store_src;
316
317 if (z_store && s_store) {
318 nir_ssa_def *srcs[2] = {
319 nir_ssa_for_src(&b, z_store->src[0], 1),
320 nir_ssa_for_src(&b, s_store->src[0], 1),
321 };
322
323 zs_store_src = nir_vec(&b, srcs, 2);
324 } else {
325 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
326 }
327
328 nir_intrinsic_instr *zs_store;
329
330 zs_store = nir_intrinsic_instr_create(b.shader,
331 nir_intrinsic_store_zs_output_pan);
332 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
333 zs_store->num_components = z_store && s_store ? 2 : 1;
334 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
335
336 /* Replace the Z and S store by a ZS store */
337 nir_builder_instr_insert(&b, &zs_store->instr);
338
339 if (z_store)
340 nir_instr_remove(&z_store->instr);
341
342 if (s_store)
343 nir_instr_remove(&s_store->instr);
344
345 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
346 progress = true;
347 }
348
349 return progress;
350 }
351
352 /* Flushes undefined values to zero */
353
354 static void
355 optimise_nir(nir_shader *nir, unsigned quirks)
356 {
357 bool progress;
358 unsigned lower_flrp =
359 (nir->options->lower_flrp16 ? 16 : 0) |
360 (nir->options->lower_flrp32 ? 32 : 0) |
361 (nir->options->lower_flrp64 ? 64 : 0);
362
363 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
364 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
365
366 nir_lower_tex_options lower_tex_options = {
367 .lower_txs_lod = true,
368 .lower_txp = ~0,
369 .lower_tex_without_implicit_lod =
370 (quirks & MIDGARD_EXPLICIT_LOD),
371
372 /* TODO: we have native gradient.. */
373 .lower_txd = true,
374 };
375
376 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
377
378 /* Must lower fdot2 after tex is lowered */
379 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
380
381 /* T720 is broken. */
382
383 if (quirks & MIDGARD_BROKEN_LOD)
384 NIR_PASS_V(nir, midgard_nir_lod_errata);
385
386 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_early);
387
388 do {
389 progress = false;
390
391 NIR_PASS(progress, nir, nir_lower_var_copies);
392 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
393
394 NIR_PASS(progress, nir, nir_copy_prop);
395 NIR_PASS(progress, nir, nir_opt_remove_phis);
396 NIR_PASS(progress, nir, nir_opt_dce);
397 NIR_PASS(progress, nir, nir_opt_dead_cf);
398 NIR_PASS(progress, nir, nir_opt_cse);
399 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
400 NIR_PASS(progress, nir, nir_opt_algebraic);
401 NIR_PASS(progress, nir, nir_opt_constant_folding);
402
403 if (lower_flrp != 0) {
404 bool lower_flrp_progress = false;
405 NIR_PASS(lower_flrp_progress,
406 nir,
407 nir_lower_flrp,
408 lower_flrp,
409 false /* always_precise */,
410 nir->options->lower_ffma);
411 if (lower_flrp_progress) {
412 NIR_PASS(progress, nir,
413 nir_opt_constant_folding);
414 progress = true;
415 }
416
417 /* Nothing should rematerialize any flrps, so we only
418 * need to do this lowering once.
419 */
420 lower_flrp = 0;
421 }
422
423 NIR_PASS(progress, nir, nir_opt_undef);
424 NIR_PASS(progress, nir, nir_undef_to_zero);
425
426 NIR_PASS(progress, nir, nir_opt_loop_unroll,
427 nir_var_shader_in |
428 nir_var_shader_out |
429 nir_var_function_temp);
430
431 NIR_PASS(progress, nir, nir_opt_vectorize);
432 } while (progress);
433
434 /* Must be run at the end to prevent creation of fsin/fcos ops */
435 NIR_PASS(progress, nir, midgard_nir_scale_trig);
436
437 do {
438 progress = false;
439
440 NIR_PASS(progress, nir, nir_opt_dce);
441 NIR_PASS(progress, nir, nir_opt_algebraic);
442 NIR_PASS(progress, nir, nir_opt_constant_folding);
443 NIR_PASS(progress, nir, nir_copy_prop);
444 } while (progress);
445
446 NIR_PASS(progress, nir, nir_opt_algebraic_late);
447 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
448
449 /* We implement booleans as 32-bit 0/~0 */
450 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
451
452 /* Now that booleans are lowered, we can run out late opts */
453 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
454 NIR_PASS(progress, nir, midgard_nir_cancel_inot);
455
456 NIR_PASS(progress, nir, nir_copy_prop);
457 NIR_PASS(progress, nir, nir_opt_dce);
458
459 /* Take us out of SSA */
460 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
461 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
462
463 /* We are a vector architecture; write combine where possible */
464 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
465 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
466
467 NIR_PASS(progress, nir, nir_opt_dce);
468 }
469
470 /* Do not actually emit a load; instead, cache the constant for inlining */
471
472 static void
473 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
474 {
475 nir_ssa_def def = instr->def;
476
477 midgard_constants *consts = rzalloc(NULL, midgard_constants);
478
479 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
480
481 #define RAW_CONST_COPY(bits) \
482 nir_const_value_to_array(consts->u##bits, instr->value, \
483 instr->def.num_components, u##bits)
484
485 switch (instr->def.bit_size) {
486 case 64:
487 RAW_CONST_COPY(64);
488 break;
489 case 32:
490 RAW_CONST_COPY(32);
491 break;
492 case 16:
493 RAW_CONST_COPY(16);
494 break;
495 case 8:
496 RAW_CONST_COPY(8);
497 break;
498 default:
499 unreachable("Invalid bit_size for load_const instruction\n");
500 }
501
502 /* Shifted for SSA, +1 for off-by-one */
503 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
504 }
505
506 /* Normally constants are embedded implicitly, but for I/O and such we have to
507 * explicitly emit a move with the constant source */
508
509 static void
510 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
511 {
512 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
513
514 if (constant_value) {
515 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
516 attach_constants(ctx, &ins, constant_value, node + 1);
517 emit_mir_instruction(ctx, ins);
518 }
519 }
520
521 static bool
522 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
523 {
524 unsigned comp = src->swizzle[0];
525
526 for (unsigned c = 1; c < nr_components; ++c) {
527 if (src->swizzle[c] != comp)
528 return true;
529 }
530
531 return false;
532 }
533
534 #define ALU_CASE(nir, _op) \
535 case nir_op_##nir: \
536 op = midgard_alu_op_##_op; \
537 assert(src_bitsize == dst_bitsize); \
538 break;
539
540 #define ALU_CHECK_CMP(sext) \
541 assert(src_bitsize == 16 || src_bitsize == 32); \
542 assert(dst_bitsize == 16 || dst_bitsize == 32); \
543
544 #define ALU_CASE_BCAST(nir, _op, count) \
545 case nir_op_##nir: \
546 op = midgard_alu_op_##_op; \
547 broadcast_swizzle = count; \
548 ALU_CHECK_CMP(true); \
549 break;
550
551 #define ALU_CASE_CMP(nir, _op, sext) \
552 case nir_op_##nir: \
553 op = midgard_alu_op_##_op; \
554 ALU_CHECK_CMP(sext); \
555 break;
556
557 /* Analyze the sizes of the dest and inputs to determine reg mode. */
558
559 static midgard_reg_mode
560 reg_mode_for_nir(nir_alu_instr *instr)
561 {
562 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
563 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
564 unsigned max_bitsize = MAX2(src_bitsize, dst_bitsize);
565
566 /* We don't have fp16 LUTs, so we'll want to emit code like:
567 *
568 * vlut.fsinr hr0, hr0
569 *
570 * where both input and output are 16-bit but the operation is carried
571 * out in 32-bit
572 */
573
574 switch (instr->op) {
575 case nir_op_fsqrt:
576 case nir_op_frcp:
577 case nir_op_frsq:
578 case nir_op_fsin:
579 case nir_op_fcos:
580 case nir_op_fexp2:
581 case nir_op_flog2:
582 max_bitsize = MAX2(max_bitsize, 32);
583 break;
584
585 /* These get lowered to moves */
586 case nir_op_pack_32_4x8:
587 max_bitsize = 8;
588 break;
589 case nir_op_pack_32_2x16:
590 max_bitsize = 16;
591 break;
592 default:
593 break;
594 }
595
596
597 switch (max_bitsize) {
598 /* Use 16 pipe for 8 since we don't support vec16 yet */
599 case 8:
600 case 16:
601 return midgard_reg_mode_16;
602 case 32:
603 return midgard_reg_mode_32;
604 case 64:
605 return midgard_reg_mode_64;
606 default:
607 unreachable("Invalid bit size");
608 }
609 }
610
611 /* Compare mir_lower_invert */
612 static bool
613 nir_accepts_inot(nir_op op, unsigned src)
614 {
615 switch (op) {
616 case nir_op_ior:
617 case nir_op_iand: /* TODO: b2f16 */
618 case nir_op_ixor:
619 return true;
620 case nir_op_b32csel:
621 /* Only the condition */
622 return (src == 0);
623 default:
624 return false;
625 }
626 }
627
628 static bool
629 mir_accept_dest_mod(compiler_context *ctx, nir_dest **dest, nir_op op)
630 {
631 if (pan_has_dest_mod(dest, op)) {
632 assert((*dest)->is_ssa);
633 BITSET_SET(ctx->already_emitted, (*dest)->ssa.index);
634 return true;
635 }
636
637 return false;
638 }
639
640 static void
641 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool *not, bool is_int, unsigned bcast_count)
642 {
643 nir_alu_src src = instr->src[i];
644
645 if (!is_int) {
646 if (pan_has_source_mod(&src, nir_op_fneg))
647 *neg = !(*neg);
648
649 if (pan_has_source_mod(&src, nir_op_fabs))
650 *abs = true;
651 }
652
653 if (nir_accepts_inot(instr->op, i) && pan_has_source_mod(&src, nir_op_inot))
654 *not = true;
655
656 unsigned bits = nir_src_bit_size(src.src);
657
658 ins->src[to] = nir_src_index(NULL, &src.src);
659 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
660
661 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
662 ins->swizzle[to][c] = src.swizzle[
663 (!bcast_count || c < bcast_count) ? c :
664 (bcast_count - 1)];
665 }
666 }
667
668 /* Midgard features both fcsel and icsel, depending on whether you want int or
669 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
670 * we should emit an int or float csel depending on what modifiers could be
671 * placed. In the absense of modifiers, this is probably arbitrary. */
672
673 static bool
674 mir_is_bcsel_float(nir_alu_instr *instr)
675 {
676 nir_op intmods[] = {
677 nir_op_i2i8, nir_op_i2i16,
678 nir_op_i2i32, nir_op_i2i64
679 };
680
681 nir_op floatmods[] = {
682 nir_op_fabs, nir_op_fneg,
683 nir_op_f2f16, nir_op_f2f32,
684 nir_op_f2f64
685 };
686
687 nir_op floatdestmods[] = {
688 nir_op_fsat, nir_op_fsat_signed, nir_op_fclamp_pos,
689 nir_op_f2f16, nir_op_f2f32
690 };
691
692 signed score = 0;
693
694 for (unsigned i = 1; i < 3; ++i) {
695 nir_alu_src s = instr->src[i];
696 for (unsigned q = 0; q < ARRAY_SIZE(intmods); ++q) {
697 if (pan_has_source_mod(&s, intmods[q]))
698 score--;
699 }
700 }
701
702 for (unsigned i = 1; i < 3; ++i) {
703 nir_alu_src s = instr->src[i];
704 for (unsigned q = 0; q < ARRAY_SIZE(floatmods); ++q) {
705 if (pan_has_source_mod(&s, floatmods[q]))
706 score++;
707 }
708 }
709
710 for (unsigned q = 0; q < ARRAY_SIZE(floatdestmods); ++q) {
711 nir_dest *dest = &instr->dest.dest;
712 if (pan_has_dest_mod(&dest, floatdestmods[q]))
713 score++;
714 }
715
716 return (score > 0);
717 }
718
719 static void
720 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
721 {
722 nir_dest *dest = &instr->dest.dest;
723
724 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index))
725 return;
726
727 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
728 * is handled elsewhere */
729
730 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
731 midgard_emit_derivatives(ctx, instr);
732 return;
733 }
734
735 bool is_ssa = dest->is_ssa;
736
737 unsigned nr_components = nir_dest_num_components(*dest);
738 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
739 unsigned op = 0;
740
741 /* Number of components valid to check for the instruction (the rest
742 * will be forced to the last), or 0 to use as-is. Relevant as
743 * ball-type instructions have a channel count in NIR but are all vec4
744 * in Midgard */
745
746 unsigned broadcast_swizzle = 0;
747
748 /* What register mode should we operate in? */
749 midgard_reg_mode reg_mode =
750 reg_mode_for_nir(instr);
751
752 /* Should we swap arguments? */
753 bool flip_src12 = false;
754
755 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
756 unsigned dst_bitsize = nir_dest_bit_size(*dest);
757
758 switch (instr->op) {
759 ALU_CASE(fadd, fadd);
760 ALU_CASE(fmul, fmul);
761 ALU_CASE(fmin, fmin);
762 ALU_CASE(fmax, fmax);
763 ALU_CASE(imin, imin);
764 ALU_CASE(imax, imax);
765 ALU_CASE(umin, umin);
766 ALU_CASE(umax, umax);
767 ALU_CASE(ffloor, ffloor);
768 ALU_CASE(fround_even, froundeven);
769 ALU_CASE(ftrunc, ftrunc);
770 ALU_CASE(fceil, fceil);
771 ALU_CASE(fdot3, fdot3);
772 ALU_CASE(fdot4, fdot4);
773 ALU_CASE(iadd, iadd);
774 ALU_CASE(isub, isub);
775 ALU_CASE(imul, imul);
776
777 /* Zero shoved as second-arg */
778 ALU_CASE(iabs, iabsdiff);
779
780 ALU_CASE(mov, imov);
781
782 ALU_CASE_CMP(feq32, feq, false);
783 ALU_CASE_CMP(fne32, fne, false);
784 ALU_CASE_CMP(flt32, flt, false);
785 ALU_CASE_CMP(ieq32, ieq, true);
786 ALU_CASE_CMP(ine32, ine, true);
787 ALU_CASE_CMP(ilt32, ilt, true);
788 ALU_CASE_CMP(ult32, ult, false);
789
790 /* We don't have a native b2f32 instruction. Instead, like many
791 * GPUs, we exploit booleans as 0/~0 for false/true, and
792 * correspondingly AND
793 * by 1.0 to do the type conversion. For the moment, prime us
794 * to emit:
795 *
796 * iand [whatever], #0
797 *
798 * At the end of emit_alu (as MIR), we'll fix-up the constant
799 */
800
801 ALU_CASE_CMP(b2f32, iand, true);
802 ALU_CASE_CMP(b2f16, iand, true);
803 ALU_CASE_CMP(b2i32, iand, true);
804
805 /* Likewise, we don't have a dedicated f2b32 instruction, but
806 * we can do a "not equal to 0.0" test. */
807
808 ALU_CASE_CMP(f2b32, fne, false);
809 ALU_CASE_CMP(i2b32, ine, true);
810
811 ALU_CASE(frcp, frcp);
812 ALU_CASE(frsq, frsqrt);
813 ALU_CASE(fsqrt, fsqrt);
814 ALU_CASE(fexp2, fexp2);
815 ALU_CASE(flog2, flog2);
816
817 ALU_CASE(f2i64, f2i_rtz);
818 ALU_CASE(f2u64, f2u_rtz);
819 ALU_CASE(i2f64, i2f_rtz);
820 ALU_CASE(u2f64, u2f_rtz);
821
822 ALU_CASE(f2i32, f2i_rtz);
823 ALU_CASE(f2u32, f2u_rtz);
824 ALU_CASE(i2f32, i2f_rtz);
825 ALU_CASE(u2f32, u2f_rtz);
826
827 ALU_CASE(f2i16, f2i_rtz);
828 ALU_CASE(f2u16, f2u_rtz);
829 ALU_CASE(i2f16, i2f_rtz);
830 ALU_CASE(u2f16, u2f_rtz);
831
832 ALU_CASE(fsin, fsin);
833 ALU_CASE(fcos, fcos);
834
835 /* We'll get 0 in the second arg, so:
836 * ~a = ~(a | 0) = nor(a, 0) */
837 ALU_CASE(inot, inor);
838 ALU_CASE(iand, iand);
839 ALU_CASE(ior, ior);
840 ALU_CASE(ixor, ixor);
841 ALU_CASE(ishl, ishl);
842 ALU_CASE(ishr, iasr);
843 ALU_CASE(ushr, ilsr);
844
845 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
846 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
847 ALU_CASE_CMP(b32all_fequal4, fball_eq, true);
848
849 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
850 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
851 ALU_CASE_CMP(b32any_fnequal4, fbany_neq, true);
852
853 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
854 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
855 ALU_CASE_CMP(b32all_iequal4, iball_eq, true);
856
857 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
858 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
859 ALU_CASE_CMP(b32any_inequal4, ibany_neq, true);
860
861 /* Source mods will be shoved in later */
862 ALU_CASE(fabs, fmov);
863 ALU_CASE(fneg, fmov);
864 ALU_CASE(fsat, fmov);
865 ALU_CASE(fsat_signed, fmov);
866 ALU_CASE(fclamp_pos, fmov);
867
868 /* For size conversion, we use a move. Ideally though we would squash
869 * these ops together; maybe that has to happen after in NIR as part of
870 * propagation...? An earlier algebraic pass ensured we step down by
871 * only / exactly one size. If stepping down, we use a dest override to
872 * reduce the size; if stepping up, we use a larger-sized move with a
873 * half source and a sign/zero-extension modifier */
874
875 case nir_op_i2i8:
876 case nir_op_i2i16:
877 case nir_op_i2i32:
878 case nir_op_i2i64:
879 case nir_op_u2u8:
880 case nir_op_u2u16:
881 case nir_op_u2u32:
882 case nir_op_u2u64:
883 case nir_op_f2f16:
884 case nir_op_f2f32:
885 case nir_op_f2f64: {
886 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
887 instr->op == nir_op_f2f64)
888 op = midgard_alu_op_fmov;
889 else
890 op = midgard_alu_op_imov;
891
892 break;
893 }
894
895 /* For greater-or-equal, we lower to less-or-equal and flip the
896 * arguments */
897
898 case nir_op_fge:
899 case nir_op_fge32:
900 case nir_op_ige32:
901 case nir_op_uge32: {
902 op =
903 instr->op == nir_op_fge ? midgard_alu_op_fle :
904 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
905 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
906 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
907 0;
908
909 flip_src12 = true;
910 ALU_CHECK_CMP(false);
911 break;
912 }
913
914 case nir_op_b32csel: {
915 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
916 bool is_float = mir_is_bcsel_float(instr);
917 op = is_float ?
918 (mixed ? midgard_alu_op_fcsel_v : midgard_alu_op_fcsel) :
919 (mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel);
920
921 break;
922 }
923
924 case nir_op_unpack_32_2x16:
925 case nir_op_unpack_32_4x8:
926 case nir_op_pack_32_2x16:
927 case nir_op_pack_32_4x8: {
928 op = midgard_alu_op_imov;
929 break;
930 }
931
932 default:
933 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
934 assert(0);
935 return;
936 }
937
938 /* Promote imov to fmov if it might help inline a constant */
939 if (op == midgard_alu_op_imov && nir_src_is_const(instr->src[0].src)
940 && nir_src_bit_size(instr->src[0].src) == 32
941 && nir_is_same_comp_swizzle(instr->src[0].swizzle,
942 nir_src_num_components(instr->src[0].src))) {
943 op = midgard_alu_op_fmov;
944 }
945
946 /* Midgard can perform certain modifiers on output of an ALU op */
947
948 unsigned outmod = 0;
949 bool is_int = midgard_is_integer_op(op);
950
951 if (midgard_is_integer_out_op(op)) {
952 outmod = midgard_outmod_int_wrap;
953 } else if (instr->op == nir_op_fsat) {
954 outmod = midgard_outmod_sat;
955 } else if (instr->op == nir_op_fsat_signed) {
956 outmod = midgard_outmod_sat_signed;
957 } else if (instr->op == nir_op_fclamp_pos) {
958 outmod = midgard_outmod_pos;
959 }
960
961 /* Fetch unit, quirks, etc information */
962 unsigned opcode_props = alu_opcode_props[op].props;
963 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
964
965 /* Look for floating point mods. We have the mods fsat, fsat_signed,
966 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
967 *
968 * fsat_signed(fpos(x)) = fsat(x)
969 * fsat_signed(fsat(x)) = fsat(x)
970 * fpos(fsat_signed(x)) = fsat(x)
971 * fpos(fsat(x)) = fsat(x)
972 * fsat(fsat_signed(x)) = fsat(x)
973 * fsat(fpos(x)) = fsat(x)
974 *
975 * So by cases any composition of output modifiers is equivalent to
976 * fsat alone.
977 */
978
979 if (!is_int && !(opcode_props & OP_TYPE_CONVERT)) {
980 bool fpos = mir_accept_dest_mod(ctx, &dest, nir_op_fclamp_pos);
981 bool fsat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat);
982 bool ssat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat_signed);
983 bool prior = (outmod != midgard_outmod_none);
984 int count = (int) prior + (int) fpos + (int) ssat + (int) fsat;
985
986 outmod = ((count > 1) || fsat) ? midgard_outmod_sat :
987 fpos ? midgard_outmod_pos :
988 ssat ? midgard_outmod_sat_signed :
989 outmod;
990 }
991
992 midgard_instruction ins = {
993 .type = TAG_ALU_4,
994 .dest = nir_dest_index(dest),
995 .dest_type = nir_op_infos[instr->op].output_type
996 | nir_dest_bit_size(*dest),
997 };
998
999 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
1000 ins.src[i] = ~0;
1001
1002 if (quirk_flipped_r24) {
1003 ins.src[0] = ~0;
1004 mir_copy_src(&ins, instr, 0, 1, &ins.src_abs[1], &ins.src_neg[1], &ins.src_invert[1], is_int, broadcast_swizzle);
1005 } else {
1006 for (unsigned i = 0; i < nr_inputs; ++i) {
1007 unsigned to = i;
1008
1009 if (instr->op == nir_op_b32csel) {
1010 /* The condition is the first argument; move
1011 * the other arguments up one to be a binary
1012 * instruction for Midgard with the condition
1013 * last */
1014
1015 if (i == 0)
1016 to = 2;
1017 else if (flip_src12)
1018 to = 2 - i;
1019 else
1020 to = i - 1;
1021 } else if (flip_src12) {
1022 to = 1 - to;
1023 }
1024
1025 mir_copy_src(&ins, instr, i, to, &ins.src_abs[to], &ins.src_neg[to], &ins.src_invert[to], is_int, broadcast_swizzle);
1026
1027 /* (!c) ? a : b = c ? b : a */
1028 if (instr->op == nir_op_b32csel && ins.src_invert[2]) {
1029 ins.src_invert[2] = false;
1030 flip_src12 ^= true;
1031 }
1032 }
1033 }
1034
1035 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
1036 /* Lowered to move */
1037 if (instr->op == nir_op_fneg)
1038 ins.src_neg[1] ^= true;
1039
1040 if (instr->op == nir_op_fabs)
1041 ins.src_abs[1] = true;
1042 }
1043
1044 ins.mask = mask_of(nr_components);
1045
1046 midgard_vector_alu alu = {
1047 .op = op,
1048 .reg_mode = reg_mode,
1049 .outmod = outmod,
1050 };
1051
1052 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1053 * components that don't exist. Note modifier => SSA => !reg => no
1054 * writemask, so we don't have to worry about writemasks here.*/
1055
1056 if (!is_ssa)
1057 ins.mask &= instr->dest.write_mask;
1058
1059 ins.alu = alu;
1060
1061 /* Late fixup for emulated instructions */
1062
1063 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1064 /* Presently, our second argument is an inline #0 constant.
1065 * Switch over to an embedded 1.0 constant (that can't fit
1066 * inline, since we're 32-bit, not 16-bit like the inline
1067 * constants) */
1068
1069 ins.has_inline_constant = false;
1070 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1071 ins.src_types[1] = nir_type_float32;
1072 ins.has_constants = true;
1073
1074 if (instr->op == nir_op_b2f32)
1075 ins.constants.f32[0] = 1.0f;
1076 else
1077 ins.constants.i32[0] = 1;
1078
1079 for (unsigned c = 0; c < 16; ++c)
1080 ins.swizzle[1][c] = 0;
1081 } else if (instr->op == nir_op_b2f16) {
1082 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1083 ins.src_types[1] = nir_type_float16;
1084 ins.has_constants = true;
1085 ins.constants.i16[0] = _mesa_float_to_half(1.0);
1086
1087 for (unsigned c = 0; c < 16; ++c)
1088 ins.swizzle[1][c] = 0;
1089 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1090 /* Lots of instructions need a 0 plonked in */
1091 ins.has_inline_constant = false;
1092 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1093 ins.src_types[1] = nir_type_uint32;
1094 ins.has_constants = true;
1095 ins.constants.u32[0] = 0;
1096
1097 for (unsigned c = 0; c < 16; ++c)
1098 ins.swizzle[1][c] = 0;
1099 } else if (instr->op == nir_op_pack_32_2x16) {
1100 ins.dest_type = nir_type_uint16;
1101 ins.mask = mask_of(nr_components * 2);
1102 ins.is_pack = true;
1103 } else if (instr->op == nir_op_pack_32_4x8) {
1104 ins.dest_type = nir_type_uint8;
1105 ins.mask = mask_of(nr_components * 4);
1106 ins.is_pack = true;
1107 } else if (instr->op == nir_op_unpack_32_2x16) {
1108 ins.dest_type = nir_type_uint32;
1109 ins.mask = mask_of(nr_components >> 1);
1110 ins.is_pack = true;
1111 } else if (instr->op == nir_op_unpack_32_4x8) {
1112 ins.dest_type = nir_type_uint32;
1113 ins.mask = mask_of(nr_components >> 2);
1114 ins.is_pack = true;
1115 }
1116
1117 /* Arrange for creation of iandnot/iornot */
1118 if (ins.src_invert[0] && !ins.src_invert[1]) {
1119 mir_flip(&ins);
1120 ins.src_invert[0] = false;
1121 ins.src_invert[1] = true;
1122 }
1123
1124 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1125 /* To avoid duplicating the lookup tables (probably), true LUT
1126 * instructions can only operate as if they were scalars. Lower
1127 * them here by changing the component. */
1128
1129 unsigned orig_mask = ins.mask;
1130
1131 unsigned swizzle_back[MIR_VEC_COMPONENTS];
1132 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
1133
1134 for (int i = 0; i < nr_components; ++i) {
1135 /* Mask the associated component, dropping the
1136 * instruction if needed */
1137
1138 ins.mask = 1 << i;
1139 ins.mask &= orig_mask;
1140
1141 if (!ins.mask)
1142 continue;
1143
1144 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1145 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1146
1147 emit_mir_instruction(ctx, ins);
1148 }
1149 } else {
1150 emit_mir_instruction(ctx, ins);
1151 }
1152 }
1153
1154 #undef ALU_CASE
1155
1156 static void
1157 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1158 {
1159 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1160 unsigned nir_mask = 0;
1161 unsigned dsize = 0;
1162
1163 if (is_read) {
1164 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1165 dsize = nir_dest_bit_size(intr->dest);
1166 } else {
1167 nir_mask = nir_intrinsic_write_mask(intr);
1168 dsize = 32;
1169 }
1170
1171 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1172 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1173 mir_set_bytemask(ins, bytemask);
1174 ins->dest_type = nir_type_uint | dsize;
1175 }
1176
1177 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1178 * optimized) versions of UBO #0 */
1179
1180 static midgard_instruction *
1181 emit_ubo_read(
1182 compiler_context *ctx,
1183 nir_instr *instr,
1184 unsigned dest,
1185 unsigned offset,
1186 nir_src *indirect_offset,
1187 unsigned indirect_shift,
1188 unsigned index)
1189 {
1190 /* TODO: half-floats */
1191
1192 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1193 ins.constants.u32[0] = offset;
1194
1195 if (instr->type == nir_instr_type_intrinsic)
1196 mir_set_intr_mask(instr, &ins, true);
1197
1198 if (indirect_offset) {
1199 ins.src[2] = nir_src_index(ctx, indirect_offset);
1200 ins.src_types[2] = nir_type_uint32;
1201 ins.load_store.arg_2 = (indirect_shift << 5);
1202 } else {
1203 ins.load_store.arg_2 = 0x1E;
1204 }
1205
1206 ins.load_store.arg_1 = index;
1207
1208 return emit_mir_instruction(ctx, ins);
1209 }
1210
1211 /* Globals are like UBOs if you squint. And shared memory is like globals if
1212 * you squint even harder */
1213
1214 static void
1215 emit_global(
1216 compiler_context *ctx,
1217 nir_instr *instr,
1218 bool is_read,
1219 unsigned srcdest,
1220 nir_src *offset,
1221 bool is_shared)
1222 {
1223 /* TODO: types */
1224
1225 midgard_instruction ins;
1226
1227 if (is_read)
1228 ins = m_ld_int4(srcdest, 0);
1229 else
1230 ins = m_st_int4(srcdest, 0);
1231
1232 mir_set_offset(ctx, &ins, offset, is_shared);
1233 mir_set_intr_mask(instr, &ins, is_read);
1234
1235 emit_mir_instruction(ctx, ins);
1236 }
1237
1238 static void
1239 emit_varying_read(
1240 compiler_context *ctx,
1241 unsigned dest, unsigned offset,
1242 unsigned nr_comp, unsigned component,
1243 nir_src *indirect_offset, nir_alu_type type, bool flat)
1244 {
1245 /* XXX: Half-floats? */
1246 /* TODO: swizzle, mask */
1247
1248 midgard_instruction ins = m_ld_vary_32(dest, offset);
1249 ins.mask = mask_of(nr_comp);
1250
1251 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1252 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1253
1254 midgard_varying_parameter p = {
1255 .is_varying = 1,
1256 .interpolation = midgard_interp_default,
1257 .flat = flat,
1258 };
1259
1260 unsigned u;
1261 memcpy(&u, &p, sizeof(p));
1262 ins.load_store.varying_parameters = u;
1263
1264 if (indirect_offset) {
1265 ins.src[2] = nir_src_index(ctx, indirect_offset);
1266 ins.src_types[2] = nir_type_uint32;
1267 } else
1268 ins.load_store.arg_2 = 0x1E;
1269
1270 ins.load_store.arg_1 = 0x9E;
1271
1272 /* Use the type appropriate load */
1273 switch (type) {
1274 case nir_type_uint32:
1275 case nir_type_bool32:
1276 ins.load_store.op = midgard_op_ld_vary_32u;
1277 break;
1278 case nir_type_int32:
1279 ins.load_store.op = midgard_op_ld_vary_32i;
1280 break;
1281 case nir_type_float32:
1282 ins.load_store.op = midgard_op_ld_vary_32;
1283 break;
1284 case nir_type_float16:
1285 ins.load_store.op = midgard_op_ld_vary_16;
1286 break;
1287 default:
1288 unreachable("Attempted to load unknown type");
1289 break;
1290 }
1291
1292 emit_mir_instruction(ctx, ins);
1293 }
1294
1295 static void
1296 emit_attr_read(
1297 compiler_context *ctx,
1298 unsigned dest, unsigned offset,
1299 unsigned nr_comp, nir_alu_type t)
1300 {
1301 midgard_instruction ins = m_ld_attr_32(dest, offset);
1302 ins.load_store.arg_1 = 0x1E;
1303 ins.load_store.arg_2 = 0x1E;
1304 ins.mask = mask_of(nr_comp);
1305
1306 /* Use the type appropriate load */
1307 switch (t) {
1308 case nir_type_uint:
1309 case nir_type_bool:
1310 ins.load_store.op = midgard_op_ld_attr_32u;
1311 break;
1312 case nir_type_int:
1313 ins.load_store.op = midgard_op_ld_attr_32i;
1314 break;
1315 case nir_type_float:
1316 ins.load_store.op = midgard_op_ld_attr_32;
1317 break;
1318 default:
1319 unreachable("Attempted to load unknown type");
1320 break;
1321 }
1322
1323 emit_mir_instruction(ctx, ins);
1324 }
1325
1326 static void
1327 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1328 unsigned nr_components, unsigned offset)
1329 {
1330 nir_dest nir_dest;
1331
1332 /* Figure out which uniform this is */
1333 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1334 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1335
1336 unsigned dest = nir_dest_index(&nir_dest);
1337
1338 /* Sysvals are prefix uniforms */
1339 unsigned uniform = ((uintptr_t) val) - 1;
1340
1341 /* Emit the read itself -- this is never indirect */
1342 midgard_instruction *ins =
1343 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1344
1345 ins->mask = mask_of(nr_components);
1346 }
1347
1348 static unsigned
1349 compute_builtin_arg(nir_op op)
1350 {
1351 switch (op) {
1352 case nir_intrinsic_load_work_group_id:
1353 return 0x14;
1354 case nir_intrinsic_load_local_invocation_id:
1355 return 0x10;
1356 default:
1357 unreachable("Invalid compute paramater loaded");
1358 }
1359 }
1360
1361 static void
1362 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1363 {
1364 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1365
1366 midgard_instruction *br = ctx->writeout_branch[rt];
1367
1368 assert(!br);
1369
1370 emit_explicit_constant(ctx, src, src);
1371
1372 struct midgard_instruction ins =
1373 v_branch(false, false);
1374
1375 ins.writeout = true;
1376
1377 /* Add dependencies */
1378 ins.src[0] = src;
1379 ins.src_types[0] = nir_type_uint32;
1380 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1381 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1382
1383 /* Emit the branch */
1384 br = emit_mir_instruction(ctx, ins);
1385 schedule_barrier(ctx);
1386 ctx->writeout_branch[rt] = br;
1387
1388 /* Push our current location = current block count - 1 = where we'll
1389 * jump to. Maybe a bit too clever for my own good */
1390
1391 br->branch.target_block = ctx->block_count - 1;
1392 }
1393
1394 static void
1395 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1396 {
1397 unsigned reg = nir_dest_index(&instr->dest);
1398 midgard_instruction ins = m_ld_compute_id(reg, 0);
1399 ins.mask = mask_of(3);
1400 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1401 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1402 emit_mir_instruction(ctx, ins);
1403 }
1404
1405 static unsigned
1406 vertex_builtin_arg(nir_op op)
1407 {
1408 switch (op) {
1409 case nir_intrinsic_load_vertex_id:
1410 return PAN_VERTEX_ID;
1411 case nir_intrinsic_load_instance_id:
1412 return PAN_INSTANCE_ID;
1413 default:
1414 unreachable("Invalid vertex builtin");
1415 }
1416 }
1417
1418 static void
1419 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1420 {
1421 unsigned reg = nir_dest_index(&instr->dest);
1422 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1423 }
1424
1425 static void
1426 emit_control_barrier(compiler_context *ctx)
1427 {
1428 midgard_instruction ins = {
1429 .type = TAG_TEXTURE_4,
1430 .dest = ~0,
1431 .src = { ~0, ~0, ~0, ~0 },
1432 .texture = {
1433 .op = TEXTURE_OP_BARRIER,
1434
1435 /* TODO: optimize */
1436 .barrier_buffer = 1,
1437 .barrier_shared = 1
1438 }
1439 };
1440
1441 emit_mir_instruction(ctx, ins);
1442 }
1443
1444 static const nir_variable *
1445 search_var(struct exec_list *vars, unsigned driver_loc)
1446 {
1447 nir_foreach_variable(var, vars) {
1448 if (var->data.driver_location == driver_loc)
1449 return var;
1450 }
1451
1452 return NULL;
1453 }
1454
1455 static unsigned
1456 mir_get_branch_cond(nir_src *src, bool *invert)
1457 {
1458 /* Wrap it. No swizzle since it's a scalar */
1459
1460 nir_alu_src alu = {
1461 .src = *src
1462 };
1463
1464 *invert = pan_has_source_mod(&alu, nir_op_inot);
1465 return nir_src_index(NULL, &alu.src);
1466 }
1467
1468 static void
1469 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1470 {
1471 unsigned offset = 0, reg;
1472
1473 switch (instr->intrinsic) {
1474 case nir_intrinsic_discard_if:
1475 case nir_intrinsic_discard: {
1476 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1477 struct midgard_instruction discard = v_branch(conditional, false);
1478 discard.branch.target_type = TARGET_DISCARD;
1479
1480 if (conditional) {
1481 discard.src[0] = mir_get_branch_cond(&instr->src[0],
1482 &discard.branch.invert_conditional);
1483 discard.src_types[0] = nir_type_uint32;
1484 }
1485
1486 emit_mir_instruction(ctx, discard);
1487 schedule_barrier(ctx);
1488
1489 break;
1490 }
1491
1492 case nir_intrinsic_load_uniform:
1493 case nir_intrinsic_load_ubo:
1494 case nir_intrinsic_load_global:
1495 case nir_intrinsic_load_shared:
1496 case nir_intrinsic_load_input:
1497 case nir_intrinsic_load_interpolated_input: {
1498 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1499 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1500 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1501 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1502 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1503 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1504
1505 /* Get the base type of the intrinsic */
1506 /* TODO: Infer type? Does it matter? */
1507 nir_alu_type t =
1508 (is_ubo || is_global || is_shared) ? nir_type_uint :
1509 (is_interp) ? nir_type_float :
1510 nir_intrinsic_type(instr);
1511
1512 t = nir_alu_type_get_base_type(t);
1513
1514 if (!(is_ubo || is_global)) {
1515 offset = nir_intrinsic_base(instr);
1516 }
1517
1518 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1519
1520 nir_src *src_offset = nir_get_io_offset_src(instr);
1521
1522 bool direct = nir_src_is_const(*src_offset);
1523 nir_src *indirect_offset = direct ? NULL : src_offset;
1524
1525 if (direct)
1526 offset += nir_src_as_uint(*src_offset);
1527
1528 /* We may need to apply a fractional offset */
1529 int component = (is_flat || is_interp) ?
1530 nir_intrinsic_component(instr) : 0;
1531 reg = nir_dest_index(&instr->dest);
1532
1533 if (is_uniform && !ctx->is_blend) {
1534 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1535 } else if (is_ubo) {
1536 nir_src index = instr->src[0];
1537
1538 /* TODO: Is indirect block number possible? */
1539 assert(nir_src_is_const(index));
1540
1541 uint32_t uindex = nir_src_as_uint(index) + 1;
1542 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1543 } else if (is_global || is_shared) {
1544 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1545 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1546 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t | nir_dest_bit_size(instr->dest), is_flat);
1547 } else if (ctx->is_blend) {
1548 /* For blend shaders, load the input color, which is
1549 * preloaded to r0 */
1550
1551 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1552 emit_mir_instruction(ctx, move);
1553 schedule_barrier(ctx);
1554 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1555 emit_attr_read(ctx, reg, offset, nr_comp, t);
1556 } else {
1557 DBG("Unknown load\n");
1558 assert(0);
1559 }
1560
1561 break;
1562 }
1563
1564 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1565 case nir_intrinsic_load_barycentric_pixel:
1566 case nir_intrinsic_load_barycentric_centroid:
1567 break;
1568
1569 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1570
1571 case nir_intrinsic_load_raw_output_pan:
1572 case nir_intrinsic_load_output_u8_as_fp16_pan:
1573 reg = nir_dest_index(&instr->dest);
1574 assert(ctx->is_blend);
1575
1576 /* T720 and below use different blend opcodes with slightly
1577 * different semantics than T760 and up */
1578
1579 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1580 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1581
1582 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1583 ld.load_store.op = old_blend ?
1584 midgard_op_ld_color_buffer_as_fp16_old :
1585 midgard_op_ld_color_buffer_as_fp16;
1586
1587 for (unsigned c = 4; c < 16; ++c)
1588 ld.swizzle[0][c] = 0;
1589
1590 ld.dest_type = nir_type_float16;
1591
1592 if (old_blend) {
1593 ld.load_store.address = 1;
1594 ld.load_store.arg_2 = 0x1E;
1595 }
1596 } else if (old_blend) {
1597 ld.load_store.op = midgard_op_ld_color_buffer_32u_old;
1598 ld.load_store.address = 16;
1599 ld.load_store.arg_2 = 0x1E;
1600 }
1601
1602 emit_mir_instruction(ctx, ld);
1603 break;
1604
1605 case nir_intrinsic_load_blend_const_color_rgba: {
1606 assert(ctx->is_blend);
1607 reg = nir_dest_index(&instr->dest);
1608
1609 /* Blend constants are embedded directly in the shader and
1610 * patched in, so we use some magic routing */
1611
1612 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1613 ins.has_constants = true;
1614 ins.has_blend_constant = true;
1615 emit_mir_instruction(ctx, ins);
1616 break;
1617 }
1618
1619 case nir_intrinsic_store_zs_output_pan: {
1620 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1621 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1622 MIDGARD_ZS_RT);
1623
1624 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1625
1626 if (!nir_intrinsic_component(instr))
1627 br->writeout_depth = true;
1628 if (nir_intrinsic_component(instr) ||
1629 instr->num_components)
1630 br->writeout_stencil = true;
1631 assert(br->writeout_depth | br->writeout_stencil);
1632 break;
1633 }
1634
1635 case nir_intrinsic_store_output:
1636 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1637
1638 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1639
1640 reg = nir_src_index(ctx, &instr->src[0]);
1641
1642 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1643 const nir_variable *var;
1644 enum midgard_rt_id rt;
1645
1646 var = search_var(&ctx->nir->outputs,
1647 nir_intrinsic_base(instr));
1648 assert(var);
1649 if (var->data.location == FRAG_RESULT_COLOR)
1650 rt = MIDGARD_COLOR_RT0;
1651 else if (var->data.location >= FRAG_RESULT_DATA0)
1652 rt = MIDGARD_COLOR_RT0 + var->data.location -
1653 FRAG_RESULT_DATA0;
1654 else
1655 assert(0);
1656
1657 emit_fragment_store(ctx, reg, rt);
1658 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1659 /* We should have been vectorized, though we don't
1660 * currently check that st_vary is emitted only once
1661 * per slot (this is relevant, since there's not a mask
1662 * parameter available on the store [set to 0 by the
1663 * blob]). We do respect the component by adjusting the
1664 * swizzle. If this is a constant source, we'll need to
1665 * emit that explicitly. */
1666
1667 emit_explicit_constant(ctx, reg, reg);
1668
1669 unsigned dst_component = nir_intrinsic_component(instr);
1670 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1671
1672 midgard_instruction st = m_st_vary_32(reg, offset);
1673 st.load_store.arg_1 = 0x9E;
1674 st.load_store.arg_2 = 0x1E;
1675
1676 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1677 case nir_type_uint:
1678 case nir_type_bool:
1679 st.load_store.op = midgard_op_st_vary_32u;
1680 break;
1681 case nir_type_int:
1682 st.load_store.op = midgard_op_st_vary_32i;
1683 break;
1684 case nir_type_float:
1685 st.load_store.op = midgard_op_st_vary_32;
1686 break;
1687 default:
1688 unreachable("Attempted to store unknown type");
1689 break;
1690 }
1691
1692 /* nir_intrinsic_component(store_intr) encodes the
1693 * destination component start. Source component offset
1694 * adjustment is taken care of in
1695 * install_registers_instr(), when offset_swizzle() is
1696 * called.
1697 */
1698 unsigned src_component = COMPONENT_X;
1699
1700 assert(nr_comp > 0);
1701 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1702 st.swizzle[0][i] = src_component;
1703 if (i >= dst_component && i < dst_component + nr_comp - 1)
1704 src_component++;
1705 }
1706
1707 emit_mir_instruction(ctx, st);
1708 } else {
1709 DBG("Unknown store\n");
1710 assert(0);
1711 }
1712
1713 break;
1714
1715 /* Special case of store_output for lowered blend shaders */
1716 case nir_intrinsic_store_raw_output_pan:
1717 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1718 reg = nir_src_index(ctx, &instr->src[0]);
1719
1720 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1721 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1722 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1723 * of:
1724 *
1725 * imov r0.xyzw, r0.xxxx
1726 */
1727
1728 unsigned expanded = make_compiler_temp(ctx);
1729
1730 midgard_instruction splatter = v_mov(reg, expanded);
1731
1732 for (unsigned c = 0; c < 16; ++c)
1733 splatter.swizzle[1][c] = 0;
1734
1735 emit_mir_instruction(ctx, splatter);
1736 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1737 } else
1738 emit_fragment_store(ctx, reg, ctx->blend_rt);
1739
1740 break;
1741
1742 case nir_intrinsic_store_global:
1743 case nir_intrinsic_store_shared:
1744 reg = nir_src_index(ctx, &instr->src[0]);
1745 emit_explicit_constant(ctx, reg, reg);
1746
1747 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1748 break;
1749
1750 case nir_intrinsic_load_ssbo_address:
1751 emit_sysval_read(ctx, &instr->instr, 1, 0);
1752 break;
1753
1754 case nir_intrinsic_get_buffer_size:
1755 emit_sysval_read(ctx, &instr->instr, 1, 8);
1756 break;
1757
1758 case nir_intrinsic_load_viewport_scale:
1759 case nir_intrinsic_load_viewport_offset:
1760 case nir_intrinsic_load_num_work_groups:
1761 case nir_intrinsic_load_sampler_lod_parameters_pan:
1762 emit_sysval_read(ctx, &instr->instr, 3, 0);
1763 break;
1764
1765 case nir_intrinsic_load_work_group_id:
1766 case nir_intrinsic_load_local_invocation_id:
1767 emit_compute_builtin(ctx, instr);
1768 break;
1769
1770 case nir_intrinsic_load_vertex_id:
1771 case nir_intrinsic_load_instance_id:
1772 emit_vertex_builtin(ctx, instr);
1773 break;
1774
1775 case nir_intrinsic_memory_barrier_buffer:
1776 case nir_intrinsic_memory_barrier_shared:
1777 break;
1778
1779 case nir_intrinsic_control_barrier:
1780 schedule_barrier(ctx);
1781 emit_control_barrier(ctx);
1782 schedule_barrier(ctx);
1783 break;
1784
1785 default:
1786 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1787 assert(0);
1788 break;
1789 }
1790 }
1791
1792 static unsigned
1793 midgard_tex_format(enum glsl_sampler_dim dim)
1794 {
1795 switch (dim) {
1796 case GLSL_SAMPLER_DIM_1D:
1797 case GLSL_SAMPLER_DIM_BUF:
1798 return MALI_TEX_1D;
1799
1800 case GLSL_SAMPLER_DIM_2D:
1801 case GLSL_SAMPLER_DIM_EXTERNAL:
1802 case GLSL_SAMPLER_DIM_RECT:
1803 return MALI_TEX_2D;
1804
1805 case GLSL_SAMPLER_DIM_3D:
1806 return MALI_TEX_3D;
1807
1808 case GLSL_SAMPLER_DIM_CUBE:
1809 return MALI_TEX_CUBE;
1810
1811 default:
1812 DBG("Unknown sampler dim type\n");
1813 assert(0);
1814 return 0;
1815 }
1816 }
1817
1818 /* Tries to attach an explicit LOD or bias as a constant. Returns whether this
1819 * was successful */
1820
1821 static bool
1822 pan_attach_constant_bias(
1823 compiler_context *ctx,
1824 nir_src lod,
1825 midgard_texture_word *word)
1826 {
1827 /* To attach as constant, it has to *be* constant */
1828
1829 if (!nir_src_is_const(lod))
1830 return false;
1831
1832 float f = nir_src_as_float(lod);
1833
1834 /* Break into fixed-point */
1835 signed lod_int = f;
1836 float lod_frac = f - lod_int;
1837
1838 /* Carry over negative fractions */
1839 if (lod_frac < 0.0) {
1840 lod_int--;
1841 lod_frac += 1.0;
1842 }
1843
1844 /* Encode */
1845 word->bias = float_to_ubyte(lod_frac);
1846 word->bias_int = lod_int;
1847
1848 return true;
1849 }
1850
1851 static void
1852 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1853 unsigned midgard_texop)
1854 {
1855 /* TODO */
1856 //assert (!instr->sampler);
1857
1858 int texture_index = instr->texture_index;
1859 int sampler_index = texture_index;
1860
1861 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1862 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1863
1864 midgard_instruction ins = {
1865 .type = TAG_TEXTURE_4,
1866 .mask = 0xF,
1867 .dest = nir_dest_index(&instr->dest),
1868 .src = { ~0, ~0, ~0, ~0 },
1869 .dest_type = dest_type,
1870 .swizzle = SWIZZLE_IDENTITY_4,
1871 .texture = {
1872 .op = midgard_texop,
1873 .format = midgard_tex_format(instr->sampler_dim),
1874 .texture_handle = texture_index,
1875 .sampler_handle = sampler_index,
1876 .shadow = instr->is_shadow,
1877 }
1878 };
1879
1880 if (instr->is_shadow && !instr->is_new_style_shadow)
1881 for (int i = 0; i < 4; ++i)
1882 ins.swizzle[0][i] = COMPONENT_X;
1883
1884 /* We may need a temporary for the coordinate */
1885
1886 bool needs_temp_coord =
1887 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1888 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1889 (instr->is_shadow);
1890
1891 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1892
1893 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1894 int index = nir_src_index(ctx, &instr->src[i].src);
1895 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1896 unsigned sz = nir_src_bit_size(instr->src[i].src);
1897 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1898
1899 switch (instr->src[i].src_type) {
1900 case nir_tex_src_coord: {
1901 emit_explicit_constant(ctx, index, index);
1902
1903 unsigned coord_mask = mask_of(instr->coord_components);
1904
1905 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1906
1907 if (flip_zw)
1908 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1909
1910 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1911 /* texelFetch is undefined on samplerCube */
1912 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1913
1914 /* For cubemaps, we use a special ld/st op to
1915 * select the face and copy the xy into the
1916 * texture register */
1917
1918 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1919 ld.src[1] = index;
1920 ld.src_types[1] = T;
1921 ld.mask = 0x3; /* xy */
1922 ld.load_store.arg_1 = 0x20;
1923 ld.swizzle[1][3] = COMPONENT_X;
1924 emit_mir_instruction(ctx, ld);
1925
1926 /* xyzw -> xyxx */
1927 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1928 ins.swizzle[1][3] = COMPONENT_X;
1929 } else if (needs_temp_coord) {
1930 /* mov coord_temp, coords */
1931 midgard_instruction mov = v_mov(index, coords);
1932 mov.mask = coord_mask;
1933
1934 if (flip_zw)
1935 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1936
1937 emit_mir_instruction(ctx, mov);
1938 } else {
1939 coords = index;
1940 }
1941
1942 ins.src[1] = coords;
1943 ins.src_types[1] = T;
1944
1945 /* Texelfetch coordinates uses all four elements
1946 * (xyz/index) regardless of texture dimensionality,
1947 * which means it's necessary to zero the unused
1948 * components to keep everything happy */
1949
1950 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1951 /* mov index.zw, #0, or generalized */
1952 midgard_instruction mov =
1953 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1954 mov.has_constants = true;
1955 mov.mask = coord_mask ^ 0xF;
1956 emit_mir_instruction(ctx, mov);
1957 }
1958
1959 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1960 /* Array component in w but NIR wants it in z,
1961 * but if we have a temp coord we already fixed
1962 * that up */
1963
1964 if (nr_components == 3) {
1965 ins.swizzle[1][2] = COMPONENT_Z;
1966 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1967 } else if (nr_components == 2) {
1968 ins.swizzle[1][2] =
1969 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1970 ins.swizzle[1][3] = COMPONENT_X;
1971 } else
1972 unreachable("Invalid texture 2D components");
1973 }
1974
1975 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1976 /* We zeroed */
1977 ins.swizzle[1][2] = COMPONENT_Z;
1978 ins.swizzle[1][3] = COMPONENT_W;
1979 }
1980
1981 break;
1982 }
1983
1984 case nir_tex_src_bias:
1985 case nir_tex_src_lod: {
1986 /* Try as a constant if we can */
1987
1988 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1989 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1990 break;
1991
1992 ins.texture.lod_register = true;
1993 ins.src[2] = index;
1994 ins.src_types[2] = T;
1995
1996 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1997 ins.swizzle[2][c] = COMPONENT_X;
1998
1999 emit_explicit_constant(ctx, index, index);
2000
2001 break;
2002 };
2003
2004 case nir_tex_src_offset: {
2005 ins.texture.offset_register = true;
2006 ins.src[3] = index;
2007 ins.src_types[3] = T;
2008
2009 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2010 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
2011
2012 emit_explicit_constant(ctx, index, index);
2013 break;
2014 };
2015
2016 case nir_tex_src_comparator: {
2017 unsigned comp = COMPONENT_Z;
2018
2019 /* mov coord_temp.foo, coords */
2020 midgard_instruction mov = v_mov(index, coords);
2021 mov.mask = 1 << comp;
2022
2023 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
2024 mov.swizzle[1][i] = COMPONENT_X;
2025
2026 emit_mir_instruction(ctx, mov);
2027 break;
2028 }
2029
2030 default: {
2031 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
2032 assert(0);
2033 }
2034 }
2035 }
2036
2037 emit_mir_instruction(ctx, ins);
2038 }
2039
2040 static void
2041 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
2042 {
2043 switch (instr->op) {
2044 case nir_texop_tex:
2045 case nir_texop_txb:
2046 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
2047 break;
2048 case nir_texop_txl:
2049 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
2050 break;
2051 case nir_texop_txf:
2052 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
2053 break;
2054 case nir_texop_txs:
2055 emit_sysval_read(ctx, &instr->instr, 4, 0);
2056 break;
2057 default: {
2058 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
2059 assert(0);
2060 }
2061 }
2062 }
2063
2064 static void
2065 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
2066 {
2067 switch (instr->type) {
2068 case nir_jump_break: {
2069 /* Emit a branch out of the loop */
2070 struct midgard_instruction br = v_branch(false, false);
2071 br.branch.target_type = TARGET_BREAK;
2072 br.branch.target_break = ctx->current_loop_depth;
2073 emit_mir_instruction(ctx, br);
2074 break;
2075 }
2076
2077 default:
2078 DBG("Unknown jump type %d\n", instr->type);
2079 break;
2080 }
2081 }
2082
2083 static void
2084 emit_instr(compiler_context *ctx, struct nir_instr *instr)
2085 {
2086 switch (instr->type) {
2087 case nir_instr_type_load_const:
2088 emit_load_const(ctx, nir_instr_as_load_const(instr));
2089 break;
2090
2091 case nir_instr_type_intrinsic:
2092 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2093 break;
2094
2095 case nir_instr_type_alu:
2096 emit_alu(ctx, nir_instr_as_alu(instr));
2097 break;
2098
2099 case nir_instr_type_tex:
2100 emit_tex(ctx, nir_instr_as_tex(instr));
2101 break;
2102
2103 case nir_instr_type_jump:
2104 emit_jump(ctx, nir_instr_as_jump(instr));
2105 break;
2106
2107 case nir_instr_type_ssa_undef:
2108 /* Spurious */
2109 break;
2110
2111 default:
2112 DBG("Unhandled instruction type\n");
2113 break;
2114 }
2115 }
2116
2117
2118 /* ALU instructions can inline or embed constants, which decreases register
2119 * pressure and saves space. */
2120
2121 #define CONDITIONAL_ATTACH(idx) { \
2122 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2123 \
2124 if (entry) { \
2125 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2126 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2127 } \
2128 }
2129
2130 static void
2131 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2132 {
2133 mir_foreach_instr_in_block(block, alu) {
2134 /* Other instructions cannot inline constants */
2135 if (alu->type != TAG_ALU_4) continue;
2136 if (alu->compact_branch) continue;
2137
2138 /* If there is already a constant here, we can do nothing */
2139 if (alu->has_constants) continue;
2140
2141 CONDITIONAL_ATTACH(0);
2142
2143 if (!alu->has_constants) {
2144 CONDITIONAL_ATTACH(1)
2145 } else if (!alu->inline_constant) {
2146 /* Corner case: _two_ vec4 constants, for instance with a
2147 * csel. For this case, we can only use a constant
2148 * register for one, we'll have to emit a move for the
2149 * other. */
2150
2151 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2152 unsigned scratch = make_compiler_temp(ctx);
2153
2154 if (entry) {
2155 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2156 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2157
2158 /* Set the source */
2159 alu->src[1] = scratch;
2160
2161 /* Inject us -before- the last instruction which set r31 */
2162 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2163 }
2164 }
2165 }
2166 }
2167
2168 /* Midgard supports two types of constants, embedded constants (128-bit) and
2169 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2170 * constants can be demoted to inline constants, for space savings and
2171 * sometimes a performance boost */
2172
2173 static void
2174 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2175 {
2176 mir_foreach_instr_in_block(block, ins) {
2177 if (!ins->has_constants) continue;
2178 if (ins->has_inline_constant) continue;
2179
2180 /* Blend constants must not be inlined by definition */
2181 if (ins->has_blend_constant) continue;
2182
2183 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2184 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2185 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2186
2187 if (!(is_16 || is_32))
2188 continue;
2189
2190 /* src1 cannot be an inline constant due to encoding
2191 * restrictions. So, if possible we try to flip the arguments
2192 * in that case */
2193
2194 int op = ins->alu.op;
2195
2196 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2197 alu_opcode_props[op].props & OP_COMMUTES) {
2198 mir_flip(ins);
2199 }
2200
2201 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2202 /* Component is from the swizzle. Take a nonzero component */
2203 assert(ins->mask);
2204 unsigned first_comp = ffs(ins->mask) - 1;
2205 unsigned component = ins->swizzle[1][first_comp];
2206
2207 /* Scale constant appropriately, if we can legally */
2208 uint16_t scaled_constant = 0;
2209
2210 if (is_16) {
2211 scaled_constant = ins->constants.u16[component];
2212 } else if (midgard_is_integer_op(op)) {
2213 scaled_constant = ins->constants.u32[component];
2214
2215 /* Constant overflow after resize */
2216 if (scaled_constant != ins->constants.u32[component])
2217 continue;
2218 } else {
2219 float original = ins->constants.f32[component];
2220 scaled_constant = _mesa_float_to_half(original);
2221
2222 /* Check for loss of precision. If this is
2223 * mediump, we don't care, but for a highp
2224 * shader, we need to pay attention. NIR
2225 * doesn't yet tell us which mode we're in!
2226 * Practically this prevents most constants
2227 * from being inlined, sadly. */
2228
2229 float fp32 = _mesa_half_to_float(scaled_constant);
2230
2231 if (fp32 != original)
2232 continue;
2233 }
2234
2235 /* Should've been const folded */
2236 if (ins->src_abs[1] || ins->src_neg[1])
2237 continue;
2238
2239 /* Make sure that the constant is not itself a vector
2240 * by checking if all accessed values are the same. */
2241
2242 const midgard_constants *cons = &ins->constants;
2243 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2244
2245 bool is_vector = false;
2246 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2247
2248 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2249 /* We only care if this component is actually used */
2250 if (!(mask & (1 << c)))
2251 continue;
2252
2253 uint32_t test = is_16 ?
2254 cons->u16[ins->swizzle[1][c]] :
2255 cons->u32[ins->swizzle[1][c]];
2256
2257 if (test != value) {
2258 is_vector = true;
2259 break;
2260 }
2261 }
2262
2263 if (is_vector)
2264 continue;
2265
2266 /* Get rid of the embedded constant */
2267 ins->has_constants = false;
2268 ins->src[1] = ~0;
2269 ins->has_inline_constant = true;
2270 ins->inline_constant = scaled_constant;
2271 }
2272 }
2273 }
2274
2275 /* Dead code elimination for branches at the end of a block - only one branch
2276 * per block is legal semantically */
2277
2278 static void
2279 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2280 {
2281 bool branched = false;
2282
2283 mir_foreach_instr_in_block_safe(block, ins) {
2284 if (!midgard_is_branch_unit(ins->unit)) continue;
2285
2286 if (branched)
2287 mir_remove_instruction(ins);
2288
2289 branched = true;
2290 }
2291 }
2292
2293 static unsigned
2294 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2295 {
2296 /* Loop to ourselves */
2297 midgard_instruction *br = ctx->writeout_branch[rt];
2298 struct midgard_instruction ins = v_branch(false, false);
2299 ins.writeout = true;
2300 ins.writeout_depth = br->writeout_depth;
2301 ins.writeout_stencil = br->writeout_stencil;
2302 ins.branch.target_block = ctx->block_count - 1;
2303 ins.constants.u32[0] = br->constants.u32[0];
2304 emit_mir_instruction(ctx, ins);
2305
2306 ctx->current_block->epilogue = true;
2307 schedule_barrier(ctx);
2308 return ins.branch.target_block;
2309 }
2310
2311 static midgard_block *
2312 emit_block(compiler_context *ctx, nir_block *block)
2313 {
2314 midgard_block *this_block = ctx->after_block;
2315 ctx->after_block = NULL;
2316
2317 if (!this_block)
2318 this_block = create_empty_block(ctx);
2319
2320 list_addtail(&this_block->base.link, &ctx->blocks);
2321
2322 this_block->scheduled = false;
2323 ++ctx->block_count;
2324
2325 /* Set up current block */
2326 list_inithead(&this_block->base.instructions);
2327 ctx->current_block = this_block;
2328
2329 nir_foreach_instr(instr, block) {
2330 emit_instr(ctx, instr);
2331 ++ctx->instruction_count;
2332 }
2333
2334 return this_block;
2335 }
2336
2337 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2338
2339 static void
2340 emit_if(struct compiler_context *ctx, nir_if *nif)
2341 {
2342 midgard_block *before_block = ctx->current_block;
2343
2344 /* Speculatively emit the branch, but we can't fill it in until later */
2345 bool inv = false;
2346 EMIT(branch, true, true);
2347 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2348 then_branch->src[0] = mir_get_branch_cond(&nif->condition, &inv);
2349 then_branch->src_types[0] = nir_type_uint32;
2350 then_branch->branch.invert_conditional = !inv;
2351
2352 /* Emit the two subblocks. */
2353 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2354 midgard_block *end_then_block = ctx->current_block;
2355
2356 /* Emit a jump from the end of the then block to the end of the else */
2357 EMIT(branch, false, false);
2358 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2359
2360 /* Emit second block, and check if it's empty */
2361
2362 int else_idx = ctx->block_count;
2363 int count_in = ctx->instruction_count;
2364 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2365 midgard_block *end_else_block = ctx->current_block;
2366 int after_else_idx = ctx->block_count;
2367
2368 /* Now that we have the subblocks emitted, fix up the branches */
2369
2370 assert(then_block);
2371 assert(else_block);
2372
2373 if (ctx->instruction_count == count_in) {
2374 /* The else block is empty, so don't emit an exit jump */
2375 mir_remove_instruction(then_exit);
2376 then_branch->branch.target_block = after_else_idx;
2377 } else {
2378 then_branch->branch.target_block = else_idx;
2379 then_exit->branch.target_block = after_else_idx;
2380 }
2381
2382 /* Wire up the successors */
2383
2384 ctx->after_block = create_empty_block(ctx);
2385
2386 pan_block_add_successor(&before_block->base, &then_block->base);
2387 pan_block_add_successor(&before_block->base, &else_block->base);
2388
2389 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2390 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2391 }
2392
2393 static void
2394 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2395 {
2396 /* Remember where we are */
2397 midgard_block *start_block = ctx->current_block;
2398
2399 /* Allocate a loop number, growing the current inner loop depth */
2400 int loop_idx = ++ctx->current_loop_depth;
2401
2402 /* Get index from before the body so we can loop back later */
2403 int start_idx = ctx->block_count;
2404
2405 /* Emit the body itself */
2406 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2407
2408 /* Branch back to loop back */
2409 struct midgard_instruction br_back = v_branch(false, false);
2410 br_back.branch.target_block = start_idx;
2411 emit_mir_instruction(ctx, br_back);
2412
2413 /* Mark down that branch in the graph. */
2414 pan_block_add_successor(&start_block->base, &loop_block->base);
2415 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2416
2417 /* Find the index of the block about to follow us (note: we don't add
2418 * one; blocks are 0-indexed so we get a fencepost problem) */
2419 int break_block_idx = ctx->block_count;
2420
2421 /* Fix up the break statements we emitted to point to the right place,
2422 * now that we can allocate a block number for them */
2423 ctx->after_block = create_empty_block(ctx);
2424
2425 mir_foreach_block_from(ctx, start_block, _block) {
2426 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2427 if (ins->type != TAG_ALU_4) continue;
2428 if (!ins->compact_branch) continue;
2429
2430 /* We found a branch -- check the type to see if we need to do anything */
2431 if (ins->branch.target_type != TARGET_BREAK) continue;
2432
2433 /* It's a break! Check if it's our break */
2434 if (ins->branch.target_break != loop_idx) continue;
2435
2436 /* Okay, cool, we're breaking out of this loop.
2437 * Rewrite from a break to a goto */
2438
2439 ins->branch.target_type = TARGET_GOTO;
2440 ins->branch.target_block = break_block_idx;
2441
2442 pan_block_add_successor(_block, &ctx->after_block->base);
2443 }
2444 }
2445
2446 /* Now that we've finished emitting the loop, free up the depth again
2447 * so we play nice with recursion amid nested loops */
2448 --ctx->current_loop_depth;
2449
2450 /* Dump loop stats */
2451 ++ctx->loop_count;
2452 }
2453
2454 static midgard_block *
2455 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2456 {
2457 midgard_block *start_block = NULL;
2458
2459 foreach_list_typed(nir_cf_node, node, node, list) {
2460 switch (node->type) {
2461 case nir_cf_node_block: {
2462 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2463
2464 if (!start_block)
2465 start_block = block;
2466
2467 break;
2468 }
2469
2470 case nir_cf_node_if:
2471 emit_if(ctx, nir_cf_node_as_if(node));
2472 break;
2473
2474 case nir_cf_node_loop:
2475 emit_loop(ctx, nir_cf_node_as_loop(node));
2476 break;
2477
2478 case nir_cf_node_function:
2479 assert(0);
2480 break;
2481 }
2482 }
2483
2484 return start_block;
2485 }
2486
2487 /* Due to lookahead, we need to report the first tag executed in the command
2488 * stream and in branch targets. An initial block might be empty, so iterate
2489 * until we find one that 'works' */
2490
2491 static unsigned
2492 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2493 {
2494 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2495
2496 mir_foreach_block_from(ctx, initial_block, _v) {
2497 midgard_block *v = (midgard_block *) _v;
2498 if (v->quadword_count) {
2499 midgard_bundle *initial_bundle =
2500 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2501
2502 return initial_bundle->tag;
2503 }
2504 }
2505
2506 /* Default to a tag 1 which will break from the shader, in case we jump
2507 * to the exit block (i.e. `return` in a compute shader) */
2508
2509 return 1;
2510 }
2511
2512 /* For each fragment writeout instruction, generate a writeout loop to
2513 * associate with it */
2514
2515 static void
2516 mir_add_writeout_loops(compiler_context *ctx)
2517 {
2518 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2519 midgard_instruction *br = ctx->writeout_branch[rt];
2520 if (!br) continue;
2521
2522 unsigned popped = br->branch.target_block;
2523 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2524 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2525 br->branch.target_type = TARGET_GOTO;
2526
2527 /* If we have more RTs, we'll need to restore back after our
2528 * loop terminates */
2529
2530 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2531 midgard_instruction uncond = v_branch(false, false);
2532 uncond.branch.target_block = popped;
2533 uncond.branch.target_type = TARGET_GOTO;
2534 emit_mir_instruction(ctx, uncond);
2535 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2536 schedule_barrier(ctx);
2537 } else {
2538 /* We're last, so we can terminate here */
2539 br->last_writeout = true;
2540 }
2541 }
2542 }
2543
2544 int
2545 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2546 {
2547 struct util_dynarray *compiled = &program->compiled;
2548
2549 midgard_debug = debug_get_option_midgard_debug();
2550
2551 /* TODO: Bound against what? */
2552 compiler_context *ctx = rzalloc(NULL, compiler_context);
2553
2554 ctx->nir = nir;
2555 ctx->stage = nir->info.stage;
2556 ctx->is_blend = is_blend;
2557 ctx->alpha_ref = program->alpha_ref;
2558 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2559 ctx->quirks = midgard_get_quirks(gpu_id);
2560
2561 /* Start off with a safe cutoff, allowing usage of all 16 work
2562 * registers. Later, we'll promote uniform reads to uniform registers
2563 * if we determine it is beneficial to do so */
2564 ctx->uniform_cutoff = 8;
2565
2566 /* Initialize at a global (not block) level hash tables */
2567
2568 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2569 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2570
2571 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2572 * (so we don't accidentally duplicate the epilogue since mesa/st has
2573 * messed with our I/O quite a bit already) */
2574
2575 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2576
2577 if (ctx->stage == MESA_SHADER_VERTEX) {
2578 NIR_PASS_V(nir, nir_lower_viewport_transform);
2579 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2580 }
2581
2582 NIR_PASS_V(nir, nir_lower_var_copies);
2583 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2584 NIR_PASS_V(nir, nir_split_var_copies);
2585 NIR_PASS_V(nir, nir_lower_var_copies);
2586 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2587 NIR_PASS_V(nir, nir_lower_var_copies);
2588 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2589
2590 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2591 NIR_PASS_V(nir, nir_lower_ssbo);
2592 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2593
2594 /* Optimisation passes */
2595
2596 optimise_nir(nir, ctx->quirks);
2597
2598 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2599 nir_print_shader(nir, stdout);
2600 }
2601
2602 /* Assign sysvals and counts, now that we're sure
2603 * (post-optimisation) */
2604
2605 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2606 program->sysval_count = ctx->sysvals.sysval_count;
2607 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2608
2609 nir_foreach_function(func, nir) {
2610 if (!func->impl)
2611 continue;
2612
2613 list_inithead(&ctx->blocks);
2614 ctx->block_count = 0;
2615 ctx->func = func;
2616 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
2617
2618 emit_cf_list(ctx, &func->impl->body);
2619 free(ctx->already_emitted);
2620 break; /* TODO: Multi-function shaders */
2621 }
2622
2623 util_dynarray_init(compiled, NULL);
2624
2625 /* Per-block lowering before opts */
2626
2627 mir_foreach_block(ctx, _block) {
2628 midgard_block *block = (midgard_block *) _block;
2629 inline_alu_constants(ctx, block);
2630 embedded_to_inline_constant(ctx, block);
2631 }
2632 /* MIR-level optimizations */
2633
2634 bool progress = false;
2635
2636 do {
2637 progress = false;
2638 progress |= midgard_opt_dead_code_eliminate(ctx);
2639
2640 mir_foreach_block(ctx, _block) {
2641 midgard_block *block = (midgard_block *) _block;
2642 progress |= midgard_opt_copy_prop(ctx, block);
2643 progress |= midgard_opt_combine_projection(ctx, block);
2644 progress |= midgard_opt_varying_projection(ctx, block);
2645 }
2646 } while (progress);
2647
2648 mir_foreach_block(ctx, _block) {
2649 midgard_block *block = (midgard_block *) _block;
2650 midgard_lower_derivatives(ctx, block);
2651 midgard_cull_dead_branch(ctx, block);
2652 }
2653
2654 if (ctx->stage == MESA_SHADER_FRAGMENT)
2655 mir_add_writeout_loops(ctx);
2656
2657 /* Analyze now that the code is known but before scheduling creates
2658 * pipeline registers which are harder to track */
2659 mir_analyze_helper_terminate(ctx);
2660 mir_analyze_helper_requirements(ctx);
2661
2662 /* Schedule! */
2663 midgard_schedule_program(ctx);
2664 mir_ra(ctx);
2665
2666 /* Now that all the bundles are scheduled and we can calculate block
2667 * sizes, emit actual branch instructions rather than placeholders */
2668
2669 int br_block_idx = 0;
2670
2671 mir_foreach_block(ctx, _block) {
2672 midgard_block *block = (midgard_block *) _block;
2673 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2674 for (int c = 0; c < bundle->instruction_count; ++c) {
2675 midgard_instruction *ins = bundle->instructions[c];
2676
2677 if (!midgard_is_branch_unit(ins->unit)) continue;
2678
2679 /* Parse some basic branch info */
2680 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2681 bool is_conditional = ins->branch.conditional;
2682 bool is_inverted = ins->branch.invert_conditional;
2683 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2684 bool is_writeout = ins->writeout;
2685
2686 /* Determine the block we're jumping to */
2687 int target_number = ins->branch.target_block;
2688
2689 /* Report the destination tag */
2690 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2691
2692 /* Count up the number of quadwords we're
2693 * jumping over = number of quadwords until
2694 * (br_block_idx, target_number) */
2695
2696 int quadword_offset = 0;
2697
2698 if (is_discard) {
2699 /* Ignored */
2700 } else if (target_number > br_block_idx) {
2701 /* Jump forward */
2702
2703 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2704 midgard_block *blk = mir_get_block(ctx, idx);
2705 assert(blk);
2706
2707 quadword_offset += blk->quadword_count;
2708 }
2709 } else {
2710 /* Jump backwards */
2711
2712 for (int idx = br_block_idx; idx >= target_number; --idx) {
2713 midgard_block *blk = mir_get_block(ctx, idx);
2714 assert(blk);
2715
2716 quadword_offset -= blk->quadword_count;
2717 }
2718 }
2719
2720 /* Unconditional extended branches (far jumps)
2721 * have issues, so we always use a conditional
2722 * branch, setting the condition to always for
2723 * unconditional. For compact unconditional
2724 * branches, cond isn't used so it doesn't
2725 * matter what we pick. */
2726
2727 midgard_condition cond =
2728 !is_conditional ? midgard_condition_always :
2729 is_inverted ? midgard_condition_false :
2730 midgard_condition_true;
2731
2732 midgard_jmp_writeout_op op =
2733 is_discard ? midgard_jmp_writeout_op_discard :
2734 is_writeout ? midgard_jmp_writeout_op_writeout :
2735 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2736 midgard_jmp_writeout_op_branch_cond;
2737
2738 if (!is_compact) {
2739 midgard_branch_extended branch =
2740 midgard_create_branch_extended(
2741 cond, op,
2742 dest_tag,
2743 quadword_offset);
2744
2745 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2746 } else if (is_conditional || is_discard) {
2747 midgard_branch_cond branch = {
2748 .op = op,
2749 .dest_tag = dest_tag,
2750 .offset = quadword_offset,
2751 .cond = cond
2752 };
2753
2754 assert(branch.offset == quadword_offset);
2755
2756 memcpy(&ins->br_compact, &branch, sizeof(branch));
2757 } else {
2758 assert(op == midgard_jmp_writeout_op_branch_uncond);
2759
2760 midgard_branch_uncond branch = {
2761 .op = op,
2762 .dest_tag = dest_tag,
2763 .offset = quadword_offset,
2764 .unknown = 1
2765 };
2766
2767 assert(branch.offset == quadword_offset);
2768
2769 memcpy(&ins->br_compact, &branch, sizeof(branch));
2770 }
2771 }
2772 }
2773
2774 ++br_block_idx;
2775 }
2776
2777 /* Emit flat binary from the instruction arrays. Iterate each block in
2778 * sequence. Save instruction boundaries such that lookahead tags can
2779 * be assigned easily */
2780
2781 /* Cache _all_ bundles in source order for lookahead across failed branches */
2782
2783 int bundle_count = 0;
2784 mir_foreach_block(ctx, _block) {
2785 midgard_block *block = (midgard_block *) _block;
2786 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2787 }
2788 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2789 int bundle_idx = 0;
2790 mir_foreach_block(ctx, _block) {
2791 midgard_block *block = (midgard_block *) _block;
2792 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2793 source_order_bundles[bundle_idx++] = bundle;
2794 }
2795 }
2796
2797 int current_bundle = 0;
2798
2799 /* Midgard prefetches instruction types, so during emission we
2800 * need to lookahead. Unless this is the last instruction, in
2801 * which we return 1. */
2802
2803 mir_foreach_block(ctx, _block) {
2804 midgard_block *block = (midgard_block *) _block;
2805 mir_foreach_bundle_in_block(block, bundle) {
2806 int lookahead = 1;
2807
2808 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2809 lookahead = source_order_bundles[current_bundle + 1]->tag;
2810
2811 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2812 ++current_bundle;
2813 }
2814
2815 /* TODO: Free deeper */
2816 //util_dynarray_fini(&block->instructions);
2817 }
2818
2819 free(source_order_bundles);
2820
2821 /* Report the very first tag executed */
2822 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2823
2824 /* Deal with off-by-one related to the fencepost problem */
2825 program->work_register_count = ctx->work_registers + 1;
2826 program->uniform_cutoff = ctx->uniform_cutoff;
2827
2828 program->blend_patch_offset = ctx->blend_constant_offset;
2829 program->tls_size = ctx->tls_size;
2830
2831 if (midgard_debug & MIDGARD_DBG_SHADERS)
2832 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2833
2834 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2835 unsigned nr_bundles = 0, nr_ins = 0;
2836
2837 /* Count instructions and bundles */
2838
2839 mir_foreach_block(ctx, _block) {
2840 midgard_block *block = (midgard_block *) _block;
2841 nr_bundles += util_dynarray_num_elements(
2842 &block->bundles, midgard_bundle);
2843
2844 mir_foreach_bundle_in_block(block, bun)
2845 nr_ins += bun->instruction_count;
2846 }
2847
2848 /* Calculate thread count. There are certain cutoffs by
2849 * register count for thread count */
2850
2851 unsigned nr_registers = program->work_register_count;
2852
2853 unsigned nr_threads =
2854 (nr_registers <= 4) ? 4 :
2855 (nr_registers <= 8) ? 2 :
2856 1;
2857
2858 /* Dump stats */
2859
2860 fprintf(stderr, "shader%d - %s shader: "
2861 "%u inst, %u bundles, %u quadwords, "
2862 "%u registers, %u threads, %u loops, "
2863 "%u:%u spills:fills\n",
2864 SHADER_DB_COUNT++,
2865 gl_shader_stage_name(ctx->stage),
2866 nr_ins, nr_bundles, ctx->quadword_count,
2867 nr_registers, nr_threads,
2868 ctx->loop_count,
2869 ctx->spills, ctx->fills);
2870 }
2871
2872 ralloc_free(ctx);
2873
2874 return 0;
2875 }