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pan/mdg: Implement b2f16
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 i.dest_type = T; \
121 } else { \
122 i.dest = ssa; \
123 i.dest_type = T; \
124 } \
125 return i; \
126 }
127
128 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
129 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
130
131 M_LOAD(ld_attr_32, nir_type_uint32);
132 M_LOAD(ld_vary_32, nir_type_uint32);
133 M_LOAD(ld_ubo_int4, nir_type_uint32);
134 M_LOAD(ld_int4, nir_type_uint32);
135 M_STORE(st_int4, nir_type_uint32);
136 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
137 M_STORE(st_vary_32, nir_type_uint32);
138 M_LOAD(ld_cubemap_coords, nir_type_uint32);
139 M_LOAD(ld_compute_id, nir_type_uint32);
140
141 static midgard_instruction
142 v_branch(bool conditional, bool invert)
143 {
144 midgard_instruction ins = {
145 .type = TAG_ALU_4,
146 .unit = ALU_ENAB_BRANCH,
147 .compact_branch = true,
148 .branch = {
149 .conditional = conditional,
150 .invert_conditional = invert
151 },
152 .dest = ~0,
153 .src = { ~0, ~0, ~0, ~0 },
154 };
155
156 return ins;
157 }
158
159 static midgard_branch_extended
160 midgard_create_branch_extended( midgard_condition cond,
161 midgard_jmp_writeout_op op,
162 unsigned dest_tag,
163 signed quadword_offset)
164 {
165 /* The condition code is actually a LUT describing a function to
166 * combine multiple condition codes. However, we only support a single
167 * condition code at the moment, so we just duplicate over a bunch of
168 * times. */
169
170 uint16_t duplicated_cond =
171 (cond << 14) |
172 (cond << 12) |
173 (cond << 10) |
174 (cond << 8) |
175 (cond << 6) |
176 (cond << 4) |
177 (cond << 2) |
178 (cond << 0);
179
180 midgard_branch_extended branch = {
181 .op = op,
182 .dest_tag = dest_tag,
183 .offset = quadword_offset,
184 .cond = duplicated_cond
185 };
186
187 return branch;
188 }
189
190 static void
191 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
192 {
193 ins->has_constants = true;
194 memcpy(&ins->constants, constants, 16);
195 }
196
197 static int
198 glsl_type_size(const struct glsl_type *type, bool bindless)
199 {
200 return glsl_count_attribute_slots(type, false);
201 }
202
203 /* Lower fdot2 to a vector multiplication followed by channel addition */
204 static void
205 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
206 {
207 if (alu->op != nir_op_fdot2)
208 return;
209
210 b->cursor = nir_before_instr(&alu->instr);
211
212 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
213 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
214
215 nir_ssa_def *product = nir_fmul(b, src0, src1);
216
217 nir_ssa_def *sum = nir_fadd(b,
218 nir_channel(b, product, 0),
219 nir_channel(b, product, 1));
220
221 /* Replace the fdot2 with this sum */
222 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
223 }
224
225 static bool
226 midgard_nir_lower_fdot2(nir_shader *shader)
227 {
228 bool progress = false;
229
230 nir_foreach_function(function, shader) {
231 if (!function->impl) continue;
232
233 nir_builder _b;
234 nir_builder *b = &_b;
235 nir_builder_init(b, function->impl);
236
237 nir_foreach_block(block, function->impl) {
238 nir_foreach_instr_safe(instr, block) {
239 if (instr->type != nir_instr_type_alu) continue;
240
241 nir_alu_instr *alu = nir_instr_as_alu(instr);
242 midgard_nir_lower_fdot2_body(b, alu);
243
244 progress |= true;
245 }
246 }
247
248 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
249
250 }
251
252 return progress;
253 }
254
255 /* Midgard can't write depth and stencil separately. It has to happen in a
256 * single store operation containing both. Let's add a panfrost specific
257 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
258 * one.
259 */
260 static bool
261 midgard_nir_lower_zs_store(nir_shader *nir)
262 {
263 if (nir->info.stage != MESA_SHADER_FRAGMENT)
264 return false;
265
266 nir_variable *z_var = NULL, *s_var = NULL;
267
268 nir_foreach_variable(var, &nir->outputs) {
269 if (var->data.location == FRAG_RESULT_DEPTH)
270 z_var = var;
271 else if (var->data.location == FRAG_RESULT_STENCIL)
272 s_var = var;
273 }
274
275 if (!z_var && !s_var)
276 return false;
277
278 bool progress = false;
279
280 nir_foreach_function(function, nir) {
281 if (!function->impl) continue;
282
283 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
284
285 nir_foreach_block(block, function->impl) {
286 nir_foreach_instr_safe(instr, block) {
287 if (instr->type != nir_instr_type_intrinsic)
288 continue;
289
290 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
291 if (intr->intrinsic != nir_intrinsic_store_output)
292 continue;
293
294 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
295 assert(!z_store);
296 z_store = intr;
297 last_store = intr;
298 }
299
300 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
301 assert(!s_store);
302 s_store = intr;
303 last_store = intr;
304 }
305 }
306 }
307
308 if (!z_store && !s_store) continue;
309
310 nir_builder b;
311 nir_builder_init(&b, function->impl);
312
313 b.cursor = nir_before_instr(&last_store->instr);
314
315 nir_ssa_def *zs_store_src;
316
317 if (z_store && s_store) {
318 nir_ssa_def *srcs[2] = {
319 nir_ssa_for_src(&b, z_store->src[0], 1),
320 nir_ssa_for_src(&b, s_store->src[0], 1),
321 };
322
323 zs_store_src = nir_vec(&b, srcs, 2);
324 } else {
325 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
326 }
327
328 nir_intrinsic_instr *zs_store;
329
330 zs_store = nir_intrinsic_instr_create(b.shader,
331 nir_intrinsic_store_zs_output_pan);
332 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
333 zs_store->num_components = z_store && s_store ? 2 : 1;
334 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
335
336 /* Replace the Z and S store by a ZS store */
337 nir_builder_instr_insert(&b, &zs_store->instr);
338
339 if (z_store)
340 nir_instr_remove(&z_store->instr);
341
342 if (s_store)
343 nir_instr_remove(&s_store->instr);
344
345 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
346 progress = true;
347 }
348
349 return progress;
350 }
351
352 /* Flushes undefined values to zero */
353
354 static void
355 optimise_nir(nir_shader *nir, unsigned quirks)
356 {
357 bool progress;
358 unsigned lower_flrp =
359 (nir->options->lower_flrp16 ? 16 : 0) |
360 (nir->options->lower_flrp32 ? 32 : 0) |
361 (nir->options->lower_flrp64 ? 64 : 0);
362
363 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
364 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
365
366 nir_lower_tex_options lower_tex_options = {
367 .lower_txs_lod = true,
368 .lower_txp = ~0,
369 .lower_tex_without_implicit_lod =
370 (quirks & MIDGARD_EXPLICIT_LOD),
371
372 /* TODO: we have native gradient.. */
373 .lower_txd = true,
374 };
375
376 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
377
378 /* Must lower fdot2 after tex is lowered */
379 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
380
381 /* T720 is broken. */
382
383 if (quirks & MIDGARD_BROKEN_LOD)
384 NIR_PASS_V(nir, midgard_nir_lod_errata);
385
386 do {
387 progress = false;
388
389 NIR_PASS(progress, nir, nir_lower_var_copies);
390 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
391
392 NIR_PASS(progress, nir, nir_copy_prop);
393 NIR_PASS(progress, nir, nir_opt_remove_phis);
394 NIR_PASS(progress, nir, nir_opt_dce);
395 NIR_PASS(progress, nir, nir_opt_dead_cf);
396 NIR_PASS(progress, nir, nir_opt_cse);
397 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
398 NIR_PASS(progress, nir, nir_opt_algebraic);
399 NIR_PASS(progress, nir, nir_opt_constant_folding);
400
401 if (lower_flrp != 0) {
402 bool lower_flrp_progress = false;
403 NIR_PASS(lower_flrp_progress,
404 nir,
405 nir_lower_flrp,
406 lower_flrp,
407 false /* always_precise */,
408 nir->options->lower_ffma);
409 if (lower_flrp_progress) {
410 NIR_PASS(progress, nir,
411 nir_opt_constant_folding);
412 progress = true;
413 }
414
415 /* Nothing should rematerialize any flrps, so we only
416 * need to do this lowering once.
417 */
418 lower_flrp = 0;
419 }
420
421 NIR_PASS(progress, nir, nir_opt_undef);
422 NIR_PASS(progress, nir, nir_undef_to_zero);
423
424 NIR_PASS(progress, nir, nir_opt_loop_unroll,
425 nir_var_shader_in |
426 nir_var_shader_out |
427 nir_var_function_temp);
428
429 NIR_PASS(progress, nir, nir_opt_vectorize);
430 } while (progress);
431
432 /* Must be run at the end to prevent creation of fsin/fcos ops */
433 NIR_PASS(progress, nir, midgard_nir_scale_trig);
434
435 do {
436 progress = false;
437
438 NIR_PASS(progress, nir, nir_opt_dce);
439 NIR_PASS(progress, nir, nir_opt_algebraic);
440 NIR_PASS(progress, nir, nir_opt_constant_folding);
441 NIR_PASS(progress, nir, nir_copy_prop);
442 } while (progress);
443
444 NIR_PASS(progress, nir, nir_opt_algebraic_late);
445 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
446
447 /* We implement booleans as 32-bit 0/~0 */
448 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
449
450 /* Now that booleans are lowered, we can run out late opts */
451 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
452 NIR_PASS(progress, nir, midgard_nir_cancel_inot);
453
454 NIR_PASS(progress, nir, nir_copy_prop);
455 NIR_PASS(progress, nir, nir_opt_dce);
456
457 /* Take us out of SSA */
458 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
459 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
460
461 /* We are a vector architecture; write combine where possible */
462 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
463 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
464
465 NIR_PASS(progress, nir, nir_opt_dce);
466 }
467
468 /* Do not actually emit a load; instead, cache the constant for inlining */
469
470 static void
471 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
472 {
473 nir_ssa_def def = instr->def;
474
475 midgard_constants *consts = rzalloc(NULL, midgard_constants);
476
477 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
478
479 #define RAW_CONST_COPY(bits) \
480 nir_const_value_to_array(consts->u##bits, instr->value, \
481 instr->def.num_components, u##bits)
482
483 switch (instr->def.bit_size) {
484 case 64:
485 RAW_CONST_COPY(64);
486 break;
487 case 32:
488 RAW_CONST_COPY(32);
489 break;
490 case 16:
491 RAW_CONST_COPY(16);
492 break;
493 case 8:
494 RAW_CONST_COPY(8);
495 break;
496 default:
497 unreachable("Invalid bit_size for load_const instruction\n");
498 }
499
500 /* Shifted for SSA, +1 for off-by-one */
501 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
502 }
503
504 /* Normally constants are embedded implicitly, but for I/O and such we have to
505 * explicitly emit a move with the constant source */
506
507 static void
508 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
509 {
510 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
511
512 if (constant_value) {
513 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
514 attach_constants(ctx, &ins, constant_value, node + 1);
515 emit_mir_instruction(ctx, ins);
516 }
517 }
518
519 static bool
520 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
521 {
522 unsigned comp = src->swizzle[0];
523
524 for (unsigned c = 1; c < nr_components; ++c) {
525 if (src->swizzle[c] != comp)
526 return true;
527 }
528
529 return false;
530 }
531
532 #define ALU_CASE(nir, _op) \
533 case nir_op_##nir: \
534 op = midgard_alu_op_##_op; \
535 assert(src_bitsize == dst_bitsize); \
536 break;
537
538 #define ALU_CHECK_CMP(sext) \
539 assert(src_bitsize == 16 || src_bitsize == 32); \
540 assert(dst_bitsize == 16 || dst_bitsize == 32); \
541
542 #define ALU_CASE_BCAST(nir, _op, count) \
543 case nir_op_##nir: \
544 op = midgard_alu_op_##_op; \
545 broadcast_swizzle = count; \
546 ALU_CHECK_CMP(true); \
547 break;
548
549 #define ALU_CASE_CMP(nir, _op, sext) \
550 case nir_op_##nir: \
551 op = midgard_alu_op_##_op; \
552 ALU_CHECK_CMP(sext); \
553 break;
554
555 /* Analyze the sizes of the dest and inputs to determine reg mode. */
556
557 static midgard_reg_mode
558 reg_mode_for_nir(nir_alu_instr *instr)
559 {
560 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
561 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
562 unsigned max_bitsize = MAX2(src_bitsize, dst_bitsize);
563
564 switch (max_bitsize) {
565 case 8:
566 return midgard_reg_mode_8;
567 case 16:
568 return midgard_reg_mode_16;
569 case 32:
570 return midgard_reg_mode_32;
571 case 64:
572 return midgard_reg_mode_64;
573 default:
574 unreachable("Invalid bit size");
575 }
576 }
577
578 /* Compare mir_lower_invert */
579 static bool
580 nir_accepts_inot(nir_op op, unsigned src)
581 {
582 switch (op) {
583 case nir_op_ior:
584 case nir_op_iand: /* TODO: b2f16 */
585 case nir_op_ixor:
586 return true;
587 case nir_op_b32csel:
588 /* Only the condition */
589 return (src == 0);
590 default:
591 return false;
592 }
593 }
594
595 static bool
596 mir_accept_dest_mod(compiler_context *ctx, nir_dest **dest, nir_op op)
597 {
598 if (pan_has_dest_mod(dest, op)) {
599 assert((*dest)->is_ssa);
600 BITSET_SET(ctx->already_emitted, (*dest)->ssa.index);
601 return true;
602 }
603
604 return false;
605 }
606
607 static void
608 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool *not, bool is_int, unsigned bcast_count)
609 {
610 nir_alu_src src = instr->src[i];
611
612 if (!is_int) {
613 if (pan_has_source_mod(&src, nir_op_fneg))
614 *neg = !(*neg);
615
616 if (pan_has_source_mod(&src, nir_op_fabs))
617 *abs = true;
618 }
619
620 if (nir_accepts_inot(instr->op, i) && pan_has_source_mod(&src, nir_op_inot))
621 *not = true;
622
623 unsigned bits = nir_src_bit_size(src.src);
624
625 ins->src[to] = nir_src_index(NULL, &src.src);
626 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
627
628 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
629 ins->swizzle[to][c] = src.swizzle[
630 (!bcast_count || c < bcast_count) ? c :
631 (bcast_count - 1)];
632 }
633 }
634
635 /* Midgard features both fcsel and icsel, depending on whether you want int or
636 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
637 * we should emit an int or float csel depending on what modifiers could be
638 * placed. In the absense of modifiers, this is probably arbitrary. */
639
640 static bool
641 mir_is_bcsel_float(nir_alu_instr *instr)
642 {
643 nir_op intmods[] = {
644 nir_op_i2i8, nir_op_i2i16,
645 nir_op_i2i32, nir_op_i2i64
646 };
647
648 nir_op floatmods[] = {
649 nir_op_fabs, nir_op_fneg,
650 nir_op_f2f16, nir_op_f2f32,
651 nir_op_f2f64
652 };
653
654 nir_op floatdestmods[] = {
655 nir_op_fsat, nir_op_fsat_signed, nir_op_fclamp_pos,
656 nir_op_f2f16, nir_op_f2f32
657 };
658
659 signed score = 0;
660
661 for (unsigned i = 1; i < 3; ++i) {
662 nir_alu_src s = instr->src[i];
663 for (unsigned q = 0; q < ARRAY_SIZE(intmods); ++q) {
664 if (pan_has_source_mod(&s, intmods[q]))
665 score--;
666 }
667 }
668
669 for (unsigned i = 1; i < 3; ++i) {
670 nir_alu_src s = instr->src[i];
671 for (unsigned q = 0; q < ARRAY_SIZE(floatmods); ++q) {
672 if (pan_has_source_mod(&s, floatmods[q]))
673 score++;
674 }
675 }
676
677 for (unsigned q = 0; q < ARRAY_SIZE(floatdestmods); ++q) {
678 nir_dest *dest = &instr->dest.dest;
679 if (pan_has_dest_mod(&dest, floatdestmods[q]))
680 score++;
681 }
682
683 return (score > 0);
684 }
685
686 static void
687 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
688 {
689 nir_dest *dest = &instr->dest.dest;
690
691 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index))
692 return;
693
694 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
695 * is handled elsewhere */
696
697 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
698 midgard_emit_derivatives(ctx, instr);
699 return;
700 }
701
702 bool is_ssa = dest->is_ssa;
703
704 unsigned nr_components = nir_dest_num_components(*dest);
705 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
706 unsigned op = 0;
707
708 /* Number of components valid to check for the instruction (the rest
709 * will be forced to the last), or 0 to use as-is. Relevant as
710 * ball-type instructions have a channel count in NIR but are all vec4
711 * in Midgard */
712
713 unsigned broadcast_swizzle = 0;
714
715 /* What register mode should we operate in? */
716 midgard_reg_mode reg_mode =
717 reg_mode_for_nir(instr);
718
719 /* Should we swap arguments? */
720 bool flip_src12 = false;
721
722 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
723 unsigned dst_bitsize = nir_dest_bit_size(*dest);
724
725 switch (instr->op) {
726 ALU_CASE(fadd, fadd);
727 ALU_CASE(fmul, fmul);
728 ALU_CASE(fmin, fmin);
729 ALU_CASE(fmax, fmax);
730 ALU_CASE(imin, imin);
731 ALU_CASE(imax, imax);
732 ALU_CASE(umin, umin);
733 ALU_CASE(umax, umax);
734 ALU_CASE(ffloor, ffloor);
735 ALU_CASE(fround_even, froundeven);
736 ALU_CASE(ftrunc, ftrunc);
737 ALU_CASE(fceil, fceil);
738 ALU_CASE(fdot3, fdot3);
739 ALU_CASE(fdot4, fdot4);
740 ALU_CASE(iadd, iadd);
741 ALU_CASE(isub, isub);
742 ALU_CASE(imul, imul);
743
744 /* Zero shoved as second-arg */
745 ALU_CASE(iabs, iabsdiff);
746
747 ALU_CASE(mov, imov);
748
749 ALU_CASE_CMP(feq32, feq, false);
750 ALU_CASE_CMP(fne32, fne, false);
751 ALU_CASE_CMP(flt32, flt, false);
752 ALU_CASE_CMP(ieq32, ieq, true);
753 ALU_CASE_CMP(ine32, ine, true);
754 ALU_CASE_CMP(ilt32, ilt, true);
755 ALU_CASE_CMP(ult32, ult, false);
756
757 /* We don't have a native b2f32 instruction. Instead, like many
758 * GPUs, we exploit booleans as 0/~0 for false/true, and
759 * correspondingly AND
760 * by 1.0 to do the type conversion. For the moment, prime us
761 * to emit:
762 *
763 * iand [whatever], #0
764 *
765 * At the end of emit_alu (as MIR), we'll fix-up the constant
766 */
767
768 ALU_CASE_CMP(b2f32, iand, true);
769 ALU_CASE_CMP(b2f16, iand, true);
770 ALU_CASE_CMP(b2i32, iand, true);
771
772 /* Likewise, we don't have a dedicated f2b32 instruction, but
773 * we can do a "not equal to 0.0" test. */
774
775 ALU_CASE_CMP(f2b32, fne, false);
776 ALU_CASE_CMP(i2b32, ine, true);
777
778 ALU_CASE(frcp, frcp);
779 ALU_CASE(frsq, frsqrt);
780 ALU_CASE(fsqrt, fsqrt);
781 ALU_CASE(fexp2, fexp2);
782 ALU_CASE(flog2, flog2);
783
784 ALU_CASE(f2i64, f2i_rtz);
785 ALU_CASE(f2u64, f2u_rtz);
786 ALU_CASE(i2f64, i2f_rtz);
787 ALU_CASE(u2f64, u2f_rtz);
788
789 ALU_CASE(f2i32, f2i_rtz);
790 ALU_CASE(f2u32, f2u_rtz);
791 ALU_CASE(i2f32, i2f_rtz);
792 ALU_CASE(u2f32, u2f_rtz);
793
794 ALU_CASE(f2i16, f2i_rtz);
795 ALU_CASE(f2u16, f2u_rtz);
796 ALU_CASE(i2f16, i2f_rtz);
797 ALU_CASE(u2f16, u2f_rtz);
798
799 ALU_CASE(fsin, fsin);
800 ALU_CASE(fcos, fcos);
801
802 /* We'll get 0 in the second arg, so:
803 * ~a = ~(a | 0) = nor(a, 0) */
804 ALU_CASE(inot, inor);
805 ALU_CASE(iand, iand);
806 ALU_CASE(ior, ior);
807 ALU_CASE(ixor, ixor);
808 ALU_CASE(ishl, ishl);
809 ALU_CASE(ishr, iasr);
810 ALU_CASE(ushr, ilsr);
811
812 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
813 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
814 ALU_CASE_CMP(b32all_fequal4, fball_eq, true);
815
816 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
817 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
818 ALU_CASE_CMP(b32any_fnequal4, fbany_neq, true);
819
820 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
821 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
822 ALU_CASE_CMP(b32all_iequal4, iball_eq, true);
823
824 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
825 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
826 ALU_CASE_CMP(b32any_inequal4, ibany_neq, true);
827
828 /* Source mods will be shoved in later */
829 ALU_CASE(fabs, fmov);
830 ALU_CASE(fneg, fmov);
831 ALU_CASE(fsat, fmov);
832 ALU_CASE(fsat_signed, fmov);
833 ALU_CASE(fclamp_pos, fmov);
834
835 /* For size conversion, we use a move. Ideally though we would squash
836 * these ops together; maybe that has to happen after in NIR as part of
837 * propagation...? An earlier algebraic pass ensured we step down by
838 * only / exactly one size. If stepping down, we use a dest override to
839 * reduce the size; if stepping up, we use a larger-sized move with a
840 * half source and a sign/zero-extension modifier */
841
842 case nir_op_i2i8:
843 case nir_op_i2i16:
844 case nir_op_i2i32:
845 case nir_op_i2i64:
846 case nir_op_u2u8:
847 case nir_op_u2u16:
848 case nir_op_u2u32:
849 case nir_op_u2u64:
850 case nir_op_f2f16:
851 case nir_op_f2f32:
852 case nir_op_f2f64: {
853 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
854 instr->op == nir_op_f2f64)
855 op = midgard_alu_op_fmov;
856 else
857 op = midgard_alu_op_imov;
858
859 break;
860 }
861
862 /* For greater-or-equal, we lower to less-or-equal and flip the
863 * arguments */
864
865 case nir_op_fge:
866 case nir_op_fge32:
867 case nir_op_ige32:
868 case nir_op_uge32: {
869 op =
870 instr->op == nir_op_fge ? midgard_alu_op_fle :
871 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
872 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
873 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
874 0;
875
876 flip_src12 = true;
877 ALU_CHECK_CMP(false);
878 break;
879 }
880
881 case nir_op_b32csel: {
882 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
883 bool is_float = mir_is_bcsel_float(instr);
884 op = is_float ?
885 (mixed ? midgard_alu_op_fcsel_v : midgard_alu_op_fcsel) :
886 (mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel);
887
888 break;
889 }
890
891 default:
892 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
893 assert(0);
894 return;
895 }
896
897 /* Promote imov to fmov if it might help inline a constant */
898 if (op == midgard_alu_op_imov && nir_src_is_const(instr->src[0].src)
899 && nir_src_bit_size(instr->src[0].src) == 32
900 && nir_is_same_comp_swizzle(instr->src[0].swizzle,
901 nir_src_num_components(instr->src[0].src))) {
902 op = midgard_alu_op_fmov;
903 }
904
905 /* Midgard can perform certain modifiers on output of an ALU op */
906
907 unsigned outmod = 0;
908 bool is_int = midgard_is_integer_op(op);
909
910 if (midgard_is_integer_out_op(op)) {
911 outmod = midgard_outmod_int_wrap;
912 } else if (instr->op == nir_op_fsat) {
913 outmod = midgard_outmod_sat;
914 } else if (instr->op == nir_op_fsat_signed) {
915 outmod = midgard_outmod_sat_signed;
916 } else if (instr->op == nir_op_fclamp_pos) {
917 outmod = midgard_outmod_pos;
918 }
919
920 /* Fetch unit, quirks, etc information */
921 unsigned opcode_props = alu_opcode_props[op].props;
922 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
923
924 /* Look for floating point mods. We have the mods fsat, fsat_signed,
925 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
926 *
927 * fsat_signed(fpos(x)) = fsat(x)
928 * fsat_signed(fsat(x)) = fsat(x)
929 * fpos(fsat_signed(x)) = fsat(x)
930 * fpos(fsat(x)) = fsat(x)
931 * fsat(fsat_signed(x)) = fsat(x)
932 * fsat(fpos(x)) = fsat(x)
933 *
934 * So by cases any composition of output modifiers is equivalent to
935 * fsat alone.
936 */
937
938 if (!is_int && !(opcode_props & OP_TYPE_CONVERT)) {
939 bool fpos = mir_accept_dest_mod(ctx, &dest, nir_op_fclamp_pos);
940 bool fsat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat);
941 bool ssat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat_signed);
942 bool prior = (outmod != midgard_outmod_none);
943 int count = (int) prior + (int) fpos + (int) ssat + (int) fsat;
944
945 outmod = ((count > 1) || fsat) ? midgard_outmod_sat :
946 fpos ? midgard_outmod_pos :
947 ssat ? midgard_outmod_sat_signed :
948 outmod;
949 }
950
951 midgard_instruction ins = {
952 .type = TAG_ALU_4,
953 .dest = nir_dest_index(dest),
954 .dest_type = nir_op_infos[instr->op].output_type
955 | nir_dest_bit_size(*dest),
956 };
957
958 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
959 ins.src[i] = ~0;
960
961 if (quirk_flipped_r24) {
962 ins.src[0] = ~0;
963 mir_copy_src(&ins, instr, 0, 1, &ins.src_abs[1], &ins.src_neg[1], &ins.src_invert[1], is_int, broadcast_swizzle);
964 } else {
965 for (unsigned i = 0; i < nr_inputs; ++i) {
966 unsigned to = i;
967
968 if (instr->op == nir_op_b32csel) {
969 /* The condition is the first argument; move
970 * the other arguments up one to be a binary
971 * instruction for Midgard with the condition
972 * last */
973
974 if (i == 0)
975 to = 2;
976 else if (flip_src12)
977 to = 2 - i;
978 else
979 to = i - 1;
980 } else if (flip_src12) {
981 to = 1 - to;
982 }
983
984 mir_copy_src(&ins, instr, i, to, &ins.src_abs[to], &ins.src_neg[to], &ins.src_invert[to], is_int, broadcast_swizzle);
985
986 /* (!c) ? a : b = c ? b : a */
987 if (instr->op == nir_op_b32csel && ins.src_invert[2]) {
988 ins.src_invert[2] = false;
989 flip_src12 ^= true;
990 }
991 }
992 }
993
994 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
995 /* Lowered to move */
996 if (instr->op == nir_op_fneg)
997 ins.src_neg[1] ^= true;
998
999 if (instr->op == nir_op_fabs)
1000 ins.src_abs[1] = true;
1001 }
1002
1003 ins.mask = mask_of(nr_components);
1004
1005 midgard_vector_alu alu = {
1006 .op = op,
1007 .reg_mode = reg_mode,
1008 .outmod = outmod,
1009 };
1010
1011 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1012 * components that don't exist. Note modifier => SSA => !reg => no
1013 * writemask, so we don't have to worry about writemasks here.*/
1014
1015 if (!is_ssa)
1016 ins.mask &= instr->dest.write_mask;
1017
1018 ins.alu = alu;
1019
1020 /* Late fixup for emulated instructions */
1021
1022 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1023 /* Presently, our second argument is an inline #0 constant.
1024 * Switch over to an embedded 1.0 constant (that can't fit
1025 * inline, since we're 32-bit, not 16-bit like the inline
1026 * constants) */
1027
1028 ins.has_inline_constant = false;
1029 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1030 ins.src_types[1] = nir_type_float32;
1031 ins.has_constants = true;
1032
1033 if (instr->op == nir_op_b2f32)
1034 ins.constants.f32[0] = 1.0f;
1035 else
1036 ins.constants.i32[0] = 1;
1037
1038 for (unsigned c = 0; c < 16; ++c)
1039 ins.swizzle[1][c] = 0;
1040 } else if (instr->op == nir_op_b2f16) {
1041 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1042 ins.src_types[1] = nir_type_float16;
1043 ins.has_constants = true;
1044 ins.constants.i16[0] = _mesa_float_to_half(1.0);
1045
1046 for (unsigned c = 0; c < 16; ++c)
1047 ins.swizzle[1][c] = 0;
1048 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1049 /* Lots of instructions need a 0 plonked in */
1050 ins.has_inline_constant = false;
1051 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1052 ins.src_types[1] = nir_type_uint32;
1053 ins.has_constants = true;
1054 ins.constants.u32[0] = 0;
1055
1056 for (unsigned c = 0; c < 16; ++c)
1057 ins.swizzle[1][c] = 0;
1058 }
1059
1060 /* Arrange for creation of iandnot/iornot */
1061 if (ins.src_invert[0] && !ins.src_invert[1]) {
1062 mir_flip(&ins);
1063 ins.src_invert[0] = false;
1064 ins.src_invert[1] = true;
1065 }
1066
1067 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1068 /* To avoid duplicating the lookup tables (probably), true LUT
1069 * instructions can only operate as if they were scalars. Lower
1070 * them here by changing the component. */
1071
1072 unsigned orig_mask = ins.mask;
1073
1074 unsigned swizzle_back[MIR_VEC_COMPONENTS];
1075 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
1076
1077 for (int i = 0; i < nr_components; ++i) {
1078 /* Mask the associated component, dropping the
1079 * instruction if needed */
1080
1081 ins.mask = 1 << i;
1082 ins.mask &= orig_mask;
1083
1084 if (!ins.mask)
1085 continue;
1086
1087 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1088 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1089
1090 emit_mir_instruction(ctx, ins);
1091 }
1092 } else {
1093 emit_mir_instruction(ctx, ins);
1094 }
1095 }
1096
1097 #undef ALU_CASE
1098
1099 static void
1100 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1101 {
1102 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1103 unsigned nir_mask = 0;
1104 unsigned dsize = 0;
1105
1106 if (is_read) {
1107 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1108 dsize = nir_dest_bit_size(intr->dest);
1109 } else {
1110 nir_mask = nir_intrinsic_write_mask(intr);
1111 dsize = 32;
1112 }
1113
1114 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1115 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1116 mir_set_bytemask(ins, bytemask);
1117
1118 if (dsize == 64)
1119 ins->load_64 = true;
1120 }
1121
1122 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1123 * optimized) versions of UBO #0 */
1124
1125 static midgard_instruction *
1126 emit_ubo_read(
1127 compiler_context *ctx,
1128 nir_instr *instr,
1129 unsigned dest,
1130 unsigned offset,
1131 nir_src *indirect_offset,
1132 unsigned indirect_shift,
1133 unsigned index)
1134 {
1135 /* TODO: half-floats */
1136
1137 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1138 ins.constants.u32[0] = offset;
1139
1140 if (instr->type == nir_instr_type_intrinsic)
1141 mir_set_intr_mask(instr, &ins, true);
1142
1143 if (indirect_offset) {
1144 ins.src[2] = nir_src_index(ctx, indirect_offset);
1145 ins.src_types[2] = nir_type_uint32;
1146 ins.load_store.arg_2 = (indirect_shift << 5);
1147 } else {
1148 ins.load_store.arg_2 = 0x1E;
1149 }
1150
1151 ins.load_store.arg_1 = index;
1152
1153 return emit_mir_instruction(ctx, ins);
1154 }
1155
1156 /* Globals are like UBOs if you squint. And shared memory is like globals if
1157 * you squint even harder */
1158
1159 static void
1160 emit_global(
1161 compiler_context *ctx,
1162 nir_instr *instr,
1163 bool is_read,
1164 unsigned srcdest,
1165 nir_src *offset,
1166 bool is_shared)
1167 {
1168 /* TODO: types */
1169
1170 midgard_instruction ins;
1171
1172 if (is_read)
1173 ins = m_ld_int4(srcdest, 0);
1174 else
1175 ins = m_st_int4(srcdest, 0);
1176
1177 mir_set_offset(ctx, &ins, offset, is_shared);
1178 mir_set_intr_mask(instr, &ins, is_read);
1179
1180 emit_mir_instruction(ctx, ins);
1181 }
1182
1183 static void
1184 emit_varying_read(
1185 compiler_context *ctx,
1186 unsigned dest, unsigned offset,
1187 unsigned nr_comp, unsigned component,
1188 nir_src *indirect_offset, nir_alu_type type, bool flat)
1189 {
1190 /* XXX: Half-floats? */
1191 /* TODO: swizzle, mask */
1192
1193 midgard_instruction ins = m_ld_vary_32(dest, offset);
1194 ins.mask = mask_of(nr_comp);
1195
1196 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1197 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1198
1199 midgard_varying_parameter p = {
1200 .is_varying = 1,
1201 .interpolation = midgard_interp_default,
1202 .flat = flat,
1203 };
1204
1205 unsigned u;
1206 memcpy(&u, &p, sizeof(p));
1207 ins.load_store.varying_parameters = u;
1208
1209 if (indirect_offset) {
1210 ins.src[2] = nir_src_index(ctx, indirect_offset);
1211 ins.src_types[2] = nir_type_uint32;
1212 } else
1213 ins.load_store.arg_2 = 0x1E;
1214
1215 ins.load_store.arg_1 = 0x9E;
1216
1217 /* Use the type appropriate load */
1218 switch (type) {
1219 case nir_type_uint:
1220 case nir_type_bool:
1221 ins.load_store.op = midgard_op_ld_vary_32u;
1222 break;
1223 case nir_type_int:
1224 ins.load_store.op = midgard_op_ld_vary_32i;
1225 break;
1226 case nir_type_float:
1227 ins.load_store.op = midgard_op_ld_vary_32;
1228 break;
1229 default:
1230 unreachable("Attempted to load unknown type");
1231 break;
1232 }
1233
1234 emit_mir_instruction(ctx, ins);
1235 }
1236
1237 static void
1238 emit_attr_read(
1239 compiler_context *ctx,
1240 unsigned dest, unsigned offset,
1241 unsigned nr_comp, nir_alu_type t)
1242 {
1243 midgard_instruction ins = m_ld_attr_32(dest, offset);
1244 ins.load_store.arg_1 = 0x1E;
1245 ins.load_store.arg_2 = 0x1E;
1246 ins.mask = mask_of(nr_comp);
1247
1248 /* Use the type appropriate load */
1249 switch (t) {
1250 case nir_type_uint:
1251 case nir_type_bool:
1252 ins.load_store.op = midgard_op_ld_attr_32u;
1253 break;
1254 case nir_type_int:
1255 ins.load_store.op = midgard_op_ld_attr_32i;
1256 break;
1257 case nir_type_float:
1258 ins.load_store.op = midgard_op_ld_attr_32;
1259 break;
1260 default:
1261 unreachable("Attempted to load unknown type");
1262 break;
1263 }
1264
1265 emit_mir_instruction(ctx, ins);
1266 }
1267
1268 static void
1269 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1270 unsigned nr_components, unsigned offset)
1271 {
1272 nir_dest nir_dest;
1273
1274 /* Figure out which uniform this is */
1275 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1276 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1277
1278 unsigned dest = nir_dest_index(&nir_dest);
1279
1280 /* Sysvals are prefix uniforms */
1281 unsigned uniform = ((uintptr_t) val) - 1;
1282
1283 /* Emit the read itself -- this is never indirect */
1284 midgard_instruction *ins =
1285 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1286
1287 ins->mask = mask_of(nr_components);
1288 }
1289
1290 static unsigned
1291 compute_builtin_arg(nir_op op)
1292 {
1293 switch (op) {
1294 case nir_intrinsic_load_work_group_id:
1295 return 0x14;
1296 case nir_intrinsic_load_local_invocation_id:
1297 return 0x10;
1298 default:
1299 unreachable("Invalid compute paramater loaded");
1300 }
1301 }
1302
1303 static void
1304 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1305 {
1306 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1307
1308 midgard_instruction *br = ctx->writeout_branch[rt];
1309
1310 assert(!br);
1311
1312 emit_explicit_constant(ctx, src, src);
1313
1314 struct midgard_instruction ins =
1315 v_branch(false, false);
1316
1317 ins.writeout = true;
1318
1319 /* Add dependencies */
1320 ins.src[0] = src;
1321 ins.src_types[0] = nir_type_uint32;
1322 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1323 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1324
1325 /* Emit the branch */
1326 br = emit_mir_instruction(ctx, ins);
1327 schedule_barrier(ctx);
1328 ctx->writeout_branch[rt] = br;
1329
1330 /* Push our current location = current block count - 1 = where we'll
1331 * jump to. Maybe a bit too clever for my own good */
1332
1333 br->branch.target_block = ctx->block_count - 1;
1334 }
1335
1336 static void
1337 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1338 {
1339 unsigned reg = nir_dest_index(&instr->dest);
1340 midgard_instruction ins = m_ld_compute_id(reg, 0);
1341 ins.mask = mask_of(3);
1342 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1343 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1344 emit_mir_instruction(ctx, ins);
1345 }
1346
1347 static unsigned
1348 vertex_builtin_arg(nir_op op)
1349 {
1350 switch (op) {
1351 case nir_intrinsic_load_vertex_id:
1352 return PAN_VERTEX_ID;
1353 case nir_intrinsic_load_instance_id:
1354 return PAN_INSTANCE_ID;
1355 default:
1356 unreachable("Invalid vertex builtin");
1357 }
1358 }
1359
1360 static void
1361 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1362 {
1363 unsigned reg = nir_dest_index(&instr->dest);
1364 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1365 }
1366
1367 static void
1368 emit_control_barrier(compiler_context *ctx)
1369 {
1370 midgard_instruction ins = {
1371 .type = TAG_TEXTURE_4,
1372 .src = { ~0, ~0, ~0, ~0 },
1373 .texture = {
1374 .op = TEXTURE_OP_BARRIER,
1375
1376 /* TODO: optimize */
1377 .barrier_buffer = 1,
1378 .barrier_shared = 1
1379 }
1380 };
1381
1382 emit_mir_instruction(ctx, ins);
1383 }
1384
1385 static const nir_variable *
1386 search_var(struct exec_list *vars, unsigned driver_loc)
1387 {
1388 nir_foreach_variable(var, vars) {
1389 if (var->data.driver_location == driver_loc)
1390 return var;
1391 }
1392
1393 return NULL;
1394 }
1395
1396 static unsigned
1397 mir_get_branch_cond(nir_src *src, bool *invert)
1398 {
1399 /* Wrap it. No swizzle since it's a scalar */
1400
1401 nir_alu_src alu = {
1402 .src = *src
1403 };
1404
1405 *invert = pan_has_source_mod(&alu, nir_op_inot);
1406 return nir_src_index(NULL, &alu.src);
1407 }
1408
1409 static void
1410 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1411 {
1412 unsigned offset = 0, reg;
1413
1414 switch (instr->intrinsic) {
1415 case nir_intrinsic_discard_if:
1416 case nir_intrinsic_discard: {
1417 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1418 struct midgard_instruction discard = v_branch(conditional, false);
1419 discard.branch.target_type = TARGET_DISCARD;
1420
1421 if (conditional) {
1422 discard.src[0] = mir_get_branch_cond(&instr->src[0],
1423 &discard.branch.invert_conditional);
1424 discard.src_types[0] = nir_type_uint32;
1425 }
1426
1427 emit_mir_instruction(ctx, discard);
1428 schedule_barrier(ctx);
1429
1430 break;
1431 }
1432
1433 case nir_intrinsic_load_uniform:
1434 case nir_intrinsic_load_ubo:
1435 case nir_intrinsic_load_global:
1436 case nir_intrinsic_load_shared:
1437 case nir_intrinsic_load_input:
1438 case nir_intrinsic_load_interpolated_input: {
1439 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1440 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1441 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1442 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1443 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1444 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1445
1446 /* Get the base type of the intrinsic */
1447 /* TODO: Infer type? Does it matter? */
1448 nir_alu_type t =
1449 (is_ubo || is_global || is_shared) ? nir_type_uint :
1450 (is_interp) ? nir_type_float :
1451 nir_intrinsic_type(instr);
1452
1453 t = nir_alu_type_get_base_type(t);
1454
1455 if (!(is_ubo || is_global)) {
1456 offset = nir_intrinsic_base(instr);
1457 }
1458
1459 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1460
1461 nir_src *src_offset = nir_get_io_offset_src(instr);
1462
1463 bool direct = nir_src_is_const(*src_offset);
1464 nir_src *indirect_offset = direct ? NULL : src_offset;
1465
1466 if (direct)
1467 offset += nir_src_as_uint(*src_offset);
1468
1469 /* We may need to apply a fractional offset */
1470 int component = (is_flat || is_interp) ?
1471 nir_intrinsic_component(instr) : 0;
1472 reg = nir_dest_index(&instr->dest);
1473
1474 if (is_uniform && !ctx->is_blend) {
1475 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1476 } else if (is_ubo) {
1477 nir_src index = instr->src[0];
1478
1479 /* TODO: Is indirect block number possible? */
1480 assert(nir_src_is_const(index));
1481
1482 uint32_t uindex = nir_src_as_uint(index) + 1;
1483 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1484 } else if (is_global || is_shared) {
1485 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1486 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1487 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1488 } else if (ctx->is_blend) {
1489 /* For blend shaders, load the input color, which is
1490 * preloaded to r0 */
1491
1492 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1493 emit_mir_instruction(ctx, move);
1494 schedule_barrier(ctx);
1495 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1496 emit_attr_read(ctx, reg, offset, nr_comp, t);
1497 } else {
1498 DBG("Unknown load\n");
1499 assert(0);
1500 }
1501
1502 break;
1503 }
1504
1505 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1506 case nir_intrinsic_load_barycentric_pixel:
1507 case nir_intrinsic_load_barycentric_centroid:
1508 break;
1509
1510 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1511
1512 case nir_intrinsic_load_raw_output_pan:
1513 case nir_intrinsic_load_output_u8_as_fp16_pan:
1514 reg = nir_dest_index(&instr->dest);
1515 assert(ctx->is_blend);
1516
1517 /* T720 and below use different blend opcodes with slightly
1518 * different semantics than T760 and up */
1519
1520 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1521 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1522
1523 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1524 ld.load_store.op = old_blend ?
1525 midgard_op_ld_color_buffer_u8_as_fp16_old :
1526 midgard_op_ld_color_buffer_u8_as_fp16;
1527
1528 if (old_blend) {
1529 ld.load_store.address = 1;
1530 ld.load_store.arg_2 = 0x1E;
1531 }
1532
1533 for (unsigned c = 4; c < 16; ++c)
1534 ld.swizzle[0][c] = 0;
1535
1536 ld.dest_type = nir_type_float16;
1537 }
1538
1539 emit_mir_instruction(ctx, ld);
1540 break;
1541
1542 case nir_intrinsic_load_blend_const_color_rgba: {
1543 assert(ctx->is_blend);
1544 reg = nir_dest_index(&instr->dest);
1545
1546 /* Blend constants are embedded directly in the shader and
1547 * patched in, so we use some magic routing */
1548
1549 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1550 ins.has_constants = true;
1551 ins.has_blend_constant = true;
1552 emit_mir_instruction(ctx, ins);
1553 break;
1554 }
1555
1556 case nir_intrinsic_store_zs_output_pan: {
1557 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1558 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1559 MIDGARD_ZS_RT);
1560
1561 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1562
1563 if (!nir_intrinsic_component(instr))
1564 br->writeout_depth = true;
1565 if (nir_intrinsic_component(instr) ||
1566 instr->num_components)
1567 br->writeout_stencil = true;
1568 assert(br->writeout_depth | br->writeout_stencil);
1569 break;
1570 }
1571
1572 case nir_intrinsic_store_output:
1573 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1574
1575 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1576
1577 reg = nir_src_index(ctx, &instr->src[0]);
1578
1579 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1580 const nir_variable *var;
1581 enum midgard_rt_id rt;
1582
1583 var = search_var(&ctx->nir->outputs,
1584 nir_intrinsic_base(instr));
1585 assert(var);
1586 if (var->data.location == FRAG_RESULT_COLOR)
1587 rt = MIDGARD_COLOR_RT0;
1588 else if (var->data.location >= FRAG_RESULT_DATA0)
1589 rt = MIDGARD_COLOR_RT0 + var->data.location -
1590 FRAG_RESULT_DATA0;
1591 else
1592 assert(0);
1593
1594 emit_fragment_store(ctx, reg, rt);
1595 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1596 /* We should have been vectorized, though we don't
1597 * currently check that st_vary is emitted only once
1598 * per slot (this is relevant, since there's not a mask
1599 * parameter available on the store [set to 0 by the
1600 * blob]). We do respect the component by adjusting the
1601 * swizzle. If this is a constant source, we'll need to
1602 * emit that explicitly. */
1603
1604 emit_explicit_constant(ctx, reg, reg);
1605
1606 unsigned dst_component = nir_intrinsic_component(instr);
1607 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1608
1609 midgard_instruction st = m_st_vary_32(reg, offset);
1610 st.load_store.arg_1 = 0x9E;
1611 st.load_store.arg_2 = 0x1E;
1612
1613 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1614 case nir_type_uint:
1615 case nir_type_bool:
1616 st.load_store.op = midgard_op_st_vary_32u;
1617 break;
1618 case nir_type_int:
1619 st.load_store.op = midgard_op_st_vary_32i;
1620 break;
1621 case nir_type_float:
1622 st.load_store.op = midgard_op_st_vary_32;
1623 break;
1624 default:
1625 unreachable("Attempted to store unknown type");
1626 break;
1627 }
1628
1629 /* nir_intrinsic_component(store_intr) encodes the
1630 * destination component start. Source component offset
1631 * adjustment is taken care of in
1632 * install_registers_instr(), when offset_swizzle() is
1633 * called.
1634 */
1635 unsigned src_component = COMPONENT_X;
1636
1637 assert(nr_comp > 0);
1638 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1639 st.swizzle[0][i] = src_component;
1640 if (i >= dst_component && i < dst_component + nr_comp - 1)
1641 src_component++;
1642 }
1643
1644 emit_mir_instruction(ctx, st);
1645 } else {
1646 DBG("Unknown store\n");
1647 assert(0);
1648 }
1649
1650 break;
1651
1652 /* Special case of store_output for lowered blend shaders */
1653 case nir_intrinsic_store_raw_output_pan:
1654 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1655 reg = nir_src_index(ctx, &instr->src[0]);
1656
1657 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1658 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1659 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1660 * of:
1661 *
1662 * imov r0.xyzw, r0.xxxx
1663 */
1664
1665 unsigned expanded = make_compiler_temp(ctx);
1666
1667 midgard_instruction splatter = v_mov(reg, expanded);
1668
1669 for (unsigned c = 0; c < 16; ++c)
1670 splatter.swizzle[1][c] = 0;
1671
1672 emit_mir_instruction(ctx, splatter);
1673 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1674 } else
1675 emit_fragment_store(ctx, reg, ctx->blend_rt);
1676
1677 break;
1678
1679 case nir_intrinsic_store_global:
1680 case nir_intrinsic_store_shared:
1681 reg = nir_src_index(ctx, &instr->src[0]);
1682 emit_explicit_constant(ctx, reg, reg);
1683
1684 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1685 break;
1686
1687 case nir_intrinsic_load_ssbo_address:
1688 emit_sysval_read(ctx, &instr->instr, 1, 0);
1689 break;
1690
1691 case nir_intrinsic_get_buffer_size:
1692 emit_sysval_read(ctx, &instr->instr, 1, 8);
1693 break;
1694
1695 case nir_intrinsic_load_viewport_scale:
1696 case nir_intrinsic_load_viewport_offset:
1697 case nir_intrinsic_load_num_work_groups:
1698 case nir_intrinsic_load_sampler_lod_parameters_pan:
1699 emit_sysval_read(ctx, &instr->instr, 3, 0);
1700 break;
1701
1702 case nir_intrinsic_load_work_group_id:
1703 case nir_intrinsic_load_local_invocation_id:
1704 emit_compute_builtin(ctx, instr);
1705 break;
1706
1707 case nir_intrinsic_load_vertex_id:
1708 case nir_intrinsic_load_instance_id:
1709 emit_vertex_builtin(ctx, instr);
1710 break;
1711
1712 case nir_intrinsic_memory_barrier_buffer:
1713 case nir_intrinsic_memory_barrier_shared:
1714 break;
1715
1716 case nir_intrinsic_control_barrier:
1717 schedule_barrier(ctx);
1718 emit_control_barrier(ctx);
1719 schedule_barrier(ctx);
1720 break;
1721
1722 default:
1723 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1724 assert(0);
1725 break;
1726 }
1727 }
1728
1729 static unsigned
1730 midgard_tex_format(enum glsl_sampler_dim dim)
1731 {
1732 switch (dim) {
1733 case GLSL_SAMPLER_DIM_1D:
1734 case GLSL_SAMPLER_DIM_BUF:
1735 return MALI_TEX_1D;
1736
1737 case GLSL_SAMPLER_DIM_2D:
1738 case GLSL_SAMPLER_DIM_EXTERNAL:
1739 case GLSL_SAMPLER_DIM_RECT:
1740 return MALI_TEX_2D;
1741
1742 case GLSL_SAMPLER_DIM_3D:
1743 return MALI_TEX_3D;
1744
1745 case GLSL_SAMPLER_DIM_CUBE:
1746 return MALI_TEX_CUBE;
1747
1748 default:
1749 DBG("Unknown sampler dim type\n");
1750 assert(0);
1751 return 0;
1752 }
1753 }
1754
1755 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1756 * was successful */
1757
1758 static bool
1759 pan_attach_constant_bias(
1760 compiler_context *ctx,
1761 nir_src lod,
1762 midgard_texture_word *word)
1763 {
1764 /* To attach as constant, it has to *be* constant */
1765
1766 if (!nir_src_is_const(lod))
1767 return false;
1768
1769 float f = nir_src_as_float(lod);
1770
1771 /* Break into fixed-point */
1772 signed lod_int = f;
1773 float lod_frac = f - lod_int;
1774
1775 /* Carry over negative fractions */
1776 if (lod_frac < 0.0) {
1777 lod_int--;
1778 lod_frac += 1.0;
1779 }
1780
1781 /* Encode */
1782 word->bias = float_to_ubyte(lod_frac);
1783 word->bias_int = lod_int;
1784
1785 return true;
1786 }
1787
1788 static void
1789 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1790 unsigned midgard_texop)
1791 {
1792 /* TODO */
1793 //assert (!instr->sampler);
1794
1795 int texture_index = instr->texture_index;
1796 int sampler_index = texture_index;
1797
1798 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1799 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1800
1801 midgard_instruction ins = {
1802 .type = TAG_TEXTURE_4,
1803 .mask = 0xF,
1804 .dest = nir_dest_index(&instr->dest),
1805 .src = { ~0, ~0, ~0, ~0 },
1806 .dest_type = dest_type,
1807 .swizzle = SWIZZLE_IDENTITY_4,
1808 .texture = {
1809 .op = midgard_texop,
1810 .format = midgard_tex_format(instr->sampler_dim),
1811 .texture_handle = texture_index,
1812 .sampler_handle = sampler_index,
1813 .shadow = instr->is_shadow,
1814 }
1815 };
1816
1817 if (instr->is_shadow && !instr->is_new_style_shadow)
1818 for (int i = 0; i < 4; ++i)
1819 ins.swizzle[0][i] = COMPONENT_X;
1820
1821 /* We may need a temporary for the coordinate */
1822
1823 bool needs_temp_coord =
1824 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1825 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1826 (instr->is_shadow);
1827
1828 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1829
1830 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1831 int index = nir_src_index(ctx, &instr->src[i].src);
1832 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1833 unsigned sz = nir_src_bit_size(instr->src[i].src);
1834 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1835
1836 switch (instr->src[i].src_type) {
1837 case nir_tex_src_coord: {
1838 emit_explicit_constant(ctx, index, index);
1839
1840 unsigned coord_mask = mask_of(instr->coord_components);
1841
1842 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1843
1844 if (flip_zw)
1845 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1846
1847 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1848 /* texelFetch is undefined on samplerCube */
1849 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1850
1851 /* For cubemaps, we use a special ld/st op to
1852 * select the face and copy the xy into the
1853 * texture register */
1854
1855 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1856 ld.src[1] = index;
1857 ld.src_types[1] = T;
1858 ld.mask = 0x3; /* xy */
1859 ld.load_store.arg_1 = 0x20;
1860 ld.swizzle[1][3] = COMPONENT_X;
1861 emit_mir_instruction(ctx, ld);
1862
1863 /* xyzw -> xyxx */
1864 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1865 ins.swizzle[1][3] = COMPONENT_X;
1866 } else if (needs_temp_coord) {
1867 /* mov coord_temp, coords */
1868 midgard_instruction mov = v_mov(index, coords);
1869 mov.mask = coord_mask;
1870
1871 if (flip_zw)
1872 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1873
1874 emit_mir_instruction(ctx, mov);
1875 } else {
1876 coords = index;
1877 }
1878
1879 ins.src[1] = coords;
1880 ins.src_types[1] = T;
1881
1882 /* Texelfetch coordinates uses all four elements
1883 * (xyz/index) regardless of texture dimensionality,
1884 * which means it's necessary to zero the unused
1885 * components to keep everything happy */
1886
1887 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1888 /* mov index.zw, #0, or generalized */
1889 midgard_instruction mov =
1890 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1891 mov.has_constants = true;
1892 mov.mask = coord_mask ^ 0xF;
1893 emit_mir_instruction(ctx, mov);
1894 }
1895
1896 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1897 /* Array component in w but NIR wants it in z,
1898 * but if we have a temp coord we already fixed
1899 * that up */
1900
1901 if (nr_components == 3) {
1902 ins.swizzle[1][2] = COMPONENT_Z;
1903 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1904 } else if (nr_components == 2) {
1905 ins.swizzle[1][2] =
1906 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1907 ins.swizzle[1][3] = COMPONENT_X;
1908 } else
1909 unreachable("Invalid texture 2D components");
1910 }
1911
1912 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1913 /* We zeroed */
1914 ins.swizzle[1][2] = COMPONENT_Z;
1915 ins.swizzle[1][3] = COMPONENT_W;
1916 }
1917
1918 break;
1919 }
1920
1921 case nir_tex_src_bias:
1922 case nir_tex_src_lod: {
1923 /* Try as a constant if we can */
1924
1925 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1926 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1927 break;
1928
1929 ins.texture.lod_register = true;
1930 ins.src[2] = index;
1931 ins.src_types[2] = T;
1932
1933 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1934 ins.swizzle[2][c] = COMPONENT_X;
1935
1936 emit_explicit_constant(ctx, index, index);
1937
1938 break;
1939 };
1940
1941 case nir_tex_src_offset: {
1942 ins.texture.offset_register = true;
1943 ins.src[3] = index;
1944 ins.src_types[3] = T;
1945
1946 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1947 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
1948
1949 emit_explicit_constant(ctx, index, index);
1950 break;
1951 };
1952
1953 case nir_tex_src_comparator: {
1954 unsigned comp = COMPONENT_Z;
1955
1956 /* mov coord_temp.foo, coords */
1957 midgard_instruction mov = v_mov(index, coords);
1958 mov.mask = 1 << comp;
1959
1960 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
1961 mov.swizzle[1][i] = COMPONENT_X;
1962
1963 emit_mir_instruction(ctx, mov);
1964 break;
1965 }
1966
1967 default: {
1968 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
1969 assert(0);
1970 }
1971 }
1972 }
1973
1974 emit_mir_instruction(ctx, ins);
1975 }
1976
1977 static void
1978 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1979 {
1980 switch (instr->op) {
1981 case nir_texop_tex:
1982 case nir_texop_txb:
1983 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
1984 break;
1985 case nir_texop_txl:
1986 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
1987 break;
1988 case nir_texop_txf:
1989 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
1990 break;
1991 case nir_texop_txs:
1992 emit_sysval_read(ctx, &instr->instr, 4, 0);
1993 break;
1994 default: {
1995 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
1996 assert(0);
1997 }
1998 }
1999 }
2000
2001 static void
2002 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
2003 {
2004 switch (instr->type) {
2005 case nir_jump_break: {
2006 /* Emit a branch out of the loop */
2007 struct midgard_instruction br = v_branch(false, false);
2008 br.branch.target_type = TARGET_BREAK;
2009 br.branch.target_break = ctx->current_loop_depth;
2010 emit_mir_instruction(ctx, br);
2011 break;
2012 }
2013
2014 default:
2015 DBG("Unknown jump type %d\n", instr->type);
2016 break;
2017 }
2018 }
2019
2020 static void
2021 emit_instr(compiler_context *ctx, struct nir_instr *instr)
2022 {
2023 switch (instr->type) {
2024 case nir_instr_type_load_const:
2025 emit_load_const(ctx, nir_instr_as_load_const(instr));
2026 break;
2027
2028 case nir_instr_type_intrinsic:
2029 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2030 break;
2031
2032 case nir_instr_type_alu:
2033 emit_alu(ctx, nir_instr_as_alu(instr));
2034 break;
2035
2036 case nir_instr_type_tex:
2037 emit_tex(ctx, nir_instr_as_tex(instr));
2038 break;
2039
2040 case nir_instr_type_jump:
2041 emit_jump(ctx, nir_instr_as_jump(instr));
2042 break;
2043
2044 case nir_instr_type_ssa_undef:
2045 /* Spurious */
2046 break;
2047
2048 default:
2049 DBG("Unhandled instruction type\n");
2050 break;
2051 }
2052 }
2053
2054
2055 /* ALU instructions can inline or embed constants, which decreases register
2056 * pressure and saves space. */
2057
2058 #define CONDITIONAL_ATTACH(idx) { \
2059 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2060 \
2061 if (entry) { \
2062 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2063 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2064 } \
2065 }
2066
2067 static void
2068 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2069 {
2070 mir_foreach_instr_in_block(block, alu) {
2071 /* Other instructions cannot inline constants */
2072 if (alu->type != TAG_ALU_4) continue;
2073 if (alu->compact_branch) continue;
2074
2075 /* If there is already a constant here, we can do nothing */
2076 if (alu->has_constants) continue;
2077
2078 CONDITIONAL_ATTACH(0);
2079
2080 if (!alu->has_constants) {
2081 CONDITIONAL_ATTACH(1)
2082 } else if (!alu->inline_constant) {
2083 /* Corner case: _two_ vec4 constants, for instance with a
2084 * csel. For this case, we can only use a constant
2085 * register for one, we'll have to emit a move for the
2086 * other. */
2087
2088 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2089 unsigned scratch = make_compiler_temp(ctx);
2090
2091 if (entry) {
2092 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2093 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2094
2095 /* Set the source */
2096 alu->src[1] = scratch;
2097
2098 /* Inject us -before- the last instruction which set r31 */
2099 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2100 }
2101 }
2102 }
2103 }
2104
2105 /* Midgard supports two types of constants, embedded constants (128-bit) and
2106 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2107 * constants can be demoted to inline constants, for space savings and
2108 * sometimes a performance boost */
2109
2110 static void
2111 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2112 {
2113 mir_foreach_instr_in_block(block, ins) {
2114 if (!ins->has_constants) continue;
2115 if (ins->has_inline_constant) continue;
2116
2117 /* Blend constants must not be inlined by definition */
2118 if (ins->has_blend_constant) continue;
2119
2120 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2121 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2122 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2123
2124 if (!(is_16 || is_32))
2125 continue;
2126
2127 /* src1 cannot be an inline constant due to encoding
2128 * restrictions. So, if possible we try to flip the arguments
2129 * in that case */
2130
2131 int op = ins->alu.op;
2132
2133 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2134 alu_opcode_props[op].props & OP_COMMUTES) {
2135 mir_flip(ins);
2136 }
2137
2138 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2139 /* Component is from the swizzle. Take a nonzero component */
2140 assert(ins->mask);
2141 unsigned first_comp = ffs(ins->mask) - 1;
2142 unsigned component = ins->swizzle[1][first_comp];
2143
2144 /* Scale constant appropriately, if we can legally */
2145 uint16_t scaled_constant = 0;
2146
2147 if (is_16) {
2148 scaled_constant = ins->constants.u16[component];
2149 } else if (midgard_is_integer_op(op)) {
2150 scaled_constant = ins->constants.u32[component];
2151
2152 /* Constant overflow after resize */
2153 if (scaled_constant != ins->constants.u32[component])
2154 continue;
2155 } else {
2156 float original = ins->constants.f32[component];
2157 scaled_constant = _mesa_float_to_half(original);
2158
2159 /* Check for loss of precision. If this is
2160 * mediump, we don't care, but for a highp
2161 * shader, we need to pay attention. NIR
2162 * doesn't yet tell us which mode we're in!
2163 * Practically this prevents most constants
2164 * from being inlined, sadly. */
2165
2166 float fp32 = _mesa_half_to_float(scaled_constant);
2167
2168 if (fp32 != original)
2169 continue;
2170 }
2171
2172 /* Should've been const folded */
2173 if (ins->src_abs[1] || ins->src_neg[1])
2174 continue;
2175
2176 /* Make sure that the constant is not itself a vector
2177 * by checking if all accessed values are the same. */
2178
2179 const midgard_constants *cons = &ins->constants;
2180 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2181
2182 bool is_vector = false;
2183 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2184
2185 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2186 /* We only care if this component is actually used */
2187 if (!(mask & (1 << c)))
2188 continue;
2189
2190 uint32_t test = is_16 ?
2191 cons->u16[ins->swizzle[1][c]] :
2192 cons->u32[ins->swizzle[1][c]];
2193
2194 if (test != value) {
2195 is_vector = true;
2196 break;
2197 }
2198 }
2199
2200 if (is_vector)
2201 continue;
2202
2203 /* Get rid of the embedded constant */
2204 ins->has_constants = false;
2205 ins->src[1] = ~0;
2206 ins->has_inline_constant = true;
2207 ins->inline_constant = scaled_constant;
2208 }
2209 }
2210 }
2211
2212 /* Dead code elimination for branches at the end of a block - only one branch
2213 * per block is legal semantically */
2214
2215 static void
2216 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2217 {
2218 bool branched = false;
2219
2220 mir_foreach_instr_in_block_safe(block, ins) {
2221 if (!midgard_is_branch_unit(ins->unit)) continue;
2222
2223 if (branched)
2224 mir_remove_instruction(ins);
2225
2226 branched = true;
2227 }
2228 }
2229
2230 static unsigned
2231 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2232 {
2233 /* Loop to ourselves */
2234 midgard_instruction *br = ctx->writeout_branch[rt];
2235 struct midgard_instruction ins = v_branch(false, false);
2236 ins.writeout = true;
2237 ins.writeout_depth = br->writeout_depth;
2238 ins.writeout_stencil = br->writeout_stencil;
2239 ins.branch.target_block = ctx->block_count - 1;
2240 ins.constants.u32[0] = br->constants.u32[0];
2241 emit_mir_instruction(ctx, ins);
2242
2243 ctx->current_block->epilogue = true;
2244 schedule_barrier(ctx);
2245 return ins.branch.target_block;
2246 }
2247
2248 static midgard_block *
2249 emit_block(compiler_context *ctx, nir_block *block)
2250 {
2251 midgard_block *this_block = ctx->after_block;
2252 ctx->after_block = NULL;
2253
2254 if (!this_block)
2255 this_block = create_empty_block(ctx);
2256
2257 list_addtail(&this_block->base.link, &ctx->blocks);
2258
2259 this_block->scheduled = false;
2260 ++ctx->block_count;
2261
2262 /* Set up current block */
2263 list_inithead(&this_block->base.instructions);
2264 ctx->current_block = this_block;
2265
2266 nir_foreach_instr(instr, block) {
2267 emit_instr(ctx, instr);
2268 ++ctx->instruction_count;
2269 }
2270
2271 return this_block;
2272 }
2273
2274 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2275
2276 static void
2277 emit_if(struct compiler_context *ctx, nir_if *nif)
2278 {
2279 midgard_block *before_block = ctx->current_block;
2280
2281 /* Speculatively emit the branch, but we can't fill it in until later */
2282 bool inv = false;
2283 EMIT(branch, true, true);
2284 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2285 then_branch->src[0] = mir_get_branch_cond(&nif->condition, &inv);
2286 then_branch->src_types[0] = nir_type_uint32;
2287 then_branch->branch.invert_conditional = !inv;
2288
2289 /* Emit the two subblocks. */
2290 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2291 midgard_block *end_then_block = ctx->current_block;
2292
2293 /* Emit a jump from the end of the then block to the end of the else */
2294 EMIT(branch, false, false);
2295 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2296
2297 /* Emit second block, and check if it's empty */
2298
2299 int else_idx = ctx->block_count;
2300 int count_in = ctx->instruction_count;
2301 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2302 midgard_block *end_else_block = ctx->current_block;
2303 int after_else_idx = ctx->block_count;
2304
2305 /* Now that we have the subblocks emitted, fix up the branches */
2306
2307 assert(then_block);
2308 assert(else_block);
2309
2310 if (ctx->instruction_count == count_in) {
2311 /* The else block is empty, so don't emit an exit jump */
2312 mir_remove_instruction(then_exit);
2313 then_branch->branch.target_block = after_else_idx;
2314 } else {
2315 then_branch->branch.target_block = else_idx;
2316 then_exit->branch.target_block = after_else_idx;
2317 }
2318
2319 /* Wire up the successors */
2320
2321 ctx->after_block = create_empty_block(ctx);
2322
2323 pan_block_add_successor(&before_block->base, &then_block->base);
2324 pan_block_add_successor(&before_block->base, &else_block->base);
2325
2326 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2327 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2328 }
2329
2330 static void
2331 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2332 {
2333 /* Remember where we are */
2334 midgard_block *start_block = ctx->current_block;
2335
2336 /* Allocate a loop number, growing the current inner loop depth */
2337 int loop_idx = ++ctx->current_loop_depth;
2338
2339 /* Get index from before the body so we can loop back later */
2340 int start_idx = ctx->block_count;
2341
2342 /* Emit the body itself */
2343 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2344
2345 /* Branch back to loop back */
2346 struct midgard_instruction br_back = v_branch(false, false);
2347 br_back.branch.target_block = start_idx;
2348 emit_mir_instruction(ctx, br_back);
2349
2350 /* Mark down that branch in the graph. */
2351 pan_block_add_successor(&start_block->base, &loop_block->base);
2352 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2353
2354 /* Find the index of the block about to follow us (note: we don't add
2355 * one; blocks are 0-indexed so we get a fencepost problem) */
2356 int break_block_idx = ctx->block_count;
2357
2358 /* Fix up the break statements we emitted to point to the right place,
2359 * now that we can allocate a block number for them */
2360 ctx->after_block = create_empty_block(ctx);
2361
2362 mir_foreach_block_from(ctx, start_block, _block) {
2363 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2364 if (ins->type != TAG_ALU_4) continue;
2365 if (!ins->compact_branch) continue;
2366
2367 /* We found a branch -- check the type to see if we need to do anything */
2368 if (ins->branch.target_type != TARGET_BREAK) continue;
2369
2370 /* It's a break! Check if it's our break */
2371 if (ins->branch.target_break != loop_idx) continue;
2372
2373 /* Okay, cool, we're breaking out of this loop.
2374 * Rewrite from a break to a goto */
2375
2376 ins->branch.target_type = TARGET_GOTO;
2377 ins->branch.target_block = break_block_idx;
2378
2379 pan_block_add_successor(_block, &ctx->after_block->base);
2380 }
2381 }
2382
2383 /* Now that we've finished emitting the loop, free up the depth again
2384 * so we play nice with recursion amid nested loops */
2385 --ctx->current_loop_depth;
2386
2387 /* Dump loop stats */
2388 ++ctx->loop_count;
2389 }
2390
2391 static midgard_block *
2392 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2393 {
2394 midgard_block *start_block = NULL;
2395
2396 foreach_list_typed(nir_cf_node, node, node, list) {
2397 switch (node->type) {
2398 case nir_cf_node_block: {
2399 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2400
2401 if (!start_block)
2402 start_block = block;
2403
2404 break;
2405 }
2406
2407 case nir_cf_node_if:
2408 emit_if(ctx, nir_cf_node_as_if(node));
2409 break;
2410
2411 case nir_cf_node_loop:
2412 emit_loop(ctx, nir_cf_node_as_loop(node));
2413 break;
2414
2415 case nir_cf_node_function:
2416 assert(0);
2417 break;
2418 }
2419 }
2420
2421 return start_block;
2422 }
2423
2424 /* Due to lookahead, we need to report the first tag executed in the command
2425 * stream and in branch targets. An initial block might be empty, so iterate
2426 * until we find one that 'works' */
2427
2428 static unsigned
2429 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2430 {
2431 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2432
2433 mir_foreach_block_from(ctx, initial_block, _v) {
2434 midgard_block *v = (midgard_block *) _v;
2435 if (v->quadword_count) {
2436 midgard_bundle *initial_bundle =
2437 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2438
2439 return initial_bundle->tag;
2440 }
2441 }
2442
2443 /* Default to a tag 1 which will break from the shader, in case we jump
2444 * to the exit block (i.e. `return` in a compute shader) */
2445
2446 return 1;
2447 }
2448
2449 /* For each fragment writeout instruction, generate a writeout loop to
2450 * associate with it */
2451
2452 static void
2453 mir_add_writeout_loops(compiler_context *ctx)
2454 {
2455 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2456 midgard_instruction *br = ctx->writeout_branch[rt];
2457 if (!br) continue;
2458
2459 unsigned popped = br->branch.target_block;
2460 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2461 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2462 br->branch.target_type = TARGET_GOTO;
2463
2464 /* If we have more RTs, we'll need to restore back after our
2465 * loop terminates */
2466
2467 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2468 midgard_instruction uncond = v_branch(false, false);
2469 uncond.branch.target_block = popped;
2470 uncond.branch.target_type = TARGET_GOTO;
2471 emit_mir_instruction(ctx, uncond);
2472 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2473 schedule_barrier(ctx);
2474 } else {
2475 /* We're last, so we can terminate here */
2476 br->last_writeout = true;
2477 }
2478 }
2479 }
2480
2481 int
2482 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2483 {
2484 struct util_dynarray *compiled = &program->compiled;
2485
2486 midgard_debug = debug_get_option_midgard_debug();
2487
2488 /* TODO: Bound against what? */
2489 compiler_context *ctx = rzalloc(NULL, compiler_context);
2490
2491 ctx->nir = nir;
2492 ctx->stage = nir->info.stage;
2493 ctx->is_blend = is_blend;
2494 ctx->alpha_ref = program->alpha_ref;
2495 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2496 ctx->quirks = midgard_get_quirks(gpu_id);
2497
2498 /* Start off with a safe cutoff, allowing usage of all 16 work
2499 * registers. Later, we'll promote uniform reads to uniform registers
2500 * if we determine it is beneficial to do so */
2501 ctx->uniform_cutoff = 8;
2502
2503 /* Initialize at a global (not block) level hash tables */
2504
2505 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2506 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2507
2508 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2509 * (so we don't accidentally duplicate the epilogue since mesa/st has
2510 * messed with our I/O quite a bit already) */
2511
2512 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2513
2514 if (ctx->stage == MESA_SHADER_VERTEX) {
2515 NIR_PASS_V(nir, nir_lower_viewport_transform);
2516 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2517 }
2518
2519 NIR_PASS_V(nir, nir_lower_var_copies);
2520 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2521 NIR_PASS_V(nir, nir_split_var_copies);
2522 NIR_PASS_V(nir, nir_lower_var_copies);
2523 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2524 NIR_PASS_V(nir, nir_lower_var_copies);
2525 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2526
2527 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2528 NIR_PASS_V(nir, nir_lower_ssbo);
2529 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2530
2531 /* Optimisation passes */
2532
2533 optimise_nir(nir, ctx->quirks);
2534
2535 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2536 nir_print_shader(nir, stdout);
2537 }
2538
2539 /* Assign sysvals and counts, now that we're sure
2540 * (post-optimisation) */
2541
2542 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2543 program->sysval_count = ctx->sysvals.sysval_count;
2544 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2545
2546 nir_foreach_function(func, nir) {
2547 if (!func->impl)
2548 continue;
2549
2550 list_inithead(&ctx->blocks);
2551 ctx->block_count = 0;
2552 ctx->func = func;
2553 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
2554
2555 emit_cf_list(ctx, &func->impl->body);
2556 free(ctx->already_emitted);
2557 break; /* TODO: Multi-function shaders */
2558 }
2559
2560 util_dynarray_init(compiled, NULL);
2561
2562 /* Per-block lowering before opts */
2563
2564 mir_foreach_block(ctx, _block) {
2565 midgard_block *block = (midgard_block *) _block;
2566 inline_alu_constants(ctx, block);
2567 embedded_to_inline_constant(ctx, block);
2568 }
2569 /* MIR-level optimizations */
2570
2571 bool progress = false;
2572
2573 do {
2574 progress = false;
2575 progress |= midgard_opt_dead_code_eliminate(ctx);
2576
2577 mir_foreach_block(ctx, _block) {
2578 midgard_block *block = (midgard_block *) _block;
2579 progress |= midgard_opt_copy_prop(ctx, block);
2580 progress |= midgard_opt_combine_projection(ctx, block);
2581 progress |= midgard_opt_varying_projection(ctx, block);
2582 }
2583 } while (progress);
2584
2585 mir_foreach_block(ctx, _block) {
2586 midgard_block *block = (midgard_block *) _block;
2587 midgard_lower_derivatives(ctx, block);
2588 midgard_cull_dead_branch(ctx, block);
2589 }
2590
2591 if (ctx->stage == MESA_SHADER_FRAGMENT)
2592 mir_add_writeout_loops(ctx);
2593
2594 /* Analyze now that the code is known but before scheduling creates
2595 * pipeline registers which are harder to track */
2596 mir_analyze_helper_terminate(ctx);
2597 mir_analyze_helper_requirements(ctx);
2598
2599 /* Schedule! */
2600 midgard_schedule_program(ctx);
2601 mir_ra(ctx);
2602
2603 /* Now that all the bundles are scheduled and we can calculate block
2604 * sizes, emit actual branch instructions rather than placeholders */
2605
2606 int br_block_idx = 0;
2607
2608 mir_foreach_block(ctx, _block) {
2609 midgard_block *block = (midgard_block *) _block;
2610 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2611 for (int c = 0; c < bundle->instruction_count; ++c) {
2612 midgard_instruction *ins = bundle->instructions[c];
2613
2614 if (!midgard_is_branch_unit(ins->unit)) continue;
2615
2616 /* Parse some basic branch info */
2617 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2618 bool is_conditional = ins->branch.conditional;
2619 bool is_inverted = ins->branch.invert_conditional;
2620 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2621 bool is_writeout = ins->writeout;
2622
2623 /* Determine the block we're jumping to */
2624 int target_number = ins->branch.target_block;
2625
2626 /* Report the destination tag */
2627 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2628
2629 /* Count up the number of quadwords we're
2630 * jumping over = number of quadwords until
2631 * (br_block_idx, target_number) */
2632
2633 int quadword_offset = 0;
2634
2635 if (is_discard) {
2636 /* Ignored */
2637 } else if (target_number > br_block_idx) {
2638 /* Jump forward */
2639
2640 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2641 midgard_block *blk = mir_get_block(ctx, idx);
2642 assert(blk);
2643
2644 quadword_offset += blk->quadword_count;
2645 }
2646 } else {
2647 /* Jump backwards */
2648
2649 for (int idx = br_block_idx; idx >= target_number; --idx) {
2650 midgard_block *blk = mir_get_block(ctx, idx);
2651 assert(blk);
2652
2653 quadword_offset -= blk->quadword_count;
2654 }
2655 }
2656
2657 /* Unconditional extended branches (far jumps)
2658 * have issues, so we always use a conditional
2659 * branch, setting the condition to always for
2660 * unconditional. For compact unconditional
2661 * branches, cond isn't used so it doesn't
2662 * matter what we pick. */
2663
2664 midgard_condition cond =
2665 !is_conditional ? midgard_condition_always :
2666 is_inverted ? midgard_condition_false :
2667 midgard_condition_true;
2668
2669 midgard_jmp_writeout_op op =
2670 is_discard ? midgard_jmp_writeout_op_discard :
2671 is_writeout ? midgard_jmp_writeout_op_writeout :
2672 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2673 midgard_jmp_writeout_op_branch_cond;
2674
2675 if (!is_compact) {
2676 midgard_branch_extended branch =
2677 midgard_create_branch_extended(
2678 cond, op,
2679 dest_tag,
2680 quadword_offset);
2681
2682 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2683 } else if (is_conditional || is_discard) {
2684 midgard_branch_cond branch = {
2685 .op = op,
2686 .dest_tag = dest_tag,
2687 .offset = quadword_offset,
2688 .cond = cond
2689 };
2690
2691 assert(branch.offset == quadword_offset);
2692
2693 memcpy(&ins->br_compact, &branch, sizeof(branch));
2694 } else {
2695 assert(op == midgard_jmp_writeout_op_branch_uncond);
2696
2697 midgard_branch_uncond branch = {
2698 .op = op,
2699 .dest_tag = dest_tag,
2700 .offset = quadword_offset,
2701 .unknown = 1
2702 };
2703
2704 assert(branch.offset == quadword_offset);
2705
2706 memcpy(&ins->br_compact, &branch, sizeof(branch));
2707 }
2708 }
2709 }
2710
2711 ++br_block_idx;
2712 }
2713
2714 /* Emit flat binary from the instruction arrays. Iterate each block in
2715 * sequence. Save instruction boundaries such that lookahead tags can
2716 * be assigned easily */
2717
2718 /* Cache _all_ bundles in source order for lookahead across failed branches */
2719
2720 int bundle_count = 0;
2721 mir_foreach_block(ctx, _block) {
2722 midgard_block *block = (midgard_block *) _block;
2723 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2724 }
2725 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2726 int bundle_idx = 0;
2727 mir_foreach_block(ctx, _block) {
2728 midgard_block *block = (midgard_block *) _block;
2729 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2730 source_order_bundles[bundle_idx++] = bundle;
2731 }
2732 }
2733
2734 int current_bundle = 0;
2735
2736 /* Midgard prefetches instruction types, so during emission we
2737 * need to lookahead. Unless this is the last instruction, in
2738 * which we return 1. */
2739
2740 mir_foreach_block(ctx, _block) {
2741 midgard_block *block = (midgard_block *) _block;
2742 mir_foreach_bundle_in_block(block, bundle) {
2743 int lookahead = 1;
2744
2745 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2746 lookahead = source_order_bundles[current_bundle + 1]->tag;
2747
2748 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2749 ++current_bundle;
2750 }
2751
2752 /* TODO: Free deeper */
2753 //util_dynarray_fini(&block->instructions);
2754 }
2755
2756 free(source_order_bundles);
2757
2758 /* Report the very first tag executed */
2759 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2760
2761 /* Deal with off-by-one related to the fencepost problem */
2762 program->work_register_count = ctx->work_registers + 1;
2763 program->uniform_cutoff = ctx->uniform_cutoff;
2764
2765 program->blend_patch_offset = ctx->blend_constant_offset;
2766 program->tls_size = ctx->tls_size;
2767
2768 if (midgard_debug & MIDGARD_DBG_SHADERS)
2769 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2770
2771 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2772 unsigned nr_bundles = 0, nr_ins = 0;
2773
2774 /* Count instructions and bundles */
2775
2776 mir_foreach_block(ctx, _block) {
2777 midgard_block *block = (midgard_block *) _block;
2778 nr_bundles += util_dynarray_num_elements(
2779 &block->bundles, midgard_bundle);
2780
2781 mir_foreach_bundle_in_block(block, bun)
2782 nr_ins += bun->instruction_count;
2783 }
2784
2785 /* Calculate thread count. There are certain cutoffs by
2786 * register count for thread count */
2787
2788 unsigned nr_registers = program->work_register_count;
2789
2790 unsigned nr_threads =
2791 (nr_registers <= 4) ? 4 :
2792 (nr_registers <= 8) ? 2 :
2793 1;
2794
2795 /* Dump stats */
2796
2797 fprintf(stderr, "shader%d - %s shader: "
2798 "%u inst, %u bundles, %u quadwords, "
2799 "%u registers, %u threads, %u loops, "
2800 "%u:%u spills:fills\n",
2801 SHADER_DB_COUNT++,
2802 gl_shader_stage_name(ctx->stage),
2803 nr_ins, nr_bundles, ctx->quadword_count,
2804 nr_registers, nr_threads,
2805 ctx->loop_count,
2806 ctx->spills, ctx->fills);
2807 }
2808
2809 ralloc_free(ctx);
2810
2811 return 0;
2812 }