2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
50 #include "midgard_quirks.h"
51 #include "panfrost-quirks.h"
52 #include "panfrost/util/pan_lower_framebuffer.h"
54 #include "disassemble.h"
56 static const struct debug_named_value debug_options
[] = {
57 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
58 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
59 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
63 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
65 unsigned SHADER_DB_COUNT
= 0;
67 int midgard_debug
= 0;
69 #define DBG(fmt, ...) \
70 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
71 fprintf(stderr, "%s:%d: "fmt, \
72 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
73 static midgard_block
*
74 create_empty_block(compiler_context
*ctx
)
76 midgard_block
*blk
= rzalloc(ctx
, midgard_block
);
78 blk
->base
.predecessors
= _mesa_set_create(blk
,
80 _mesa_key_pointer_equal
);
82 blk
->base
.name
= ctx
->block_source_count
++;
88 schedule_barrier(compiler_context
*ctx
)
90 midgard_block
*temp
= ctx
->after_block
;
91 ctx
->after_block
= create_empty_block(ctx
);
93 list_addtail(&ctx
->after_block
->base
.link
, &ctx
->blocks
);
94 list_inithead(&ctx
->after_block
->base
.instructions
);
95 pan_block_add_successor(&ctx
->current_block
->base
, &ctx
->after_block
->base
);
96 ctx
->current_block
= ctx
->after_block
;
97 ctx
->after_block
= temp
;
100 /* Helpers to generate midgard_instruction's using macro magic, since every
101 * driver seems to do it that way */
103 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
105 #define M_LOAD_STORE(name, store, T) \
106 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
107 midgard_instruction i = { \
108 .type = TAG_LOAD_STORE_4, \
111 .src = { ~0, ~0, ~0, ~0 }, \
112 .swizzle = SWIZZLE_IDENTITY_4, \
114 .op = midgard_op_##name, \
121 i.src_types[0] = T; \
130 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
131 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
133 M_LOAD(ld_attr_32
, nir_type_uint32
);
134 M_LOAD(ld_vary_32
, nir_type_uint32
);
135 M_LOAD(ld_ubo_int4
, nir_type_uint32
);
136 M_LOAD(ld_int4
, nir_type_uint32
);
137 M_STORE(st_int4
, nir_type_uint32
);
138 M_LOAD(ld_color_buffer_32u
, nir_type_uint32
);
139 M_LOAD(ld_color_buffer_as_fp16
, nir_type_float16
);
140 M_LOAD(ld_color_buffer_as_fp32
, nir_type_float32
);
141 M_STORE(st_vary_32
, nir_type_uint32
);
142 M_LOAD(ld_cubemap_coords
, nir_type_uint32
);
143 M_LOAD(ld_compute_id
, nir_type_uint32
);
145 static midgard_instruction
146 v_branch(bool conditional
, bool invert
)
148 midgard_instruction ins
= {
150 .unit
= ALU_ENAB_BRANCH
,
151 .compact_branch
= true,
153 .conditional
= conditional
,
154 .invert_conditional
= invert
157 .src
= { ~0, ~0, ~0, ~0 },
163 static midgard_branch_extended
164 midgard_create_branch_extended( midgard_condition cond
,
165 midgard_jmp_writeout_op op
,
167 signed quadword_offset
)
169 /* The condition code is actually a LUT describing a function to
170 * combine multiple condition codes. However, we only support a single
171 * condition code at the moment, so we just duplicate over a bunch of
174 uint16_t duplicated_cond
=
184 midgard_branch_extended branch
= {
186 .dest_tag
= dest_tag
,
187 .offset
= quadword_offset
,
188 .cond
= duplicated_cond
195 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
197 ins
->has_constants
= true;
198 memcpy(&ins
->constants
, constants
, 16);
202 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
204 return glsl_count_attribute_slots(type
, false);
207 /* Lower fdot2 to a vector multiplication followed by channel addition */
209 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
211 if (alu
->op
!= nir_op_fdot2
)
214 b
->cursor
= nir_before_instr(&alu
->instr
);
216 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
217 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
219 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
221 nir_ssa_def
*sum
= nir_fadd(b
,
222 nir_channel(b
, product
, 0),
223 nir_channel(b
, product
, 1));
225 /* Replace the fdot2 with this sum */
226 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
230 midgard_nir_lower_fdot2(nir_shader
*shader
)
232 bool progress
= false;
234 nir_foreach_function(function
, shader
) {
235 if (!function
->impl
) continue;
238 nir_builder
*b
= &_b
;
239 nir_builder_init(b
, function
->impl
);
241 nir_foreach_block(block
, function
->impl
) {
242 nir_foreach_instr_safe(instr
, block
) {
243 if (instr
->type
!= nir_instr_type_alu
) continue;
245 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
246 midgard_nir_lower_fdot2_body(b
, alu
);
252 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
259 static const nir_variable
*
260 search_var(nir_shader
*nir
, nir_variable_mode mode
, unsigned driver_loc
)
262 nir_foreach_variable_with_modes(var
, nir
, mode
) {
263 if (var
->data
.driver_location
== driver_loc
)
270 /* Midgard can write all of color, depth and stencil in a single writeout
271 * operation, so we merge depth/stencil stores with color stores.
272 * If there are no color stores, we add a write to the "depth RT".
275 midgard_nir_lower_zs_store(nir_shader
*nir
)
277 if (nir
->info
.stage
!= MESA_SHADER_FRAGMENT
)
280 nir_variable
*z_var
= NULL
, *s_var
= NULL
;
282 nir_foreach_shader_out_variable(var
, nir
) {
283 if (var
->data
.location
== FRAG_RESULT_DEPTH
)
285 else if (var
->data
.location
== FRAG_RESULT_STENCIL
)
289 if (!z_var
&& !s_var
)
292 bool progress
= false;
294 nir_foreach_function(function
, nir
) {
295 if (!function
->impl
) continue;
297 nir_intrinsic_instr
*z_store
= NULL
, *s_store
= NULL
;
299 nir_foreach_block(block
, function
->impl
) {
300 nir_foreach_instr_safe(instr
, block
) {
301 if (instr
->type
!= nir_instr_type_intrinsic
)
304 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
305 if (intr
->intrinsic
!= nir_intrinsic_store_output
)
308 if (z_var
&& nir_intrinsic_base(intr
) == z_var
->data
.driver_location
) {
313 if (s_var
&& nir_intrinsic_base(intr
) == s_var
->data
.driver_location
) {
320 if (!z_store
&& !s_store
) continue;
322 bool replaced
= false;
324 nir_foreach_block(block
, function
->impl
) {
325 nir_foreach_instr_safe(instr
, block
) {
326 if (instr
->type
!= nir_instr_type_intrinsic
)
329 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
330 if (intr
->intrinsic
!= nir_intrinsic_store_output
)
333 const nir_variable
*var
= search_var(nir
, nir_var_shader_out
, nir_intrinsic_base(intr
));
336 if (var
->data
.location
!= FRAG_RESULT_COLOR
&&
337 var
->data
.location
< FRAG_RESULT_DATA0
)
343 assert(nir_src_is_const(intr
->src
[1]) && "no indirect outputs");
346 nir_builder_init(&b
, function
->impl
);
348 assert(!z_store
|| z_store
->instr
.block
== instr
->block
);
349 assert(!s_store
|| s_store
->instr
.block
== instr
->block
);
350 b
.cursor
= nir_after_block_before_jump(instr
->block
);
352 nir_intrinsic_instr
*combined_store
;
353 combined_store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_combined_output_pan
);
355 combined_store
->num_components
= intr
->src
[0].ssa
->num_components
;
357 nir_intrinsic_set_base(combined_store
, nir_intrinsic_base(intr
));
359 unsigned writeout
= PAN_WRITEOUT_C
;
361 writeout
|= PAN_WRITEOUT_Z
;
363 writeout
|= PAN_WRITEOUT_S
;
365 nir_intrinsic_set_component(combined_store
, writeout
);
367 struct nir_ssa_def
*zero
= nir_imm_int(&b
, 0);
369 struct nir_ssa_def
*src
[4] = {
372 z_store
? z_store
->src
[0].ssa
: zero
,
373 s_store
? s_store
->src
[0].ssa
: zero
,
376 for (int i
= 0; i
< 4; ++i
)
377 combined_store
->src
[i
] = nir_src_for_ssa(src
[i
]);
379 nir_builder_instr_insert(&b
, &combined_store
->instr
);
381 nir_instr_remove(instr
);
387 /* Insert a store to the depth RT (0xff) if needed */
390 nir_builder_init(&b
, function
->impl
);
392 nir_block
*block
= NULL
;
393 if (z_store
&& s_store
)
394 assert(z_store
->instr
.block
== s_store
->instr
.block
);
397 block
= z_store
->instr
.block
;
399 block
= s_store
->instr
.block
;
401 b
.cursor
= nir_after_block_before_jump(block
);
403 nir_intrinsic_instr
*combined_store
;
404 combined_store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_combined_output_pan
);
406 combined_store
->num_components
= 4;
410 base
= nir_intrinsic_base(z_store
);
412 base
= nir_intrinsic_base(s_store
);
413 nir_intrinsic_set_base(combined_store
, base
);
415 unsigned writeout
= 0;
417 writeout
|= PAN_WRITEOUT_Z
;
419 writeout
|= PAN_WRITEOUT_S
;
421 nir_intrinsic_set_component(combined_store
, writeout
);
423 struct nir_ssa_def
*zero
= nir_imm_int(&b
, 0);
425 struct nir_ssa_def
*src
[4] = {
426 nir_imm_vec4(&b
, 0, 0, 0, 0),
428 z_store
? z_store
->src
[0].ssa
: zero
,
429 s_store
? s_store
->src
[0].ssa
: zero
,
432 for (int i
= 0; i
< 4; ++i
)
433 combined_store
->src
[i
] = nir_src_for_ssa(src
[i
]);
435 nir_builder_instr_insert(&b
, &combined_store
->instr
);
439 nir_instr_remove(&z_store
->instr
);
442 nir_instr_remove(&s_store
->instr
);
444 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
451 /* Real writeout stores, which break execution, need to be moved to after
452 * dual-source stores, which are just standard register writes. */
454 midgard_nir_reorder_writeout(nir_shader
*nir
)
456 bool progress
= false;
458 nir_foreach_function(function
, nir
) {
459 if (!function
->impl
) continue;
461 nir_foreach_block(block
, function
->impl
) {
462 nir_instr
*last_writeout
= NULL
;
464 nir_foreach_instr_reverse_safe(instr
, block
) {
465 if (instr
->type
!= nir_instr_type_intrinsic
)
468 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
469 if (intr
->intrinsic
!= nir_intrinsic_store_output
)
472 const nir_variable
*var
= search_var(nir
, nir_var_shader_out
, nir_intrinsic_base(intr
));
474 if (var
->data
.index
) {
476 last_writeout
= instr
;
483 /* This is a real store, so move it to after dual-source stores */
484 exec_node_remove(&instr
->node
);
485 exec_node_insert_after(&last_writeout
->node
, &instr
->node
);
495 /* Flushes undefined values to zero */
498 optimise_nir(nir_shader
*nir
, unsigned quirks
, bool is_blend
)
501 unsigned lower_flrp
=
502 (nir
->options
->lower_flrp16
? 16 : 0) |
503 (nir
->options
->lower_flrp32
? 32 : 0) |
504 (nir
->options
->lower_flrp64
? 64 : 0);
506 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
507 NIR_PASS(progress
, nir
, nir_lower_idiv
, nir_lower_idiv_fast
);
509 nir_lower_tex_options lower_tex_options
= {
510 .lower_txs_lod
= true,
512 .lower_tex_without_implicit_lod
=
513 (quirks
& MIDGARD_EXPLICIT_LOD
),
515 /* TODO: we have native gradient.. */
519 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
521 /* Must lower fdot2 after tex is lowered */
522 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
524 /* T720 is broken. */
526 if (quirks
& MIDGARD_BROKEN_LOD
)
527 NIR_PASS_V(nir
, midgard_nir_lod_errata
);
529 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_early
);
534 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
535 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
537 NIR_PASS(progress
, nir
, nir_copy_prop
);
538 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
539 NIR_PASS(progress
, nir
, nir_opt_dce
);
540 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
541 NIR_PASS(progress
, nir
, nir_opt_cse
);
542 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
543 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
544 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
546 if (lower_flrp
!= 0) {
547 bool lower_flrp_progress
= false;
548 NIR_PASS(lower_flrp_progress
,
552 false /* always_precise */,
553 nir
->options
->lower_ffma
);
554 if (lower_flrp_progress
) {
555 NIR_PASS(progress
, nir
,
556 nir_opt_constant_folding
);
560 /* Nothing should rematerialize any flrps, so we only
561 * need to do this lowering once.
566 NIR_PASS(progress
, nir
, nir_opt_undef
);
567 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
569 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
572 nir_var_function_temp
);
574 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
577 /* Run after opts so it can hit more */
579 NIR_PASS(progress
, nir
, nir_fuse_io_16
);
581 /* Must be run at the end to prevent creation of fsin/fcos ops */
582 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
587 NIR_PASS(progress
, nir
, nir_opt_dce
);
588 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
589 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
590 NIR_PASS(progress
, nir
, nir_copy_prop
);
593 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
594 NIR_PASS(progress
, nir
, nir_opt_algebraic_distribute_src_mods
);
596 /* We implement booleans as 32-bit 0/~0 */
597 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
599 /* Now that booleans are lowered, we can run out late opts */
600 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
601 NIR_PASS(progress
, nir
, midgard_nir_cancel_inot
);
603 NIR_PASS(progress
, nir
, nir_copy_prop
);
604 NIR_PASS(progress
, nir
, nir_opt_dce
);
606 /* Take us out of SSA */
607 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
608 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
610 /* We are a vector architecture; write combine where possible */
611 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
612 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
614 NIR_PASS(progress
, nir
, nir_opt_dce
);
617 /* Do not actually emit a load; instead, cache the constant for inlining */
620 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
622 nir_ssa_def def
= instr
->def
;
624 midgard_constants
*consts
= rzalloc(NULL
, midgard_constants
);
626 assert(instr
->def
.num_components
* instr
->def
.bit_size
<= sizeof(*consts
) * 8);
628 #define RAW_CONST_COPY(bits) \
629 nir_const_value_to_array(consts->u##bits, instr->value, \
630 instr->def.num_components, u##bits)
632 switch (instr
->def
.bit_size
) {
646 unreachable("Invalid bit_size for load_const instruction\n");
649 /* Shifted for SSA, +1 for off-by-one */
650 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (def
.index
<< 1) + 1, consts
);
653 /* Normally constants are embedded implicitly, but for I/O and such we have to
654 * explicitly emit a move with the constant source */
657 emit_explicit_constant(compiler_context
*ctx
, unsigned node
, unsigned to
)
659 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, node
+ 1);
661 if (constant_value
) {
662 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), to
);
663 attach_constants(ctx
, &ins
, constant_value
, node
+ 1);
664 emit_mir_instruction(ctx
, ins
);
669 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
671 unsigned comp
= src
->swizzle
[0];
673 for (unsigned c
= 1; c
< nr_components
; ++c
) {
674 if (src
->swizzle
[c
] != comp
)
681 #define ALU_CASE(nir, _op) \
683 op = midgard_alu_op_##_op; \
684 assert(src_bitsize == dst_bitsize); \
687 #define ALU_CASE_RTZ(nir, _op) \
689 op = midgard_alu_op_##_op; \
690 roundmode = MIDGARD_RTZ; \
693 #define ALU_CHECK_CMP(sext) \
694 assert(src_bitsize == 16 || src_bitsize == 32); \
695 assert(dst_bitsize == 16 || dst_bitsize == 32); \
697 #define ALU_CASE_BCAST(nir, _op, count) \
699 op = midgard_alu_op_##_op; \
700 broadcast_swizzle = count; \
701 ALU_CHECK_CMP(true); \
704 #define ALU_CASE_CMP(nir, _op, sext) \
706 op = midgard_alu_op_##_op; \
707 ALU_CHECK_CMP(sext); \
710 /* Compare mir_lower_invert */
712 nir_accepts_inot(nir_op op
, unsigned src
)
716 case nir_op_iand
: /* TODO: b2f16 */
720 /* Only the condition */
728 mir_accept_dest_mod(compiler_context
*ctx
, nir_dest
**dest
, nir_op op
)
730 if (pan_has_dest_mod(dest
, op
)) {
731 assert((*dest
)->is_ssa
);
732 BITSET_SET(ctx
->already_emitted
, (*dest
)->ssa
.index
);
739 /* Look for floating point mods. We have the mods fsat, fsat_signed,
740 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
742 * fsat_signed(fpos(x)) = fsat(x)
743 * fsat_signed(fsat(x)) = fsat(x)
744 * fpos(fsat_signed(x)) = fsat(x)
745 * fpos(fsat(x)) = fsat(x)
746 * fsat(fsat_signed(x)) = fsat(x)
747 * fsat(fpos(x)) = fsat(x)
749 * So by cases any composition of output modifiers is equivalent to
753 mir_determine_float_outmod(compiler_context
*ctx
, nir_dest
**dest
, unsigned prior_outmod
)
755 bool fpos
= mir_accept_dest_mod(ctx
, dest
, nir_op_fclamp_pos
);
756 bool fsat
= mir_accept_dest_mod(ctx
, dest
, nir_op_fsat
);
757 bool ssat
= mir_accept_dest_mod(ctx
, dest
, nir_op_fsat_signed
);
758 bool prior
= (prior_outmod
!= midgard_outmod_none
);
759 int count
= (int) prior
+ (int) fpos
+ (int) ssat
+ (int) fsat
;
761 return ((count
> 1) || fsat
) ? midgard_outmod_sat
:
762 fpos
? midgard_outmod_pos
:
763 ssat
? midgard_outmod_sat_signed
:
768 mir_copy_src(midgard_instruction
*ins
, nir_alu_instr
*instr
, unsigned i
, unsigned to
, bool *abs
, bool *neg
, bool *not, enum midgard_roundmode
*roundmode
, bool is_int
, unsigned bcast_count
)
770 nir_alu_src src
= instr
->src
[i
];
773 if (pan_has_source_mod(&src
, nir_op_fneg
))
776 if (pan_has_source_mod(&src
, nir_op_fabs
))
780 if (nir_accepts_inot(instr
->op
, i
) && pan_has_source_mod(&src
, nir_op_inot
))
784 if (pan_has_source_mod(&src
, nir_op_fround_even
))
785 *roundmode
= MIDGARD_RTE
;
787 if (pan_has_source_mod(&src
, nir_op_ftrunc
))
788 *roundmode
= MIDGARD_RTZ
;
790 if (pan_has_source_mod(&src
, nir_op_ffloor
))
791 *roundmode
= MIDGARD_RTN
;
793 if (pan_has_source_mod(&src
, nir_op_fceil
))
794 *roundmode
= MIDGARD_RTP
;
797 unsigned bits
= nir_src_bit_size(src
.src
);
799 ins
->src
[to
] = nir_src_index(NULL
, &src
.src
);
800 ins
->src_types
[to
] = nir_op_infos
[instr
->op
].input_types
[i
] | bits
;
802 for (unsigned c
= 0; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
803 ins
->swizzle
[to
][c
] = src
.swizzle
[
804 (!bcast_count
|| c
< bcast_count
) ? c
:
809 /* Midgard features both fcsel and icsel, depending on whether you want int or
810 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
811 * we should emit an int or float csel depending on what modifiers could be
812 * placed. In the absense of modifiers, this is probably arbitrary. */
815 mir_is_bcsel_float(nir_alu_instr
*instr
)
818 nir_op_i2i8
, nir_op_i2i16
,
819 nir_op_i2i32
, nir_op_i2i64
822 nir_op floatmods
[] = {
823 nir_op_fabs
, nir_op_fneg
,
824 nir_op_f2f16
, nir_op_f2f32
,
828 nir_op floatdestmods
[] = {
829 nir_op_fsat
, nir_op_fsat_signed
, nir_op_fclamp_pos
,
830 nir_op_f2f16
, nir_op_f2f32
835 for (unsigned i
= 1; i
< 3; ++i
) {
836 nir_alu_src s
= instr
->src
[i
];
837 for (unsigned q
= 0; q
< ARRAY_SIZE(intmods
); ++q
) {
838 if (pan_has_source_mod(&s
, intmods
[q
]))
843 for (unsigned i
= 1; i
< 3; ++i
) {
844 nir_alu_src s
= instr
->src
[i
];
845 for (unsigned q
= 0; q
< ARRAY_SIZE(floatmods
); ++q
) {
846 if (pan_has_source_mod(&s
, floatmods
[q
]))
851 for (unsigned q
= 0; q
< ARRAY_SIZE(floatdestmods
); ++q
) {
852 nir_dest
*dest
= &instr
->dest
.dest
;
853 if (pan_has_dest_mod(&dest
, floatdestmods
[q
]))
861 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
863 nir_dest
*dest
= &instr
->dest
.dest
;
865 if (dest
->is_ssa
&& BITSET_TEST(ctx
->already_emitted
, dest
->ssa
.index
))
868 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
869 * is handled elsewhere */
871 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddy
) {
872 midgard_emit_derivatives(ctx
, instr
);
876 bool is_ssa
= dest
->is_ssa
;
878 unsigned nr_components
= nir_dest_num_components(*dest
);
879 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
882 /* Number of components valid to check for the instruction (the rest
883 * will be forced to the last), or 0 to use as-is. Relevant as
884 * ball-type instructions have a channel count in NIR but are all vec4
887 unsigned broadcast_swizzle
= 0;
889 /* Should we swap arguments? */
890 bool flip_src12
= false;
892 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
893 unsigned dst_bitsize
= nir_dest_bit_size(*dest
);
895 enum midgard_roundmode roundmode
= MIDGARD_RTE
;
898 ALU_CASE(fadd
, fadd
);
899 ALU_CASE(fmul
, fmul
);
900 ALU_CASE(fmin
, fmin
);
901 ALU_CASE(fmax
, fmax
);
902 ALU_CASE(imin
, imin
);
903 ALU_CASE(imax
, imax
);
904 ALU_CASE(umin
, umin
);
905 ALU_CASE(umax
, umax
);
906 ALU_CASE(ffloor
, ffloor
);
907 ALU_CASE(fround_even
, froundeven
);
908 ALU_CASE(ftrunc
, ftrunc
);
909 ALU_CASE(fceil
, fceil
);
910 ALU_CASE(fdot3
, fdot3
);
911 ALU_CASE(fdot4
, fdot4
);
912 ALU_CASE(iadd
, iadd
);
913 ALU_CASE(isub
, isub
);
914 ALU_CASE(imul
, imul
);
916 /* Zero shoved as second-arg */
917 ALU_CASE(iabs
, iabsdiff
);
921 ALU_CASE_CMP(feq32
, feq
, false);
922 ALU_CASE_CMP(fne32
, fne
, false);
923 ALU_CASE_CMP(flt32
, flt
, false);
924 ALU_CASE_CMP(ieq32
, ieq
, true);
925 ALU_CASE_CMP(ine32
, ine
, true);
926 ALU_CASE_CMP(ilt32
, ilt
, true);
927 ALU_CASE_CMP(ult32
, ult
, false);
929 /* We don't have a native b2f32 instruction. Instead, like many
930 * GPUs, we exploit booleans as 0/~0 for false/true, and
931 * correspondingly AND
932 * by 1.0 to do the type conversion. For the moment, prime us
935 * iand [whatever], #0
937 * At the end of emit_alu (as MIR), we'll fix-up the constant
940 ALU_CASE_CMP(b2f32
, iand
, true);
941 ALU_CASE_CMP(b2f16
, iand
, true);
942 ALU_CASE_CMP(b2i32
, iand
, true);
944 /* Likewise, we don't have a dedicated f2b32 instruction, but
945 * we can do a "not equal to 0.0" test. */
947 ALU_CASE_CMP(f2b32
, fne
, false);
948 ALU_CASE_CMP(i2b32
, ine
, true);
950 ALU_CASE(frcp
, frcp
);
951 ALU_CASE(frsq
, frsqrt
);
952 ALU_CASE(fsqrt
, fsqrt
);
953 ALU_CASE(fexp2
, fexp2
);
954 ALU_CASE(flog2
, flog2
);
956 ALU_CASE_RTZ(f2i64
, f2i_rte
);
957 ALU_CASE_RTZ(f2u64
, f2u_rte
);
958 ALU_CASE_RTZ(i2f64
, i2f_rte
);
959 ALU_CASE_RTZ(u2f64
, u2f_rte
);
961 ALU_CASE_RTZ(f2i32
, f2i_rte
);
962 ALU_CASE_RTZ(f2u32
, f2u_rte
);
963 ALU_CASE_RTZ(i2f32
, i2f_rte
);
964 ALU_CASE_RTZ(u2f32
, u2f_rte
);
966 ALU_CASE_RTZ(f2i8
, f2i_rte
);
967 ALU_CASE_RTZ(f2u8
, f2u_rte
);
969 ALU_CASE_RTZ(f2i16
, f2i_rte
);
970 ALU_CASE_RTZ(f2u16
, f2u_rte
);
971 ALU_CASE_RTZ(i2f16
, i2f_rte
);
972 ALU_CASE_RTZ(u2f16
, u2f_rte
);
974 ALU_CASE(fsin
, fsin
);
975 ALU_CASE(fcos
, fcos
);
977 /* We'll get 0 in the second arg, so:
978 * ~a = ~(a | 0) = nor(a, 0) */
979 ALU_CASE(inot
, inor
);
980 ALU_CASE(iand
, iand
);
982 ALU_CASE(ixor
, ixor
);
983 ALU_CASE(ishl
, ishl
);
984 ALU_CASE(ishr
, iasr
);
985 ALU_CASE(ushr
, ilsr
);
987 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
988 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
989 ALU_CASE_CMP(b32all_fequal4
, fball_eq
, true);
991 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
992 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
993 ALU_CASE_CMP(b32any_fnequal4
, fbany_neq
, true);
995 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
996 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
997 ALU_CASE_CMP(b32all_iequal4
, iball_eq
, true);
999 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
1000 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
1001 ALU_CASE_CMP(b32any_inequal4
, ibany_neq
, true);
1003 /* Source mods will be shoved in later */
1004 ALU_CASE(fabs
, fmov
);
1005 ALU_CASE(fneg
, fmov
);
1006 ALU_CASE(fsat
, fmov
);
1007 ALU_CASE(fsat_signed
, fmov
);
1008 ALU_CASE(fclamp_pos
, fmov
);
1010 /* For size conversion, we use a move. Ideally though we would squash
1011 * these ops together; maybe that has to happen after in NIR as part of
1012 * propagation...? An earlier algebraic pass ensured we step down by
1013 * only / exactly one size. If stepping down, we use a dest override to
1014 * reduce the size; if stepping up, we use a larger-sized move with a
1015 * half source and a sign/zero-extension modifier */
1027 case nir_op_f2f64
: {
1028 if (instr
->op
== nir_op_f2f16
|| instr
->op
== nir_op_f2f32
||
1029 instr
->op
== nir_op_f2f64
)
1030 op
= midgard_alu_op_fmov
;
1032 op
= midgard_alu_op_imov
;
1037 /* For greater-or-equal, we lower to less-or-equal and flip the
1043 case nir_op_uge32
: {
1045 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
1046 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
1047 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
1048 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
1052 ALU_CHECK_CMP(false);
1056 case nir_op_b32csel
: {
1057 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
1058 bool is_float
= mir_is_bcsel_float(instr
);
1060 (mixed
? midgard_alu_op_fcsel_v
: midgard_alu_op_fcsel
) :
1061 (mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
);
1066 case nir_op_unpack_32_2x16
:
1067 case nir_op_unpack_32_4x8
:
1068 case nir_op_pack_32_2x16
:
1069 case nir_op_pack_32_4x8
: {
1070 op
= midgard_alu_op_imov
;
1075 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1080 /* Promote imov to fmov if it might help inline a constant */
1081 if (op
== midgard_alu_op_imov
&& nir_src_is_const(instr
->src
[0].src
)
1082 && nir_src_bit_size(instr
->src
[0].src
) == 32
1083 && nir_is_same_comp_swizzle(instr
->src
[0].swizzle
,
1084 nir_src_num_components(instr
->src
[0].src
))) {
1085 op
= midgard_alu_op_fmov
;
1088 /* Midgard can perform certain modifiers on output of an ALU op */
1090 unsigned outmod
= 0;
1091 bool is_int
= midgard_is_integer_op(op
);
1093 if (midgard_is_integer_out_op(op
)) {
1094 outmod
= midgard_outmod_int_wrap
;
1095 } else if (instr
->op
== nir_op_fsat
) {
1096 outmod
= midgard_outmod_sat
;
1097 } else if (instr
->op
== nir_op_fsat_signed
) {
1098 outmod
= midgard_outmod_sat_signed
;
1099 } else if (instr
->op
== nir_op_fclamp_pos
) {
1100 outmod
= midgard_outmod_pos
;
1103 /* Fetch unit, quirks, etc information */
1104 unsigned opcode_props
= alu_opcode_props
[op
].props
;
1105 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1107 if (!midgard_is_integer_out_op(op
)) {
1108 outmod
= mir_determine_float_outmod(ctx
, &dest
, outmod
);
1111 midgard_instruction ins
= {
1113 .dest
= nir_dest_index(dest
),
1114 .dest_type
= nir_op_infos
[instr
->op
].output_type
1115 | nir_dest_bit_size(*dest
),
1116 .roundmode
= roundmode
,
1119 enum midgard_roundmode
*roundptr
= (opcode_props
& MIDGARD_ROUNDS
) ?
1120 &ins
.roundmode
: NULL
;
1122 for (unsigned i
= nr_inputs
; i
< ARRAY_SIZE(ins
.src
); ++i
)
1125 if (quirk_flipped_r24
) {
1127 mir_copy_src(&ins
, instr
, 0, 1, &ins
.src_abs
[1], &ins
.src_neg
[1], &ins
.src_invert
[1], roundptr
, is_int
, broadcast_swizzle
);
1129 for (unsigned i
= 0; i
< nr_inputs
; ++i
) {
1132 if (instr
->op
== nir_op_b32csel
) {
1133 /* The condition is the first argument; move
1134 * the other arguments up one to be a binary
1135 * instruction for Midgard with the condition
1140 else if (flip_src12
)
1144 } else if (flip_src12
) {
1148 mir_copy_src(&ins
, instr
, i
, to
, &ins
.src_abs
[to
], &ins
.src_neg
[to
], &ins
.src_invert
[to
], roundptr
, is_int
, broadcast_swizzle
);
1150 /* (!c) ? a : b = c ? b : a */
1151 if (instr
->op
== nir_op_b32csel
&& ins
.src_invert
[2]) {
1152 ins
.src_invert
[2] = false;
1158 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
1159 /* Lowered to move */
1160 if (instr
->op
== nir_op_fneg
)
1161 ins
.src_neg
[1] ^= true;
1163 if (instr
->op
== nir_op_fabs
)
1164 ins
.src_abs
[1] = true;
1167 ins
.mask
= mask_of(nr_components
);
1169 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1170 * components that don't exist. Note modifier => SSA => !reg => no
1171 * writemask, so we don't have to worry about writemasks here.*/
1174 ins
.mask
&= instr
->dest
.write_mask
;
1177 ins
.outmod
= outmod
;
1179 /* Late fixup for emulated instructions */
1181 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1182 /* Presently, our second argument is an inline #0 constant.
1183 * Switch over to an embedded 1.0 constant (that can't fit
1184 * inline, since we're 32-bit, not 16-bit like the inline
1187 ins
.has_inline_constant
= false;
1188 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1189 ins
.src_types
[1] = nir_type_float32
;
1190 ins
.has_constants
= true;
1192 if (instr
->op
== nir_op_b2f32
)
1193 ins
.constants
.f32
[0] = 1.0f
;
1195 ins
.constants
.i32
[0] = 1;
1197 for (unsigned c
= 0; c
< 16; ++c
)
1198 ins
.swizzle
[1][c
] = 0;
1199 } else if (instr
->op
== nir_op_b2f16
) {
1200 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1201 ins
.src_types
[1] = nir_type_float16
;
1202 ins
.has_constants
= true;
1203 ins
.constants
.i16
[0] = _mesa_float_to_half(1.0);
1205 for (unsigned c
= 0; c
< 16; ++c
)
1206 ins
.swizzle
[1][c
] = 0;
1207 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1208 /* Lots of instructions need a 0 plonked in */
1209 ins
.has_inline_constant
= false;
1210 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1211 ins
.src_types
[1] = ins
.src_types
[0];
1212 ins
.has_constants
= true;
1213 ins
.constants
.u32
[0] = 0;
1215 for (unsigned c
= 0; c
< 16; ++c
)
1216 ins
.swizzle
[1][c
] = 0;
1217 } else if (instr
->op
== nir_op_pack_32_2x16
) {
1218 ins
.dest_type
= nir_type_uint16
;
1219 ins
.mask
= mask_of(nr_components
* 2);
1221 } else if (instr
->op
== nir_op_pack_32_4x8
) {
1222 ins
.dest_type
= nir_type_uint8
;
1223 ins
.mask
= mask_of(nr_components
* 4);
1225 } else if (instr
->op
== nir_op_unpack_32_2x16
) {
1226 ins
.dest_type
= nir_type_uint32
;
1227 ins
.mask
= mask_of(nr_components
>> 1);
1229 } else if (instr
->op
== nir_op_unpack_32_4x8
) {
1230 ins
.dest_type
= nir_type_uint32
;
1231 ins
.mask
= mask_of(nr_components
>> 2);
1235 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1236 /* To avoid duplicating the lookup tables (probably), true LUT
1237 * instructions can only operate as if they were scalars. Lower
1238 * them here by changing the component. */
1240 unsigned orig_mask
= ins
.mask
;
1242 unsigned swizzle_back
[MIR_VEC_COMPONENTS
];
1243 memcpy(&swizzle_back
, ins
.swizzle
[0], sizeof(swizzle_back
));
1245 midgard_instruction ins_split
[MIR_VEC_COMPONENTS
];
1246 unsigned ins_count
= 0;
1248 for (int i
= 0; i
< nr_components
; ++i
) {
1249 /* Mask the associated component, dropping the
1250 * instruction if needed */
1253 ins
.mask
&= orig_mask
;
1255 for (unsigned j
= 0; j
< ins_count
; ++j
) {
1256 if (swizzle_back
[i
] == ins_split
[j
].swizzle
[0][0]) {
1257 ins_split
[j
].mask
|= ins
.mask
;
1266 for (unsigned j
= 0; j
< MIR_VEC_COMPONENTS
; ++j
)
1267 ins
.swizzle
[0][j
] = swizzle_back
[i
]; /* Pull from the correct component */
1269 ins_split
[ins_count
] = ins
;
1274 for (unsigned i
= 0; i
< ins_count
; ++i
) {
1275 emit_mir_instruction(ctx
, ins_split
[i
]);
1278 emit_mir_instruction(ctx
, ins
);
1285 mir_set_intr_mask(nir_instr
*instr
, midgard_instruction
*ins
, bool is_read
)
1287 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
1288 unsigned nir_mask
= 0;
1292 nir_mask
= mask_of(nir_intrinsic_dest_components(intr
));
1293 dsize
= nir_dest_bit_size(intr
->dest
);
1295 nir_mask
= nir_intrinsic_write_mask(intr
);
1299 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1300 unsigned bytemask
= pan_to_bytemask(dsize
, nir_mask
);
1301 mir_set_bytemask(ins
, bytemask
);
1302 ins
->dest_type
= nir_type_uint
| dsize
;
1305 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1306 * optimized) versions of UBO #0 */
1308 static midgard_instruction
*
1310 compiler_context
*ctx
,
1314 nir_src
*indirect_offset
,
1315 unsigned indirect_shift
,
1318 /* TODO: half-floats */
1320 midgard_instruction ins
= m_ld_ubo_int4(dest
, 0);
1321 ins
.constants
.u32
[0] = offset
;
1323 if (instr
->type
== nir_instr_type_intrinsic
)
1324 mir_set_intr_mask(instr
, &ins
, true);
1326 if (indirect_offset
) {
1327 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1328 ins
.src_types
[2] = nir_type_uint32
;
1329 ins
.load_store
.arg_2
= (indirect_shift
<< 5);
1331 /* X component for the whole swizzle to prevent register
1332 * pressure from ballooning from the extra components */
1333 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
.swizzle
[2]); ++i
)
1334 ins
.swizzle
[2][i
] = 0;
1336 ins
.load_store
.arg_2
= 0x1E;
1339 ins
.load_store
.arg_1
= index
;
1341 return emit_mir_instruction(ctx
, ins
);
1344 /* Globals are like UBOs if you squint. And shared memory is like globals if
1345 * you squint even harder */
1349 compiler_context
*ctx
,
1358 midgard_instruction ins
;
1361 ins
= m_ld_int4(srcdest
, 0);
1363 ins
= m_st_int4(srcdest
, 0);
1365 mir_set_offset(ctx
, &ins
, offset
, is_shared
);
1366 mir_set_intr_mask(instr
, &ins
, is_read
);
1368 emit_mir_instruction(ctx
, ins
);
1373 compiler_context
*ctx
,
1374 unsigned dest
, unsigned offset
,
1375 unsigned nr_comp
, unsigned component
,
1376 nir_src
*indirect_offset
, nir_alu_type type
, bool flat
)
1378 /* XXX: Half-floats? */
1379 /* TODO: swizzle, mask */
1381 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1382 ins
.mask
= mask_of(nr_comp
);
1383 ins
.dest_type
= type
;
1385 if (type
== nir_type_float16
) {
1386 /* Ensure we are aligned so we can pack it later */
1387 ins
.mask
= mask_of(ALIGN_POT(nr_comp
, 2));
1390 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
.swizzle
[0]); ++i
)
1391 ins
.swizzle
[0][i
] = MIN2(i
+ component
, COMPONENT_W
);
1393 midgard_varying_parameter p
= {
1395 .interpolation
= midgard_interp_default
,
1400 memcpy(&u
, &p
, sizeof(p
));
1401 ins
.load_store
.varying_parameters
= u
;
1403 if (indirect_offset
) {
1404 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1405 ins
.src_types
[2] = nir_type_uint32
;
1407 ins
.load_store
.arg_2
= 0x1E;
1409 ins
.load_store
.arg_1
= 0x9E;
1411 /* Use the type appropriate load */
1413 case nir_type_uint32
:
1414 case nir_type_bool32
:
1415 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1417 case nir_type_int32
:
1418 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1420 case nir_type_float32
:
1421 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1423 case nir_type_float16
:
1424 ins
.load_store
.op
= midgard_op_ld_vary_16
;
1427 unreachable("Attempted to load unknown type");
1431 emit_mir_instruction(ctx
, ins
);
1436 compiler_context
*ctx
,
1437 unsigned dest
, unsigned offset
,
1438 unsigned nr_comp
, nir_alu_type t
)
1440 midgard_instruction ins
= m_ld_attr_32(dest
, offset
);
1441 ins
.load_store
.arg_1
= 0x1E;
1442 ins
.load_store
.arg_2
= 0x1E;
1443 ins
.mask
= mask_of(nr_comp
);
1445 /* Use the type appropriate load */
1449 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1452 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1454 case nir_type_float
:
1455 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1458 unreachable("Attempted to load unknown type");
1462 emit_mir_instruction(ctx
, ins
);
1466 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
,
1467 unsigned nr_components
, unsigned offset
)
1471 /* Figure out which uniform this is */
1472 int sysval
= panfrost_sysval_for_instr(instr
, &nir_dest
);
1473 void *val
= _mesa_hash_table_u64_search(ctx
->sysvals
.sysval_to_id
, sysval
);
1475 unsigned dest
= nir_dest_index(&nir_dest
);
1477 /* Sysvals are prefix uniforms */
1478 unsigned uniform
= ((uintptr_t) val
) - 1;
1480 /* Emit the read itself -- this is never indirect */
1481 midgard_instruction
*ins
=
1482 emit_ubo_read(ctx
, instr
, dest
, (uniform
* 16) + offset
, NULL
, 0, 0);
1484 ins
->mask
= mask_of(nr_components
);
1488 compute_builtin_arg(nir_op op
)
1491 case nir_intrinsic_load_work_group_id
:
1493 case nir_intrinsic_load_local_invocation_id
:
1496 unreachable("Invalid compute paramater loaded");
1501 emit_fragment_store(compiler_context
*ctx
, unsigned src
, unsigned src_z
, unsigned src_s
, enum midgard_rt_id rt
)
1503 assert(rt
< ARRAY_SIZE(ctx
->writeout_branch
));
1505 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
1509 emit_explicit_constant(ctx
, src
, src
);
1511 struct midgard_instruction ins
=
1512 v_branch(false, false);
1514 bool depth_only
= (rt
== MIDGARD_ZS_RT
);
1516 ins
.writeout
= depth_only
? 0 : PAN_WRITEOUT_C
;
1518 /* Add dependencies */
1520 ins
.src_types
[0] = nir_type_uint32
;
1521 ins
.constants
.u32
[0] = depth_only
? 0xFF : (rt
- MIDGARD_COLOR_RT0
) * 0x100;
1522 for (int i
= 0; i
< 4; ++i
)
1523 ins
.swizzle
[0][i
] = i
;
1526 emit_explicit_constant(ctx
, src_z
, src_z
);
1528 ins
.src_types
[2] = nir_type_uint32
;
1529 ins
.writeout
|= PAN_WRITEOUT_Z
;
1532 emit_explicit_constant(ctx
, src_s
, src_s
);
1534 ins
.src_types
[3] = nir_type_uint32
;
1535 ins
.writeout
|= PAN_WRITEOUT_S
;
1538 /* Emit the branch */
1539 br
= emit_mir_instruction(ctx
, ins
);
1540 schedule_barrier(ctx
);
1541 ctx
->writeout_branch
[rt
] = br
;
1543 /* Push our current location = current block count - 1 = where we'll
1544 * jump to. Maybe a bit too clever for my own good */
1546 br
->branch
.target_block
= ctx
->block_count
- 1;
1550 emit_compute_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1552 unsigned reg
= nir_dest_index(&instr
->dest
);
1553 midgard_instruction ins
= m_ld_compute_id(reg
, 0);
1554 ins
.mask
= mask_of(3);
1555 ins
.swizzle
[0][3] = COMPONENT_X
; /* xyzx */
1556 ins
.load_store
.arg_1
= compute_builtin_arg(instr
->intrinsic
);
1557 emit_mir_instruction(ctx
, ins
);
1561 vertex_builtin_arg(nir_op op
)
1564 case nir_intrinsic_load_vertex_id
:
1565 return PAN_VERTEX_ID
;
1566 case nir_intrinsic_load_instance_id
:
1567 return PAN_INSTANCE_ID
;
1569 unreachable("Invalid vertex builtin");
1574 emit_vertex_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1576 unsigned reg
= nir_dest_index(&instr
->dest
);
1577 emit_attr_read(ctx
, reg
, vertex_builtin_arg(instr
->intrinsic
), 1, nir_type_int
);
1581 emit_msaa_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1583 unsigned reg
= nir_dest_index(&instr
->dest
);
1585 midgard_instruction ld
= m_ld_color_buffer_32u(reg
, 0);
1586 ld
.load_store
.op
= midgard_op_ld_color_buffer_32u_old
;
1587 ld
.load_store
.address
= 97;
1588 ld
.load_store
.arg_2
= 0x1E;
1590 for (int i
= 0; i
< 4; ++i
)
1591 ld
.swizzle
[0][i
] = COMPONENT_X
;
1593 emit_mir_instruction(ctx
, ld
);
1597 emit_control_barrier(compiler_context
*ctx
)
1599 midgard_instruction ins
= {
1600 .type
= TAG_TEXTURE_4
,
1602 .src
= { ~0, ~0, ~0, ~0 },
1603 .op
= TEXTURE_OP_BARRIER
,
1605 /* TODO: optimize */
1606 .out_of_order
= MIDGARD_BARRIER_BUFFER
|
1607 MIDGARD_BARRIER_SHARED
,
1611 emit_mir_instruction(ctx
, ins
);
1615 mir_get_branch_cond(nir_src
*src
, bool *invert
)
1617 /* Wrap it. No swizzle since it's a scalar */
1623 *invert
= pan_has_source_mod(&alu
, nir_op_inot
);
1624 return nir_src_index(NULL
, &alu
.src
);
1628 output_load_rt_addr(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1631 return ctx
->blend_rt
;
1633 const nir_variable
*var
;
1634 var
= search_var(ctx
->nir
, nir_var_shader_out
, nir_intrinsic_base(instr
));
1637 unsigned loc
= var
->data
.location
;
1639 if (loc
== FRAG_RESULT_COLOR
)
1640 loc
= FRAG_RESULT_DATA0
;
1642 if (loc
>= FRAG_RESULT_DATA0
)
1643 return loc
- FRAG_RESULT_DATA0
;
1645 if (loc
== FRAG_RESULT_DEPTH
)
1647 if (loc
== FRAG_RESULT_STENCIL
)
1650 unreachable("Invalid RT to load from");
1654 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1656 unsigned offset
= 0, reg
;
1658 switch (instr
->intrinsic
) {
1659 case nir_intrinsic_discard_if
:
1660 case nir_intrinsic_discard
: {
1661 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1662 struct midgard_instruction discard
= v_branch(conditional
, false);
1663 discard
.branch
.target_type
= TARGET_DISCARD
;
1666 discard
.src
[0] = mir_get_branch_cond(&instr
->src
[0],
1667 &discard
.branch
.invert_conditional
);
1668 discard
.src_types
[0] = nir_type_uint32
;
1671 emit_mir_instruction(ctx
, discard
);
1672 schedule_barrier(ctx
);
1677 case nir_intrinsic_load_uniform
:
1678 case nir_intrinsic_load_ubo
:
1679 case nir_intrinsic_load_global
:
1680 case nir_intrinsic_load_shared
:
1681 case nir_intrinsic_load_input
:
1682 case nir_intrinsic_load_interpolated_input
: {
1683 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1684 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1685 bool is_global
= instr
->intrinsic
== nir_intrinsic_load_global
;
1686 bool is_shared
= instr
->intrinsic
== nir_intrinsic_load_shared
;
1687 bool is_flat
= instr
->intrinsic
== nir_intrinsic_load_input
;
1688 bool is_interp
= instr
->intrinsic
== nir_intrinsic_load_interpolated_input
;
1690 /* Get the base type of the intrinsic */
1691 /* TODO: Infer type? Does it matter? */
1693 (is_ubo
|| is_global
|| is_shared
) ? nir_type_uint
:
1694 (is_interp
) ? nir_type_float
:
1695 nir_intrinsic_type(instr
);
1697 t
= nir_alu_type_get_base_type(t
);
1699 if (!(is_ubo
|| is_global
)) {
1700 offset
= nir_intrinsic_base(instr
);
1703 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1705 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1707 bool direct
= nir_src_is_const(*src_offset
);
1708 nir_src
*indirect_offset
= direct
? NULL
: src_offset
;
1711 offset
+= nir_src_as_uint(*src_offset
);
1713 /* We may need to apply a fractional offset */
1714 int component
= (is_flat
|| is_interp
) ?
1715 nir_intrinsic_component(instr
) : 0;
1716 reg
= nir_dest_index(&instr
->dest
);
1718 if (is_uniform
&& !ctx
->is_blend
) {
1719 emit_ubo_read(ctx
, &instr
->instr
, reg
, (ctx
->sysvals
.sysval_count
+ offset
) * 16, indirect_offset
, 4, 0);
1720 } else if (is_ubo
) {
1721 nir_src index
= instr
->src
[0];
1723 /* TODO: Is indirect block number possible? */
1724 assert(nir_src_is_const(index
));
1726 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1727 emit_ubo_read(ctx
, &instr
->instr
, reg
, offset
, indirect_offset
, 0, uindex
);
1728 } else if (is_global
|| is_shared
) {
1729 emit_global(ctx
, &instr
->instr
, true, reg
, src_offset
, is_shared
);
1730 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1731 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, indirect_offset
, t
| nir_dest_bit_size(instr
->dest
), is_flat
);
1732 } else if (ctx
->is_blend
) {
1733 /* ctx->blend_input will be precoloured to r0/r2, where
1734 * the input is preloaded */
1736 unsigned *input
= offset
? &ctx
->blend_src1
: &ctx
->blend_input
;
1741 emit_mir_instruction(ctx
, v_mov(*input
, reg
));
1742 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1743 emit_attr_read(ctx
, reg
, offset
, nr_comp
, t
);
1745 DBG("Unknown load\n");
1752 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1753 case nir_intrinsic_load_barycentric_pixel
:
1754 case nir_intrinsic_load_barycentric_centroid
:
1757 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1759 case nir_intrinsic_load_raw_output_pan
: {
1760 reg
= nir_dest_index(&instr
->dest
);
1762 /* T720 and below use different blend opcodes with slightly
1763 * different semantics than T760 and up */
1765 midgard_instruction ld
= m_ld_color_buffer_32u(reg
, 0);
1767 ld
.load_store
.arg_2
= output_load_rt_addr(ctx
, instr
);
1769 if (nir_src_is_const(instr
->src
[0])) {
1770 ld
.load_store
.arg_1
= nir_src_as_uint(instr
->src
[0]);
1772 ld
.load_store
.varying_parameters
= 2;
1773 ld
.src
[1] = nir_src_index(ctx
, &instr
->src
[0]);
1774 ld
.src_types
[1] = nir_type_int32
;
1777 if (ctx
->quirks
& MIDGARD_OLD_BLEND
) {
1778 ld
.load_store
.op
= midgard_op_ld_color_buffer_32u_old
;
1779 ld
.load_store
.address
= 16;
1780 ld
.load_store
.arg_2
= 0x1E;
1783 emit_mir_instruction(ctx
, ld
);
1787 case nir_intrinsic_load_output
: {
1788 reg
= nir_dest_index(&instr
->dest
);
1790 unsigned bits
= nir_dest_bit_size(instr
->dest
);
1792 midgard_instruction ld
;
1794 ld
= m_ld_color_buffer_as_fp16(reg
, 0);
1796 ld
= m_ld_color_buffer_as_fp32(reg
, 0);
1798 ld
.load_store
.arg_2
= output_load_rt_addr(ctx
, instr
);
1800 for (unsigned c
= 4; c
< 16; ++c
)
1801 ld
.swizzle
[0][c
] = 0;
1803 if (ctx
->quirks
& MIDGARD_OLD_BLEND
) {
1805 ld
.load_store
.op
= midgard_op_ld_color_buffer_as_fp16_old
;
1807 ld
.load_store
.op
= midgard_op_ld_color_buffer_as_fp32_old
;
1808 ld
.load_store
.address
= 1;
1809 ld
.load_store
.arg_2
= 0x1E;
1812 emit_mir_instruction(ctx
, ld
);
1816 case nir_intrinsic_load_blend_const_color_rgba
: {
1817 assert(ctx
->is_blend
);
1818 reg
= nir_dest_index(&instr
->dest
);
1820 /* Blend constants are embedded directly in the shader and
1821 * patched in, so we use some magic routing */
1823 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), reg
);
1824 ins
.has_constants
= true;
1825 ins
.has_blend_constant
= true;
1826 emit_mir_instruction(ctx
, ins
);
1830 case nir_intrinsic_store_output
:
1831 case nir_intrinsic_store_combined_output_pan
:
1832 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1834 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1836 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1838 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1839 bool combined
= instr
->intrinsic
==
1840 nir_intrinsic_store_combined_output_pan
;
1842 const nir_variable
*var
;
1843 var
= search_var(ctx
->nir
, nir_var_shader_out
,
1844 nir_intrinsic_base(instr
));
1847 /* Dual-source blend writeout is done by leaving the
1848 * value in r2 for the blend shader to use. */
1849 if (var
->data
.index
) {
1850 if (instr
->src
[0].is_ssa
) {
1851 emit_explicit_constant(ctx
, reg
, reg
);
1853 unsigned out
= make_compiler_temp(ctx
);
1855 midgard_instruction ins
= v_mov(reg
, out
);
1856 emit_mir_instruction(ctx
, ins
);
1858 ctx
->blend_src1
= out
;
1860 ctx
->blend_src1
= reg
;
1866 enum midgard_rt_id rt
;
1867 if (var
->data
.location
== FRAG_RESULT_COLOR
)
1868 rt
= MIDGARD_COLOR_RT0
;
1869 else if (var
->data
.location
>= FRAG_RESULT_DATA0
)
1870 rt
= MIDGARD_COLOR_RT0
+ var
->data
.location
-
1877 unsigned reg_z
= ~0, reg_s
= ~0;
1879 unsigned writeout
= nir_intrinsic_component(instr
);
1880 if (writeout
& PAN_WRITEOUT_Z
)
1881 reg_z
= nir_src_index(ctx
, &instr
->src
[2]);
1882 if (writeout
& PAN_WRITEOUT_S
)
1883 reg_s
= nir_src_index(ctx
, &instr
->src
[3]);
1886 emit_fragment_store(ctx
, reg
, reg_z
, reg_s
, rt
);
1887 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1888 assert(instr
->intrinsic
== nir_intrinsic_store_output
);
1890 /* We should have been vectorized, though we don't
1891 * currently check that st_vary is emitted only once
1892 * per slot (this is relevant, since there's not a mask
1893 * parameter available on the store [set to 0 by the
1894 * blob]). We do respect the component by adjusting the
1895 * swizzle. If this is a constant source, we'll need to
1896 * emit that explicitly. */
1898 emit_explicit_constant(ctx
, reg
, reg
);
1900 unsigned dst_component
= nir_intrinsic_component(instr
);
1901 unsigned nr_comp
= nir_src_num_components(instr
->src
[0]);
1903 midgard_instruction st
= m_st_vary_32(reg
, offset
);
1904 st
.load_store
.arg_1
= 0x9E;
1905 st
.load_store
.arg_2
= 0x1E;
1907 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr
))) {
1910 st
.load_store
.op
= midgard_op_st_vary_32u
;
1913 st
.load_store
.op
= midgard_op_st_vary_32i
;
1915 case nir_type_float
:
1916 st
.load_store
.op
= midgard_op_st_vary_32
;
1919 unreachable("Attempted to store unknown type");
1923 /* nir_intrinsic_component(store_intr) encodes the
1924 * destination component start. Source component offset
1925 * adjustment is taken care of in
1926 * install_registers_instr(), when offset_swizzle() is
1929 unsigned src_component
= COMPONENT_X
;
1931 assert(nr_comp
> 0);
1932 for (unsigned i
= 0; i
< ARRAY_SIZE(st
.swizzle
); ++i
) {
1933 st
.swizzle
[0][i
] = src_component
;
1934 if (i
>= dst_component
&& i
< dst_component
+ nr_comp
- 1)
1938 emit_mir_instruction(ctx
, st
);
1940 DBG("Unknown store\n");
1946 /* Special case of store_output for lowered blend shaders */
1947 case nir_intrinsic_store_raw_output_pan
:
1948 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1949 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1950 emit_fragment_store(ctx
, reg
, ~0, ~0, ctx
->blend_rt
);
1953 case nir_intrinsic_store_global
:
1954 case nir_intrinsic_store_shared
:
1955 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1956 emit_explicit_constant(ctx
, reg
, reg
);
1958 emit_global(ctx
, &instr
->instr
, false, reg
, &instr
->src
[1], instr
->intrinsic
== nir_intrinsic_store_shared
);
1961 case nir_intrinsic_load_ssbo_address
:
1962 emit_sysval_read(ctx
, &instr
->instr
, 1, 0);
1965 case nir_intrinsic_get_buffer_size
:
1966 emit_sysval_read(ctx
, &instr
->instr
, 1, 8);
1969 case nir_intrinsic_load_viewport_scale
:
1970 case nir_intrinsic_load_viewport_offset
:
1971 case nir_intrinsic_load_num_work_groups
:
1972 case nir_intrinsic_load_sampler_lod_parameters_pan
:
1973 emit_sysval_read(ctx
, &instr
->instr
, 3, 0);
1976 case nir_intrinsic_load_work_group_id
:
1977 case nir_intrinsic_load_local_invocation_id
:
1978 emit_compute_builtin(ctx
, instr
);
1981 case nir_intrinsic_load_vertex_id
:
1982 case nir_intrinsic_load_instance_id
:
1983 emit_vertex_builtin(ctx
, instr
);
1986 case nir_intrinsic_load_sample_id
:
1987 emit_msaa_builtin(ctx
, instr
);
1990 case nir_intrinsic_memory_barrier_buffer
:
1991 case nir_intrinsic_memory_barrier_shared
:
1994 case nir_intrinsic_control_barrier
:
1995 schedule_barrier(ctx
);
1996 emit_control_barrier(ctx
);
1997 schedule_barrier(ctx
);
2001 fprintf(stderr
, "Unhandled intrinsic %s\n", nir_intrinsic_infos
[instr
->intrinsic
].name
);
2008 midgard_tex_format(enum glsl_sampler_dim dim
)
2011 case GLSL_SAMPLER_DIM_1D
:
2012 case GLSL_SAMPLER_DIM_BUF
:
2015 case GLSL_SAMPLER_DIM_2D
:
2016 case GLSL_SAMPLER_DIM_MS
:
2017 case GLSL_SAMPLER_DIM_EXTERNAL
:
2018 case GLSL_SAMPLER_DIM_RECT
:
2021 case GLSL_SAMPLER_DIM_3D
:
2024 case GLSL_SAMPLER_DIM_CUBE
:
2025 return MALI_TEX_CUBE
;
2028 DBG("Unknown sampler dim type\n");
2034 /* Tries to attach an explicit LOD or bias as a constant. Returns whether this
2038 pan_attach_constant_bias(
2039 compiler_context
*ctx
,
2041 midgard_texture_word
*word
)
2043 /* To attach as constant, it has to *be* constant */
2045 if (!nir_src_is_const(lod
))
2048 float f
= nir_src_as_float(lod
);
2050 /* Break into fixed-point */
2052 float lod_frac
= f
- lod_int
;
2054 /* Carry over negative fractions */
2055 if (lod_frac
< 0.0) {
2061 word
->bias
= float_to_ubyte(lod_frac
);
2062 word
->bias_int
= lod_int
;
2068 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
2069 unsigned midgard_texop
)
2072 //assert (!instr->sampler);
2074 nir_dest
*dest
= &instr
->dest
;
2076 int texture_index
= instr
->texture_index
;
2077 int sampler_index
= texture_index
;
2079 nir_alu_type dest_base
= nir_alu_type_get_base_type(instr
->dest_type
);
2080 nir_alu_type dest_type
= dest_base
| nir_dest_bit_size(*dest
);
2082 /* texture instructions support float outmods */
2083 unsigned outmod
= midgard_outmod_none
;
2084 if (dest_base
== nir_type_float
) {
2085 outmod
= mir_determine_float_outmod(ctx
, &dest
, 0);
2088 midgard_instruction ins
= {
2089 .type
= TAG_TEXTURE_4
,
2091 .dest
= nir_dest_index(dest
),
2092 .src
= { ~0, ~0, ~0, ~0 },
2093 .dest_type
= dest_type
,
2094 .swizzle
= SWIZZLE_IDENTITY_4
,
2096 .op
= midgard_texop
,
2098 .format
= midgard_tex_format(instr
->sampler_dim
),
2099 .texture_handle
= texture_index
,
2100 .sampler_handle
= sampler_index
,
2101 .shadow
= instr
->is_shadow
,
2105 if (instr
->is_shadow
&& !instr
->is_new_style_shadow
)
2106 for (int i
= 0; i
< 4; ++i
)
2107 ins
.swizzle
[0][i
] = COMPONENT_X
;
2109 /* We may need a temporary for the coordinate */
2111 bool needs_temp_coord
=
2112 (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) ||
2113 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) ||
2116 unsigned coords
= needs_temp_coord
? make_compiler_temp_reg(ctx
) : 0;
2118 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
2119 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
2120 unsigned nr_components
= nir_src_num_components(instr
->src
[i
].src
);
2121 unsigned sz
= nir_src_bit_size(instr
->src
[i
].src
);
2122 nir_alu_type T
= nir_tex_instr_src_type(instr
, i
) | sz
;
2124 switch (instr
->src
[i
].src_type
) {
2125 case nir_tex_src_coord
: {
2126 emit_explicit_constant(ctx
, index
, index
);
2128 unsigned coord_mask
= mask_of(instr
->coord_components
);
2130 bool flip_zw
= (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) && (coord_mask
& (1 << COMPONENT_Z
));
2133 coord_mask
^= ((1 << COMPONENT_Z
) | (1 << COMPONENT_W
));
2135 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2136 /* texelFetch is undefined on samplerCube */
2137 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
2139 /* For cubemaps, we use a special ld/st op to
2140 * select the face and copy the xy into the
2141 * texture register */
2143 midgard_instruction ld
= m_ld_cubemap_coords(coords
, 0);
2145 ld
.src_types
[1] = T
;
2146 ld
.mask
= 0x3; /* xy */
2147 ld
.load_store
.arg_1
= 0x20;
2148 ld
.swizzle
[1][3] = COMPONENT_X
;
2149 emit_mir_instruction(ctx
, ld
);
2152 ins
.swizzle
[1][2] = instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
2153 ins
.swizzle
[1][3] = COMPONENT_X
;
2154 } else if (needs_temp_coord
) {
2155 /* mov coord_temp, coords */
2156 midgard_instruction mov
= v_mov(index
, coords
);
2157 mov
.mask
= coord_mask
;
2160 mov
.swizzle
[1][COMPONENT_W
] = COMPONENT_Z
;
2162 emit_mir_instruction(ctx
, mov
);
2167 ins
.src
[1] = coords
;
2168 ins
.src_types
[1] = T
;
2170 /* Texelfetch coordinates uses all four elements
2171 * (xyz/index) regardless of texture dimensionality,
2172 * which means it's necessary to zero the unused
2173 * components to keep everything happy */
2175 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
2176 /* mov index.zw, #0, or generalized */
2177 midgard_instruction mov
=
2178 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), coords
);
2179 mov
.has_constants
= true;
2180 mov
.mask
= coord_mask
^ 0xF;
2181 emit_mir_instruction(ctx
, mov
);
2184 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) {
2185 /* Array component in w but NIR wants it in z,
2186 * but if we have a temp coord we already fixed
2189 if (nr_components
== 3) {
2190 ins
.swizzle
[1][2] = COMPONENT_Z
;
2191 ins
.swizzle
[1][3] = needs_temp_coord
? COMPONENT_W
: COMPONENT_Z
;
2192 } else if (nr_components
== 2) {
2194 instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
2195 ins
.swizzle
[1][3] = COMPONENT_X
;
2197 unreachable("Invalid texture 2D components");
2200 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
2202 ins
.swizzle
[1][2] = COMPONENT_Z
;
2203 ins
.swizzle
[1][3] = COMPONENT_W
;
2209 case nir_tex_src_bias
:
2210 case nir_tex_src_lod
: {
2211 /* Try as a constant if we can */
2213 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
2214 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
2217 ins
.texture
.lod_register
= true;
2219 ins
.src_types
[2] = T
;
2221 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
2222 ins
.swizzle
[2][c
] = COMPONENT_X
;
2224 emit_explicit_constant(ctx
, index
, index
);
2229 case nir_tex_src_offset
: {
2230 ins
.texture
.offset_register
= true;
2232 ins
.src_types
[3] = T
;
2234 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
2235 ins
.swizzle
[3][c
] = (c
> COMPONENT_Z
) ? 0 : c
;
2237 emit_explicit_constant(ctx
, index
, index
);
2241 case nir_tex_src_comparator
:
2242 case nir_tex_src_ms_index
: {
2243 unsigned comp
= COMPONENT_Z
;
2245 /* mov coord_temp.foo, coords */
2246 midgard_instruction mov
= v_mov(index
, coords
);
2247 mov
.mask
= 1 << comp
;
2249 for (unsigned i
= 0; i
< MIR_VEC_COMPONENTS
; ++i
)
2250 mov
.swizzle
[1][i
] = COMPONENT_X
;
2252 emit_mir_instruction(ctx
, mov
);
2257 fprintf(stderr
, "Unknown texture source type: %d\n", instr
->src
[i
].src_type
);
2263 emit_mir_instruction(ctx
, ins
);
2267 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
2269 switch (instr
->op
) {
2272 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
2275 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
2278 case nir_texop_txf_ms
:
2279 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
2282 emit_sysval_read(ctx
, &instr
->instr
, 4, 0);
2285 fprintf(stderr
, "Unhandled texture op: %d\n", instr
->op
);
2292 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
2294 switch (instr
->type
) {
2295 case nir_jump_break
: {
2296 /* Emit a branch out of the loop */
2297 struct midgard_instruction br
= v_branch(false, false);
2298 br
.branch
.target_type
= TARGET_BREAK
;
2299 br
.branch
.target_break
= ctx
->current_loop_depth
;
2300 emit_mir_instruction(ctx
, br
);
2305 DBG("Unknown jump type %d\n", instr
->type
);
2311 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
2313 switch (instr
->type
) {
2314 case nir_instr_type_load_const
:
2315 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2318 case nir_instr_type_intrinsic
:
2319 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2322 case nir_instr_type_alu
:
2323 emit_alu(ctx
, nir_instr_as_alu(instr
));
2326 case nir_instr_type_tex
:
2327 emit_tex(ctx
, nir_instr_as_tex(instr
));
2330 case nir_instr_type_jump
:
2331 emit_jump(ctx
, nir_instr_as_jump(instr
));
2334 case nir_instr_type_ssa_undef
:
2339 DBG("Unhandled instruction type\n");
2345 /* ALU instructions can inline or embed constants, which decreases register
2346 * pressure and saves space. */
2348 #define CONDITIONAL_ATTACH(idx) { \
2349 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2352 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2353 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2358 inline_alu_constants(compiler_context
*ctx
, midgard_block
*block
)
2360 mir_foreach_instr_in_block(block
, alu
) {
2361 /* Other instructions cannot inline constants */
2362 if (alu
->type
!= TAG_ALU_4
) continue;
2363 if (alu
->compact_branch
) continue;
2365 /* If there is already a constant here, we can do nothing */
2366 if (alu
->has_constants
) continue;
2368 CONDITIONAL_ATTACH(0);
2370 if (!alu
->has_constants
) {
2371 CONDITIONAL_ATTACH(1)
2372 } else if (!alu
->inline_constant
) {
2373 /* Corner case: _two_ vec4 constants, for instance with a
2374 * csel. For this case, we can only use a constant
2375 * register for one, we'll have to emit a move for the
2378 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->src
[1] + 1);
2379 unsigned scratch
= make_compiler_temp(ctx
);
2382 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), scratch
);
2383 attach_constants(ctx
, &ins
, entry
, alu
->src
[1] + 1);
2385 /* Set the source */
2386 alu
->src
[1] = scratch
;
2388 /* Inject us -before- the last instruction which set r31 */
2389 mir_insert_instruction_before(ctx
, mir_prev_op(alu
), ins
);
2396 max_bitsize_for_alu(midgard_instruction
*ins
)
2398 unsigned max_bitsize
= 0;
2399 for (int i
= 0; i
< MIR_SRC_COUNT
; i
++) {
2400 if (ins
->src
[i
] == ~0) continue;
2401 unsigned src_bitsize
= nir_alu_type_get_type_size(ins
->src_types
[i
]);
2402 max_bitsize
= MAX2(src_bitsize
, max_bitsize
);
2404 unsigned dst_bitsize
= nir_alu_type_get_type_size(ins
->dest_type
);
2405 max_bitsize
= MAX2(dst_bitsize
, max_bitsize
);
2407 /* We don't have fp16 LUTs, so we'll want to emit code like:
2409 * vlut.fsinr hr0, hr0
2411 * where both input and output are 16-bit but the operation is carried
2416 case midgard_alu_op_fsqrt
:
2417 case midgard_alu_op_frcp
:
2418 case midgard_alu_op_frsqrt
:
2419 case midgard_alu_op_fsin
:
2420 case midgard_alu_op_fcos
:
2421 case midgard_alu_op_fexp2
:
2422 case midgard_alu_op_flog2
:
2423 max_bitsize
= MAX2(max_bitsize
, 32);
2434 reg_mode_for_bitsize(unsigned bitsize
)
2437 /* use 16 pipe for 8 since we don't support vec16 yet */
2440 return midgard_reg_mode_16
;
2442 return midgard_reg_mode_32
;
2444 return midgard_reg_mode_64
;
2446 unreachable("invalid bit size");
2450 /* Midgard supports two types of constants, embedded constants (128-bit) and
2451 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2452 * constants can be demoted to inline constants, for space savings and
2453 * sometimes a performance boost */
2456 embedded_to_inline_constant(compiler_context
*ctx
, midgard_block
*block
)
2458 mir_foreach_instr_in_block(block
, ins
) {
2459 if (!ins
->has_constants
) continue;
2460 if (ins
->has_inline_constant
) continue;
2462 /* Blend constants must not be inlined by definition */
2463 if (ins
->has_blend_constant
) continue;
2465 unsigned max_bitsize
= max_bitsize_for_alu(ins
);
2467 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2468 bool is_16
= max_bitsize
== 16;
2469 bool is_32
= max_bitsize
== 32;
2471 if (!(is_16
|| is_32
))
2474 /* src1 cannot be an inline constant due to encoding
2475 * restrictions. So, if possible we try to flip the arguments
2480 if (ins
->src
[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
) &&
2481 alu_opcode_props
[op
].props
& OP_COMMUTES
) {
2485 if (ins
->src
[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2486 /* Component is from the swizzle. Take a nonzero component */
2488 unsigned first_comp
= ffs(ins
->mask
) - 1;
2489 unsigned component
= ins
->swizzle
[1][first_comp
];
2491 /* Scale constant appropriately, if we can legally */
2492 int16_t scaled_constant
= 0;
2495 scaled_constant
= ins
->constants
.u16
[component
];
2496 } else if (midgard_is_integer_op(op
)) {
2497 scaled_constant
= ins
->constants
.u32
[component
];
2499 /* Constant overflow after resize */
2500 if (scaled_constant
!= ins
->constants
.u32
[component
])
2503 float original
= ins
->constants
.f32
[component
];
2504 scaled_constant
= _mesa_float_to_half(original
);
2506 /* Check for loss of precision. If this is
2507 * mediump, we don't care, but for a highp
2508 * shader, we need to pay attention. NIR
2509 * doesn't yet tell us which mode we're in!
2510 * Practically this prevents most constants
2511 * from being inlined, sadly. */
2513 float fp32
= _mesa_half_to_float(scaled_constant
);
2515 if (fp32
!= original
)
2519 /* Should've been const folded */
2520 if (ins
->src_abs
[1] || ins
->src_neg
[1])
2523 /* Make sure that the constant is not itself a vector
2524 * by checking if all accessed values are the same. */
2526 const midgard_constants
*cons
= &ins
->constants
;
2527 uint32_t value
= is_16
? cons
->u16
[component
] : cons
->u32
[component
];
2529 bool is_vector
= false;
2530 unsigned mask
= effective_writemask(ins
->op
, ins
->mask
);
2532 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
) {
2533 /* We only care if this component is actually used */
2534 if (!(mask
& (1 << c
)))
2537 uint32_t test
= is_16
?
2538 cons
->u16
[ins
->swizzle
[1][c
]] :
2539 cons
->u32
[ins
->swizzle
[1][c
]];
2541 if (test
!= value
) {
2550 /* Get rid of the embedded constant */
2551 ins
->has_constants
= false;
2553 ins
->has_inline_constant
= true;
2554 ins
->inline_constant
= scaled_constant
;
2559 /* Dead code elimination for branches at the end of a block - only one branch
2560 * per block is legal semantically */
2563 midgard_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
2565 bool branched
= false;
2567 mir_foreach_instr_in_block_safe(block
, ins
) {
2568 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2571 mir_remove_instruction(ins
);
2577 /* We want to force the invert on AND/OR to the second slot to legalize into
2578 * iandnot/iornot. The relevant patterns are for AND (and OR respectively)
2580 * ~a & #b = ~a & ~(#~b)
2585 midgard_legalize_invert(compiler_context
*ctx
, midgard_block
*block
)
2587 mir_foreach_instr_in_block(block
, ins
) {
2588 if (ins
->type
!= TAG_ALU_4
) continue;
2590 if (ins
->op
!= midgard_alu_op_iand
&&
2591 ins
->op
!= midgard_alu_op_ior
) continue;
2593 if (ins
->src_invert
[1] || !ins
->src_invert
[0]) continue;
2595 if (ins
->has_inline_constant
) {
2596 /* ~(#~a) = ~(~#a) = a, so valid, and forces both
2598 ins
->inline_constant
= ~ins
->inline_constant
;
2599 ins
->src_invert
[1] = true;
2601 /* Flip to the right invert order. Note
2602 * has_inline_constant false by assumption on the
2603 * branch, so flipping makes sense. */
2610 emit_fragment_epilogue(compiler_context
*ctx
, unsigned rt
)
2612 /* Loop to ourselves */
2613 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
2614 struct midgard_instruction ins
= v_branch(false, false);
2615 ins
.writeout
= br
->writeout
;
2616 ins
.branch
.target_block
= ctx
->block_count
- 1;
2617 ins
.constants
.u32
[0] = br
->constants
.u32
[0];
2618 memcpy(&ins
.src_types
, &br
->src_types
, sizeof(ins
.src_types
));
2619 emit_mir_instruction(ctx
, ins
);
2621 ctx
->current_block
->epilogue
= true;
2622 schedule_barrier(ctx
);
2623 return ins
.branch
.target_block
;
2626 static midgard_block
*
2627 emit_block_init(compiler_context
*ctx
)
2629 midgard_block
*this_block
= ctx
->after_block
;
2630 ctx
->after_block
= NULL
;
2633 this_block
= create_empty_block(ctx
);
2635 list_addtail(&this_block
->base
.link
, &ctx
->blocks
);
2637 this_block
->scheduled
= false;
2640 /* Set up current block */
2641 list_inithead(&this_block
->base
.instructions
);
2642 ctx
->current_block
= this_block
;
2647 static midgard_block
*
2648 emit_block(compiler_context
*ctx
, nir_block
*block
)
2650 midgard_block
*this_block
= emit_block_init(ctx
);
2652 nir_foreach_instr(instr
, block
) {
2653 emit_instr(ctx
, instr
);
2654 ++ctx
->instruction_count
;
2660 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2663 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2665 midgard_block
*before_block
= ctx
->current_block
;
2667 /* Speculatively emit the branch, but we can't fill it in until later */
2669 EMIT(branch
, true, true);
2670 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2671 then_branch
->src
[0] = mir_get_branch_cond(&nif
->condition
, &inv
);
2672 then_branch
->src_types
[0] = nir_type_uint32
;
2673 then_branch
->branch
.invert_conditional
= !inv
;
2675 /* Emit the two subblocks. */
2676 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2677 midgard_block
*end_then_block
= ctx
->current_block
;
2679 /* Emit a jump from the end of the then block to the end of the else */
2680 EMIT(branch
, false, false);
2681 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2683 /* Emit second block, and check if it's empty */
2685 int else_idx
= ctx
->block_count
;
2686 int count_in
= ctx
->instruction_count
;
2687 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2688 midgard_block
*end_else_block
= ctx
->current_block
;
2689 int after_else_idx
= ctx
->block_count
;
2691 /* Now that we have the subblocks emitted, fix up the branches */
2696 if (ctx
->instruction_count
== count_in
) {
2697 /* The else block is empty, so don't emit an exit jump */
2698 mir_remove_instruction(then_exit
);
2699 then_branch
->branch
.target_block
= after_else_idx
;
2701 then_branch
->branch
.target_block
= else_idx
;
2702 then_exit
->branch
.target_block
= after_else_idx
;
2705 /* Wire up the successors */
2707 ctx
->after_block
= create_empty_block(ctx
);
2709 pan_block_add_successor(&before_block
->base
, &then_block
->base
);
2710 pan_block_add_successor(&before_block
->base
, &else_block
->base
);
2712 pan_block_add_successor(&end_then_block
->base
, &ctx
->after_block
->base
);
2713 pan_block_add_successor(&end_else_block
->base
, &ctx
->after_block
->base
);
2717 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2719 /* Remember where we are */
2720 midgard_block
*start_block
= ctx
->current_block
;
2722 /* Allocate a loop number, growing the current inner loop depth */
2723 int loop_idx
= ++ctx
->current_loop_depth
;
2725 /* Get index from before the body so we can loop back later */
2726 int start_idx
= ctx
->block_count
;
2728 /* Emit the body itself */
2729 midgard_block
*loop_block
= emit_cf_list(ctx
, &nloop
->body
);
2731 /* Branch back to loop back */
2732 struct midgard_instruction br_back
= v_branch(false, false);
2733 br_back
.branch
.target_block
= start_idx
;
2734 emit_mir_instruction(ctx
, br_back
);
2736 /* Mark down that branch in the graph. */
2737 pan_block_add_successor(&start_block
->base
, &loop_block
->base
);
2738 pan_block_add_successor(&ctx
->current_block
->base
, &loop_block
->base
);
2740 /* Find the index of the block about to follow us (note: we don't add
2741 * one; blocks are 0-indexed so we get a fencepost problem) */
2742 int break_block_idx
= ctx
->block_count
;
2744 /* Fix up the break statements we emitted to point to the right place,
2745 * now that we can allocate a block number for them */
2746 ctx
->after_block
= create_empty_block(ctx
);
2748 mir_foreach_block_from(ctx
, start_block
, _block
) {
2749 mir_foreach_instr_in_block(((midgard_block
*) _block
), ins
) {
2750 if (ins
->type
!= TAG_ALU_4
) continue;
2751 if (!ins
->compact_branch
) continue;
2753 /* We found a branch -- check the type to see if we need to do anything */
2754 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2756 /* It's a break! Check if it's our break */
2757 if (ins
->branch
.target_break
!= loop_idx
) continue;
2759 /* Okay, cool, we're breaking out of this loop.
2760 * Rewrite from a break to a goto */
2762 ins
->branch
.target_type
= TARGET_GOTO
;
2763 ins
->branch
.target_block
= break_block_idx
;
2765 pan_block_add_successor(_block
, &ctx
->after_block
->base
);
2769 /* Now that we've finished emitting the loop, free up the depth again
2770 * so we play nice with recursion amid nested loops */
2771 --ctx
->current_loop_depth
;
2773 /* Dump loop stats */
2777 static midgard_block
*
2778 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2780 midgard_block
*start_block
= NULL
;
2782 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2783 switch (node
->type
) {
2784 case nir_cf_node_block
: {
2785 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2788 start_block
= block
;
2793 case nir_cf_node_if
:
2794 emit_if(ctx
, nir_cf_node_as_if(node
));
2797 case nir_cf_node_loop
:
2798 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2801 case nir_cf_node_function
:
2810 /* Due to lookahead, we need to report the first tag executed in the command
2811 * stream and in branch targets. An initial block might be empty, so iterate
2812 * until we find one that 'works' */
2815 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2817 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2819 mir_foreach_block_from(ctx
, initial_block
, _v
) {
2820 midgard_block
*v
= (midgard_block
*) _v
;
2821 if (v
->quadword_count
) {
2822 midgard_bundle
*initial_bundle
=
2823 util_dynarray_element(&v
->bundles
, midgard_bundle
, 0);
2825 return initial_bundle
->tag
;
2829 /* Default to a tag 1 which will break from the shader, in case we jump
2830 * to the exit block (i.e. `return` in a compute shader) */
2835 /* For each fragment writeout instruction, generate a writeout loop to
2836 * associate with it */
2839 mir_add_writeout_loops(compiler_context
*ctx
)
2841 for (unsigned rt
= 0; rt
< ARRAY_SIZE(ctx
->writeout_branch
); ++rt
) {
2842 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
2845 unsigned popped
= br
->branch
.target_block
;
2846 pan_block_add_successor(&(mir_get_block(ctx
, popped
- 1)->base
), &ctx
->current_block
->base
);
2847 br
->branch
.target_block
= emit_fragment_epilogue(ctx
, rt
);
2848 br
->branch
.target_type
= TARGET_GOTO
;
2850 /* If we have more RTs, we'll need to restore back after our
2851 * loop terminates */
2853 if ((rt
+ 1) < ARRAY_SIZE(ctx
->writeout_branch
) && ctx
->writeout_branch
[rt
+ 1]) {
2854 midgard_instruction uncond
= v_branch(false, false);
2855 uncond
.branch
.target_block
= popped
;
2856 uncond
.branch
.target_type
= TARGET_GOTO
;
2857 emit_mir_instruction(ctx
, uncond
);
2858 pan_block_add_successor(&ctx
->current_block
->base
, &(mir_get_block(ctx
, popped
)->base
));
2859 schedule_barrier(ctx
);
2861 /* We're last, so we can terminate here */
2862 br
->last_writeout
= true;
2868 midgard_compile_shader_nir(nir_shader
*nir
, panfrost_program
*program
, bool is_blend
, unsigned blend_rt
, unsigned gpu_id
, bool shaderdb
, bool silent
)
2870 struct util_dynarray
*compiled
= &program
->compiled
;
2872 midgard_debug
= debug_get_option_midgard_debug();
2874 /* TODO: Bound against what? */
2875 compiler_context
*ctx
= rzalloc(NULL
, compiler_context
);
2878 ctx
->stage
= nir
->info
.stage
;
2879 ctx
->is_blend
= is_blend
;
2880 ctx
->alpha_ref
= program
->alpha_ref
;
2881 ctx
->blend_rt
= MIDGARD_COLOR_RT0
+ blend_rt
;
2882 ctx
->blend_input
= ~0;
2883 ctx
->blend_src1
= ~0;
2884 ctx
->quirks
= midgard_get_quirks(gpu_id
);
2886 /* Start off with a safe cutoff, allowing usage of all 16 work
2887 * registers. Later, we'll promote uniform reads to uniform registers
2888 * if we determine it is beneficial to do so */
2889 ctx
->uniform_cutoff
= 8;
2891 /* Initialize at a global (not block) level hash tables */
2893 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2894 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2896 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2897 * (so we don't accidentally duplicate the epilogue since mesa/st has
2898 * messed with our I/O quite a bit already) */
2900 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2902 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2903 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2904 NIR_PASS_V(nir
, nir_lower_point_size
, 1.0, 1024.0);
2907 NIR_PASS_V(nir
, nir_lower_var_copies
);
2908 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2909 NIR_PASS_V(nir
, nir_split_var_copies
);
2910 NIR_PASS_V(nir
, nir_lower_var_copies
);
2911 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2912 NIR_PASS_V(nir
, nir_lower_var_copies
);
2913 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2915 unsigned pan_quirks
= panfrost_get_quirks(gpu_id
);
2916 NIR_PASS_V(nir
, pan_lower_framebuffer
,
2917 program
->rt_formats
, is_blend
, pan_quirks
);
2919 NIR_PASS_V(nir
, nir_lower_io
, nir_var_shader_in
| nir_var_shader_out
,
2921 NIR_PASS_V(nir
, nir_lower_ssbo
);
2922 NIR_PASS_V(nir
, midgard_nir_lower_zs_store
);
2924 /* Optimisation passes */
2926 optimise_nir(nir
, ctx
->quirks
, is_blend
);
2928 NIR_PASS_V(nir
, midgard_nir_reorder_writeout
);
2930 if ((midgard_debug
& MIDGARD_DBG_SHADERS
) && !silent
) {
2931 nir_print_shader(nir
, stdout
);
2934 /* Assign sysvals and counts, now that we're sure
2935 * (post-optimisation) */
2937 panfrost_nir_assign_sysvals(&ctx
->sysvals
, nir
);
2938 program
->sysval_count
= ctx
->sysvals
.sysval_count
;
2939 memcpy(program
->sysvals
, ctx
->sysvals
.sysvals
, sizeof(ctx
->sysvals
.sysvals
[0]) * ctx
->sysvals
.sysval_count
);
2941 nir_foreach_function(func
, nir
) {
2945 list_inithead(&ctx
->blocks
);
2946 ctx
->block_count
= 0;
2948 ctx
->already_emitted
= calloc(BITSET_WORDS(func
->impl
->ssa_alloc
), sizeof(BITSET_WORD
));
2950 if (nir
->info
.outputs_read
&& !is_blend
) {
2951 emit_block_init(ctx
);
2953 struct midgard_instruction wait
= v_branch(false, false);
2954 wait
.branch
.target_type
= TARGET_TILEBUF_WAIT
;
2956 emit_mir_instruction(ctx
, wait
);
2958 ++ctx
->instruction_count
;
2961 emit_cf_list(ctx
, &func
->impl
->body
);
2962 free(ctx
->already_emitted
);
2963 break; /* TODO: Multi-function shaders */
2966 util_dynarray_init(compiled
, NULL
);
2968 /* Per-block lowering before opts */
2970 mir_foreach_block(ctx
, _block
) {
2971 midgard_block
*block
= (midgard_block
*) _block
;
2972 inline_alu_constants(ctx
, block
);
2973 embedded_to_inline_constant(ctx
, block
);
2975 /* MIR-level optimizations */
2977 bool progress
= false;
2981 progress
|= midgard_opt_dead_code_eliminate(ctx
);
2983 mir_foreach_block(ctx
, _block
) {
2984 midgard_block
*block
= (midgard_block
*) _block
;
2985 progress
|= midgard_opt_copy_prop(ctx
, block
);
2986 progress
|= midgard_opt_combine_projection(ctx
, block
);
2987 progress
|= midgard_opt_varying_projection(ctx
, block
);
2991 mir_foreach_block(ctx
, _block
) {
2992 midgard_block
*block
= (midgard_block
*) _block
;
2993 midgard_lower_derivatives(ctx
, block
);
2994 midgard_legalize_invert(ctx
, block
);
2995 midgard_cull_dead_branch(ctx
, block
);
2998 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
2999 mir_add_writeout_loops(ctx
);
3001 /* Analyze now that the code is known but before scheduling creates
3002 * pipeline registers which are harder to track */
3003 mir_analyze_helper_terminate(ctx
);
3004 mir_analyze_helper_requirements(ctx
);
3007 midgard_schedule_program(ctx
);
3010 /* Now that all the bundles are scheduled and we can calculate block
3011 * sizes, emit actual branch instructions rather than placeholders */
3013 int br_block_idx
= 0;
3015 mir_foreach_block(ctx
, _block
) {
3016 midgard_block
*block
= (midgard_block
*) _block
;
3017 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3018 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3019 midgard_instruction
*ins
= bundle
->instructions
[c
];
3021 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3023 /* Parse some basic branch info */
3024 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3025 bool is_conditional
= ins
->branch
.conditional
;
3026 bool is_inverted
= ins
->branch
.invert_conditional
;
3027 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3028 bool is_tilebuf_wait
= ins
->branch
.target_type
== TARGET_TILEBUF_WAIT
;
3029 bool is_special
= is_discard
|| is_tilebuf_wait
;
3030 bool is_writeout
= ins
->writeout
;
3032 /* Determine the block we're jumping to */
3033 int target_number
= ins
->branch
.target_block
;
3035 /* Report the destination tag */
3036 int dest_tag
= is_discard
? 0 :
3037 is_tilebuf_wait
? bundle
->tag
:
3038 midgard_get_first_tag_from_block(ctx
, target_number
);
3040 /* Count up the number of quadwords we're
3041 * jumping over = number of quadwords until
3042 * (br_block_idx, target_number) */
3044 int quadword_offset
= 0;
3048 } else if (is_tilebuf_wait
) {
3049 quadword_offset
= -1;
3050 } else if (target_number
> br_block_idx
) {
3053 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3054 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3057 quadword_offset
+= blk
->quadword_count
;
3060 /* Jump backwards */
3062 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3063 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3066 quadword_offset
-= blk
->quadword_count
;
3070 /* Unconditional extended branches (far jumps)
3071 * have issues, so we always use a conditional
3072 * branch, setting the condition to always for
3073 * unconditional. For compact unconditional
3074 * branches, cond isn't used so it doesn't
3075 * matter what we pick. */
3077 midgard_condition cond
=
3078 !is_conditional
? midgard_condition_always
:
3079 is_inverted
? midgard_condition_false
:
3080 midgard_condition_true
;
3082 midgard_jmp_writeout_op op
=
3083 is_discard
? midgard_jmp_writeout_op_discard
:
3084 is_tilebuf_wait
? midgard_jmp_writeout_op_tilebuffer_pending
:
3085 is_writeout
? midgard_jmp_writeout_op_writeout
:
3086 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
3087 midgard_jmp_writeout_op_branch_cond
;
3090 midgard_branch_extended branch
=
3091 midgard_create_branch_extended(
3096 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
3097 } else if (is_conditional
|| is_special
) {
3098 midgard_branch_cond branch
= {
3100 .dest_tag
= dest_tag
,
3101 .offset
= quadword_offset
,
3105 assert(branch
.offset
== quadword_offset
);
3107 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3109 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
3111 midgard_branch_uncond branch
= {
3113 .dest_tag
= dest_tag
,
3114 .offset
= quadword_offset
,
3118 assert(branch
.offset
== quadword_offset
);
3120 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3128 /* Emit flat binary from the instruction arrays. Iterate each block in
3129 * sequence. Save instruction boundaries such that lookahead tags can
3130 * be assigned easily */
3132 /* Cache _all_ bundles in source order for lookahead across failed branches */
3134 int bundle_count
= 0;
3135 mir_foreach_block(ctx
, _block
) {
3136 midgard_block
*block
= (midgard_block
*) _block
;
3137 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3139 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3141 mir_foreach_block(ctx
, _block
) {
3142 midgard_block
*block
= (midgard_block
*) _block
;
3143 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3144 source_order_bundles
[bundle_idx
++] = bundle
;
3148 int current_bundle
= 0;
3150 /* Midgard prefetches instruction types, so during emission we
3151 * need to lookahead. Unless this is the last instruction, in
3152 * which we return 1. */
3154 mir_foreach_block(ctx
, _block
) {
3155 midgard_block
*block
= (midgard_block
*) _block
;
3156 mir_foreach_bundle_in_block(block
, bundle
) {
3159 if (!bundle
->last_writeout
&& (current_bundle
+ 1 < bundle_count
))
3160 lookahead
= source_order_bundles
[current_bundle
+ 1]->tag
;
3162 emit_binary_bundle(ctx
, block
, bundle
, compiled
, lookahead
);
3166 /* TODO: Free deeper */
3167 //util_dynarray_fini(&block->instructions);
3170 free(source_order_bundles
);
3172 /* Report the very first tag executed */
3173 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3175 /* Deal with off-by-one related to the fencepost problem */
3176 program
->work_register_count
= ctx
->work_registers
+ 1;
3177 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3179 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3180 program
->tls_size
= ctx
->tls_size
;
3182 if ((midgard_debug
& MIDGARD_DBG_SHADERS
) && !silent
)
3183 disassemble_midgard(stdout
, program
->compiled
.data
, program
->compiled
.size
, gpu_id
, ctx
->stage
);
3185 if ((midgard_debug
& MIDGARD_DBG_SHADERDB
|| shaderdb
) && !silent
) {
3186 unsigned nr_bundles
= 0, nr_ins
= 0;
3188 /* Count instructions and bundles */
3190 mir_foreach_block(ctx
, _block
) {
3191 midgard_block
*block
= (midgard_block
*) _block
;
3192 nr_bundles
+= util_dynarray_num_elements(
3193 &block
->bundles
, midgard_bundle
);
3195 mir_foreach_bundle_in_block(block
, bun
)
3196 nr_ins
+= bun
->instruction_count
;
3199 /* Calculate thread count. There are certain cutoffs by
3200 * register count for thread count */
3202 unsigned nr_registers
= program
->work_register_count
;
3204 unsigned nr_threads
=
3205 (nr_registers
<= 4) ? 4 :
3206 (nr_registers
<= 8) ? 2 :
3211 fprintf(stderr
, "shader%d - %s shader: "
3212 "%u inst, %u bundles, %u quadwords, "
3213 "%u registers, %u threads, %u loops, "
3214 "%u:%u spills:fills\n",
3216 ctx
->is_blend
? "PAN_SHADER_BLEND" :
3217 gl_shader_stage_name(ctx
->stage
),
3218 nr_ins
, nr_bundles
, ctx
->quadword_count
,
3219 nr_registers
, nr_threads
,
3221 ctx
->spills
, ctx
->fills
);