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pan/mdg: Replace writeout booleans with a single value
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 i.dest_type = T; \
121 } else { \
122 i.dest = ssa; \
123 i.dest_type = T; \
124 } \
125 return i; \
126 }
127
128 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
129 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
130
131 M_LOAD(ld_attr_32, nir_type_uint32);
132 M_LOAD(ld_vary_32, nir_type_uint32);
133 M_LOAD(ld_ubo_int4, nir_type_uint32);
134 M_LOAD(ld_int4, nir_type_uint32);
135 M_STORE(st_int4, nir_type_uint32);
136 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
137 M_LOAD(ld_color_buffer_as_fp16, nir_type_float16);
138 M_STORE(st_vary_32, nir_type_uint32);
139 M_LOAD(ld_cubemap_coords, nir_type_uint32);
140 M_LOAD(ld_compute_id, nir_type_uint32);
141
142 static midgard_instruction
143 v_branch(bool conditional, bool invert)
144 {
145 midgard_instruction ins = {
146 .type = TAG_ALU_4,
147 .unit = ALU_ENAB_BRANCH,
148 .compact_branch = true,
149 .branch = {
150 .conditional = conditional,
151 .invert_conditional = invert
152 },
153 .dest = ~0,
154 .src = { ~0, ~0, ~0, ~0 },
155 };
156
157 return ins;
158 }
159
160 static midgard_branch_extended
161 midgard_create_branch_extended( midgard_condition cond,
162 midgard_jmp_writeout_op op,
163 unsigned dest_tag,
164 signed quadword_offset)
165 {
166 /* The condition code is actually a LUT describing a function to
167 * combine multiple condition codes. However, we only support a single
168 * condition code at the moment, so we just duplicate over a bunch of
169 * times. */
170
171 uint16_t duplicated_cond =
172 (cond << 14) |
173 (cond << 12) |
174 (cond << 10) |
175 (cond << 8) |
176 (cond << 6) |
177 (cond << 4) |
178 (cond << 2) |
179 (cond << 0);
180
181 midgard_branch_extended branch = {
182 .op = op,
183 .dest_tag = dest_tag,
184 .offset = quadword_offset,
185 .cond = duplicated_cond
186 };
187
188 return branch;
189 }
190
191 static void
192 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
193 {
194 ins->has_constants = true;
195 memcpy(&ins->constants, constants, 16);
196 }
197
198 static int
199 glsl_type_size(const struct glsl_type *type, bool bindless)
200 {
201 return glsl_count_attribute_slots(type, false);
202 }
203
204 /* Lower fdot2 to a vector multiplication followed by channel addition */
205 static void
206 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
207 {
208 if (alu->op != nir_op_fdot2)
209 return;
210
211 b->cursor = nir_before_instr(&alu->instr);
212
213 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
214 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
215
216 nir_ssa_def *product = nir_fmul(b, src0, src1);
217
218 nir_ssa_def *sum = nir_fadd(b,
219 nir_channel(b, product, 0),
220 nir_channel(b, product, 1));
221
222 /* Replace the fdot2 with this sum */
223 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
224 }
225
226 static bool
227 midgard_nir_lower_fdot2(nir_shader *shader)
228 {
229 bool progress = false;
230
231 nir_foreach_function(function, shader) {
232 if (!function->impl) continue;
233
234 nir_builder _b;
235 nir_builder *b = &_b;
236 nir_builder_init(b, function->impl);
237
238 nir_foreach_block(block, function->impl) {
239 nir_foreach_instr_safe(instr, block) {
240 if (instr->type != nir_instr_type_alu) continue;
241
242 nir_alu_instr *alu = nir_instr_as_alu(instr);
243 midgard_nir_lower_fdot2_body(b, alu);
244
245 progress |= true;
246 }
247 }
248
249 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
250
251 }
252
253 return progress;
254 }
255
256 /* Flushes undefined values to zero */
257
258 static void
259 optimise_nir(nir_shader *nir, unsigned quirks, bool is_blend)
260 {
261 bool progress;
262 unsigned lower_flrp =
263 (nir->options->lower_flrp16 ? 16 : 0) |
264 (nir->options->lower_flrp32 ? 32 : 0) |
265 (nir->options->lower_flrp64 ? 64 : 0);
266
267 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
268 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
269
270 nir_lower_tex_options lower_tex_options = {
271 .lower_txs_lod = true,
272 .lower_txp = ~0,
273 .lower_tex_without_implicit_lod =
274 (quirks & MIDGARD_EXPLICIT_LOD),
275
276 /* TODO: we have native gradient.. */
277 .lower_txd = true,
278 };
279
280 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
281
282 /* Must lower fdot2 after tex is lowered */
283 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
284
285 /* T720 is broken. */
286
287 if (quirks & MIDGARD_BROKEN_LOD)
288 NIR_PASS_V(nir, midgard_nir_lod_errata);
289
290 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_early);
291
292 if (!is_blend)
293 NIR_PASS(progress, nir, nir_fuse_io_16);
294
295 do {
296 progress = false;
297
298 NIR_PASS(progress, nir, nir_lower_var_copies);
299 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
300
301 NIR_PASS(progress, nir, nir_copy_prop);
302 NIR_PASS(progress, nir, nir_opt_remove_phis);
303 NIR_PASS(progress, nir, nir_opt_dce);
304 NIR_PASS(progress, nir, nir_opt_dead_cf);
305 NIR_PASS(progress, nir, nir_opt_cse);
306 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
307 NIR_PASS(progress, nir, nir_opt_algebraic);
308 NIR_PASS(progress, nir, nir_opt_constant_folding);
309
310 if (lower_flrp != 0) {
311 bool lower_flrp_progress = false;
312 NIR_PASS(lower_flrp_progress,
313 nir,
314 nir_lower_flrp,
315 lower_flrp,
316 false /* always_precise */,
317 nir->options->lower_ffma);
318 if (lower_flrp_progress) {
319 NIR_PASS(progress, nir,
320 nir_opt_constant_folding);
321 progress = true;
322 }
323
324 /* Nothing should rematerialize any flrps, so we only
325 * need to do this lowering once.
326 */
327 lower_flrp = 0;
328 }
329
330 NIR_PASS(progress, nir, nir_opt_undef);
331 NIR_PASS(progress, nir, nir_undef_to_zero);
332
333 NIR_PASS(progress, nir, nir_opt_loop_unroll,
334 nir_var_shader_in |
335 nir_var_shader_out |
336 nir_var_function_temp);
337
338 NIR_PASS(progress, nir, nir_opt_vectorize);
339 } while (progress);
340
341 /* Must be run at the end to prevent creation of fsin/fcos ops */
342 NIR_PASS(progress, nir, midgard_nir_scale_trig);
343
344 do {
345 progress = false;
346
347 NIR_PASS(progress, nir, nir_opt_dce);
348 NIR_PASS(progress, nir, nir_opt_algebraic);
349 NIR_PASS(progress, nir, nir_opt_constant_folding);
350 NIR_PASS(progress, nir, nir_copy_prop);
351 } while (progress);
352
353 NIR_PASS(progress, nir, nir_opt_algebraic_late);
354 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
355
356 /* We implement booleans as 32-bit 0/~0 */
357 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
358
359 /* Now that booleans are lowered, we can run out late opts */
360 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
361 NIR_PASS(progress, nir, midgard_nir_cancel_inot);
362
363 NIR_PASS(progress, nir, nir_copy_prop);
364 NIR_PASS(progress, nir, nir_opt_dce);
365
366 /* Take us out of SSA */
367 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
368 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
369
370 /* We are a vector architecture; write combine where possible */
371 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
372 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
373
374 NIR_PASS(progress, nir, nir_opt_dce);
375 }
376
377 /* Do not actually emit a load; instead, cache the constant for inlining */
378
379 static void
380 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
381 {
382 nir_ssa_def def = instr->def;
383
384 midgard_constants *consts = rzalloc(NULL, midgard_constants);
385
386 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
387
388 #define RAW_CONST_COPY(bits) \
389 nir_const_value_to_array(consts->u##bits, instr->value, \
390 instr->def.num_components, u##bits)
391
392 switch (instr->def.bit_size) {
393 case 64:
394 RAW_CONST_COPY(64);
395 break;
396 case 32:
397 RAW_CONST_COPY(32);
398 break;
399 case 16:
400 RAW_CONST_COPY(16);
401 break;
402 case 8:
403 RAW_CONST_COPY(8);
404 break;
405 default:
406 unreachable("Invalid bit_size for load_const instruction\n");
407 }
408
409 /* Shifted for SSA, +1 for off-by-one */
410 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
411 }
412
413 /* Normally constants are embedded implicitly, but for I/O and such we have to
414 * explicitly emit a move with the constant source */
415
416 static void
417 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
418 {
419 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
420
421 if (constant_value) {
422 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
423 attach_constants(ctx, &ins, constant_value, node + 1);
424 emit_mir_instruction(ctx, ins);
425 }
426 }
427
428 static bool
429 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
430 {
431 unsigned comp = src->swizzle[0];
432
433 for (unsigned c = 1; c < nr_components; ++c) {
434 if (src->swizzle[c] != comp)
435 return true;
436 }
437
438 return false;
439 }
440
441 #define ALU_CASE(nir, _op) \
442 case nir_op_##nir: \
443 op = midgard_alu_op_##_op; \
444 assert(src_bitsize == dst_bitsize); \
445 break;
446
447 #define ALU_CASE_RTZ(nir, _op) \
448 case nir_op_##nir: \
449 op = midgard_alu_op_##_op; \
450 roundmode = MIDGARD_RTZ; \
451 break;
452
453 #define ALU_CHECK_CMP(sext) \
454 assert(src_bitsize == 16 || src_bitsize == 32); \
455 assert(dst_bitsize == 16 || dst_bitsize == 32); \
456
457 #define ALU_CASE_BCAST(nir, _op, count) \
458 case nir_op_##nir: \
459 op = midgard_alu_op_##_op; \
460 broadcast_swizzle = count; \
461 ALU_CHECK_CMP(true); \
462 break;
463
464 #define ALU_CASE_CMP(nir, _op, sext) \
465 case nir_op_##nir: \
466 op = midgard_alu_op_##_op; \
467 ALU_CHECK_CMP(sext); \
468 break;
469
470 /* Analyze the sizes of the dest and inputs to determine reg mode. */
471
472 static midgard_reg_mode
473 reg_mode_for_nir(nir_alu_instr *instr)
474 {
475 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
476 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
477 unsigned max_bitsize = MAX2(src_bitsize, dst_bitsize);
478
479 /* We don't have fp16 LUTs, so we'll want to emit code like:
480 *
481 * vlut.fsinr hr0, hr0
482 *
483 * where both input and output are 16-bit but the operation is carried
484 * out in 32-bit
485 */
486
487 switch (instr->op) {
488 case nir_op_fsqrt:
489 case nir_op_frcp:
490 case nir_op_frsq:
491 case nir_op_fsin:
492 case nir_op_fcos:
493 case nir_op_fexp2:
494 case nir_op_flog2:
495 max_bitsize = MAX2(max_bitsize, 32);
496 break;
497
498 /* These get lowered to moves */
499 case nir_op_pack_32_4x8:
500 max_bitsize = 8;
501 break;
502 case nir_op_pack_32_2x16:
503 max_bitsize = 16;
504 break;
505 default:
506 break;
507 }
508
509
510 switch (max_bitsize) {
511 /* Use 16 pipe for 8 since we don't support vec16 yet */
512 case 8:
513 case 16:
514 return midgard_reg_mode_16;
515 case 32:
516 return midgard_reg_mode_32;
517 case 64:
518 return midgard_reg_mode_64;
519 default:
520 unreachable("Invalid bit size");
521 }
522 }
523
524 /* Compare mir_lower_invert */
525 static bool
526 nir_accepts_inot(nir_op op, unsigned src)
527 {
528 switch (op) {
529 case nir_op_ior:
530 case nir_op_iand: /* TODO: b2f16 */
531 case nir_op_ixor:
532 return true;
533 case nir_op_b32csel:
534 /* Only the condition */
535 return (src == 0);
536 default:
537 return false;
538 }
539 }
540
541 static bool
542 mir_accept_dest_mod(compiler_context *ctx, nir_dest **dest, nir_op op)
543 {
544 if (pan_has_dest_mod(dest, op)) {
545 assert((*dest)->is_ssa);
546 BITSET_SET(ctx->already_emitted, (*dest)->ssa.index);
547 return true;
548 }
549
550 return false;
551 }
552
553 static void
554 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool *not, enum midgard_roundmode *roundmode, bool is_int, unsigned bcast_count)
555 {
556 nir_alu_src src = instr->src[i];
557
558 if (!is_int) {
559 if (pan_has_source_mod(&src, nir_op_fneg))
560 *neg = !(*neg);
561
562 if (pan_has_source_mod(&src, nir_op_fabs))
563 *abs = true;
564 }
565
566 if (nir_accepts_inot(instr->op, i) && pan_has_source_mod(&src, nir_op_inot))
567 *not = true;
568
569 if (roundmode) {
570 if (pan_has_source_mod(&src, nir_op_fround_even))
571 *roundmode = MIDGARD_RTE;
572
573 if (pan_has_source_mod(&src, nir_op_ftrunc))
574 *roundmode = MIDGARD_RTZ;
575
576 if (pan_has_source_mod(&src, nir_op_ffloor))
577 *roundmode = MIDGARD_RTN;
578
579 if (pan_has_source_mod(&src, nir_op_fceil))
580 *roundmode = MIDGARD_RTP;
581 }
582
583 unsigned bits = nir_src_bit_size(src.src);
584
585 ins->src[to] = nir_src_index(NULL, &src.src);
586 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
587
588 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
589 ins->swizzle[to][c] = src.swizzle[
590 (!bcast_count || c < bcast_count) ? c :
591 (bcast_count - 1)];
592 }
593 }
594
595 /* Midgard features both fcsel and icsel, depending on whether you want int or
596 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
597 * we should emit an int or float csel depending on what modifiers could be
598 * placed. In the absense of modifiers, this is probably arbitrary. */
599
600 static bool
601 mir_is_bcsel_float(nir_alu_instr *instr)
602 {
603 nir_op intmods[] = {
604 nir_op_i2i8, nir_op_i2i16,
605 nir_op_i2i32, nir_op_i2i64
606 };
607
608 nir_op floatmods[] = {
609 nir_op_fabs, nir_op_fneg,
610 nir_op_f2f16, nir_op_f2f32,
611 nir_op_f2f64
612 };
613
614 nir_op floatdestmods[] = {
615 nir_op_fsat, nir_op_fsat_signed, nir_op_fclamp_pos,
616 nir_op_f2f16, nir_op_f2f32
617 };
618
619 signed score = 0;
620
621 for (unsigned i = 1; i < 3; ++i) {
622 nir_alu_src s = instr->src[i];
623 for (unsigned q = 0; q < ARRAY_SIZE(intmods); ++q) {
624 if (pan_has_source_mod(&s, intmods[q]))
625 score--;
626 }
627 }
628
629 for (unsigned i = 1; i < 3; ++i) {
630 nir_alu_src s = instr->src[i];
631 for (unsigned q = 0; q < ARRAY_SIZE(floatmods); ++q) {
632 if (pan_has_source_mod(&s, floatmods[q]))
633 score++;
634 }
635 }
636
637 for (unsigned q = 0; q < ARRAY_SIZE(floatdestmods); ++q) {
638 nir_dest *dest = &instr->dest.dest;
639 if (pan_has_dest_mod(&dest, floatdestmods[q]))
640 score++;
641 }
642
643 return (score > 0);
644 }
645
646 static void
647 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
648 {
649 nir_dest *dest = &instr->dest.dest;
650
651 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index))
652 return;
653
654 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
655 * is handled elsewhere */
656
657 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
658 midgard_emit_derivatives(ctx, instr);
659 return;
660 }
661
662 bool is_ssa = dest->is_ssa;
663
664 unsigned nr_components = nir_dest_num_components(*dest);
665 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
666 unsigned op = 0;
667
668 /* Number of components valid to check for the instruction (the rest
669 * will be forced to the last), or 0 to use as-is. Relevant as
670 * ball-type instructions have a channel count in NIR but are all vec4
671 * in Midgard */
672
673 unsigned broadcast_swizzle = 0;
674
675 /* What register mode should we operate in? */
676 midgard_reg_mode reg_mode =
677 reg_mode_for_nir(instr);
678
679 /* Should we swap arguments? */
680 bool flip_src12 = false;
681
682 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
683 unsigned dst_bitsize = nir_dest_bit_size(*dest);
684
685 enum midgard_roundmode roundmode = MIDGARD_RTE;
686
687 switch (instr->op) {
688 ALU_CASE(fadd, fadd);
689 ALU_CASE(fmul, fmul);
690 ALU_CASE(fmin, fmin);
691 ALU_CASE(fmax, fmax);
692 ALU_CASE(imin, imin);
693 ALU_CASE(imax, imax);
694 ALU_CASE(umin, umin);
695 ALU_CASE(umax, umax);
696 ALU_CASE(ffloor, ffloor);
697 ALU_CASE(fround_even, froundeven);
698 ALU_CASE(ftrunc, ftrunc);
699 ALU_CASE(fceil, fceil);
700 ALU_CASE(fdot3, fdot3);
701 ALU_CASE(fdot4, fdot4);
702 ALU_CASE(iadd, iadd);
703 ALU_CASE(isub, isub);
704 ALU_CASE(imul, imul);
705
706 /* Zero shoved as second-arg */
707 ALU_CASE(iabs, iabsdiff);
708
709 ALU_CASE(mov, imov);
710
711 ALU_CASE_CMP(feq32, feq, false);
712 ALU_CASE_CMP(fne32, fne, false);
713 ALU_CASE_CMP(flt32, flt, false);
714 ALU_CASE_CMP(ieq32, ieq, true);
715 ALU_CASE_CMP(ine32, ine, true);
716 ALU_CASE_CMP(ilt32, ilt, true);
717 ALU_CASE_CMP(ult32, ult, false);
718
719 /* We don't have a native b2f32 instruction. Instead, like many
720 * GPUs, we exploit booleans as 0/~0 for false/true, and
721 * correspondingly AND
722 * by 1.0 to do the type conversion. For the moment, prime us
723 * to emit:
724 *
725 * iand [whatever], #0
726 *
727 * At the end of emit_alu (as MIR), we'll fix-up the constant
728 */
729
730 ALU_CASE_CMP(b2f32, iand, true);
731 ALU_CASE_CMP(b2f16, iand, true);
732 ALU_CASE_CMP(b2i32, iand, true);
733
734 /* Likewise, we don't have a dedicated f2b32 instruction, but
735 * we can do a "not equal to 0.0" test. */
736
737 ALU_CASE_CMP(f2b32, fne, false);
738 ALU_CASE_CMP(i2b32, ine, true);
739
740 ALU_CASE(frcp, frcp);
741 ALU_CASE(frsq, frsqrt);
742 ALU_CASE(fsqrt, fsqrt);
743 ALU_CASE(fexp2, fexp2);
744 ALU_CASE(flog2, flog2);
745
746 ALU_CASE_RTZ(f2i64, f2i_rte);
747 ALU_CASE_RTZ(f2u64, f2u_rte);
748 ALU_CASE_RTZ(i2f64, i2f_rte);
749 ALU_CASE_RTZ(u2f64, u2f_rte);
750
751 ALU_CASE_RTZ(f2i32, f2i_rte);
752 ALU_CASE_RTZ(f2u32, f2u_rte);
753 ALU_CASE_RTZ(i2f32, i2f_rte);
754 ALU_CASE_RTZ(u2f32, u2f_rte);
755
756 ALU_CASE_RTZ(f2i8, f2i_rte);
757 ALU_CASE_RTZ(f2u8, f2u_rte);
758
759 ALU_CASE_RTZ(f2i16, f2i_rte);
760 ALU_CASE_RTZ(f2u16, f2u_rte);
761 ALU_CASE_RTZ(i2f16, i2f_rte);
762 ALU_CASE_RTZ(u2f16, u2f_rte);
763
764 ALU_CASE(fsin, fsin);
765 ALU_CASE(fcos, fcos);
766
767 /* We'll get 0 in the second arg, so:
768 * ~a = ~(a | 0) = nor(a, 0) */
769 ALU_CASE(inot, inor);
770 ALU_CASE(iand, iand);
771 ALU_CASE(ior, ior);
772 ALU_CASE(ixor, ixor);
773 ALU_CASE(ishl, ishl);
774 ALU_CASE(ishr, iasr);
775 ALU_CASE(ushr, ilsr);
776
777 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
778 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
779 ALU_CASE_CMP(b32all_fequal4, fball_eq, true);
780
781 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
782 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
783 ALU_CASE_CMP(b32any_fnequal4, fbany_neq, true);
784
785 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
786 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
787 ALU_CASE_CMP(b32all_iequal4, iball_eq, true);
788
789 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
790 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
791 ALU_CASE_CMP(b32any_inequal4, ibany_neq, true);
792
793 /* Source mods will be shoved in later */
794 ALU_CASE(fabs, fmov);
795 ALU_CASE(fneg, fmov);
796 ALU_CASE(fsat, fmov);
797 ALU_CASE(fsat_signed, fmov);
798 ALU_CASE(fclamp_pos, fmov);
799
800 /* For size conversion, we use a move. Ideally though we would squash
801 * these ops together; maybe that has to happen after in NIR as part of
802 * propagation...? An earlier algebraic pass ensured we step down by
803 * only / exactly one size. If stepping down, we use a dest override to
804 * reduce the size; if stepping up, we use a larger-sized move with a
805 * half source and a sign/zero-extension modifier */
806
807 case nir_op_i2i8:
808 case nir_op_i2i16:
809 case nir_op_i2i32:
810 case nir_op_i2i64:
811 case nir_op_u2u8:
812 case nir_op_u2u16:
813 case nir_op_u2u32:
814 case nir_op_u2u64:
815 case nir_op_f2f16:
816 case nir_op_f2f32:
817 case nir_op_f2f64: {
818 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
819 instr->op == nir_op_f2f64)
820 op = midgard_alu_op_fmov;
821 else
822 op = midgard_alu_op_imov;
823
824 break;
825 }
826
827 /* For greater-or-equal, we lower to less-or-equal and flip the
828 * arguments */
829
830 case nir_op_fge:
831 case nir_op_fge32:
832 case nir_op_ige32:
833 case nir_op_uge32: {
834 op =
835 instr->op == nir_op_fge ? midgard_alu_op_fle :
836 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
837 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
838 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
839 0;
840
841 flip_src12 = true;
842 ALU_CHECK_CMP(false);
843 break;
844 }
845
846 case nir_op_b32csel: {
847 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
848 bool is_float = mir_is_bcsel_float(instr);
849 op = is_float ?
850 (mixed ? midgard_alu_op_fcsel_v : midgard_alu_op_fcsel) :
851 (mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel);
852
853 break;
854 }
855
856 case nir_op_unpack_32_2x16:
857 case nir_op_unpack_32_4x8:
858 case nir_op_pack_32_2x16:
859 case nir_op_pack_32_4x8: {
860 op = midgard_alu_op_imov;
861 break;
862 }
863
864 default:
865 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
866 assert(0);
867 return;
868 }
869
870 /* Promote imov to fmov if it might help inline a constant */
871 if (op == midgard_alu_op_imov && nir_src_is_const(instr->src[0].src)
872 && nir_src_bit_size(instr->src[0].src) == 32
873 && nir_is_same_comp_swizzle(instr->src[0].swizzle,
874 nir_src_num_components(instr->src[0].src))) {
875 op = midgard_alu_op_fmov;
876 }
877
878 /* Midgard can perform certain modifiers on output of an ALU op */
879
880 unsigned outmod = 0;
881 bool is_int = midgard_is_integer_op(op);
882
883 if (midgard_is_integer_out_op(op)) {
884 outmod = midgard_outmod_int_wrap;
885 } else if (instr->op == nir_op_fsat) {
886 outmod = midgard_outmod_sat;
887 } else if (instr->op == nir_op_fsat_signed) {
888 outmod = midgard_outmod_sat_signed;
889 } else if (instr->op == nir_op_fclamp_pos) {
890 outmod = midgard_outmod_pos;
891 }
892
893 /* Fetch unit, quirks, etc information */
894 unsigned opcode_props = alu_opcode_props[op].props;
895 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
896
897 /* Look for floating point mods. We have the mods fsat, fsat_signed,
898 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
899 *
900 * fsat_signed(fpos(x)) = fsat(x)
901 * fsat_signed(fsat(x)) = fsat(x)
902 * fpos(fsat_signed(x)) = fsat(x)
903 * fpos(fsat(x)) = fsat(x)
904 * fsat(fsat_signed(x)) = fsat(x)
905 * fsat(fpos(x)) = fsat(x)
906 *
907 * So by cases any composition of output modifiers is equivalent to
908 * fsat alone.
909 */
910
911 if (!is_int && !(opcode_props & OP_TYPE_CONVERT)) {
912 bool fpos = mir_accept_dest_mod(ctx, &dest, nir_op_fclamp_pos);
913 bool fsat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat);
914 bool ssat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat_signed);
915 bool prior = (outmod != midgard_outmod_none);
916 int count = (int) prior + (int) fpos + (int) ssat + (int) fsat;
917
918 outmod = ((count > 1) || fsat) ? midgard_outmod_sat :
919 fpos ? midgard_outmod_pos :
920 ssat ? midgard_outmod_sat_signed :
921 outmod;
922 }
923
924 midgard_instruction ins = {
925 .type = TAG_ALU_4,
926 .dest = nir_dest_index(dest),
927 .dest_type = nir_op_infos[instr->op].output_type
928 | nir_dest_bit_size(*dest),
929 .roundmode = roundmode,
930 };
931
932 enum midgard_roundmode *roundptr = (opcode_props & MIDGARD_ROUNDS) ?
933 &ins.roundmode : NULL;
934
935 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
936 ins.src[i] = ~0;
937
938 if (quirk_flipped_r24) {
939 ins.src[0] = ~0;
940 mir_copy_src(&ins, instr, 0, 1, &ins.src_abs[1], &ins.src_neg[1], &ins.src_invert[1], roundptr, is_int, broadcast_swizzle);
941 } else {
942 for (unsigned i = 0; i < nr_inputs; ++i) {
943 unsigned to = i;
944
945 if (instr->op == nir_op_b32csel) {
946 /* The condition is the first argument; move
947 * the other arguments up one to be a binary
948 * instruction for Midgard with the condition
949 * last */
950
951 if (i == 0)
952 to = 2;
953 else if (flip_src12)
954 to = 2 - i;
955 else
956 to = i - 1;
957 } else if (flip_src12) {
958 to = 1 - to;
959 }
960
961 mir_copy_src(&ins, instr, i, to, &ins.src_abs[to], &ins.src_neg[to], &ins.src_invert[to], roundptr, is_int, broadcast_swizzle);
962
963 /* (!c) ? a : b = c ? b : a */
964 if (instr->op == nir_op_b32csel && ins.src_invert[2]) {
965 ins.src_invert[2] = false;
966 flip_src12 ^= true;
967 }
968 }
969 }
970
971 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
972 /* Lowered to move */
973 if (instr->op == nir_op_fneg)
974 ins.src_neg[1] ^= true;
975
976 if (instr->op == nir_op_fabs)
977 ins.src_abs[1] = true;
978 }
979
980 ins.mask = mask_of(nr_components);
981
982 midgard_vector_alu alu = {
983 .op = op,
984 .reg_mode = reg_mode,
985 .outmod = outmod,
986 };
987
988 /* Apply writemask if non-SSA, keeping in mind that we can't write to
989 * components that don't exist. Note modifier => SSA => !reg => no
990 * writemask, so we don't have to worry about writemasks here.*/
991
992 if (!is_ssa)
993 ins.mask &= instr->dest.write_mask;
994
995 ins.alu = alu;
996
997 /* Late fixup for emulated instructions */
998
999 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1000 /* Presently, our second argument is an inline #0 constant.
1001 * Switch over to an embedded 1.0 constant (that can't fit
1002 * inline, since we're 32-bit, not 16-bit like the inline
1003 * constants) */
1004
1005 ins.has_inline_constant = false;
1006 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1007 ins.src_types[1] = nir_type_float32;
1008 ins.has_constants = true;
1009
1010 if (instr->op == nir_op_b2f32)
1011 ins.constants.f32[0] = 1.0f;
1012 else
1013 ins.constants.i32[0] = 1;
1014
1015 for (unsigned c = 0; c < 16; ++c)
1016 ins.swizzle[1][c] = 0;
1017 } else if (instr->op == nir_op_b2f16) {
1018 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1019 ins.src_types[1] = nir_type_float16;
1020 ins.has_constants = true;
1021 ins.constants.i16[0] = _mesa_float_to_half(1.0);
1022
1023 for (unsigned c = 0; c < 16; ++c)
1024 ins.swizzle[1][c] = 0;
1025 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1026 /* Lots of instructions need a 0 plonked in */
1027 ins.has_inline_constant = false;
1028 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1029 ins.src_types[1] = nir_type_uint32;
1030 ins.has_constants = true;
1031 ins.constants.u32[0] = 0;
1032
1033 for (unsigned c = 0; c < 16; ++c)
1034 ins.swizzle[1][c] = 0;
1035 } else if (instr->op == nir_op_pack_32_2x16) {
1036 ins.dest_type = nir_type_uint16;
1037 ins.mask = mask_of(nr_components * 2);
1038 ins.is_pack = true;
1039 } else if (instr->op == nir_op_pack_32_4x8) {
1040 ins.dest_type = nir_type_uint8;
1041 ins.mask = mask_of(nr_components * 4);
1042 ins.is_pack = true;
1043 } else if (instr->op == nir_op_unpack_32_2x16) {
1044 ins.dest_type = nir_type_uint32;
1045 ins.mask = mask_of(nr_components >> 1);
1046 ins.is_pack = true;
1047 } else if (instr->op == nir_op_unpack_32_4x8) {
1048 ins.dest_type = nir_type_uint32;
1049 ins.mask = mask_of(nr_components >> 2);
1050 ins.is_pack = true;
1051 }
1052
1053 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1054 /* To avoid duplicating the lookup tables (probably), true LUT
1055 * instructions can only operate as if they were scalars. Lower
1056 * them here by changing the component. */
1057
1058 unsigned orig_mask = ins.mask;
1059
1060 unsigned swizzle_back[MIR_VEC_COMPONENTS];
1061 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
1062
1063 for (int i = 0; i < nr_components; ++i) {
1064 /* Mask the associated component, dropping the
1065 * instruction if needed */
1066
1067 ins.mask = 1 << i;
1068 ins.mask &= orig_mask;
1069
1070 if (!ins.mask)
1071 continue;
1072
1073 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1074 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1075
1076 emit_mir_instruction(ctx, ins);
1077 }
1078 } else {
1079 emit_mir_instruction(ctx, ins);
1080 }
1081 }
1082
1083 #undef ALU_CASE
1084
1085 static void
1086 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1087 {
1088 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1089 unsigned nir_mask = 0;
1090 unsigned dsize = 0;
1091
1092 if (is_read) {
1093 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1094 dsize = nir_dest_bit_size(intr->dest);
1095 } else {
1096 nir_mask = nir_intrinsic_write_mask(intr);
1097 dsize = 32;
1098 }
1099
1100 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1101 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1102 mir_set_bytemask(ins, bytemask);
1103 ins->dest_type = nir_type_uint | dsize;
1104 }
1105
1106 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1107 * optimized) versions of UBO #0 */
1108
1109 static midgard_instruction *
1110 emit_ubo_read(
1111 compiler_context *ctx,
1112 nir_instr *instr,
1113 unsigned dest,
1114 unsigned offset,
1115 nir_src *indirect_offset,
1116 unsigned indirect_shift,
1117 unsigned index)
1118 {
1119 /* TODO: half-floats */
1120
1121 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1122 ins.constants.u32[0] = offset;
1123
1124 if (instr->type == nir_instr_type_intrinsic)
1125 mir_set_intr_mask(instr, &ins, true);
1126
1127 if (indirect_offset) {
1128 ins.src[2] = nir_src_index(ctx, indirect_offset);
1129 ins.src_types[2] = nir_type_uint32;
1130 ins.load_store.arg_2 = (indirect_shift << 5);
1131 } else {
1132 ins.load_store.arg_2 = 0x1E;
1133 }
1134
1135 ins.load_store.arg_1 = index;
1136
1137 return emit_mir_instruction(ctx, ins);
1138 }
1139
1140 /* Globals are like UBOs if you squint. And shared memory is like globals if
1141 * you squint even harder */
1142
1143 static void
1144 emit_global(
1145 compiler_context *ctx,
1146 nir_instr *instr,
1147 bool is_read,
1148 unsigned srcdest,
1149 nir_src *offset,
1150 bool is_shared)
1151 {
1152 /* TODO: types */
1153
1154 midgard_instruction ins;
1155
1156 if (is_read)
1157 ins = m_ld_int4(srcdest, 0);
1158 else
1159 ins = m_st_int4(srcdest, 0);
1160
1161 mir_set_offset(ctx, &ins, offset, is_shared);
1162 mir_set_intr_mask(instr, &ins, is_read);
1163
1164 emit_mir_instruction(ctx, ins);
1165 }
1166
1167 static void
1168 emit_varying_read(
1169 compiler_context *ctx,
1170 unsigned dest, unsigned offset,
1171 unsigned nr_comp, unsigned component,
1172 nir_src *indirect_offset, nir_alu_type type, bool flat)
1173 {
1174 /* XXX: Half-floats? */
1175 /* TODO: swizzle, mask */
1176
1177 midgard_instruction ins = m_ld_vary_32(dest, offset);
1178 ins.mask = mask_of(nr_comp);
1179 ins.dest_type = type;
1180
1181 if (type == nir_type_float16) {
1182 /* Ensure we are aligned so we can pack it later */
1183 ins.mask = mask_of(ALIGN_POT(nr_comp, 2));
1184 }
1185
1186 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1187 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1188
1189 midgard_varying_parameter p = {
1190 .is_varying = 1,
1191 .interpolation = midgard_interp_default,
1192 .flat = flat,
1193 };
1194
1195 unsigned u;
1196 memcpy(&u, &p, sizeof(p));
1197 ins.load_store.varying_parameters = u;
1198
1199 if (indirect_offset) {
1200 ins.src[2] = nir_src_index(ctx, indirect_offset);
1201 ins.src_types[2] = nir_type_uint32;
1202 } else
1203 ins.load_store.arg_2 = 0x1E;
1204
1205 ins.load_store.arg_1 = 0x9E;
1206
1207 /* Use the type appropriate load */
1208 switch (type) {
1209 case nir_type_uint32:
1210 case nir_type_bool32:
1211 ins.load_store.op = midgard_op_ld_vary_32u;
1212 break;
1213 case nir_type_int32:
1214 ins.load_store.op = midgard_op_ld_vary_32i;
1215 break;
1216 case nir_type_float32:
1217 ins.load_store.op = midgard_op_ld_vary_32;
1218 break;
1219 case nir_type_float16:
1220 ins.load_store.op = midgard_op_ld_vary_16;
1221 break;
1222 default:
1223 unreachable("Attempted to load unknown type");
1224 break;
1225 }
1226
1227 emit_mir_instruction(ctx, ins);
1228 }
1229
1230 static void
1231 emit_attr_read(
1232 compiler_context *ctx,
1233 unsigned dest, unsigned offset,
1234 unsigned nr_comp, nir_alu_type t)
1235 {
1236 midgard_instruction ins = m_ld_attr_32(dest, offset);
1237 ins.load_store.arg_1 = 0x1E;
1238 ins.load_store.arg_2 = 0x1E;
1239 ins.mask = mask_of(nr_comp);
1240
1241 /* Use the type appropriate load */
1242 switch (t) {
1243 case nir_type_uint:
1244 case nir_type_bool:
1245 ins.load_store.op = midgard_op_ld_attr_32u;
1246 break;
1247 case nir_type_int:
1248 ins.load_store.op = midgard_op_ld_attr_32i;
1249 break;
1250 case nir_type_float:
1251 ins.load_store.op = midgard_op_ld_attr_32;
1252 break;
1253 default:
1254 unreachable("Attempted to load unknown type");
1255 break;
1256 }
1257
1258 emit_mir_instruction(ctx, ins);
1259 }
1260
1261 static void
1262 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1263 unsigned nr_components, unsigned offset)
1264 {
1265 nir_dest nir_dest;
1266
1267 /* Figure out which uniform this is */
1268 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1269 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1270
1271 unsigned dest = nir_dest_index(&nir_dest);
1272
1273 /* Sysvals are prefix uniforms */
1274 unsigned uniform = ((uintptr_t) val) - 1;
1275
1276 /* Emit the read itself -- this is never indirect */
1277 midgard_instruction *ins =
1278 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1279
1280 ins->mask = mask_of(nr_components);
1281 }
1282
1283 static unsigned
1284 compute_builtin_arg(nir_op op)
1285 {
1286 switch (op) {
1287 case nir_intrinsic_load_work_group_id:
1288 return 0x14;
1289 case nir_intrinsic_load_local_invocation_id:
1290 return 0x10;
1291 default:
1292 unreachable("Invalid compute paramater loaded");
1293 }
1294 }
1295
1296 static void
1297 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1298 {
1299 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1300
1301 midgard_instruction *br = ctx->writeout_branch[rt];
1302
1303 assert(!br);
1304
1305 emit_explicit_constant(ctx, src, src);
1306
1307 struct midgard_instruction ins =
1308 v_branch(false, false);
1309
1310 bool depth_only = (rt == MIDGARD_ZS_RT);
1311
1312 ins.writeout = depth_only ? PAN_WRITEOUT_Z : PAN_WRITEOUT_C;
1313
1314 /* Add dependencies */
1315 ins.src[0] = src;
1316 ins.src_types[0] = nir_type_uint32;
1317 ins.constants.u32[0] = depth_only ? 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1318 for (int i = 0; i < 4; ++i)
1319 ins.swizzle[0][i] = i;
1320
1321 /* Emit the branch */
1322 br = emit_mir_instruction(ctx, ins);
1323 schedule_barrier(ctx);
1324 ctx->writeout_branch[rt] = br;
1325
1326 /* Push our current location = current block count - 1 = where we'll
1327 * jump to. Maybe a bit too clever for my own good */
1328
1329 br->branch.target_block = ctx->block_count - 1;
1330 }
1331
1332 static void
1333 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1334 {
1335 unsigned reg = nir_dest_index(&instr->dest);
1336 midgard_instruction ins = m_ld_compute_id(reg, 0);
1337 ins.mask = mask_of(3);
1338 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1339 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1340 emit_mir_instruction(ctx, ins);
1341 }
1342
1343 static unsigned
1344 vertex_builtin_arg(nir_op op)
1345 {
1346 switch (op) {
1347 case nir_intrinsic_load_vertex_id:
1348 return PAN_VERTEX_ID;
1349 case nir_intrinsic_load_instance_id:
1350 return PAN_INSTANCE_ID;
1351 default:
1352 unreachable("Invalid vertex builtin");
1353 }
1354 }
1355
1356 static void
1357 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1358 {
1359 unsigned reg = nir_dest_index(&instr->dest);
1360 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1361 }
1362
1363 static void
1364 emit_control_barrier(compiler_context *ctx)
1365 {
1366 midgard_instruction ins = {
1367 .type = TAG_TEXTURE_4,
1368 .dest = ~0,
1369 .src = { ~0, ~0, ~0, ~0 },
1370 .texture = {
1371 .op = TEXTURE_OP_BARRIER,
1372
1373 /* TODO: optimize */
1374 .out_of_order = MIDGARD_BARRIER_BUFFER |
1375 MIDGARD_BARRIER_SHARED ,
1376 }
1377 };
1378
1379 emit_mir_instruction(ctx, ins);
1380 }
1381
1382 static const nir_variable *
1383 search_var(struct exec_list *vars, unsigned driver_loc)
1384 {
1385 nir_foreach_variable(var, vars) {
1386 if (var->data.driver_location == driver_loc)
1387 return var;
1388 }
1389
1390 return NULL;
1391 }
1392
1393 static unsigned
1394 mir_get_branch_cond(nir_src *src, bool *invert)
1395 {
1396 /* Wrap it. No swizzle since it's a scalar */
1397
1398 nir_alu_src alu = {
1399 .src = *src
1400 };
1401
1402 *invert = pan_has_source_mod(&alu, nir_op_inot);
1403 return nir_src_index(NULL, &alu.src);
1404 }
1405
1406 static void
1407 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1408 {
1409 unsigned offset = 0, reg;
1410
1411 switch (instr->intrinsic) {
1412 case nir_intrinsic_discard_if:
1413 case nir_intrinsic_discard: {
1414 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1415 struct midgard_instruction discard = v_branch(conditional, false);
1416 discard.branch.target_type = TARGET_DISCARD;
1417
1418 if (conditional) {
1419 discard.src[0] = mir_get_branch_cond(&instr->src[0],
1420 &discard.branch.invert_conditional);
1421 discard.src_types[0] = nir_type_uint32;
1422 }
1423
1424 emit_mir_instruction(ctx, discard);
1425 schedule_barrier(ctx);
1426
1427 break;
1428 }
1429
1430 case nir_intrinsic_load_uniform:
1431 case nir_intrinsic_load_ubo:
1432 case nir_intrinsic_load_global:
1433 case nir_intrinsic_load_shared:
1434 case nir_intrinsic_load_input:
1435 case nir_intrinsic_load_interpolated_input: {
1436 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1437 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1438 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1439 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1440 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1441 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1442
1443 /* Get the base type of the intrinsic */
1444 /* TODO: Infer type? Does it matter? */
1445 nir_alu_type t =
1446 (is_ubo || is_global || is_shared) ? nir_type_uint :
1447 (is_interp) ? nir_type_float :
1448 nir_intrinsic_type(instr);
1449
1450 t = nir_alu_type_get_base_type(t);
1451
1452 if (!(is_ubo || is_global)) {
1453 offset = nir_intrinsic_base(instr);
1454 }
1455
1456 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1457
1458 nir_src *src_offset = nir_get_io_offset_src(instr);
1459
1460 bool direct = nir_src_is_const(*src_offset);
1461 nir_src *indirect_offset = direct ? NULL : src_offset;
1462
1463 if (direct)
1464 offset += nir_src_as_uint(*src_offset);
1465
1466 /* We may need to apply a fractional offset */
1467 int component = (is_flat || is_interp) ?
1468 nir_intrinsic_component(instr) : 0;
1469 reg = nir_dest_index(&instr->dest);
1470
1471 if (is_uniform && !ctx->is_blend) {
1472 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1473 } else if (is_ubo) {
1474 nir_src index = instr->src[0];
1475
1476 /* TODO: Is indirect block number possible? */
1477 assert(nir_src_is_const(index));
1478
1479 uint32_t uindex = nir_src_as_uint(index) + 1;
1480 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1481 } else if (is_global || is_shared) {
1482 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1483 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1484 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t | nir_dest_bit_size(instr->dest), is_flat);
1485 } else if (ctx->is_blend) {
1486 /* For blend shaders, load the input color, which is
1487 * preloaded to r0 */
1488
1489 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1490 emit_mir_instruction(ctx, move);
1491 schedule_barrier(ctx);
1492 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1493 emit_attr_read(ctx, reg, offset, nr_comp, t);
1494 } else {
1495 DBG("Unknown load\n");
1496 assert(0);
1497 }
1498
1499 break;
1500 }
1501
1502 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1503 case nir_intrinsic_load_barycentric_pixel:
1504 case nir_intrinsic_load_barycentric_centroid:
1505 break;
1506
1507 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1508
1509 case nir_intrinsic_load_raw_output_pan: {
1510 reg = nir_dest_index(&instr->dest);
1511 assert(ctx->is_blend);
1512
1513 /* T720 and below use different blend opcodes with slightly
1514 * different semantics than T760 and up */
1515
1516 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1517
1518 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1519 ld.load_store.op = midgard_op_ld_color_buffer_32u_old;
1520 ld.load_store.address = 16;
1521 ld.load_store.arg_2 = 0x1E;
1522 }
1523
1524 emit_mir_instruction(ctx, ld);
1525 break;
1526 }
1527
1528 case nir_intrinsic_load_output: {
1529 reg = nir_dest_index(&instr->dest);
1530 assert(ctx->is_blend);
1531
1532 midgard_instruction ld = m_ld_color_buffer_as_fp16(reg, 0);
1533
1534 for (unsigned c = 4; c < 16; ++c)
1535 ld.swizzle[0][c] = 0;
1536
1537 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1538 ld.load_store.op = midgard_op_ld_color_buffer_as_fp16_old;
1539 ld.load_store.address = 1;
1540 ld.load_store.arg_2 = 0x1E;
1541 }
1542
1543 emit_mir_instruction(ctx, ld);
1544 break;
1545 }
1546
1547 case nir_intrinsic_load_blend_const_color_rgba: {
1548 assert(ctx->is_blend);
1549 reg = nir_dest_index(&instr->dest);
1550
1551 /* Blend constants are embedded directly in the shader and
1552 * patched in, so we use some magic routing */
1553
1554 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1555 ins.has_constants = true;
1556 ins.has_blend_constant = true;
1557 emit_mir_instruction(ctx, ins);
1558 break;
1559 }
1560
1561 case nir_intrinsic_store_output:
1562 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1563
1564 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1565
1566 reg = nir_src_index(ctx, &instr->src[0]);
1567
1568 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1569 const nir_variable *var;
1570 enum midgard_rt_id rt;
1571
1572 var = search_var(&ctx->nir->outputs,
1573 nir_intrinsic_base(instr));
1574 assert(var);
1575 if (var->data.location == FRAG_RESULT_COLOR)
1576 rt = MIDGARD_COLOR_RT0;
1577 else if (var->data.location >= FRAG_RESULT_DATA0)
1578 rt = MIDGARD_COLOR_RT0 + var->data.location -
1579 FRAG_RESULT_DATA0;
1580 else
1581 assert(0);
1582
1583 emit_fragment_store(ctx, reg, rt);
1584 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1585 /* We should have been vectorized, though we don't
1586 * currently check that st_vary is emitted only once
1587 * per slot (this is relevant, since there's not a mask
1588 * parameter available on the store [set to 0 by the
1589 * blob]). We do respect the component by adjusting the
1590 * swizzle. If this is a constant source, we'll need to
1591 * emit that explicitly. */
1592
1593 emit_explicit_constant(ctx, reg, reg);
1594
1595 unsigned dst_component = nir_intrinsic_component(instr);
1596 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1597
1598 midgard_instruction st = m_st_vary_32(reg, offset);
1599 st.load_store.arg_1 = 0x9E;
1600 st.load_store.arg_2 = 0x1E;
1601
1602 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1603 case nir_type_uint:
1604 case nir_type_bool:
1605 st.load_store.op = midgard_op_st_vary_32u;
1606 break;
1607 case nir_type_int:
1608 st.load_store.op = midgard_op_st_vary_32i;
1609 break;
1610 case nir_type_float:
1611 st.load_store.op = midgard_op_st_vary_32;
1612 break;
1613 default:
1614 unreachable("Attempted to store unknown type");
1615 break;
1616 }
1617
1618 /* nir_intrinsic_component(store_intr) encodes the
1619 * destination component start. Source component offset
1620 * adjustment is taken care of in
1621 * install_registers_instr(), when offset_swizzle() is
1622 * called.
1623 */
1624 unsigned src_component = COMPONENT_X;
1625
1626 assert(nr_comp > 0);
1627 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1628 st.swizzle[0][i] = src_component;
1629 if (i >= dst_component && i < dst_component + nr_comp - 1)
1630 src_component++;
1631 }
1632
1633 emit_mir_instruction(ctx, st);
1634 } else {
1635 DBG("Unknown store\n");
1636 assert(0);
1637 }
1638
1639 break;
1640
1641 /* Special case of store_output for lowered blend shaders */
1642 case nir_intrinsic_store_raw_output_pan:
1643 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1644 reg = nir_src_index(ctx, &instr->src[0]);
1645 emit_fragment_store(ctx, reg, ctx->blend_rt);
1646 break;
1647
1648 case nir_intrinsic_store_global:
1649 case nir_intrinsic_store_shared:
1650 reg = nir_src_index(ctx, &instr->src[0]);
1651 emit_explicit_constant(ctx, reg, reg);
1652
1653 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1654 break;
1655
1656 case nir_intrinsic_load_ssbo_address:
1657 emit_sysval_read(ctx, &instr->instr, 1, 0);
1658 break;
1659
1660 case nir_intrinsic_get_buffer_size:
1661 emit_sysval_read(ctx, &instr->instr, 1, 8);
1662 break;
1663
1664 case nir_intrinsic_load_viewport_scale:
1665 case nir_intrinsic_load_viewport_offset:
1666 case nir_intrinsic_load_num_work_groups:
1667 case nir_intrinsic_load_sampler_lod_parameters_pan:
1668 emit_sysval_read(ctx, &instr->instr, 3, 0);
1669 break;
1670
1671 case nir_intrinsic_load_work_group_id:
1672 case nir_intrinsic_load_local_invocation_id:
1673 emit_compute_builtin(ctx, instr);
1674 break;
1675
1676 case nir_intrinsic_load_vertex_id:
1677 case nir_intrinsic_load_instance_id:
1678 emit_vertex_builtin(ctx, instr);
1679 break;
1680
1681 case nir_intrinsic_memory_barrier_buffer:
1682 case nir_intrinsic_memory_barrier_shared:
1683 break;
1684
1685 case nir_intrinsic_control_barrier:
1686 schedule_barrier(ctx);
1687 emit_control_barrier(ctx);
1688 schedule_barrier(ctx);
1689 break;
1690
1691 default:
1692 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1693 assert(0);
1694 break;
1695 }
1696 }
1697
1698 static unsigned
1699 midgard_tex_format(enum glsl_sampler_dim dim)
1700 {
1701 switch (dim) {
1702 case GLSL_SAMPLER_DIM_1D:
1703 case GLSL_SAMPLER_DIM_BUF:
1704 return MALI_TEX_1D;
1705
1706 case GLSL_SAMPLER_DIM_2D:
1707 case GLSL_SAMPLER_DIM_EXTERNAL:
1708 case GLSL_SAMPLER_DIM_RECT:
1709 return MALI_TEX_2D;
1710
1711 case GLSL_SAMPLER_DIM_3D:
1712 return MALI_TEX_3D;
1713
1714 case GLSL_SAMPLER_DIM_CUBE:
1715 return MALI_TEX_CUBE;
1716
1717 default:
1718 DBG("Unknown sampler dim type\n");
1719 assert(0);
1720 return 0;
1721 }
1722 }
1723
1724 /* Tries to attach an explicit LOD or bias as a constant. Returns whether this
1725 * was successful */
1726
1727 static bool
1728 pan_attach_constant_bias(
1729 compiler_context *ctx,
1730 nir_src lod,
1731 midgard_texture_word *word)
1732 {
1733 /* To attach as constant, it has to *be* constant */
1734
1735 if (!nir_src_is_const(lod))
1736 return false;
1737
1738 float f = nir_src_as_float(lod);
1739
1740 /* Break into fixed-point */
1741 signed lod_int = f;
1742 float lod_frac = f - lod_int;
1743
1744 /* Carry over negative fractions */
1745 if (lod_frac < 0.0) {
1746 lod_int--;
1747 lod_frac += 1.0;
1748 }
1749
1750 /* Encode */
1751 word->bias = float_to_ubyte(lod_frac);
1752 word->bias_int = lod_int;
1753
1754 return true;
1755 }
1756
1757 static void
1758 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1759 unsigned midgard_texop)
1760 {
1761 /* TODO */
1762 //assert (!instr->sampler);
1763
1764 int texture_index = instr->texture_index;
1765 int sampler_index = texture_index;
1766
1767 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1768 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1769
1770 midgard_instruction ins = {
1771 .type = TAG_TEXTURE_4,
1772 .mask = 0xF,
1773 .dest = nir_dest_index(&instr->dest),
1774 .src = { ~0, ~0, ~0, ~0 },
1775 .dest_type = dest_type,
1776 .swizzle = SWIZZLE_IDENTITY_4,
1777 .texture = {
1778 .op = midgard_texop,
1779 .format = midgard_tex_format(instr->sampler_dim),
1780 .texture_handle = texture_index,
1781 .sampler_handle = sampler_index,
1782 .shadow = instr->is_shadow,
1783 }
1784 };
1785
1786 if (instr->is_shadow && !instr->is_new_style_shadow)
1787 for (int i = 0; i < 4; ++i)
1788 ins.swizzle[0][i] = COMPONENT_X;
1789
1790 /* We may need a temporary for the coordinate */
1791
1792 bool needs_temp_coord =
1793 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1794 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1795 (instr->is_shadow);
1796
1797 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1798
1799 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1800 int index = nir_src_index(ctx, &instr->src[i].src);
1801 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1802 unsigned sz = nir_src_bit_size(instr->src[i].src);
1803 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1804
1805 switch (instr->src[i].src_type) {
1806 case nir_tex_src_coord: {
1807 emit_explicit_constant(ctx, index, index);
1808
1809 unsigned coord_mask = mask_of(instr->coord_components);
1810
1811 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1812
1813 if (flip_zw)
1814 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1815
1816 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1817 /* texelFetch is undefined on samplerCube */
1818 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1819
1820 /* For cubemaps, we use a special ld/st op to
1821 * select the face and copy the xy into the
1822 * texture register */
1823
1824 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1825 ld.src[1] = index;
1826 ld.src_types[1] = T;
1827 ld.mask = 0x3; /* xy */
1828 ld.load_store.arg_1 = 0x20;
1829 ld.swizzle[1][3] = COMPONENT_X;
1830 emit_mir_instruction(ctx, ld);
1831
1832 /* xyzw -> xyxx */
1833 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1834 ins.swizzle[1][3] = COMPONENT_X;
1835 } else if (needs_temp_coord) {
1836 /* mov coord_temp, coords */
1837 midgard_instruction mov = v_mov(index, coords);
1838 mov.mask = coord_mask;
1839
1840 if (flip_zw)
1841 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1842
1843 emit_mir_instruction(ctx, mov);
1844 } else {
1845 coords = index;
1846 }
1847
1848 ins.src[1] = coords;
1849 ins.src_types[1] = T;
1850
1851 /* Texelfetch coordinates uses all four elements
1852 * (xyz/index) regardless of texture dimensionality,
1853 * which means it's necessary to zero the unused
1854 * components to keep everything happy */
1855
1856 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1857 /* mov index.zw, #0, or generalized */
1858 midgard_instruction mov =
1859 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1860 mov.has_constants = true;
1861 mov.mask = coord_mask ^ 0xF;
1862 emit_mir_instruction(ctx, mov);
1863 }
1864
1865 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1866 /* Array component in w but NIR wants it in z,
1867 * but if we have a temp coord we already fixed
1868 * that up */
1869
1870 if (nr_components == 3) {
1871 ins.swizzle[1][2] = COMPONENT_Z;
1872 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1873 } else if (nr_components == 2) {
1874 ins.swizzle[1][2] =
1875 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1876 ins.swizzle[1][3] = COMPONENT_X;
1877 } else
1878 unreachable("Invalid texture 2D components");
1879 }
1880
1881 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1882 /* We zeroed */
1883 ins.swizzle[1][2] = COMPONENT_Z;
1884 ins.swizzle[1][3] = COMPONENT_W;
1885 }
1886
1887 break;
1888 }
1889
1890 case nir_tex_src_bias:
1891 case nir_tex_src_lod: {
1892 /* Try as a constant if we can */
1893
1894 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1895 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1896 break;
1897
1898 ins.texture.lod_register = true;
1899 ins.src[2] = index;
1900 ins.src_types[2] = T;
1901
1902 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1903 ins.swizzle[2][c] = COMPONENT_X;
1904
1905 emit_explicit_constant(ctx, index, index);
1906
1907 break;
1908 };
1909
1910 case nir_tex_src_offset: {
1911 ins.texture.offset_register = true;
1912 ins.src[3] = index;
1913 ins.src_types[3] = T;
1914
1915 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1916 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
1917
1918 emit_explicit_constant(ctx, index, index);
1919 break;
1920 };
1921
1922 case nir_tex_src_comparator: {
1923 unsigned comp = COMPONENT_Z;
1924
1925 /* mov coord_temp.foo, coords */
1926 midgard_instruction mov = v_mov(index, coords);
1927 mov.mask = 1 << comp;
1928
1929 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
1930 mov.swizzle[1][i] = COMPONENT_X;
1931
1932 emit_mir_instruction(ctx, mov);
1933 break;
1934 }
1935
1936 default: {
1937 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
1938 assert(0);
1939 }
1940 }
1941 }
1942
1943 emit_mir_instruction(ctx, ins);
1944 }
1945
1946 static void
1947 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1948 {
1949 switch (instr->op) {
1950 case nir_texop_tex:
1951 case nir_texop_txb:
1952 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
1953 break;
1954 case nir_texop_txl:
1955 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
1956 break;
1957 case nir_texop_txf:
1958 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
1959 break;
1960 case nir_texop_txs:
1961 emit_sysval_read(ctx, &instr->instr, 4, 0);
1962 break;
1963 default: {
1964 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
1965 assert(0);
1966 }
1967 }
1968 }
1969
1970 static void
1971 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1972 {
1973 switch (instr->type) {
1974 case nir_jump_break: {
1975 /* Emit a branch out of the loop */
1976 struct midgard_instruction br = v_branch(false, false);
1977 br.branch.target_type = TARGET_BREAK;
1978 br.branch.target_break = ctx->current_loop_depth;
1979 emit_mir_instruction(ctx, br);
1980 break;
1981 }
1982
1983 default:
1984 DBG("Unknown jump type %d\n", instr->type);
1985 break;
1986 }
1987 }
1988
1989 static void
1990 emit_instr(compiler_context *ctx, struct nir_instr *instr)
1991 {
1992 switch (instr->type) {
1993 case nir_instr_type_load_const:
1994 emit_load_const(ctx, nir_instr_as_load_const(instr));
1995 break;
1996
1997 case nir_instr_type_intrinsic:
1998 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1999 break;
2000
2001 case nir_instr_type_alu:
2002 emit_alu(ctx, nir_instr_as_alu(instr));
2003 break;
2004
2005 case nir_instr_type_tex:
2006 emit_tex(ctx, nir_instr_as_tex(instr));
2007 break;
2008
2009 case nir_instr_type_jump:
2010 emit_jump(ctx, nir_instr_as_jump(instr));
2011 break;
2012
2013 case nir_instr_type_ssa_undef:
2014 /* Spurious */
2015 break;
2016
2017 default:
2018 DBG("Unhandled instruction type\n");
2019 break;
2020 }
2021 }
2022
2023
2024 /* ALU instructions can inline or embed constants, which decreases register
2025 * pressure and saves space. */
2026
2027 #define CONDITIONAL_ATTACH(idx) { \
2028 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2029 \
2030 if (entry) { \
2031 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2032 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2033 } \
2034 }
2035
2036 static void
2037 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2038 {
2039 mir_foreach_instr_in_block(block, alu) {
2040 /* Other instructions cannot inline constants */
2041 if (alu->type != TAG_ALU_4) continue;
2042 if (alu->compact_branch) continue;
2043
2044 /* If there is already a constant here, we can do nothing */
2045 if (alu->has_constants) continue;
2046
2047 CONDITIONAL_ATTACH(0);
2048
2049 if (!alu->has_constants) {
2050 CONDITIONAL_ATTACH(1)
2051 } else if (!alu->inline_constant) {
2052 /* Corner case: _two_ vec4 constants, for instance with a
2053 * csel. For this case, we can only use a constant
2054 * register for one, we'll have to emit a move for the
2055 * other. */
2056
2057 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2058 unsigned scratch = make_compiler_temp(ctx);
2059
2060 if (entry) {
2061 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2062 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2063
2064 /* Set the source */
2065 alu->src[1] = scratch;
2066
2067 /* Inject us -before- the last instruction which set r31 */
2068 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2069 }
2070 }
2071 }
2072 }
2073
2074 /* Midgard supports two types of constants, embedded constants (128-bit) and
2075 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2076 * constants can be demoted to inline constants, for space savings and
2077 * sometimes a performance boost */
2078
2079 static void
2080 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2081 {
2082 mir_foreach_instr_in_block(block, ins) {
2083 if (!ins->has_constants) continue;
2084 if (ins->has_inline_constant) continue;
2085
2086 /* Blend constants must not be inlined by definition */
2087 if (ins->has_blend_constant) continue;
2088
2089 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2090 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2091 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2092
2093 if (!(is_16 || is_32))
2094 continue;
2095
2096 /* src1 cannot be an inline constant due to encoding
2097 * restrictions. So, if possible we try to flip the arguments
2098 * in that case */
2099
2100 int op = ins->alu.op;
2101
2102 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2103 alu_opcode_props[op].props & OP_COMMUTES) {
2104 mir_flip(ins);
2105 }
2106
2107 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2108 /* Component is from the swizzle. Take a nonzero component */
2109 assert(ins->mask);
2110 unsigned first_comp = ffs(ins->mask) - 1;
2111 unsigned component = ins->swizzle[1][first_comp];
2112
2113 /* Scale constant appropriately, if we can legally */
2114 int16_t scaled_constant = 0;
2115
2116 if (is_16) {
2117 scaled_constant = ins->constants.u16[component];
2118 } else if (midgard_is_integer_op(op)) {
2119 scaled_constant = ins->constants.u32[component];
2120
2121 /* Constant overflow after resize */
2122 if (scaled_constant != ins->constants.u32[component])
2123 continue;
2124 } else {
2125 float original = ins->constants.f32[component];
2126 scaled_constant = _mesa_float_to_half(original);
2127
2128 /* Check for loss of precision. If this is
2129 * mediump, we don't care, but for a highp
2130 * shader, we need to pay attention. NIR
2131 * doesn't yet tell us which mode we're in!
2132 * Practically this prevents most constants
2133 * from being inlined, sadly. */
2134
2135 float fp32 = _mesa_half_to_float(scaled_constant);
2136
2137 if (fp32 != original)
2138 continue;
2139 }
2140
2141 /* Should've been const folded */
2142 if (ins->src_abs[1] || ins->src_neg[1])
2143 continue;
2144
2145 /* Make sure that the constant is not itself a vector
2146 * by checking if all accessed values are the same. */
2147
2148 const midgard_constants *cons = &ins->constants;
2149 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2150
2151 bool is_vector = false;
2152 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2153
2154 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2155 /* We only care if this component is actually used */
2156 if (!(mask & (1 << c)))
2157 continue;
2158
2159 uint32_t test = is_16 ?
2160 cons->u16[ins->swizzle[1][c]] :
2161 cons->u32[ins->swizzle[1][c]];
2162
2163 if (test != value) {
2164 is_vector = true;
2165 break;
2166 }
2167 }
2168
2169 if (is_vector)
2170 continue;
2171
2172 /* Get rid of the embedded constant */
2173 ins->has_constants = false;
2174 ins->src[1] = ~0;
2175 ins->has_inline_constant = true;
2176 ins->inline_constant = scaled_constant;
2177 }
2178 }
2179 }
2180
2181 /* Dead code elimination for branches at the end of a block - only one branch
2182 * per block is legal semantically */
2183
2184 static void
2185 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2186 {
2187 bool branched = false;
2188
2189 mir_foreach_instr_in_block_safe(block, ins) {
2190 if (!midgard_is_branch_unit(ins->unit)) continue;
2191
2192 if (branched)
2193 mir_remove_instruction(ins);
2194
2195 branched = true;
2196 }
2197 }
2198
2199 /* We want to force the invert on AND/OR to the second slot to legalize into
2200 * iandnot/iornot. The relevant patterns are for AND (and OR respectively)
2201 *
2202 * ~a & #b = ~a & ~(#~b)
2203 * ~a & b = b & ~a
2204 */
2205
2206 static void
2207 midgard_legalize_invert(compiler_context *ctx, midgard_block *block)
2208 {
2209 mir_foreach_instr_in_block(block, ins) {
2210 if (ins->type != TAG_ALU_4) continue;
2211
2212 if (ins->alu.op != midgard_alu_op_iand &&
2213 ins->alu.op != midgard_alu_op_ior) continue;
2214
2215 if (ins->src_invert[1] || !ins->src_invert[0]) continue;
2216
2217 if (ins->has_inline_constant) {
2218 /* ~(#~a) = ~(~#a) = a, so valid, and forces both
2219 * inverts on */
2220 ins->inline_constant = ~ins->inline_constant;
2221 ins->src_invert[1] = true;
2222 } else {
2223 /* Flip to the right invert order. Note
2224 * has_inline_constant false by assumption on the
2225 * branch, so flipping makes sense. */
2226 mir_flip(ins);
2227 }
2228 }
2229 }
2230
2231 static unsigned
2232 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2233 {
2234 /* Loop to ourselves */
2235 midgard_instruction *br = ctx->writeout_branch[rt];
2236 struct midgard_instruction ins = v_branch(false, false);
2237 ins.writeout = br->writeout;
2238 ins.branch.target_block = ctx->block_count - 1;
2239 ins.constants.u32[0] = br->constants.u32[0];
2240 memcpy(&ins.src_types, &br->src_types, sizeof(ins.src_types));
2241 emit_mir_instruction(ctx, ins);
2242
2243 ctx->current_block->epilogue = true;
2244 schedule_barrier(ctx);
2245 return ins.branch.target_block;
2246 }
2247
2248 static midgard_block *
2249 emit_block(compiler_context *ctx, nir_block *block)
2250 {
2251 midgard_block *this_block = ctx->after_block;
2252 ctx->after_block = NULL;
2253
2254 if (!this_block)
2255 this_block = create_empty_block(ctx);
2256
2257 list_addtail(&this_block->base.link, &ctx->blocks);
2258
2259 this_block->scheduled = false;
2260 ++ctx->block_count;
2261
2262 /* Set up current block */
2263 list_inithead(&this_block->base.instructions);
2264 ctx->current_block = this_block;
2265
2266 nir_foreach_instr(instr, block) {
2267 emit_instr(ctx, instr);
2268 ++ctx->instruction_count;
2269 }
2270
2271 return this_block;
2272 }
2273
2274 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2275
2276 static void
2277 emit_if(struct compiler_context *ctx, nir_if *nif)
2278 {
2279 midgard_block *before_block = ctx->current_block;
2280
2281 /* Speculatively emit the branch, but we can't fill it in until later */
2282 bool inv = false;
2283 EMIT(branch, true, true);
2284 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2285 then_branch->src[0] = mir_get_branch_cond(&nif->condition, &inv);
2286 then_branch->src_types[0] = nir_type_uint32;
2287 then_branch->branch.invert_conditional = !inv;
2288
2289 /* Emit the two subblocks. */
2290 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2291 midgard_block *end_then_block = ctx->current_block;
2292
2293 /* Emit a jump from the end of the then block to the end of the else */
2294 EMIT(branch, false, false);
2295 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2296
2297 /* Emit second block, and check if it's empty */
2298
2299 int else_idx = ctx->block_count;
2300 int count_in = ctx->instruction_count;
2301 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2302 midgard_block *end_else_block = ctx->current_block;
2303 int after_else_idx = ctx->block_count;
2304
2305 /* Now that we have the subblocks emitted, fix up the branches */
2306
2307 assert(then_block);
2308 assert(else_block);
2309
2310 if (ctx->instruction_count == count_in) {
2311 /* The else block is empty, so don't emit an exit jump */
2312 mir_remove_instruction(then_exit);
2313 then_branch->branch.target_block = after_else_idx;
2314 } else {
2315 then_branch->branch.target_block = else_idx;
2316 then_exit->branch.target_block = after_else_idx;
2317 }
2318
2319 /* Wire up the successors */
2320
2321 ctx->after_block = create_empty_block(ctx);
2322
2323 pan_block_add_successor(&before_block->base, &then_block->base);
2324 pan_block_add_successor(&before_block->base, &else_block->base);
2325
2326 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2327 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2328 }
2329
2330 static void
2331 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2332 {
2333 /* Remember where we are */
2334 midgard_block *start_block = ctx->current_block;
2335
2336 /* Allocate a loop number, growing the current inner loop depth */
2337 int loop_idx = ++ctx->current_loop_depth;
2338
2339 /* Get index from before the body so we can loop back later */
2340 int start_idx = ctx->block_count;
2341
2342 /* Emit the body itself */
2343 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2344
2345 /* Branch back to loop back */
2346 struct midgard_instruction br_back = v_branch(false, false);
2347 br_back.branch.target_block = start_idx;
2348 emit_mir_instruction(ctx, br_back);
2349
2350 /* Mark down that branch in the graph. */
2351 pan_block_add_successor(&start_block->base, &loop_block->base);
2352 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2353
2354 /* Find the index of the block about to follow us (note: we don't add
2355 * one; blocks are 0-indexed so we get a fencepost problem) */
2356 int break_block_idx = ctx->block_count;
2357
2358 /* Fix up the break statements we emitted to point to the right place,
2359 * now that we can allocate a block number for them */
2360 ctx->after_block = create_empty_block(ctx);
2361
2362 mir_foreach_block_from(ctx, start_block, _block) {
2363 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2364 if (ins->type != TAG_ALU_4) continue;
2365 if (!ins->compact_branch) continue;
2366
2367 /* We found a branch -- check the type to see if we need to do anything */
2368 if (ins->branch.target_type != TARGET_BREAK) continue;
2369
2370 /* It's a break! Check if it's our break */
2371 if (ins->branch.target_break != loop_idx) continue;
2372
2373 /* Okay, cool, we're breaking out of this loop.
2374 * Rewrite from a break to a goto */
2375
2376 ins->branch.target_type = TARGET_GOTO;
2377 ins->branch.target_block = break_block_idx;
2378
2379 pan_block_add_successor(_block, &ctx->after_block->base);
2380 }
2381 }
2382
2383 /* Now that we've finished emitting the loop, free up the depth again
2384 * so we play nice with recursion amid nested loops */
2385 --ctx->current_loop_depth;
2386
2387 /* Dump loop stats */
2388 ++ctx->loop_count;
2389 }
2390
2391 static midgard_block *
2392 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2393 {
2394 midgard_block *start_block = NULL;
2395
2396 foreach_list_typed(nir_cf_node, node, node, list) {
2397 switch (node->type) {
2398 case nir_cf_node_block: {
2399 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2400
2401 if (!start_block)
2402 start_block = block;
2403
2404 break;
2405 }
2406
2407 case nir_cf_node_if:
2408 emit_if(ctx, nir_cf_node_as_if(node));
2409 break;
2410
2411 case nir_cf_node_loop:
2412 emit_loop(ctx, nir_cf_node_as_loop(node));
2413 break;
2414
2415 case nir_cf_node_function:
2416 assert(0);
2417 break;
2418 }
2419 }
2420
2421 return start_block;
2422 }
2423
2424 /* Due to lookahead, we need to report the first tag executed in the command
2425 * stream and in branch targets. An initial block might be empty, so iterate
2426 * until we find one that 'works' */
2427
2428 static unsigned
2429 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2430 {
2431 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2432
2433 mir_foreach_block_from(ctx, initial_block, _v) {
2434 midgard_block *v = (midgard_block *) _v;
2435 if (v->quadword_count) {
2436 midgard_bundle *initial_bundle =
2437 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2438
2439 return initial_bundle->tag;
2440 }
2441 }
2442
2443 /* Default to a tag 1 which will break from the shader, in case we jump
2444 * to the exit block (i.e. `return` in a compute shader) */
2445
2446 return 1;
2447 }
2448
2449 /* For each fragment writeout instruction, generate a writeout loop to
2450 * associate with it */
2451
2452 static void
2453 mir_add_writeout_loops(compiler_context *ctx)
2454 {
2455 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2456 midgard_instruction *br = ctx->writeout_branch[rt];
2457 if (!br) continue;
2458
2459 unsigned popped = br->branch.target_block;
2460 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2461 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2462 br->branch.target_type = TARGET_GOTO;
2463
2464 /* If we have more RTs, we'll need to restore back after our
2465 * loop terminates */
2466
2467 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2468 midgard_instruction uncond = v_branch(false, false);
2469 uncond.branch.target_block = popped;
2470 uncond.branch.target_type = TARGET_GOTO;
2471 emit_mir_instruction(ctx, uncond);
2472 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2473 schedule_barrier(ctx);
2474 } else {
2475 /* We're last, so we can terminate here */
2476 br->last_writeout = true;
2477 }
2478 }
2479 }
2480
2481 int
2482 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2483 {
2484 struct util_dynarray *compiled = &program->compiled;
2485
2486 midgard_debug = debug_get_option_midgard_debug();
2487
2488 /* TODO: Bound against what? */
2489 compiler_context *ctx = rzalloc(NULL, compiler_context);
2490
2491 ctx->nir = nir;
2492 ctx->stage = nir->info.stage;
2493 ctx->is_blend = is_blend;
2494 ctx->alpha_ref = program->alpha_ref;
2495 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2496 ctx->quirks = midgard_get_quirks(gpu_id);
2497
2498 /* Start off with a safe cutoff, allowing usage of all 16 work
2499 * registers. Later, we'll promote uniform reads to uniform registers
2500 * if we determine it is beneficial to do so */
2501 ctx->uniform_cutoff = 8;
2502
2503 /* Initialize at a global (not block) level hash tables */
2504
2505 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2506 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2507
2508 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2509 * (so we don't accidentally duplicate the epilogue since mesa/st has
2510 * messed with our I/O quite a bit already) */
2511
2512 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2513
2514 if (ctx->stage == MESA_SHADER_VERTEX) {
2515 NIR_PASS_V(nir, nir_lower_viewport_transform);
2516 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2517 }
2518
2519 NIR_PASS_V(nir, nir_lower_var_copies);
2520 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2521 NIR_PASS_V(nir, nir_split_var_copies);
2522 NIR_PASS_V(nir, nir_lower_var_copies);
2523 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2524 NIR_PASS_V(nir, nir_lower_var_copies);
2525 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2526
2527 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2528 NIR_PASS_V(nir, nir_lower_ssbo);
2529
2530 /* Optimisation passes */
2531
2532 optimise_nir(nir, ctx->quirks, is_blend);
2533
2534 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2535 nir_print_shader(nir, stdout);
2536 }
2537
2538 /* Assign sysvals and counts, now that we're sure
2539 * (post-optimisation) */
2540
2541 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2542 program->sysval_count = ctx->sysvals.sysval_count;
2543 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2544
2545 nir_foreach_function(func, nir) {
2546 if (!func->impl)
2547 continue;
2548
2549 list_inithead(&ctx->blocks);
2550 ctx->block_count = 0;
2551 ctx->func = func;
2552 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
2553
2554 emit_cf_list(ctx, &func->impl->body);
2555 free(ctx->already_emitted);
2556 break; /* TODO: Multi-function shaders */
2557 }
2558
2559 util_dynarray_init(compiled, NULL);
2560
2561 /* Per-block lowering before opts */
2562
2563 mir_foreach_block(ctx, _block) {
2564 midgard_block *block = (midgard_block *) _block;
2565 inline_alu_constants(ctx, block);
2566 embedded_to_inline_constant(ctx, block);
2567 }
2568 /* MIR-level optimizations */
2569
2570 bool progress = false;
2571
2572 do {
2573 progress = false;
2574 progress |= midgard_opt_dead_code_eliminate(ctx);
2575
2576 mir_foreach_block(ctx, _block) {
2577 midgard_block *block = (midgard_block *) _block;
2578 progress |= midgard_opt_copy_prop(ctx, block);
2579 progress |= midgard_opt_combine_projection(ctx, block);
2580 progress |= midgard_opt_varying_projection(ctx, block);
2581 }
2582 } while (progress);
2583
2584 mir_foreach_block(ctx, _block) {
2585 midgard_block *block = (midgard_block *) _block;
2586 midgard_lower_derivatives(ctx, block);
2587 midgard_legalize_invert(ctx, block);
2588 midgard_cull_dead_branch(ctx, block);
2589 }
2590
2591 if (ctx->stage == MESA_SHADER_FRAGMENT)
2592 mir_add_writeout_loops(ctx);
2593
2594 /* Analyze now that the code is known but before scheduling creates
2595 * pipeline registers which are harder to track */
2596 mir_analyze_helper_terminate(ctx);
2597 mir_analyze_helper_requirements(ctx);
2598
2599 /* Schedule! */
2600 midgard_schedule_program(ctx);
2601 mir_ra(ctx);
2602
2603 /* Now that all the bundles are scheduled and we can calculate block
2604 * sizes, emit actual branch instructions rather than placeholders */
2605
2606 int br_block_idx = 0;
2607
2608 mir_foreach_block(ctx, _block) {
2609 midgard_block *block = (midgard_block *) _block;
2610 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2611 for (int c = 0; c < bundle->instruction_count; ++c) {
2612 midgard_instruction *ins = bundle->instructions[c];
2613
2614 if (!midgard_is_branch_unit(ins->unit)) continue;
2615
2616 /* Parse some basic branch info */
2617 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2618 bool is_conditional = ins->branch.conditional;
2619 bool is_inverted = ins->branch.invert_conditional;
2620 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2621 bool is_writeout = ins->writeout;
2622
2623 /* Determine the block we're jumping to */
2624 int target_number = ins->branch.target_block;
2625
2626 /* Report the destination tag */
2627 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2628
2629 /* Count up the number of quadwords we're
2630 * jumping over = number of quadwords until
2631 * (br_block_idx, target_number) */
2632
2633 int quadword_offset = 0;
2634
2635 if (is_discard) {
2636 /* Ignored */
2637 } else if (target_number > br_block_idx) {
2638 /* Jump forward */
2639
2640 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2641 midgard_block *blk = mir_get_block(ctx, idx);
2642 assert(blk);
2643
2644 quadword_offset += blk->quadword_count;
2645 }
2646 } else {
2647 /* Jump backwards */
2648
2649 for (int idx = br_block_idx; idx >= target_number; --idx) {
2650 midgard_block *blk = mir_get_block(ctx, idx);
2651 assert(blk);
2652
2653 quadword_offset -= blk->quadword_count;
2654 }
2655 }
2656
2657 /* Unconditional extended branches (far jumps)
2658 * have issues, so we always use a conditional
2659 * branch, setting the condition to always for
2660 * unconditional. For compact unconditional
2661 * branches, cond isn't used so it doesn't
2662 * matter what we pick. */
2663
2664 midgard_condition cond =
2665 !is_conditional ? midgard_condition_always :
2666 is_inverted ? midgard_condition_false :
2667 midgard_condition_true;
2668
2669 midgard_jmp_writeout_op op =
2670 is_discard ? midgard_jmp_writeout_op_discard :
2671 is_writeout ? midgard_jmp_writeout_op_writeout :
2672 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2673 midgard_jmp_writeout_op_branch_cond;
2674
2675 if (!is_compact) {
2676 midgard_branch_extended branch =
2677 midgard_create_branch_extended(
2678 cond, op,
2679 dest_tag,
2680 quadword_offset);
2681
2682 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2683 } else if (is_conditional || is_discard) {
2684 midgard_branch_cond branch = {
2685 .op = op,
2686 .dest_tag = dest_tag,
2687 .offset = quadword_offset,
2688 .cond = cond
2689 };
2690
2691 assert(branch.offset == quadword_offset);
2692
2693 memcpy(&ins->br_compact, &branch, sizeof(branch));
2694 } else {
2695 assert(op == midgard_jmp_writeout_op_branch_uncond);
2696
2697 midgard_branch_uncond branch = {
2698 .op = op,
2699 .dest_tag = dest_tag,
2700 .offset = quadword_offset,
2701 .unknown = 1
2702 };
2703
2704 assert(branch.offset == quadword_offset);
2705
2706 memcpy(&ins->br_compact, &branch, sizeof(branch));
2707 }
2708 }
2709 }
2710
2711 ++br_block_idx;
2712 }
2713
2714 /* Emit flat binary from the instruction arrays. Iterate each block in
2715 * sequence. Save instruction boundaries such that lookahead tags can
2716 * be assigned easily */
2717
2718 /* Cache _all_ bundles in source order for lookahead across failed branches */
2719
2720 int bundle_count = 0;
2721 mir_foreach_block(ctx, _block) {
2722 midgard_block *block = (midgard_block *) _block;
2723 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2724 }
2725 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2726 int bundle_idx = 0;
2727 mir_foreach_block(ctx, _block) {
2728 midgard_block *block = (midgard_block *) _block;
2729 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2730 source_order_bundles[bundle_idx++] = bundle;
2731 }
2732 }
2733
2734 int current_bundle = 0;
2735
2736 /* Midgard prefetches instruction types, so during emission we
2737 * need to lookahead. Unless this is the last instruction, in
2738 * which we return 1. */
2739
2740 mir_foreach_block(ctx, _block) {
2741 midgard_block *block = (midgard_block *) _block;
2742 mir_foreach_bundle_in_block(block, bundle) {
2743 int lookahead = 1;
2744
2745 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2746 lookahead = source_order_bundles[current_bundle + 1]->tag;
2747
2748 emit_binary_bundle(ctx, block, bundle, compiled, lookahead);
2749 ++current_bundle;
2750 }
2751
2752 /* TODO: Free deeper */
2753 //util_dynarray_fini(&block->instructions);
2754 }
2755
2756 free(source_order_bundles);
2757
2758 /* Report the very first tag executed */
2759 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2760
2761 /* Deal with off-by-one related to the fencepost problem */
2762 program->work_register_count = ctx->work_registers + 1;
2763 program->uniform_cutoff = ctx->uniform_cutoff;
2764
2765 program->blend_patch_offset = ctx->blend_constant_offset;
2766 program->tls_size = ctx->tls_size;
2767
2768 if (midgard_debug & MIDGARD_DBG_SHADERS)
2769 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2770
2771 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2772 unsigned nr_bundles = 0, nr_ins = 0;
2773
2774 /* Count instructions and bundles */
2775
2776 mir_foreach_block(ctx, _block) {
2777 midgard_block *block = (midgard_block *) _block;
2778 nr_bundles += util_dynarray_num_elements(
2779 &block->bundles, midgard_bundle);
2780
2781 mir_foreach_bundle_in_block(block, bun)
2782 nr_ins += bun->instruction_count;
2783 }
2784
2785 /* Calculate thread count. There are certain cutoffs by
2786 * register count for thread count */
2787
2788 unsigned nr_registers = program->work_register_count;
2789
2790 unsigned nr_threads =
2791 (nr_registers <= 4) ? 4 :
2792 (nr_registers <= 8) ? 2 :
2793 1;
2794
2795 /* Dump stats */
2796
2797 fprintf(stderr, "shader%d - %s shader: "
2798 "%u inst, %u bundles, %u quadwords, "
2799 "%u registers, %u threads, %u loops, "
2800 "%u:%u spills:fills\n",
2801 SHADER_DB_COUNT++,
2802 ctx->is_blend ? "PAN_SHADER_BLEND" :
2803 gl_shader_stage_name(ctx->stage),
2804 nr_ins, nr_bundles, ctx->quadword_count,
2805 nr_registers, nr_threads,
2806 ctx->loop_count,
2807 ctx->spills, ctx->fills);
2808 }
2809
2810 ralloc_free(ctx);
2811
2812 return 0;
2813 }