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pan/mdg: Remove .pos propagation pass
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 } else { \
121 i.dest = ssa; \
122 i.dest_type = T; \
123 } \
124 return i; \
125 }
126
127 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
128 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
129
130 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
131 * the corresponding Midgard source */
132
133 static midgard_vector_alu_src
134 vector_alu_modifiers(nir_alu_src *src, bool is_int, unsigned broadcast_count,
135 bool half, bool sext)
136 {
137 /* Figure out how many components there are so we can adjust.
138 * Specifically we want to broadcast the last channel so things like
139 * ball2/3 work.
140 */
141
142 if (broadcast_count && src) {
143 uint8_t last_component = src->swizzle[broadcast_count - 1];
144
145 for (unsigned c = broadcast_count; c < NIR_MAX_VEC_COMPONENTS; ++c) {
146 src->swizzle[c] = last_component;
147 }
148 }
149
150 midgard_vector_alu_src alu_src = {
151 .rep_low = 0,
152 .rep_high = 0,
153 .half = half
154 };
155
156 if (is_int) {
157 alu_src.mod = midgard_int_normal;
158
159 /* Sign/zero-extend if needed */
160
161 if (half) {
162 alu_src.mod = sext ?
163 midgard_int_sign_extend
164 : midgard_int_zero_extend;
165 }
166
167 /* These should have been lowered away */
168 if (src)
169 assert(!(src->abs || src->negate));
170 } else {
171 if (src)
172 alu_src.mod = (src->abs << 0) | (src->negate << 1);
173 }
174
175 return alu_src;
176 }
177
178 M_LOAD(ld_attr_32, nir_type_uint32);
179 M_LOAD(ld_vary_32, nir_type_uint32);
180 M_LOAD(ld_ubo_int4, nir_type_uint32);
181 M_LOAD(ld_int4, nir_type_uint32);
182 M_STORE(st_int4, nir_type_uint32);
183 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
184 M_STORE(st_vary_32, nir_type_uint32);
185 M_LOAD(ld_cubemap_coords, nir_type_uint32);
186 M_LOAD(ld_compute_id, nir_type_uint32);
187
188 static midgard_instruction
189 v_branch(bool conditional, bool invert)
190 {
191 midgard_instruction ins = {
192 .type = TAG_ALU_4,
193 .unit = ALU_ENAB_BRANCH,
194 .compact_branch = true,
195 .branch = {
196 .conditional = conditional,
197 .invert_conditional = invert
198 },
199 .dest = ~0,
200 .src = { ~0, ~0, ~0, ~0 },
201 };
202
203 return ins;
204 }
205
206 static midgard_branch_extended
207 midgard_create_branch_extended( midgard_condition cond,
208 midgard_jmp_writeout_op op,
209 unsigned dest_tag,
210 signed quadword_offset)
211 {
212 /* The condition code is actually a LUT describing a function to
213 * combine multiple condition codes. However, we only support a single
214 * condition code at the moment, so we just duplicate over a bunch of
215 * times. */
216
217 uint16_t duplicated_cond =
218 (cond << 14) |
219 (cond << 12) |
220 (cond << 10) |
221 (cond << 8) |
222 (cond << 6) |
223 (cond << 4) |
224 (cond << 2) |
225 (cond << 0);
226
227 midgard_branch_extended branch = {
228 .op = op,
229 .dest_tag = dest_tag,
230 .offset = quadword_offset,
231 .cond = duplicated_cond
232 };
233
234 return branch;
235 }
236
237 static void
238 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
239 {
240 ins->has_constants = true;
241 memcpy(&ins->constants, constants, 16);
242 }
243
244 static int
245 glsl_type_size(const struct glsl_type *type, bool bindless)
246 {
247 return glsl_count_attribute_slots(type, false);
248 }
249
250 /* Lower fdot2 to a vector multiplication followed by channel addition */
251 static void
252 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
253 {
254 if (alu->op != nir_op_fdot2)
255 return;
256
257 b->cursor = nir_before_instr(&alu->instr);
258
259 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
260 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
261
262 nir_ssa_def *product = nir_fmul(b, src0, src1);
263
264 nir_ssa_def *sum = nir_fadd(b,
265 nir_channel(b, product, 0),
266 nir_channel(b, product, 1));
267
268 /* Replace the fdot2 with this sum */
269 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
270 }
271
272 static bool
273 midgard_nir_lower_fdot2(nir_shader *shader)
274 {
275 bool progress = false;
276
277 nir_foreach_function(function, shader) {
278 if (!function->impl) continue;
279
280 nir_builder _b;
281 nir_builder *b = &_b;
282 nir_builder_init(b, function->impl);
283
284 nir_foreach_block(block, function->impl) {
285 nir_foreach_instr_safe(instr, block) {
286 if (instr->type != nir_instr_type_alu) continue;
287
288 nir_alu_instr *alu = nir_instr_as_alu(instr);
289 midgard_nir_lower_fdot2_body(b, alu);
290
291 progress |= true;
292 }
293 }
294
295 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
296
297 }
298
299 return progress;
300 }
301
302 /* Midgard can't write depth and stencil separately. It has to happen in a
303 * single store operation containing both. Let's add a panfrost specific
304 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
305 * one.
306 */
307 static bool
308 midgard_nir_lower_zs_store(nir_shader *nir)
309 {
310 if (nir->info.stage != MESA_SHADER_FRAGMENT)
311 return false;
312
313 nir_variable *z_var = NULL, *s_var = NULL;
314
315 nir_foreach_variable(var, &nir->outputs) {
316 if (var->data.location == FRAG_RESULT_DEPTH)
317 z_var = var;
318 else if (var->data.location == FRAG_RESULT_STENCIL)
319 s_var = var;
320 }
321
322 if (!z_var && !s_var)
323 return false;
324
325 bool progress = false;
326
327 nir_foreach_function(function, nir) {
328 if (!function->impl) continue;
329
330 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
331
332 nir_foreach_block(block, function->impl) {
333 nir_foreach_instr_safe(instr, block) {
334 if (instr->type != nir_instr_type_intrinsic)
335 continue;
336
337 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
338 if (intr->intrinsic != nir_intrinsic_store_output)
339 continue;
340
341 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
342 assert(!z_store);
343 z_store = intr;
344 last_store = intr;
345 }
346
347 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
348 assert(!s_store);
349 s_store = intr;
350 last_store = intr;
351 }
352 }
353 }
354
355 if (!z_store && !s_store) continue;
356
357 nir_builder b;
358 nir_builder_init(&b, function->impl);
359
360 b.cursor = nir_before_instr(&last_store->instr);
361
362 nir_ssa_def *zs_store_src;
363
364 if (z_store && s_store) {
365 nir_ssa_def *srcs[2] = {
366 nir_ssa_for_src(&b, z_store->src[0], 1),
367 nir_ssa_for_src(&b, s_store->src[0], 1),
368 };
369
370 zs_store_src = nir_vec(&b, srcs, 2);
371 } else {
372 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
373 }
374
375 nir_intrinsic_instr *zs_store;
376
377 zs_store = nir_intrinsic_instr_create(b.shader,
378 nir_intrinsic_store_zs_output_pan);
379 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
380 zs_store->num_components = z_store && s_store ? 2 : 1;
381 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
382
383 /* Replace the Z and S store by a ZS store */
384 nir_builder_instr_insert(&b, &zs_store->instr);
385
386 if (z_store)
387 nir_instr_remove(&z_store->instr);
388
389 if (s_store)
390 nir_instr_remove(&s_store->instr);
391
392 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
393 progress = true;
394 }
395
396 return progress;
397 }
398
399 /* Flushes undefined values to zero */
400
401 static void
402 optimise_nir(nir_shader *nir, unsigned quirks)
403 {
404 bool progress;
405 unsigned lower_flrp =
406 (nir->options->lower_flrp16 ? 16 : 0) |
407 (nir->options->lower_flrp32 ? 32 : 0) |
408 (nir->options->lower_flrp64 ? 64 : 0);
409
410 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
411 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
412
413 nir_lower_tex_options lower_tex_options = {
414 .lower_txs_lod = true,
415 .lower_txp = ~0,
416 .lower_tex_without_implicit_lod =
417 (quirks & MIDGARD_EXPLICIT_LOD),
418
419 /* TODO: we have native gradient.. */
420 .lower_txd = true,
421 };
422
423 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
424
425 /* Must lower fdot2 after tex is lowered */
426 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
427
428 /* T720 is broken. */
429
430 if (quirks & MIDGARD_BROKEN_LOD)
431 NIR_PASS_V(nir, midgard_nir_lod_errata);
432
433 do {
434 progress = false;
435
436 NIR_PASS(progress, nir, nir_lower_var_copies);
437 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
438
439 NIR_PASS(progress, nir, nir_copy_prop);
440 NIR_PASS(progress, nir, nir_opt_remove_phis);
441 NIR_PASS(progress, nir, nir_opt_dce);
442 NIR_PASS(progress, nir, nir_opt_dead_cf);
443 NIR_PASS(progress, nir, nir_opt_cse);
444 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
445 NIR_PASS(progress, nir, nir_opt_algebraic);
446 NIR_PASS(progress, nir, nir_opt_constant_folding);
447
448 if (lower_flrp != 0) {
449 bool lower_flrp_progress = false;
450 NIR_PASS(lower_flrp_progress,
451 nir,
452 nir_lower_flrp,
453 lower_flrp,
454 false /* always_precise */,
455 nir->options->lower_ffma);
456 if (lower_flrp_progress) {
457 NIR_PASS(progress, nir,
458 nir_opt_constant_folding);
459 progress = true;
460 }
461
462 /* Nothing should rematerialize any flrps, so we only
463 * need to do this lowering once.
464 */
465 lower_flrp = 0;
466 }
467
468 NIR_PASS(progress, nir, nir_opt_undef);
469 NIR_PASS(progress, nir, nir_undef_to_zero);
470
471 NIR_PASS(progress, nir, nir_opt_loop_unroll,
472 nir_var_shader_in |
473 nir_var_shader_out |
474 nir_var_function_temp);
475
476 NIR_PASS(progress, nir, nir_opt_vectorize);
477 } while (progress);
478
479 /* Must be run at the end to prevent creation of fsin/fcos ops */
480 NIR_PASS(progress, nir, midgard_nir_scale_trig);
481
482 do {
483 progress = false;
484
485 NIR_PASS(progress, nir, nir_opt_dce);
486 NIR_PASS(progress, nir, nir_opt_algebraic);
487 NIR_PASS(progress, nir, nir_opt_constant_folding);
488 NIR_PASS(progress, nir, nir_copy_prop);
489 } while (progress);
490
491 NIR_PASS(progress, nir, nir_opt_algebraic_late);
492 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
493
494 /* We implement booleans as 32-bit 0/~0 */
495 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
496
497 /* Now that booleans are lowered, we can run out late opts */
498 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
499
500 /* Lower mods for float ops only. Integer ops don't support modifiers
501 * (saturate doesn't make sense on integers, neg/abs require dedicated
502 * instructions) */
503
504 NIR_PASS(progress, nir, nir_lower_to_source_mods, nir_lower_float_source_mods);
505 NIR_PASS(progress, nir, nir_copy_prop);
506 NIR_PASS(progress, nir, nir_opt_dce);
507
508 /* Take us out of SSA */
509 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
510 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
511
512 /* We are a vector architecture; write combine where possible */
513 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
514 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
515
516 NIR_PASS(progress, nir, nir_opt_dce);
517 }
518
519 /* Do not actually emit a load; instead, cache the constant for inlining */
520
521 static void
522 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
523 {
524 nir_ssa_def def = instr->def;
525
526 midgard_constants *consts = rzalloc(NULL, midgard_constants);
527
528 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
529
530 #define RAW_CONST_COPY(bits) \
531 nir_const_value_to_array(consts->u##bits, instr->value, \
532 instr->def.num_components, u##bits)
533
534 switch (instr->def.bit_size) {
535 case 64:
536 RAW_CONST_COPY(64);
537 break;
538 case 32:
539 RAW_CONST_COPY(32);
540 break;
541 case 16:
542 RAW_CONST_COPY(16);
543 break;
544 case 8:
545 RAW_CONST_COPY(8);
546 break;
547 default:
548 unreachable("Invalid bit_size for load_const instruction\n");
549 }
550
551 /* Shifted for SSA, +1 for off-by-one */
552 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
553 }
554
555 /* Normally constants are embedded implicitly, but for I/O and such we have to
556 * explicitly emit a move with the constant source */
557
558 static void
559 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
560 {
561 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
562
563 if (constant_value) {
564 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
565 attach_constants(ctx, &ins, constant_value, node + 1);
566 emit_mir_instruction(ctx, ins);
567 }
568 }
569
570 static bool
571 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
572 {
573 unsigned comp = src->swizzle[0];
574
575 for (unsigned c = 1; c < nr_components; ++c) {
576 if (src->swizzle[c] != comp)
577 return true;
578 }
579
580 return false;
581 }
582
583 #define ALU_CASE(nir, _op) \
584 case nir_op_##nir: \
585 op = midgard_alu_op_##_op; \
586 assert(src_bitsize == dst_bitsize); \
587 break;
588
589 #define ALU_CASE_BCAST(nir, _op, count) \
590 case nir_op_##nir: \
591 op = midgard_alu_op_##_op; \
592 broadcast_swizzle = count; \
593 assert(src_bitsize == dst_bitsize); \
594 break;
595 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
596 * special treatment override this anyway. */
597
598 static midgard_reg_mode
599 reg_mode_for_nir(nir_alu_instr *instr)
600 {
601 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
602
603 switch (src_bitsize) {
604 case 8:
605 return midgard_reg_mode_8;
606 case 16:
607 return midgard_reg_mode_16;
608 case 32:
609 return midgard_reg_mode_32;
610 case 64:
611 return midgard_reg_mode_64;
612 default:
613 unreachable("Invalid bit size");
614 }
615 }
616
617 static void
618 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to)
619 {
620 unsigned bits = nir_src_bit_size(instr->src[i].src);
621
622 ins->src[to] = nir_src_index(NULL, &instr->src[i].src);
623 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
624 }
625
626 static void
627 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
628 {
629 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
630 * is handled elsewhere */
631
632 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
633 midgard_emit_derivatives(ctx, instr);
634 return;
635 }
636
637 bool is_ssa = instr->dest.dest.is_ssa;
638
639 unsigned nr_components = nir_dest_num_components(instr->dest.dest);
640 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
641 unsigned op = 0;
642
643 /* Number of components valid to check for the instruction (the rest
644 * will be forced to the last), or 0 to use as-is. Relevant as
645 * ball-type instructions have a channel count in NIR but are all vec4
646 * in Midgard */
647
648 unsigned broadcast_swizzle = 0;
649
650 /* What register mode should we operate in? */
651 midgard_reg_mode reg_mode =
652 reg_mode_for_nir(instr);
653
654 /* Do we need a destination override? Used for inline
655 * type conversion */
656
657 midgard_dest_override dest_override =
658 midgard_dest_override_none;
659
660 /* Should we use a smaller respective source and sign-extend? */
661
662 bool half_1 = false, sext_1 = false;
663 bool half_2 = false, sext_2 = false;
664
665 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
666 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
667
668 switch (instr->op) {
669 ALU_CASE(fadd, fadd);
670 ALU_CASE(fmul, fmul);
671 ALU_CASE(fmin, fmin);
672 ALU_CASE(fmax, fmax);
673 ALU_CASE(imin, imin);
674 ALU_CASE(imax, imax);
675 ALU_CASE(umin, umin);
676 ALU_CASE(umax, umax);
677 ALU_CASE(ffloor, ffloor);
678 ALU_CASE(fround_even, froundeven);
679 ALU_CASE(ftrunc, ftrunc);
680 ALU_CASE(fceil, fceil);
681 ALU_CASE(fdot3, fdot3);
682 ALU_CASE(fdot4, fdot4);
683 ALU_CASE(iadd, iadd);
684 ALU_CASE(isub, isub);
685 ALU_CASE(imul, imul);
686
687 /* Zero shoved as second-arg */
688 ALU_CASE(iabs, iabsdiff);
689
690 ALU_CASE(mov, imov);
691
692 ALU_CASE(feq32, feq);
693 ALU_CASE(fne32, fne);
694 ALU_CASE(flt32, flt);
695 ALU_CASE(ieq32, ieq);
696 ALU_CASE(ine32, ine);
697 ALU_CASE(ilt32, ilt);
698 ALU_CASE(ult32, ult);
699
700 /* We don't have a native b2f32 instruction. Instead, like many
701 * GPUs, we exploit booleans as 0/~0 for false/true, and
702 * correspondingly AND
703 * by 1.0 to do the type conversion. For the moment, prime us
704 * to emit:
705 *
706 * iand [whatever], #0
707 *
708 * At the end of emit_alu (as MIR), we'll fix-up the constant
709 */
710
711 ALU_CASE(b2f32, iand);
712 ALU_CASE(b2i32, iand);
713
714 /* Likewise, we don't have a dedicated f2b32 instruction, but
715 * we can do a "not equal to 0.0" test. */
716
717 ALU_CASE(f2b32, fne);
718 ALU_CASE(i2b32, ine);
719
720 ALU_CASE(frcp, frcp);
721 ALU_CASE(frsq, frsqrt);
722 ALU_CASE(fsqrt, fsqrt);
723 ALU_CASE(fexp2, fexp2);
724 ALU_CASE(flog2, flog2);
725
726 ALU_CASE(f2i64, f2i_rtz);
727 ALU_CASE(f2u64, f2u_rtz);
728 ALU_CASE(i2f64, i2f_rtz);
729 ALU_CASE(u2f64, u2f_rtz);
730
731 ALU_CASE(f2i32, f2i_rtz);
732 ALU_CASE(f2u32, f2u_rtz);
733 ALU_CASE(i2f32, i2f_rtz);
734 ALU_CASE(u2f32, u2f_rtz);
735
736 ALU_CASE(f2i16, f2i_rtz);
737 ALU_CASE(f2u16, f2u_rtz);
738 ALU_CASE(i2f16, i2f_rtz);
739 ALU_CASE(u2f16, u2f_rtz);
740
741 ALU_CASE(fsin, fsin);
742 ALU_CASE(fcos, fcos);
743
744 /* We'll set invert */
745 ALU_CASE(inot, imov);
746 ALU_CASE(iand, iand);
747 ALU_CASE(ior, ior);
748 ALU_CASE(ixor, ixor);
749 ALU_CASE(ishl, ishl);
750 ALU_CASE(ishr, iasr);
751 ALU_CASE(ushr, ilsr);
752
753 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
754 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
755 ALU_CASE(b32all_fequal4, fball_eq);
756
757 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
758 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
759 ALU_CASE(b32any_fnequal4, fbany_neq);
760
761 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
762 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
763 ALU_CASE(b32all_iequal4, iball_eq);
764
765 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
766 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
767 ALU_CASE(b32any_inequal4, ibany_neq);
768
769 /* Source mods will be shoved in later */
770 ALU_CASE(fabs, fmov);
771 ALU_CASE(fneg, fmov);
772 ALU_CASE(fsat, fmov);
773
774 /* For size conversion, we use a move. Ideally though we would squash
775 * these ops together; maybe that has to happen after in NIR as part of
776 * propagation...? An earlier algebraic pass ensured we step down by
777 * only / exactly one size. If stepping down, we use a dest override to
778 * reduce the size; if stepping up, we use a larger-sized move with a
779 * half source and a sign/zero-extension modifier */
780
781 case nir_op_i2i8:
782 case nir_op_i2i16:
783 case nir_op_i2i32:
784 case nir_op_i2i64:
785 /* If we end up upscale, we'll need a sign-extend on the
786 * operand (the second argument) */
787
788 sext_2 = true;
789 /* fallthrough */
790 case nir_op_u2u8:
791 case nir_op_u2u16:
792 case nir_op_u2u32:
793 case nir_op_u2u64:
794 case nir_op_f2f16:
795 case nir_op_f2f32:
796 case nir_op_f2f64: {
797 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
798 instr->op == nir_op_f2f64)
799 op = midgard_alu_op_fmov;
800 else
801 op = midgard_alu_op_imov;
802
803 if (dst_bitsize == (src_bitsize * 2)) {
804 /* Converting up */
805 half_2 = true;
806
807 /* Use a greater register mode */
808 reg_mode++;
809 } else if (src_bitsize == (dst_bitsize * 2)) {
810 /* Converting down */
811 dest_override = midgard_dest_override_lower;
812 }
813
814 break;
815 }
816
817 /* For greater-or-equal, we lower to less-or-equal and flip the
818 * arguments */
819
820 case nir_op_fge:
821 case nir_op_fge32:
822 case nir_op_ige32:
823 case nir_op_uge32: {
824 op =
825 instr->op == nir_op_fge ? midgard_alu_op_fle :
826 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
827 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
828 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
829 0;
830
831 /* Swap via temporary */
832 nir_alu_src temp = instr->src[1];
833 instr->src[1] = instr->src[0];
834 instr->src[0] = temp;
835
836 break;
837 }
838
839 case nir_op_b32csel: {
840 /* Midgard features both fcsel and icsel, depending on
841 * the type of the arguments/output. However, as long
842 * as we're careful we can _always_ use icsel and
843 * _never_ need fcsel, since the latter does additional
844 * floating-point-specific processing whereas the
845 * former just moves bits on the wire. It's not obvious
846 * why these are separate opcodes, save for the ability
847 * to do things like sat/pos/abs/neg for free */
848
849 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
850 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
851
852 /* The condition is the first argument; move the other
853 * arguments up one to be a binary instruction for
854 * Midgard with the condition last */
855
856 nir_alu_src temp = instr->src[2];
857
858 instr->src[2] = instr->src[0];
859 instr->src[0] = instr->src[1];
860 instr->src[1] = temp;
861
862 break;
863 }
864
865 default:
866 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
867 assert(0);
868 return;
869 }
870
871 /* Midgard can perform certain modifiers on output of an ALU op */
872 unsigned outmod;
873
874 if (midgard_is_integer_out_op(op)) {
875 outmod = midgard_outmod_int_wrap;
876 } else {
877 bool sat = instr->dest.saturate || instr->op == nir_op_fsat;
878 outmod = sat ? midgard_outmod_sat : midgard_outmod_none;
879 }
880
881
882 /* Fetch unit, quirks, etc information */
883 unsigned opcode_props = alu_opcode_props[op].props;
884 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
885
886 midgard_instruction ins = {
887 .type = TAG_ALU_4,
888 .dest = nir_dest_index(&instr->dest.dest),
889 .dest_type = nir_op_infos[instr->op].output_type
890 | nir_dest_bit_size(instr->dest.dest),
891 };
892
893 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
894 ins.src[i] = ~0;
895
896 if (quirk_flipped_r24) {
897 ins.src[0] = ~0;
898 mir_copy_src(&ins, instr, 0, 1);
899 } else {
900 for (unsigned i = 0; i < nr_inputs; ++i)
901 mir_copy_src(&ins, instr, i, quirk_flipped_r24 ? 1 : i);
902 }
903
904 nir_alu_src *nirmods[3] = { NULL };
905
906 if (nr_inputs >= 2) {
907 nirmods[0] = &instr->src[0];
908 nirmods[1] = &instr->src[1];
909 } else if (nr_inputs == 1) {
910 nirmods[quirk_flipped_r24] = &instr->src[0];
911 } else {
912 assert(0);
913 }
914
915 if (nr_inputs == 3)
916 nirmods[2] = &instr->src[2];
917
918 /* These were lowered to a move, so apply the corresponding mod */
919
920 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
921 nir_alu_src *s = nirmods[quirk_flipped_r24];
922
923 if (instr->op == nir_op_fneg)
924 s->negate = !s->negate;
925
926 if (instr->op == nir_op_fabs)
927 s->abs = !s->abs;
928 }
929
930 bool is_int = midgard_is_integer_op(op);
931
932 ins.mask = mask_of(nr_components);
933
934 midgard_vector_alu alu = {
935 .op = op,
936 .reg_mode = reg_mode,
937 .dest_override = dest_override,
938 .outmod = outmod,
939
940 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int, broadcast_swizzle, half_1, sext_1)),
941 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int, broadcast_swizzle, half_2, sext_2)),
942 };
943
944 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
945
946 if (!is_ssa)
947 ins.mask &= instr->dest.write_mask;
948
949 for (unsigned m = 0; m < 3; ++m) {
950 if (!nirmods[m])
951 continue;
952
953 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c)
954 ins.swizzle[m][c] = nirmods[m]->swizzle[c];
955
956 /* Replicate. TODO: remove when vec16 lands */
957 for (unsigned c = NIR_MAX_VEC_COMPONENTS; c < MIR_VEC_COMPONENTS; ++c)
958 ins.swizzle[m][c] = nirmods[m]->swizzle[NIR_MAX_VEC_COMPONENTS - 1];
959 }
960
961 if (nr_inputs == 3) {
962 /* Conditions can't have mods */
963 assert(!nirmods[2]->abs);
964 assert(!nirmods[2]->negate);
965 }
966
967 ins.alu = alu;
968
969 /* Late fixup for emulated instructions */
970
971 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
972 /* Presently, our second argument is an inline #0 constant.
973 * Switch over to an embedded 1.0 constant (that can't fit
974 * inline, since we're 32-bit, not 16-bit like the inline
975 * constants) */
976
977 ins.has_inline_constant = false;
978 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
979 ins.src_types[1] = nir_type_float32;
980 ins.has_constants = true;
981
982 if (instr->op == nir_op_b2f32)
983 ins.constants.f32[0] = 1.0f;
984 else
985 ins.constants.i32[0] = 1;
986
987 for (unsigned c = 0; c < 16; ++c)
988 ins.swizzle[1][c] = 0;
989 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
990 /* Lots of instructions need a 0 plonked in */
991 ins.has_inline_constant = false;
992 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
993 ins.src_types[1] = nir_type_uint32;
994 ins.has_constants = true;
995 ins.constants.u32[0] = 0;
996
997 for (unsigned c = 0; c < 16; ++c)
998 ins.swizzle[1][c] = 0;
999 } else if (instr->op == nir_op_inot) {
1000 ins.invert = true;
1001 }
1002
1003 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1004 /* To avoid duplicating the lookup tables (probably), true LUT
1005 * instructions can only operate as if they were scalars. Lower
1006 * them here by changing the component. */
1007
1008 unsigned orig_mask = ins.mask;
1009
1010 for (int i = 0; i < nr_components; ++i) {
1011 /* Mask the associated component, dropping the
1012 * instruction if needed */
1013
1014 ins.mask = 1 << i;
1015 ins.mask &= orig_mask;
1016
1017 if (!ins.mask)
1018 continue;
1019
1020 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1021 ins.swizzle[0][j] = nirmods[0]->swizzle[i]; /* Pull from the correct component */
1022
1023 emit_mir_instruction(ctx, ins);
1024 }
1025 } else {
1026 emit_mir_instruction(ctx, ins);
1027 }
1028 }
1029
1030 #undef ALU_CASE
1031
1032 static void
1033 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1034 {
1035 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1036 unsigned nir_mask = 0;
1037 unsigned dsize = 0;
1038
1039 if (is_read) {
1040 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1041 dsize = nir_dest_bit_size(intr->dest);
1042 } else {
1043 nir_mask = nir_intrinsic_write_mask(intr);
1044 dsize = 32;
1045 }
1046
1047 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1048 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1049 mir_set_bytemask(ins, bytemask);
1050
1051 if (dsize == 64)
1052 ins->load_64 = true;
1053 }
1054
1055 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1056 * optimized) versions of UBO #0 */
1057
1058 static midgard_instruction *
1059 emit_ubo_read(
1060 compiler_context *ctx,
1061 nir_instr *instr,
1062 unsigned dest,
1063 unsigned offset,
1064 nir_src *indirect_offset,
1065 unsigned indirect_shift,
1066 unsigned index)
1067 {
1068 /* TODO: half-floats */
1069
1070 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1071 ins.constants.u32[0] = offset;
1072
1073 if (instr->type == nir_instr_type_intrinsic)
1074 mir_set_intr_mask(instr, &ins, true);
1075
1076 if (indirect_offset) {
1077 ins.src[2] = nir_src_index(ctx, indirect_offset);
1078 ins.src_types[2] = nir_type_uint32;
1079 ins.load_store.arg_2 = (indirect_shift << 5);
1080 } else {
1081 ins.load_store.arg_2 = 0x1E;
1082 }
1083
1084 ins.load_store.arg_1 = index;
1085
1086 return emit_mir_instruction(ctx, ins);
1087 }
1088
1089 /* Globals are like UBOs if you squint. And shared memory is like globals if
1090 * you squint even harder */
1091
1092 static void
1093 emit_global(
1094 compiler_context *ctx,
1095 nir_instr *instr,
1096 bool is_read,
1097 unsigned srcdest,
1098 nir_src *offset,
1099 bool is_shared)
1100 {
1101 /* TODO: types */
1102
1103 midgard_instruction ins;
1104
1105 if (is_read)
1106 ins = m_ld_int4(srcdest, 0);
1107 else
1108 ins = m_st_int4(srcdest, 0);
1109
1110 mir_set_offset(ctx, &ins, offset, is_shared);
1111 mir_set_intr_mask(instr, &ins, is_read);
1112
1113 emit_mir_instruction(ctx, ins);
1114 }
1115
1116 static void
1117 emit_varying_read(
1118 compiler_context *ctx,
1119 unsigned dest, unsigned offset,
1120 unsigned nr_comp, unsigned component,
1121 nir_src *indirect_offset, nir_alu_type type, bool flat)
1122 {
1123 /* XXX: Half-floats? */
1124 /* TODO: swizzle, mask */
1125
1126 midgard_instruction ins = m_ld_vary_32(dest, offset);
1127 ins.mask = mask_of(nr_comp);
1128
1129 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1130 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1131
1132 midgard_varying_parameter p = {
1133 .is_varying = 1,
1134 .interpolation = midgard_interp_default,
1135 .flat = flat,
1136 };
1137
1138 unsigned u;
1139 memcpy(&u, &p, sizeof(p));
1140 ins.load_store.varying_parameters = u;
1141
1142 if (indirect_offset) {
1143 ins.src[2] = nir_src_index(ctx, indirect_offset);
1144 ins.src_types[2] = nir_type_uint32;
1145 } else
1146 ins.load_store.arg_2 = 0x1E;
1147
1148 ins.load_store.arg_1 = 0x9E;
1149
1150 /* Use the type appropriate load */
1151 switch (type) {
1152 case nir_type_uint:
1153 case nir_type_bool:
1154 ins.load_store.op = midgard_op_ld_vary_32u;
1155 break;
1156 case nir_type_int:
1157 ins.load_store.op = midgard_op_ld_vary_32i;
1158 break;
1159 case nir_type_float:
1160 ins.load_store.op = midgard_op_ld_vary_32;
1161 break;
1162 default:
1163 unreachable("Attempted to load unknown type");
1164 break;
1165 }
1166
1167 emit_mir_instruction(ctx, ins);
1168 }
1169
1170 static void
1171 emit_attr_read(
1172 compiler_context *ctx,
1173 unsigned dest, unsigned offset,
1174 unsigned nr_comp, nir_alu_type t)
1175 {
1176 midgard_instruction ins = m_ld_attr_32(dest, offset);
1177 ins.load_store.arg_1 = 0x1E;
1178 ins.load_store.arg_2 = 0x1E;
1179 ins.mask = mask_of(nr_comp);
1180
1181 /* Use the type appropriate load */
1182 switch (t) {
1183 case nir_type_uint:
1184 case nir_type_bool:
1185 ins.load_store.op = midgard_op_ld_attr_32u;
1186 break;
1187 case nir_type_int:
1188 ins.load_store.op = midgard_op_ld_attr_32i;
1189 break;
1190 case nir_type_float:
1191 ins.load_store.op = midgard_op_ld_attr_32;
1192 break;
1193 default:
1194 unreachable("Attempted to load unknown type");
1195 break;
1196 }
1197
1198 emit_mir_instruction(ctx, ins);
1199 }
1200
1201 static void
1202 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1203 unsigned nr_components, unsigned offset)
1204 {
1205 nir_dest nir_dest;
1206
1207 /* Figure out which uniform this is */
1208 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1209 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1210
1211 unsigned dest = nir_dest_index(&nir_dest);
1212
1213 /* Sysvals are prefix uniforms */
1214 unsigned uniform = ((uintptr_t) val) - 1;
1215
1216 /* Emit the read itself -- this is never indirect */
1217 midgard_instruction *ins =
1218 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1219
1220 ins->mask = mask_of(nr_components);
1221 }
1222
1223 static unsigned
1224 compute_builtin_arg(nir_op op)
1225 {
1226 switch (op) {
1227 case nir_intrinsic_load_work_group_id:
1228 return 0x14;
1229 case nir_intrinsic_load_local_invocation_id:
1230 return 0x10;
1231 default:
1232 unreachable("Invalid compute paramater loaded");
1233 }
1234 }
1235
1236 static void
1237 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1238 {
1239 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1240
1241 midgard_instruction *br = ctx->writeout_branch[rt];
1242
1243 assert(!br);
1244
1245 emit_explicit_constant(ctx, src, src);
1246
1247 struct midgard_instruction ins =
1248 v_branch(false, false);
1249
1250 ins.writeout = true;
1251
1252 /* Add dependencies */
1253 ins.src[0] = src;
1254 ins.src_types[0] = nir_type_uint32;
1255 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1256 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1257
1258 /* Emit the branch */
1259 br = emit_mir_instruction(ctx, ins);
1260 schedule_barrier(ctx);
1261 ctx->writeout_branch[rt] = br;
1262
1263 /* Push our current location = current block count - 1 = where we'll
1264 * jump to. Maybe a bit too clever for my own good */
1265
1266 br->branch.target_block = ctx->block_count - 1;
1267 }
1268
1269 static void
1270 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1271 {
1272 unsigned reg = nir_dest_index(&instr->dest);
1273 midgard_instruction ins = m_ld_compute_id(reg, 0);
1274 ins.mask = mask_of(3);
1275 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1276 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1277 emit_mir_instruction(ctx, ins);
1278 }
1279
1280 static unsigned
1281 vertex_builtin_arg(nir_op op)
1282 {
1283 switch (op) {
1284 case nir_intrinsic_load_vertex_id:
1285 return PAN_VERTEX_ID;
1286 case nir_intrinsic_load_instance_id:
1287 return PAN_INSTANCE_ID;
1288 default:
1289 unreachable("Invalid vertex builtin");
1290 }
1291 }
1292
1293 static void
1294 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1295 {
1296 unsigned reg = nir_dest_index(&instr->dest);
1297 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1298 }
1299
1300 static void
1301 emit_control_barrier(compiler_context *ctx)
1302 {
1303 midgard_instruction ins = {
1304 .type = TAG_TEXTURE_4,
1305 .src = { ~0, ~0, ~0, ~0 },
1306 .texture = {
1307 .op = TEXTURE_OP_BARRIER,
1308
1309 /* TODO: optimize */
1310 .barrier_buffer = 1,
1311 .barrier_shared = 1
1312 }
1313 };
1314
1315 emit_mir_instruction(ctx, ins);
1316 }
1317
1318 static const nir_variable *
1319 search_var(struct exec_list *vars, unsigned driver_loc)
1320 {
1321 nir_foreach_variable(var, vars) {
1322 if (var->data.driver_location == driver_loc)
1323 return var;
1324 }
1325
1326 return NULL;
1327 }
1328
1329 static void
1330 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1331 {
1332 unsigned offset = 0, reg;
1333
1334 switch (instr->intrinsic) {
1335 case nir_intrinsic_discard_if:
1336 case nir_intrinsic_discard: {
1337 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1338 struct midgard_instruction discard = v_branch(conditional, false);
1339 discard.branch.target_type = TARGET_DISCARD;
1340
1341 if (conditional) {
1342 discard.src[0] = nir_src_index(ctx, &instr->src[0]);
1343 discard.src_types[0] = nir_type_uint32;
1344 }
1345
1346 emit_mir_instruction(ctx, discard);
1347 schedule_barrier(ctx);
1348
1349 break;
1350 }
1351
1352 case nir_intrinsic_load_uniform:
1353 case nir_intrinsic_load_ubo:
1354 case nir_intrinsic_load_global:
1355 case nir_intrinsic_load_shared:
1356 case nir_intrinsic_load_input:
1357 case nir_intrinsic_load_interpolated_input: {
1358 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1359 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1360 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1361 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1362 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1363 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1364
1365 /* Get the base type of the intrinsic */
1366 /* TODO: Infer type? Does it matter? */
1367 nir_alu_type t =
1368 (is_ubo || is_global || is_shared) ? nir_type_uint :
1369 (is_interp) ? nir_type_float :
1370 nir_intrinsic_type(instr);
1371
1372 t = nir_alu_type_get_base_type(t);
1373
1374 if (!(is_ubo || is_global)) {
1375 offset = nir_intrinsic_base(instr);
1376 }
1377
1378 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1379
1380 nir_src *src_offset = nir_get_io_offset_src(instr);
1381
1382 bool direct = nir_src_is_const(*src_offset);
1383 nir_src *indirect_offset = direct ? NULL : src_offset;
1384
1385 if (direct)
1386 offset += nir_src_as_uint(*src_offset);
1387
1388 /* We may need to apply a fractional offset */
1389 int component = (is_flat || is_interp) ?
1390 nir_intrinsic_component(instr) : 0;
1391 reg = nir_dest_index(&instr->dest);
1392
1393 if (is_uniform && !ctx->is_blend) {
1394 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1395 } else if (is_ubo) {
1396 nir_src index = instr->src[0];
1397
1398 /* TODO: Is indirect block number possible? */
1399 assert(nir_src_is_const(index));
1400
1401 uint32_t uindex = nir_src_as_uint(index) + 1;
1402 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1403 } else if (is_global || is_shared) {
1404 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1405 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1406 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1407 } else if (ctx->is_blend) {
1408 /* For blend shaders, load the input color, which is
1409 * preloaded to r0 */
1410
1411 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1412 emit_mir_instruction(ctx, move);
1413 schedule_barrier(ctx);
1414 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1415 emit_attr_read(ctx, reg, offset, nr_comp, t);
1416 } else {
1417 DBG("Unknown load\n");
1418 assert(0);
1419 }
1420
1421 break;
1422 }
1423
1424 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1425 case nir_intrinsic_load_barycentric_pixel:
1426 case nir_intrinsic_load_barycentric_centroid:
1427 break;
1428
1429 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1430
1431 case nir_intrinsic_load_raw_output_pan:
1432 case nir_intrinsic_load_output_u8_as_fp16_pan:
1433 reg = nir_dest_index(&instr->dest);
1434 assert(ctx->is_blend);
1435
1436 /* T720 and below use different blend opcodes with slightly
1437 * different semantics than T760 and up */
1438
1439 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1440 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1441
1442 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1443 ld.load_store.op = old_blend ?
1444 midgard_op_ld_color_buffer_u8_as_fp16_old :
1445 midgard_op_ld_color_buffer_u8_as_fp16;
1446
1447 if (old_blend) {
1448 ld.load_store.address = 1;
1449 ld.load_store.arg_2 = 0x1E;
1450 }
1451
1452 for (unsigned c = 2; c < 16; ++c)
1453 ld.swizzle[0][c] = 0;
1454 }
1455
1456 emit_mir_instruction(ctx, ld);
1457 break;
1458
1459 case nir_intrinsic_load_blend_const_color_rgba: {
1460 assert(ctx->is_blend);
1461 reg = nir_dest_index(&instr->dest);
1462
1463 /* Blend constants are embedded directly in the shader and
1464 * patched in, so we use some magic routing */
1465
1466 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1467 ins.has_constants = true;
1468 ins.has_blend_constant = true;
1469 emit_mir_instruction(ctx, ins);
1470 break;
1471 }
1472
1473 case nir_intrinsic_store_zs_output_pan: {
1474 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1475 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1476 MIDGARD_ZS_RT);
1477
1478 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1479
1480 if (!nir_intrinsic_component(instr))
1481 br->writeout_depth = true;
1482 if (nir_intrinsic_component(instr) ||
1483 instr->num_components)
1484 br->writeout_stencil = true;
1485 assert(br->writeout_depth | br->writeout_stencil);
1486 break;
1487 }
1488
1489 case nir_intrinsic_store_output:
1490 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1491
1492 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1493
1494 reg = nir_src_index(ctx, &instr->src[0]);
1495
1496 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1497 const nir_variable *var;
1498 enum midgard_rt_id rt;
1499
1500 var = search_var(&ctx->nir->outputs,
1501 nir_intrinsic_base(instr));
1502 assert(var);
1503 if (var->data.location == FRAG_RESULT_COLOR)
1504 rt = MIDGARD_COLOR_RT0;
1505 else if (var->data.location >= FRAG_RESULT_DATA0)
1506 rt = MIDGARD_COLOR_RT0 + var->data.location -
1507 FRAG_RESULT_DATA0;
1508 else
1509 assert(0);
1510
1511 emit_fragment_store(ctx, reg, rt);
1512 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1513 /* We should have been vectorized, though we don't
1514 * currently check that st_vary is emitted only once
1515 * per slot (this is relevant, since there's not a mask
1516 * parameter available on the store [set to 0 by the
1517 * blob]). We do respect the component by adjusting the
1518 * swizzle. If this is a constant source, we'll need to
1519 * emit that explicitly. */
1520
1521 emit_explicit_constant(ctx, reg, reg);
1522
1523 unsigned dst_component = nir_intrinsic_component(instr);
1524 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1525
1526 midgard_instruction st = m_st_vary_32(reg, offset);
1527 st.load_store.arg_1 = 0x9E;
1528 st.load_store.arg_2 = 0x1E;
1529
1530 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1531 case nir_type_uint:
1532 case nir_type_bool:
1533 st.load_store.op = midgard_op_st_vary_32u;
1534 break;
1535 case nir_type_int:
1536 st.load_store.op = midgard_op_st_vary_32i;
1537 break;
1538 case nir_type_float:
1539 st.load_store.op = midgard_op_st_vary_32;
1540 break;
1541 default:
1542 unreachable("Attempted to store unknown type");
1543 break;
1544 }
1545
1546 /* nir_intrinsic_component(store_intr) encodes the
1547 * destination component start. Source component offset
1548 * adjustment is taken care of in
1549 * install_registers_instr(), when offset_swizzle() is
1550 * called.
1551 */
1552 unsigned src_component = COMPONENT_X;
1553
1554 assert(nr_comp > 0);
1555 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1556 st.swizzle[0][i] = src_component;
1557 if (i >= dst_component && i < dst_component + nr_comp - 1)
1558 src_component++;
1559 }
1560
1561 emit_mir_instruction(ctx, st);
1562 } else {
1563 DBG("Unknown store\n");
1564 assert(0);
1565 }
1566
1567 break;
1568
1569 /* Special case of store_output for lowered blend shaders */
1570 case nir_intrinsic_store_raw_output_pan:
1571 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1572 reg = nir_src_index(ctx, &instr->src[0]);
1573
1574 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1575 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1576 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1577 * of:
1578 *
1579 * imov r0.xyzw, r0.xxxx
1580 */
1581
1582 unsigned expanded = make_compiler_temp(ctx);
1583
1584 midgard_instruction splatter = v_mov(reg, expanded);
1585
1586 for (unsigned c = 0; c < 16; ++c)
1587 splatter.swizzle[1][c] = 0;
1588
1589 emit_mir_instruction(ctx, splatter);
1590 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1591 } else
1592 emit_fragment_store(ctx, reg, ctx->blend_rt);
1593
1594 break;
1595
1596 case nir_intrinsic_store_global:
1597 case nir_intrinsic_store_shared:
1598 reg = nir_src_index(ctx, &instr->src[0]);
1599 emit_explicit_constant(ctx, reg, reg);
1600
1601 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1602 break;
1603
1604 case nir_intrinsic_load_ssbo_address:
1605 emit_sysval_read(ctx, &instr->instr, 1, 0);
1606 break;
1607
1608 case nir_intrinsic_get_buffer_size:
1609 emit_sysval_read(ctx, &instr->instr, 1, 8);
1610 break;
1611
1612 case nir_intrinsic_load_viewport_scale:
1613 case nir_intrinsic_load_viewport_offset:
1614 case nir_intrinsic_load_num_work_groups:
1615 case nir_intrinsic_load_sampler_lod_parameters_pan:
1616 emit_sysval_read(ctx, &instr->instr, 3, 0);
1617 break;
1618
1619 case nir_intrinsic_load_work_group_id:
1620 case nir_intrinsic_load_local_invocation_id:
1621 emit_compute_builtin(ctx, instr);
1622 break;
1623
1624 case nir_intrinsic_load_vertex_id:
1625 case nir_intrinsic_load_instance_id:
1626 emit_vertex_builtin(ctx, instr);
1627 break;
1628
1629 case nir_intrinsic_memory_barrier_buffer:
1630 case nir_intrinsic_memory_barrier_shared:
1631 break;
1632
1633 case nir_intrinsic_control_barrier:
1634 schedule_barrier(ctx);
1635 emit_control_barrier(ctx);
1636 schedule_barrier(ctx);
1637 break;
1638
1639 default:
1640 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1641 assert(0);
1642 break;
1643 }
1644 }
1645
1646 static unsigned
1647 midgard_tex_format(enum glsl_sampler_dim dim)
1648 {
1649 switch (dim) {
1650 case GLSL_SAMPLER_DIM_1D:
1651 case GLSL_SAMPLER_DIM_BUF:
1652 return MALI_TEX_1D;
1653
1654 case GLSL_SAMPLER_DIM_2D:
1655 case GLSL_SAMPLER_DIM_EXTERNAL:
1656 case GLSL_SAMPLER_DIM_RECT:
1657 return MALI_TEX_2D;
1658
1659 case GLSL_SAMPLER_DIM_3D:
1660 return MALI_TEX_3D;
1661
1662 case GLSL_SAMPLER_DIM_CUBE:
1663 return MALI_TEX_CUBE;
1664
1665 default:
1666 DBG("Unknown sampler dim type\n");
1667 assert(0);
1668 return 0;
1669 }
1670 }
1671
1672 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1673 * was successful */
1674
1675 static bool
1676 pan_attach_constant_bias(
1677 compiler_context *ctx,
1678 nir_src lod,
1679 midgard_texture_word *word)
1680 {
1681 /* To attach as constant, it has to *be* constant */
1682
1683 if (!nir_src_is_const(lod))
1684 return false;
1685
1686 float f = nir_src_as_float(lod);
1687
1688 /* Break into fixed-point */
1689 signed lod_int = f;
1690 float lod_frac = f - lod_int;
1691
1692 /* Carry over negative fractions */
1693 if (lod_frac < 0.0) {
1694 lod_int--;
1695 lod_frac += 1.0;
1696 }
1697
1698 /* Encode */
1699 word->bias = float_to_ubyte(lod_frac);
1700 word->bias_int = lod_int;
1701
1702 return true;
1703 }
1704
1705 static void
1706 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1707 unsigned midgard_texop)
1708 {
1709 /* TODO */
1710 //assert (!instr->sampler);
1711
1712 int texture_index = instr->texture_index;
1713 int sampler_index = texture_index;
1714
1715 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1716 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1717
1718 midgard_instruction ins = {
1719 .type = TAG_TEXTURE_4,
1720 .mask = 0xF,
1721 .dest = nir_dest_index(&instr->dest),
1722 .src = { ~0, ~0, ~0, ~0 },
1723 .dest_type = dest_type,
1724 .swizzle = SWIZZLE_IDENTITY_4,
1725 .texture = {
1726 .op = midgard_texop,
1727 .format = midgard_tex_format(instr->sampler_dim),
1728 .texture_handle = texture_index,
1729 .sampler_handle = sampler_index,
1730 .shadow = instr->is_shadow,
1731 }
1732 };
1733
1734 if (instr->is_shadow && !instr->is_new_style_shadow)
1735 for (int i = 0; i < 4; ++i)
1736 ins.swizzle[0][i] = COMPONENT_X;
1737
1738 /* We may need a temporary for the coordinate */
1739
1740 bool needs_temp_coord =
1741 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1742 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1743 (instr->is_shadow);
1744
1745 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1746
1747 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1748 int index = nir_src_index(ctx, &instr->src[i].src);
1749 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1750 unsigned sz = nir_src_bit_size(instr->src[i].src);
1751 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1752
1753 switch (instr->src[i].src_type) {
1754 case nir_tex_src_coord: {
1755 emit_explicit_constant(ctx, index, index);
1756
1757 unsigned coord_mask = mask_of(instr->coord_components);
1758
1759 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1760
1761 if (flip_zw)
1762 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1763
1764 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1765 /* texelFetch is undefined on samplerCube */
1766 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1767
1768 /* For cubemaps, we use a special ld/st op to
1769 * select the face and copy the xy into the
1770 * texture register */
1771
1772 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1773 ld.src[1] = index;
1774 ld.src_types[1] = T;
1775 ld.mask = 0x3; /* xy */
1776 ld.load_store.arg_1 = 0x20;
1777 ld.swizzle[1][3] = COMPONENT_X;
1778 emit_mir_instruction(ctx, ld);
1779
1780 /* xyzw -> xyxx */
1781 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1782 ins.swizzle[1][3] = COMPONENT_X;
1783 } else if (needs_temp_coord) {
1784 /* mov coord_temp, coords */
1785 midgard_instruction mov = v_mov(index, coords);
1786 mov.mask = coord_mask;
1787
1788 if (flip_zw)
1789 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1790
1791 emit_mir_instruction(ctx, mov);
1792 } else {
1793 coords = index;
1794 }
1795
1796 ins.src[1] = coords;
1797 ins.src_types[1] = T;
1798
1799 /* Texelfetch coordinates uses all four elements
1800 * (xyz/index) regardless of texture dimensionality,
1801 * which means it's necessary to zero the unused
1802 * components to keep everything happy */
1803
1804 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1805 /* mov index.zw, #0, or generalized */
1806 midgard_instruction mov =
1807 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1808 mov.has_constants = true;
1809 mov.mask = coord_mask ^ 0xF;
1810 emit_mir_instruction(ctx, mov);
1811 }
1812
1813 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1814 /* Array component in w but NIR wants it in z,
1815 * but if we have a temp coord we already fixed
1816 * that up */
1817
1818 if (nr_components == 3) {
1819 ins.swizzle[1][2] = COMPONENT_Z;
1820 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1821 } else if (nr_components == 2) {
1822 ins.swizzle[1][2] =
1823 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1824 ins.swizzle[1][3] = COMPONENT_X;
1825 } else
1826 unreachable("Invalid texture 2D components");
1827 }
1828
1829 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1830 /* We zeroed */
1831 ins.swizzle[1][2] = COMPONENT_Z;
1832 ins.swizzle[1][3] = COMPONENT_W;
1833 }
1834
1835 break;
1836 }
1837
1838 case nir_tex_src_bias:
1839 case nir_tex_src_lod: {
1840 /* Try as a constant if we can */
1841
1842 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1843 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1844 break;
1845
1846 ins.texture.lod_register = true;
1847 ins.src[2] = index;
1848 ins.src_types[2] = T;
1849
1850 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1851 ins.swizzle[2][c] = COMPONENT_X;
1852
1853 emit_explicit_constant(ctx, index, index);
1854
1855 break;
1856 };
1857
1858 case nir_tex_src_offset: {
1859 ins.texture.offset_register = true;
1860 ins.src[3] = index;
1861 ins.src_types[3] = T;
1862
1863 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1864 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
1865
1866 emit_explicit_constant(ctx, index, index);
1867 break;
1868 };
1869
1870 case nir_tex_src_comparator: {
1871 unsigned comp = COMPONENT_Z;
1872
1873 /* mov coord_temp.foo, coords */
1874 midgard_instruction mov = v_mov(index, coords);
1875 mov.mask = 1 << comp;
1876
1877 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
1878 mov.swizzle[1][i] = COMPONENT_X;
1879
1880 emit_mir_instruction(ctx, mov);
1881 break;
1882 }
1883
1884 default: {
1885 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
1886 assert(0);
1887 }
1888 }
1889 }
1890
1891 emit_mir_instruction(ctx, ins);
1892 }
1893
1894 static void
1895 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1896 {
1897 switch (instr->op) {
1898 case nir_texop_tex:
1899 case nir_texop_txb:
1900 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
1901 break;
1902 case nir_texop_txl:
1903 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
1904 break;
1905 case nir_texop_txf:
1906 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
1907 break;
1908 case nir_texop_txs:
1909 emit_sysval_read(ctx, &instr->instr, 4, 0);
1910 break;
1911 default: {
1912 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
1913 assert(0);
1914 }
1915 }
1916 }
1917
1918 static void
1919 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1920 {
1921 switch (instr->type) {
1922 case nir_jump_break: {
1923 /* Emit a branch out of the loop */
1924 struct midgard_instruction br = v_branch(false, false);
1925 br.branch.target_type = TARGET_BREAK;
1926 br.branch.target_break = ctx->current_loop_depth;
1927 emit_mir_instruction(ctx, br);
1928 break;
1929 }
1930
1931 default:
1932 DBG("Unknown jump type %d\n", instr->type);
1933 break;
1934 }
1935 }
1936
1937 static void
1938 emit_instr(compiler_context *ctx, struct nir_instr *instr)
1939 {
1940 switch (instr->type) {
1941 case nir_instr_type_load_const:
1942 emit_load_const(ctx, nir_instr_as_load_const(instr));
1943 break;
1944
1945 case nir_instr_type_intrinsic:
1946 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1947 break;
1948
1949 case nir_instr_type_alu:
1950 emit_alu(ctx, nir_instr_as_alu(instr));
1951 break;
1952
1953 case nir_instr_type_tex:
1954 emit_tex(ctx, nir_instr_as_tex(instr));
1955 break;
1956
1957 case nir_instr_type_jump:
1958 emit_jump(ctx, nir_instr_as_jump(instr));
1959 break;
1960
1961 case nir_instr_type_ssa_undef:
1962 /* Spurious */
1963 break;
1964
1965 default:
1966 DBG("Unhandled instruction type\n");
1967 break;
1968 }
1969 }
1970
1971
1972 /* ALU instructions can inline or embed constants, which decreases register
1973 * pressure and saves space. */
1974
1975 #define CONDITIONAL_ATTACH(idx) { \
1976 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
1977 \
1978 if (entry) { \
1979 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
1980 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1981 } \
1982 }
1983
1984 static void
1985 inline_alu_constants(compiler_context *ctx, midgard_block *block)
1986 {
1987 mir_foreach_instr_in_block(block, alu) {
1988 /* Other instructions cannot inline constants */
1989 if (alu->type != TAG_ALU_4) continue;
1990 if (alu->compact_branch) continue;
1991
1992 /* If there is already a constant here, we can do nothing */
1993 if (alu->has_constants) continue;
1994
1995 CONDITIONAL_ATTACH(0);
1996
1997 if (!alu->has_constants) {
1998 CONDITIONAL_ATTACH(1)
1999 } else if (!alu->inline_constant) {
2000 /* Corner case: _two_ vec4 constants, for instance with a
2001 * csel. For this case, we can only use a constant
2002 * register for one, we'll have to emit a move for the
2003 * other. */
2004
2005 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2006 unsigned scratch = make_compiler_temp(ctx);
2007
2008 if (entry) {
2009 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2010 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2011
2012 /* Set the source */
2013 alu->src[1] = scratch;
2014
2015 /* Inject us -before- the last instruction which set r31 */
2016 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2017 }
2018 }
2019 }
2020 }
2021
2022 /* Midgard supports two types of constants, embedded constants (128-bit) and
2023 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2024 * constants can be demoted to inline constants, for space savings and
2025 * sometimes a performance boost */
2026
2027 static void
2028 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2029 {
2030 mir_foreach_instr_in_block(block, ins) {
2031 if (!ins->has_constants) continue;
2032 if (ins->has_inline_constant) continue;
2033
2034 /* Blend constants must not be inlined by definition */
2035 if (ins->has_blend_constant) continue;
2036
2037 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2038 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2039 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2040
2041 if (!(is_16 || is_32))
2042 continue;
2043
2044 /* src1 cannot be an inline constant due to encoding
2045 * restrictions. So, if possible we try to flip the arguments
2046 * in that case */
2047
2048 int op = ins->alu.op;
2049
2050 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2051 alu_opcode_props[op].props & OP_COMMUTES) {
2052 mir_flip(ins);
2053 }
2054
2055 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2056 /* Extract the source information */
2057
2058 midgard_vector_alu_src *src;
2059 int q = ins->alu.src2;
2060 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
2061 src = m;
2062
2063 /* Component is from the swizzle. Take a nonzero component */
2064 assert(ins->mask);
2065 unsigned first_comp = ffs(ins->mask) - 1;
2066 unsigned component = ins->swizzle[1][first_comp];
2067
2068 /* Scale constant appropriately, if we can legally */
2069 uint16_t scaled_constant = 0;
2070
2071 if (is_16) {
2072 scaled_constant = ins->constants.u16[component];
2073 } else if (midgard_is_integer_op(op)) {
2074 scaled_constant = ins->constants.u32[component];
2075
2076 /* Constant overflow after resize */
2077 if (scaled_constant != ins->constants.u32[component])
2078 continue;
2079 } else {
2080 float original = ins->constants.f32[component];
2081 scaled_constant = _mesa_float_to_half(original);
2082
2083 /* Check for loss of precision. If this is
2084 * mediump, we don't care, but for a highp
2085 * shader, we need to pay attention. NIR
2086 * doesn't yet tell us which mode we're in!
2087 * Practically this prevents most constants
2088 * from being inlined, sadly. */
2089
2090 float fp32 = _mesa_half_to_float(scaled_constant);
2091
2092 if (fp32 != original)
2093 continue;
2094 }
2095
2096 /* We don't know how to handle these with a constant */
2097
2098 if (mir_nontrivial_source2_mod_simple(ins) || src->rep_low || src->rep_high) {
2099 DBG("Bailing inline constant...\n");
2100 continue;
2101 }
2102
2103 /* Make sure that the constant is not itself a vector
2104 * by checking if all accessed values are the same. */
2105
2106 const midgard_constants *cons = &ins->constants;
2107 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2108
2109 bool is_vector = false;
2110 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2111
2112 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2113 /* We only care if this component is actually used */
2114 if (!(mask & (1 << c)))
2115 continue;
2116
2117 uint32_t test = is_16 ?
2118 cons->u16[ins->swizzle[1][c]] :
2119 cons->u32[ins->swizzle[1][c]];
2120
2121 if (test != value) {
2122 is_vector = true;
2123 break;
2124 }
2125 }
2126
2127 if (is_vector)
2128 continue;
2129
2130 /* Get rid of the embedded constant */
2131 ins->has_constants = false;
2132 ins->src[1] = ~0;
2133 ins->has_inline_constant = true;
2134 ins->inline_constant = scaled_constant;
2135 }
2136 }
2137 }
2138
2139 /* Dead code elimination for branches at the end of a block - only one branch
2140 * per block is legal semantically */
2141
2142 static void
2143 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2144 {
2145 bool branched = false;
2146
2147 mir_foreach_instr_in_block_safe(block, ins) {
2148 if (!midgard_is_branch_unit(ins->unit)) continue;
2149
2150 if (branched)
2151 mir_remove_instruction(ins);
2152
2153 branched = true;
2154 }
2155 }
2156
2157 static unsigned
2158 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2159 {
2160 /* Loop to ourselves */
2161 midgard_instruction *br = ctx->writeout_branch[rt];
2162 struct midgard_instruction ins = v_branch(false, false);
2163 ins.writeout = true;
2164 ins.writeout_depth = br->writeout_depth;
2165 ins.writeout_stencil = br->writeout_stencil;
2166 ins.branch.target_block = ctx->block_count - 1;
2167 ins.constants.u32[0] = br->constants.u32[0];
2168 emit_mir_instruction(ctx, ins);
2169
2170 ctx->current_block->epilogue = true;
2171 schedule_barrier(ctx);
2172 return ins.branch.target_block;
2173 }
2174
2175 static midgard_block *
2176 emit_block(compiler_context *ctx, nir_block *block)
2177 {
2178 midgard_block *this_block = ctx->after_block;
2179 ctx->after_block = NULL;
2180
2181 if (!this_block)
2182 this_block = create_empty_block(ctx);
2183
2184 list_addtail(&this_block->base.link, &ctx->blocks);
2185
2186 this_block->scheduled = false;
2187 ++ctx->block_count;
2188
2189 /* Set up current block */
2190 list_inithead(&this_block->base.instructions);
2191 ctx->current_block = this_block;
2192
2193 nir_foreach_instr(instr, block) {
2194 emit_instr(ctx, instr);
2195 ++ctx->instruction_count;
2196 }
2197
2198 return this_block;
2199 }
2200
2201 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2202
2203 static void
2204 emit_if(struct compiler_context *ctx, nir_if *nif)
2205 {
2206 midgard_block *before_block = ctx->current_block;
2207
2208 /* Speculatively emit the branch, but we can't fill it in until later */
2209 EMIT(branch, true, true);
2210 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2211 then_branch->src[0] = nir_src_index(ctx, &nif->condition);
2212 then_branch->src_types[0] = nir_type_uint32;
2213
2214 /* Emit the two subblocks. */
2215 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2216 midgard_block *end_then_block = ctx->current_block;
2217
2218 /* Emit a jump from the end of the then block to the end of the else */
2219 EMIT(branch, false, false);
2220 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2221
2222 /* Emit second block, and check if it's empty */
2223
2224 int else_idx = ctx->block_count;
2225 int count_in = ctx->instruction_count;
2226 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2227 midgard_block *end_else_block = ctx->current_block;
2228 int after_else_idx = ctx->block_count;
2229
2230 /* Now that we have the subblocks emitted, fix up the branches */
2231
2232 assert(then_block);
2233 assert(else_block);
2234
2235 if (ctx->instruction_count == count_in) {
2236 /* The else block is empty, so don't emit an exit jump */
2237 mir_remove_instruction(then_exit);
2238 then_branch->branch.target_block = after_else_idx;
2239 } else {
2240 then_branch->branch.target_block = else_idx;
2241 then_exit->branch.target_block = after_else_idx;
2242 }
2243
2244 /* Wire up the successors */
2245
2246 ctx->after_block = create_empty_block(ctx);
2247
2248 pan_block_add_successor(&before_block->base, &then_block->base);
2249 pan_block_add_successor(&before_block->base, &else_block->base);
2250
2251 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2252 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2253 }
2254
2255 static void
2256 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2257 {
2258 /* Remember where we are */
2259 midgard_block *start_block = ctx->current_block;
2260
2261 /* Allocate a loop number, growing the current inner loop depth */
2262 int loop_idx = ++ctx->current_loop_depth;
2263
2264 /* Get index from before the body so we can loop back later */
2265 int start_idx = ctx->block_count;
2266
2267 /* Emit the body itself */
2268 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2269
2270 /* Branch back to loop back */
2271 struct midgard_instruction br_back = v_branch(false, false);
2272 br_back.branch.target_block = start_idx;
2273 emit_mir_instruction(ctx, br_back);
2274
2275 /* Mark down that branch in the graph. */
2276 pan_block_add_successor(&start_block->base, &loop_block->base);
2277 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2278
2279 /* Find the index of the block about to follow us (note: we don't add
2280 * one; blocks are 0-indexed so we get a fencepost problem) */
2281 int break_block_idx = ctx->block_count;
2282
2283 /* Fix up the break statements we emitted to point to the right place,
2284 * now that we can allocate a block number for them */
2285 ctx->after_block = create_empty_block(ctx);
2286
2287 mir_foreach_block_from(ctx, start_block, _block) {
2288 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2289 if (ins->type != TAG_ALU_4) continue;
2290 if (!ins->compact_branch) continue;
2291
2292 /* We found a branch -- check the type to see if we need to do anything */
2293 if (ins->branch.target_type != TARGET_BREAK) continue;
2294
2295 /* It's a break! Check if it's our break */
2296 if (ins->branch.target_break != loop_idx) continue;
2297
2298 /* Okay, cool, we're breaking out of this loop.
2299 * Rewrite from a break to a goto */
2300
2301 ins->branch.target_type = TARGET_GOTO;
2302 ins->branch.target_block = break_block_idx;
2303
2304 pan_block_add_successor(_block, &ctx->after_block->base);
2305 }
2306 }
2307
2308 /* Now that we've finished emitting the loop, free up the depth again
2309 * so we play nice with recursion amid nested loops */
2310 --ctx->current_loop_depth;
2311
2312 /* Dump loop stats */
2313 ++ctx->loop_count;
2314 }
2315
2316 static midgard_block *
2317 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2318 {
2319 midgard_block *start_block = NULL;
2320
2321 foreach_list_typed(nir_cf_node, node, node, list) {
2322 switch (node->type) {
2323 case nir_cf_node_block: {
2324 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2325
2326 if (!start_block)
2327 start_block = block;
2328
2329 break;
2330 }
2331
2332 case nir_cf_node_if:
2333 emit_if(ctx, nir_cf_node_as_if(node));
2334 break;
2335
2336 case nir_cf_node_loop:
2337 emit_loop(ctx, nir_cf_node_as_loop(node));
2338 break;
2339
2340 case nir_cf_node_function:
2341 assert(0);
2342 break;
2343 }
2344 }
2345
2346 return start_block;
2347 }
2348
2349 /* Due to lookahead, we need to report the first tag executed in the command
2350 * stream and in branch targets. An initial block might be empty, so iterate
2351 * until we find one that 'works' */
2352
2353 static unsigned
2354 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2355 {
2356 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2357
2358 mir_foreach_block_from(ctx, initial_block, _v) {
2359 midgard_block *v = (midgard_block *) _v;
2360 if (v->quadword_count) {
2361 midgard_bundle *initial_bundle =
2362 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2363
2364 return initial_bundle->tag;
2365 }
2366 }
2367
2368 /* Default to a tag 1 which will break from the shader, in case we jump
2369 * to the exit block (i.e. `return` in a compute shader) */
2370
2371 return 1;
2372 }
2373
2374 /* For each fragment writeout instruction, generate a writeout loop to
2375 * associate with it */
2376
2377 static void
2378 mir_add_writeout_loops(compiler_context *ctx)
2379 {
2380 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2381 midgard_instruction *br = ctx->writeout_branch[rt];
2382 if (!br) continue;
2383
2384 unsigned popped = br->branch.target_block;
2385 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2386 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2387 br->branch.target_type = TARGET_GOTO;
2388
2389 /* If we have more RTs, we'll need to restore back after our
2390 * loop terminates */
2391
2392 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2393 midgard_instruction uncond = v_branch(false, false);
2394 uncond.branch.target_block = popped;
2395 uncond.branch.target_type = TARGET_GOTO;
2396 emit_mir_instruction(ctx, uncond);
2397 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2398 schedule_barrier(ctx);
2399 } else {
2400 /* We're last, so we can terminate here */
2401 br->last_writeout = true;
2402 }
2403 }
2404 }
2405
2406 int
2407 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2408 {
2409 struct util_dynarray *compiled = &program->compiled;
2410
2411 midgard_debug = debug_get_option_midgard_debug();
2412
2413 /* TODO: Bound against what? */
2414 compiler_context *ctx = rzalloc(NULL, compiler_context);
2415
2416 ctx->nir = nir;
2417 ctx->stage = nir->info.stage;
2418 ctx->is_blend = is_blend;
2419 ctx->alpha_ref = program->alpha_ref;
2420 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2421 ctx->quirks = midgard_get_quirks(gpu_id);
2422
2423 /* Start off with a safe cutoff, allowing usage of all 16 work
2424 * registers. Later, we'll promote uniform reads to uniform registers
2425 * if we determine it is beneficial to do so */
2426 ctx->uniform_cutoff = 8;
2427
2428 /* Initialize at a global (not block) level hash tables */
2429
2430 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2431 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2432
2433 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2434 * (so we don't accidentally duplicate the epilogue since mesa/st has
2435 * messed with our I/O quite a bit already) */
2436
2437 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2438
2439 if (ctx->stage == MESA_SHADER_VERTEX) {
2440 NIR_PASS_V(nir, nir_lower_viewport_transform);
2441 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2442 }
2443
2444 NIR_PASS_V(nir, nir_lower_var_copies);
2445 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2446 NIR_PASS_V(nir, nir_split_var_copies);
2447 NIR_PASS_V(nir, nir_lower_var_copies);
2448 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2449 NIR_PASS_V(nir, nir_lower_var_copies);
2450 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2451
2452 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2453 NIR_PASS_V(nir, nir_lower_ssbo);
2454 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2455
2456 /* Optimisation passes */
2457
2458 optimise_nir(nir, ctx->quirks);
2459
2460 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2461 nir_print_shader(nir, stdout);
2462 }
2463
2464 /* Assign sysvals and counts, now that we're sure
2465 * (post-optimisation) */
2466
2467 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2468 program->sysval_count = ctx->sysvals.sysval_count;
2469 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2470
2471 nir_foreach_function(func, nir) {
2472 if (!func->impl)
2473 continue;
2474
2475 list_inithead(&ctx->blocks);
2476 ctx->block_count = 0;
2477 ctx->func = func;
2478
2479 emit_cf_list(ctx, &func->impl->body);
2480 break; /* TODO: Multi-function shaders */
2481 }
2482
2483 util_dynarray_init(compiled, NULL);
2484
2485 /* Per-block lowering before opts */
2486
2487 mir_foreach_block(ctx, _block) {
2488 midgard_block *block = (midgard_block *) _block;
2489 inline_alu_constants(ctx, block);
2490 midgard_opt_promote_fmov(ctx, block);
2491 embedded_to_inline_constant(ctx, block);
2492 }
2493 /* MIR-level optimizations */
2494
2495 bool progress = false;
2496
2497 do {
2498 progress = false;
2499
2500 mir_foreach_block(ctx, _block) {
2501 midgard_block *block = (midgard_block *) _block;
2502 progress |= midgard_opt_copy_prop(ctx, block);
2503 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2504 progress |= midgard_opt_combine_projection(ctx, block);
2505 progress |= midgard_opt_varying_projection(ctx, block);
2506 progress |= midgard_opt_not_propagate(ctx, block);
2507 progress |= midgard_opt_fuse_src_invert(ctx, block);
2508 progress |= midgard_opt_fuse_dest_invert(ctx, block);
2509 progress |= midgard_opt_csel_invert(ctx, block);
2510 progress |= midgard_opt_drop_cmp_invert(ctx, block);
2511 progress |= midgard_opt_invert_branch(ctx, block);
2512 }
2513 } while (progress);
2514
2515 mir_foreach_block(ctx, _block) {
2516 midgard_block *block = (midgard_block *) _block;
2517 midgard_lower_invert(ctx, block);
2518 midgard_lower_derivatives(ctx, block);
2519 }
2520
2521 /* Nested control-flow can result in dead branches at the end of the
2522 * block. This messes with our analysis and is just dead code, so cull
2523 * them */
2524 mir_foreach_block(ctx, _block) {
2525 midgard_block *block = (midgard_block *) _block;
2526 midgard_cull_dead_branch(ctx, block);
2527 }
2528
2529 /* Ensure we were lowered */
2530 mir_foreach_instr_global(ctx, ins) {
2531 assert(!ins->invert);
2532 }
2533
2534 if (ctx->stage == MESA_SHADER_FRAGMENT)
2535 mir_add_writeout_loops(ctx);
2536
2537 /* Analyze now that the code is known but before scheduling creates
2538 * pipeline registers which are harder to track */
2539 mir_analyze_helper_terminate(ctx);
2540 mir_analyze_helper_requirements(ctx);
2541
2542 /* Schedule! */
2543 midgard_schedule_program(ctx);
2544 mir_ra(ctx);
2545
2546 /* Now that all the bundles are scheduled and we can calculate block
2547 * sizes, emit actual branch instructions rather than placeholders */
2548
2549 int br_block_idx = 0;
2550
2551 mir_foreach_block(ctx, _block) {
2552 midgard_block *block = (midgard_block *) _block;
2553 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2554 for (int c = 0; c < bundle->instruction_count; ++c) {
2555 midgard_instruction *ins = bundle->instructions[c];
2556
2557 if (!midgard_is_branch_unit(ins->unit)) continue;
2558
2559 /* Parse some basic branch info */
2560 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2561 bool is_conditional = ins->branch.conditional;
2562 bool is_inverted = ins->branch.invert_conditional;
2563 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2564 bool is_writeout = ins->writeout;
2565
2566 /* Determine the block we're jumping to */
2567 int target_number = ins->branch.target_block;
2568
2569 /* Report the destination tag */
2570 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2571
2572 /* Count up the number of quadwords we're
2573 * jumping over = number of quadwords until
2574 * (br_block_idx, target_number) */
2575
2576 int quadword_offset = 0;
2577
2578 if (is_discard) {
2579 /* Ignored */
2580 } else if (target_number > br_block_idx) {
2581 /* Jump forward */
2582
2583 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2584 midgard_block *blk = mir_get_block(ctx, idx);
2585 assert(blk);
2586
2587 quadword_offset += blk->quadword_count;
2588 }
2589 } else {
2590 /* Jump backwards */
2591
2592 for (int idx = br_block_idx; idx >= target_number; --idx) {
2593 midgard_block *blk = mir_get_block(ctx, idx);
2594 assert(blk);
2595
2596 quadword_offset -= blk->quadword_count;
2597 }
2598 }
2599
2600 /* Unconditional extended branches (far jumps)
2601 * have issues, so we always use a conditional
2602 * branch, setting the condition to always for
2603 * unconditional. For compact unconditional
2604 * branches, cond isn't used so it doesn't
2605 * matter what we pick. */
2606
2607 midgard_condition cond =
2608 !is_conditional ? midgard_condition_always :
2609 is_inverted ? midgard_condition_false :
2610 midgard_condition_true;
2611
2612 midgard_jmp_writeout_op op =
2613 is_discard ? midgard_jmp_writeout_op_discard :
2614 is_writeout ? midgard_jmp_writeout_op_writeout :
2615 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2616 midgard_jmp_writeout_op_branch_cond;
2617
2618 if (!is_compact) {
2619 midgard_branch_extended branch =
2620 midgard_create_branch_extended(
2621 cond, op,
2622 dest_tag,
2623 quadword_offset);
2624
2625 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2626 } else if (is_conditional || is_discard) {
2627 midgard_branch_cond branch = {
2628 .op = op,
2629 .dest_tag = dest_tag,
2630 .offset = quadword_offset,
2631 .cond = cond
2632 };
2633
2634 assert(branch.offset == quadword_offset);
2635
2636 memcpy(&ins->br_compact, &branch, sizeof(branch));
2637 } else {
2638 assert(op == midgard_jmp_writeout_op_branch_uncond);
2639
2640 midgard_branch_uncond branch = {
2641 .op = op,
2642 .dest_tag = dest_tag,
2643 .offset = quadword_offset,
2644 .unknown = 1
2645 };
2646
2647 assert(branch.offset == quadword_offset);
2648
2649 memcpy(&ins->br_compact, &branch, sizeof(branch));
2650 }
2651 }
2652 }
2653
2654 ++br_block_idx;
2655 }
2656
2657 /* Emit flat binary from the instruction arrays. Iterate each block in
2658 * sequence. Save instruction boundaries such that lookahead tags can
2659 * be assigned easily */
2660
2661 /* Cache _all_ bundles in source order for lookahead across failed branches */
2662
2663 int bundle_count = 0;
2664 mir_foreach_block(ctx, _block) {
2665 midgard_block *block = (midgard_block *) _block;
2666 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2667 }
2668 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2669 int bundle_idx = 0;
2670 mir_foreach_block(ctx, _block) {
2671 midgard_block *block = (midgard_block *) _block;
2672 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2673 source_order_bundles[bundle_idx++] = bundle;
2674 }
2675 }
2676
2677 int current_bundle = 0;
2678
2679 /* Midgard prefetches instruction types, so during emission we
2680 * need to lookahead. Unless this is the last instruction, in
2681 * which we return 1. */
2682
2683 mir_foreach_block(ctx, _block) {
2684 midgard_block *block = (midgard_block *) _block;
2685 mir_foreach_bundle_in_block(block, bundle) {
2686 int lookahead = 1;
2687
2688 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2689 lookahead = source_order_bundles[current_bundle + 1]->tag;
2690
2691 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2692 ++current_bundle;
2693 }
2694
2695 /* TODO: Free deeper */
2696 //util_dynarray_fini(&block->instructions);
2697 }
2698
2699 free(source_order_bundles);
2700
2701 /* Report the very first tag executed */
2702 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2703
2704 /* Deal with off-by-one related to the fencepost problem */
2705 program->work_register_count = ctx->work_registers + 1;
2706 program->uniform_cutoff = ctx->uniform_cutoff;
2707
2708 program->blend_patch_offset = ctx->blend_constant_offset;
2709 program->tls_size = ctx->tls_size;
2710
2711 if (midgard_debug & MIDGARD_DBG_SHADERS)
2712 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2713
2714 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2715 unsigned nr_bundles = 0, nr_ins = 0;
2716
2717 /* Count instructions and bundles */
2718
2719 mir_foreach_block(ctx, _block) {
2720 midgard_block *block = (midgard_block *) _block;
2721 nr_bundles += util_dynarray_num_elements(
2722 &block->bundles, midgard_bundle);
2723
2724 mir_foreach_bundle_in_block(block, bun)
2725 nr_ins += bun->instruction_count;
2726 }
2727
2728 /* Calculate thread count. There are certain cutoffs by
2729 * register count for thread count */
2730
2731 unsigned nr_registers = program->work_register_count;
2732
2733 unsigned nr_threads =
2734 (nr_registers <= 4) ? 4 :
2735 (nr_registers <= 8) ? 2 :
2736 1;
2737
2738 /* Dump stats */
2739
2740 fprintf(stderr, "shader%d - %s shader: "
2741 "%u inst, %u bundles, %u quadwords, "
2742 "%u registers, %u threads, %u loops, "
2743 "%u:%u spills:fills\n",
2744 SHADER_DB_COUNT++,
2745 gl_shader_stage_name(ctx->stage),
2746 nr_ins, nr_bundles, ctx->quadword_count,
2747 nr_registers, nr_threads,
2748 ctx->loop_count,
2749 ctx->spills, ctx->fills);
2750 }
2751
2752 ralloc_free(ctx);
2753
2754 return 0;
2755 }