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pan/mdg: Eliminate load_64
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 i.dest_type = T; \
121 } else { \
122 i.dest = ssa; \
123 i.dest_type = T; \
124 } \
125 return i; \
126 }
127
128 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
129 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
130
131 M_LOAD(ld_attr_32, nir_type_uint32);
132 M_LOAD(ld_vary_32, nir_type_uint32);
133 M_LOAD(ld_ubo_int4, nir_type_uint32);
134 M_LOAD(ld_int4, nir_type_uint32);
135 M_STORE(st_int4, nir_type_uint32);
136 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
137 M_STORE(st_vary_32, nir_type_uint32);
138 M_LOAD(ld_cubemap_coords, nir_type_uint32);
139 M_LOAD(ld_compute_id, nir_type_uint32);
140
141 static midgard_instruction
142 v_branch(bool conditional, bool invert)
143 {
144 midgard_instruction ins = {
145 .type = TAG_ALU_4,
146 .unit = ALU_ENAB_BRANCH,
147 .compact_branch = true,
148 .branch = {
149 .conditional = conditional,
150 .invert_conditional = invert
151 },
152 .dest = ~0,
153 .src = { ~0, ~0, ~0, ~0 },
154 };
155
156 return ins;
157 }
158
159 static midgard_branch_extended
160 midgard_create_branch_extended( midgard_condition cond,
161 midgard_jmp_writeout_op op,
162 unsigned dest_tag,
163 signed quadword_offset)
164 {
165 /* The condition code is actually a LUT describing a function to
166 * combine multiple condition codes. However, we only support a single
167 * condition code at the moment, so we just duplicate over a bunch of
168 * times. */
169
170 uint16_t duplicated_cond =
171 (cond << 14) |
172 (cond << 12) |
173 (cond << 10) |
174 (cond << 8) |
175 (cond << 6) |
176 (cond << 4) |
177 (cond << 2) |
178 (cond << 0);
179
180 midgard_branch_extended branch = {
181 .op = op,
182 .dest_tag = dest_tag,
183 .offset = quadword_offset,
184 .cond = duplicated_cond
185 };
186
187 return branch;
188 }
189
190 static void
191 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
192 {
193 ins->has_constants = true;
194 memcpy(&ins->constants, constants, 16);
195 }
196
197 static int
198 glsl_type_size(const struct glsl_type *type, bool bindless)
199 {
200 return glsl_count_attribute_slots(type, false);
201 }
202
203 /* Lower fdot2 to a vector multiplication followed by channel addition */
204 static void
205 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
206 {
207 if (alu->op != nir_op_fdot2)
208 return;
209
210 b->cursor = nir_before_instr(&alu->instr);
211
212 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
213 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
214
215 nir_ssa_def *product = nir_fmul(b, src0, src1);
216
217 nir_ssa_def *sum = nir_fadd(b,
218 nir_channel(b, product, 0),
219 nir_channel(b, product, 1));
220
221 /* Replace the fdot2 with this sum */
222 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
223 }
224
225 static bool
226 midgard_nir_lower_fdot2(nir_shader *shader)
227 {
228 bool progress = false;
229
230 nir_foreach_function(function, shader) {
231 if (!function->impl) continue;
232
233 nir_builder _b;
234 nir_builder *b = &_b;
235 nir_builder_init(b, function->impl);
236
237 nir_foreach_block(block, function->impl) {
238 nir_foreach_instr_safe(instr, block) {
239 if (instr->type != nir_instr_type_alu) continue;
240
241 nir_alu_instr *alu = nir_instr_as_alu(instr);
242 midgard_nir_lower_fdot2_body(b, alu);
243
244 progress |= true;
245 }
246 }
247
248 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
249
250 }
251
252 return progress;
253 }
254
255 /* Midgard can't write depth and stencil separately. It has to happen in a
256 * single store operation containing both. Let's add a panfrost specific
257 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
258 * one.
259 */
260 static bool
261 midgard_nir_lower_zs_store(nir_shader *nir)
262 {
263 if (nir->info.stage != MESA_SHADER_FRAGMENT)
264 return false;
265
266 nir_variable *z_var = NULL, *s_var = NULL;
267
268 nir_foreach_variable(var, &nir->outputs) {
269 if (var->data.location == FRAG_RESULT_DEPTH)
270 z_var = var;
271 else if (var->data.location == FRAG_RESULT_STENCIL)
272 s_var = var;
273 }
274
275 if (!z_var && !s_var)
276 return false;
277
278 bool progress = false;
279
280 nir_foreach_function(function, nir) {
281 if (!function->impl) continue;
282
283 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
284
285 nir_foreach_block(block, function->impl) {
286 nir_foreach_instr_safe(instr, block) {
287 if (instr->type != nir_instr_type_intrinsic)
288 continue;
289
290 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
291 if (intr->intrinsic != nir_intrinsic_store_output)
292 continue;
293
294 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
295 assert(!z_store);
296 z_store = intr;
297 last_store = intr;
298 }
299
300 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
301 assert(!s_store);
302 s_store = intr;
303 last_store = intr;
304 }
305 }
306 }
307
308 if (!z_store && !s_store) continue;
309
310 nir_builder b;
311 nir_builder_init(&b, function->impl);
312
313 b.cursor = nir_before_instr(&last_store->instr);
314
315 nir_ssa_def *zs_store_src;
316
317 if (z_store && s_store) {
318 nir_ssa_def *srcs[2] = {
319 nir_ssa_for_src(&b, z_store->src[0], 1),
320 nir_ssa_for_src(&b, s_store->src[0], 1),
321 };
322
323 zs_store_src = nir_vec(&b, srcs, 2);
324 } else {
325 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
326 }
327
328 nir_intrinsic_instr *zs_store;
329
330 zs_store = nir_intrinsic_instr_create(b.shader,
331 nir_intrinsic_store_zs_output_pan);
332 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
333 zs_store->num_components = z_store && s_store ? 2 : 1;
334 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
335
336 /* Replace the Z and S store by a ZS store */
337 nir_builder_instr_insert(&b, &zs_store->instr);
338
339 if (z_store)
340 nir_instr_remove(&z_store->instr);
341
342 if (s_store)
343 nir_instr_remove(&s_store->instr);
344
345 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
346 progress = true;
347 }
348
349 return progress;
350 }
351
352 /* Flushes undefined values to zero */
353
354 static void
355 optimise_nir(nir_shader *nir, unsigned quirks)
356 {
357 bool progress;
358 unsigned lower_flrp =
359 (nir->options->lower_flrp16 ? 16 : 0) |
360 (nir->options->lower_flrp32 ? 32 : 0) |
361 (nir->options->lower_flrp64 ? 64 : 0);
362
363 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
364 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
365
366 nir_lower_tex_options lower_tex_options = {
367 .lower_txs_lod = true,
368 .lower_txp = ~0,
369 .lower_tex_without_implicit_lod =
370 (quirks & MIDGARD_EXPLICIT_LOD),
371
372 /* TODO: we have native gradient.. */
373 .lower_txd = true,
374 };
375
376 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
377
378 /* Must lower fdot2 after tex is lowered */
379 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
380
381 /* T720 is broken. */
382
383 if (quirks & MIDGARD_BROKEN_LOD)
384 NIR_PASS_V(nir, midgard_nir_lod_errata);
385
386 do {
387 progress = false;
388
389 NIR_PASS(progress, nir, nir_lower_var_copies);
390 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
391
392 NIR_PASS(progress, nir, nir_copy_prop);
393 NIR_PASS(progress, nir, nir_opt_remove_phis);
394 NIR_PASS(progress, nir, nir_opt_dce);
395 NIR_PASS(progress, nir, nir_opt_dead_cf);
396 NIR_PASS(progress, nir, nir_opt_cse);
397 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
398 NIR_PASS(progress, nir, nir_opt_algebraic);
399 NIR_PASS(progress, nir, nir_opt_constant_folding);
400
401 if (lower_flrp != 0) {
402 bool lower_flrp_progress = false;
403 NIR_PASS(lower_flrp_progress,
404 nir,
405 nir_lower_flrp,
406 lower_flrp,
407 false /* always_precise */,
408 nir->options->lower_ffma);
409 if (lower_flrp_progress) {
410 NIR_PASS(progress, nir,
411 nir_opt_constant_folding);
412 progress = true;
413 }
414
415 /* Nothing should rematerialize any flrps, so we only
416 * need to do this lowering once.
417 */
418 lower_flrp = 0;
419 }
420
421 NIR_PASS(progress, nir, nir_opt_undef);
422 NIR_PASS(progress, nir, nir_undef_to_zero);
423
424 NIR_PASS(progress, nir, nir_opt_loop_unroll,
425 nir_var_shader_in |
426 nir_var_shader_out |
427 nir_var_function_temp);
428
429 NIR_PASS(progress, nir, nir_opt_vectorize);
430 } while (progress);
431
432 /* Must be run at the end to prevent creation of fsin/fcos ops */
433 NIR_PASS(progress, nir, midgard_nir_scale_trig);
434
435 do {
436 progress = false;
437
438 NIR_PASS(progress, nir, nir_opt_dce);
439 NIR_PASS(progress, nir, nir_opt_algebraic);
440 NIR_PASS(progress, nir, nir_opt_constant_folding);
441 NIR_PASS(progress, nir, nir_copy_prop);
442 } while (progress);
443
444 NIR_PASS(progress, nir, nir_opt_algebraic_late);
445 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
446
447 /* We implement booleans as 32-bit 0/~0 */
448 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
449
450 /* Now that booleans are lowered, we can run out late opts */
451 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
452 NIR_PASS(progress, nir, midgard_nir_cancel_inot);
453
454 NIR_PASS(progress, nir, nir_copy_prop);
455 NIR_PASS(progress, nir, nir_opt_dce);
456
457 /* Take us out of SSA */
458 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
459 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
460
461 /* We are a vector architecture; write combine where possible */
462 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
463 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
464
465 NIR_PASS(progress, nir, nir_opt_dce);
466 }
467
468 /* Do not actually emit a load; instead, cache the constant for inlining */
469
470 static void
471 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
472 {
473 nir_ssa_def def = instr->def;
474
475 midgard_constants *consts = rzalloc(NULL, midgard_constants);
476
477 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
478
479 #define RAW_CONST_COPY(bits) \
480 nir_const_value_to_array(consts->u##bits, instr->value, \
481 instr->def.num_components, u##bits)
482
483 switch (instr->def.bit_size) {
484 case 64:
485 RAW_CONST_COPY(64);
486 break;
487 case 32:
488 RAW_CONST_COPY(32);
489 break;
490 case 16:
491 RAW_CONST_COPY(16);
492 break;
493 case 8:
494 RAW_CONST_COPY(8);
495 break;
496 default:
497 unreachable("Invalid bit_size for load_const instruction\n");
498 }
499
500 /* Shifted for SSA, +1 for off-by-one */
501 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
502 }
503
504 /* Normally constants are embedded implicitly, but for I/O and such we have to
505 * explicitly emit a move with the constant source */
506
507 static void
508 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
509 {
510 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
511
512 if (constant_value) {
513 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
514 attach_constants(ctx, &ins, constant_value, node + 1);
515 emit_mir_instruction(ctx, ins);
516 }
517 }
518
519 static bool
520 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
521 {
522 unsigned comp = src->swizzle[0];
523
524 for (unsigned c = 1; c < nr_components; ++c) {
525 if (src->swizzle[c] != comp)
526 return true;
527 }
528
529 return false;
530 }
531
532 #define ALU_CASE(nir, _op) \
533 case nir_op_##nir: \
534 op = midgard_alu_op_##_op; \
535 assert(src_bitsize == dst_bitsize); \
536 break;
537
538 #define ALU_CHECK_CMP(sext) \
539 assert(src_bitsize == 16 || src_bitsize == 32); \
540 assert(dst_bitsize == 16 || dst_bitsize == 32); \
541
542 #define ALU_CASE_BCAST(nir, _op, count) \
543 case nir_op_##nir: \
544 op = midgard_alu_op_##_op; \
545 broadcast_swizzle = count; \
546 ALU_CHECK_CMP(true); \
547 break;
548
549 #define ALU_CASE_CMP(nir, _op, sext) \
550 case nir_op_##nir: \
551 op = midgard_alu_op_##_op; \
552 ALU_CHECK_CMP(sext); \
553 break;
554
555 /* Analyze the sizes of the dest and inputs to determine reg mode. */
556
557 static midgard_reg_mode
558 reg_mode_for_nir(nir_alu_instr *instr)
559 {
560 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
561 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
562 unsigned max_bitsize = MAX2(src_bitsize, dst_bitsize);
563
564 /* We don't have fp16 LUTs, so we'll want to emit code like:
565 *
566 * vlut.fsinr hr0, hr0
567 *
568 * where both input and output are 16-bit but the operation is carried
569 * out in 32-bit
570 */
571
572 switch (instr->op) {
573 case nir_op_fsqrt:
574 case nir_op_frcp:
575 case nir_op_frsq:
576 case nir_op_fsin:
577 case nir_op_fcos:
578 case nir_op_fexp2:
579 case nir_op_flog2:
580 max_bitsize = MAX2(max_bitsize, 32);
581 default:
582 break;
583 }
584
585 switch (max_bitsize) {
586 case 8:
587 return midgard_reg_mode_8;
588 case 16:
589 return midgard_reg_mode_16;
590 case 32:
591 return midgard_reg_mode_32;
592 case 64:
593 return midgard_reg_mode_64;
594 default:
595 unreachable("Invalid bit size");
596 }
597 }
598
599 /* Compare mir_lower_invert */
600 static bool
601 nir_accepts_inot(nir_op op, unsigned src)
602 {
603 switch (op) {
604 case nir_op_ior:
605 case nir_op_iand: /* TODO: b2f16 */
606 case nir_op_ixor:
607 return true;
608 case nir_op_b32csel:
609 /* Only the condition */
610 return (src == 0);
611 default:
612 return false;
613 }
614 }
615
616 static bool
617 mir_accept_dest_mod(compiler_context *ctx, nir_dest **dest, nir_op op)
618 {
619 if (pan_has_dest_mod(dest, op)) {
620 assert((*dest)->is_ssa);
621 BITSET_SET(ctx->already_emitted, (*dest)->ssa.index);
622 return true;
623 }
624
625 return false;
626 }
627
628 static void
629 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool *not, bool is_int, unsigned bcast_count)
630 {
631 nir_alu_src src = instr->src[i];
632
633 if (!is_int) {
634 if (pan_has_source_mod(&src, nir_op_fneg))
635 *neg = !(*neg);
636
637 if (pan_has_source_mod(&src, nir_op_fabs))
638 *abs = true;
639 }
640
641 if (nir_accepts_inot(instr->op, i) && pan_has_source_mod(&src, nir_op_inot))
642 *not = true;
643
644 unsigned bits = nir_src_bit_size(src.src);
645
646 ins->src[to] = nir_src_index(NULL, &src.src);
647 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
648
649 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
650 ins->swizzle[to][c] = src.swizzle[
651 (!bcast_count || c < bcast_count) ? c :
652 (bcast_count - 1)];
653 }
654 }
655
656 /* Midgard features both fcsel and icsel, depending on whether you want int or
657 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
658 * we should emit an int or float csel depending on what modifiers could be
659 * placed. In the absense of modifiers, this is probably arbitrary. */
660
661 static bool
662 mir_is_bcsel_float(nir_alu_instr *instr)
663 {
664 nir_op intmods[] = {
665 nir_op_i2i8, nir_op_i2i16,
666 nir_op_i2i32, nir_op_i2i64
667 };
668
669 nir_op floatmods[] = {
670 nir_op_fabs, nir_op_fneg,
671 nir_op_f2f16, nir_op_f2f32,
672 nir_op_f2f64
673 };
674
675 nir_op floatdestmods[] = {
676 nir_op_fsat, nir_op_fsat_signed, nir_op_fclamp_pos,
677 nir_op_f2f16, nir_op_f2f32
678 };
679
680 signed score = 0;
681
682 for (unsigned i = 1; i < 3; ++i) {
683 nir_alu_src s = instr->src[i];
684 for (unsigned q = 0; q < ARRAY_SIZE(intmods); ++q) {
685 if (pan_has_source_mod(&s, intmods[q]))
686 score--;
687 }
688 }
689
690 for (unsigned i = 1; i < 3; ++i) {
691 nir_alu_src s = instr->src[i];
692 for (unsigned q = 0; q < ARRAY_SIZE(floatmods); ++q) {
693 if (pan_has_source_mod(&s, floatmods[q]))
694 score++;
695 }
696 }
697
698 for (unsigned q = 0; q < ARRAY_SIZE(floatdestmods); ++q) {
699 nir_dest *dest = &instr->dest.dest;
700 if (pan_has_dest_mod(&dest, floatdestmods[q]))
701 score++;
702 }
703
704 return (score > 0);
705 }
706
707 static void
708 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
709 {
710 nir_dest *dest = &instr->dest.dest;
711
712 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index))
713 return;
714
715 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
716 * is handled elsewhere */
717
718 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
719 midgard_emit_derivatives(ctx, instr);
720 return;
721 }
722
723 bool is_ssa = dest->is_ssa;
724
725 unsigned nr_components = nir_dest_num_components(*dest);
726 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
727 unsigned op = 0;
728
729 /* Number of components valid to check for the instruction (the rest
730 * will be forced to the last), or 0 to use as-is. Relevant as
731 * ball-type instructions have a channel count in NIR but are all vec4
732 * in Midgard */
733
734 unsigned broadcast_swizzle = 0;
735
736 /* What register mode should we operate in? */
737 midgard_reg_mode reg_mode =
738 reg_mode_for_nir(instr);
739
740 /* Should we swap arguments? */
741 bool flip_src12 = false;
742
743 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
744 unsigned dst_bitsize = nir_dest_bit_size(*dest);
745
746 switch (instr->op) {
747 ALU_CASE(fadd, fadd);
748 ALU_CASE(fmul, fmul);
749 ALU_CASE(fmin, fmin);
750 ALU_CASE(fmax, fmax);
751 ALU_CASE(imin, imin);
752 ALU_CASE(imax, imax);
753 ALU_CASE(umin, umin);
754 ALU_CASE(umax, umax);
755 ALU_CASE(ffloor, ffloor);
756 ALU_CASE(fround_even, froundeven);
757 ALU_CASE(ftrunc, ftrunc);
758 ALU_CASE(fceil, fceil);
759 ALU_CASE(fdot3, fdot3);
760 ALU_CASE(fdot4, fdot4);
761 ALU_CASE(iadd, iadd);
762 ALU_CASE(isub, isub);
763 ALU_CASE(imul, imul);
764
765 /* Zero shoved as second-arg */
766 ALU_CASE(iabs, iabsdiff);
767
768 ALU_CASE(mov, imov);
769
770 ALU_CASE_CMP(feq32, feq, false);
771 ALU_CASE_CMP(fne32, fne, false);
772 ALU_CASE_CMP(flt32, flt, false);
773 ALU_CASE_CMP(ieq32, ieq, true);
774 ALU_CASE_CMP(ine32, ine, true);
775 ALU_CASE_CMP(ilt32, ilt, true);
776 ALU_CASE_CMP(ult32, ult, false);
777
778 /* We don't have a native b2f32 instruction. Instead, like many
779 * GPUs, we exploit booleans as 0/~0 for false/true, and
780 * correspondingly AND
781 * by 1.0 to do the type conversion. For the moment, prime us
782 * to emit:
783 *
784 * iand [whatever], #0
785 *
786 * At the end of emit_alu (as MIR), we'll fix-up the constant
787 */
788
789 ALU_CASE_CMP(b2f32, iand, true);
790 ALU_CASE_CMP(b2f16, iand, true);
791 ALU_CASE_CMP(b2i32, iand, true);
792
793 /* Likewise, we don't have a dedicated f2b32 instruction, but
794 * we can do a "not equal to 0.0" test. */
795
796 ALU_CASE_CMP(f2b32, fne, false);
797 ALU_CASE_CMP(i2b32, ine, true);
798
799 ALU_CASE(frcp, frcp);
800 ALU_CASE(frsq, frsqrt);
801 ALU_CASE(fsqrt, fsqrt);
802 ALU_CASE(fexp2, fexp2);
803 ALU_CASE(flog2, flog2);
804
805 ALU_CASE(f2i64, f2i_rtz);
806 ALU_CASE(f2u64, f2u_rtz);
807 ALU_CASE(i2f64, i2f_rtz);
808 ALU_CASE(u2f64, u2f_rtz);
809
810 ALU_CASE(f2i32, f2i_rtz);
811 ALU_CASE(f2u32, f2u_rtz);
812 ALU_CASE(i2f32, i2f_rtz);
813 ALU_CASE(u2f32, u2f_rtz);
814
815 ALU_CASE(f2i16, f2i_rtz);
816 ALU_CASE(f2u16, f2u_rtz);
817 ALU_CASE(i2f16, i2f_rtz);
818 ALU_CASE(u2f16, u2f_rtz);
819
820 ALU_CASE(fsin, fsin);
821 ALU_CASE(fcos, fcos);
822
823 /* We'll get 0 in the second arg, so:
824 * ~a = ~(a | 0) = nor(a, 0) */
825 ALU_CASE(inot, inor);
826 ALU_CASE(iand, iand);
827 ALU_CASE(ior, ior);
828 ALU_CASE(ixor, ixor);
829 ALU_CASE(ishl, ishl);
830 ALU_CASE(ishr, iasr);
831 ALU_CASE(ushr, ilsr);
832
833 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
834 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
835 ALU_CASE_CMP(b32all_fequal4, fball_eq, true);
836
837 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
838 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
839 ALU_CASE_CMP(b32any_fnequal4, fbany_neq, true);
840
841 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
842 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
843 ALU_CASE_CMP(b32all_iequal4, iball_eq, true);
844
845 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
846 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
847 ALU_CASE_CMP(b32any_inequal4, ibany_neq, true);
848
849 /* Source mods will be shoved in later */
850 ALU_CASE(fabs, fmov);
851 ALU_CASE(fneg, fmov);
852 ALU_CASE(fsat, fmov);
853 ALU_CASE(fsat_signed, fmov);
854 ALU_CASE(fclamp_pos, fmov);
855
856 /* For size conversion, we use a move. Ideally though we would squash
857 * these ops together; maybe that has to happen after in NIR as part of
858 * propagation...? An earlier algebraic pass ensured we step down by
859 * only / exactly one size. If stepping down, we use a dest override to
860 * reduce the size; if stepping up, we use a larger-sized move with a
861 * half source and a sign/zero-extension modifier */
862
863 case nir_op_i2i8:
864 case nir_op_i2i16:
865 case nir_op_i2i32:
866 case nir_op_i2i64:
867 case nir_op_u2u8:
868 case nir_op_u2u16:
869 case nir_op_u2u32:
870 case nir_op_u2u64:
871 case nir_op_f2f16:
872 case nir_op_f2f32:
873 case nir_op_f2f64: {
874 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
875 instr->op == nir_op_f2f64)
876 op = midgard_alu_op_fmov;
877 else
878 op = midgard_alu_op_imov;
879
880 break;
881 }
882
883 /* For greater-or-equal, we lower to less-or-equal and flip the
884 * arguments */
885
886 case nir_op_fge:
887 case nir_op_fge32:
888 case nir_op_ige32:
889 case nir_op_uge32: {
890 op =
891 instr->op == nir_op_fge ? midgard_alu_op_fle :
892 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
893 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
894 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
895 0;
896
897 flip_src12 = true;
898 ALU_CHECK_CMP(false);
899 break;
900 }
901
902 case nir_op_b32csel: {
903 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
904 bool is_float = mir_is_bcsel_float(instr);
905 op = is_float ?
906 (mixed ? midgard_alu_op_fcsel_v : midgard_alu_op_fcsel) :
907 (mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel);
908
909 break;
910 }
911
912 default:
913 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
914 assert(0);
915 return;
916 }
917
918 /* Promote imov to fmov if it might help inline a constant */
919 if (op == midgard_alu_op_imov && nir_src_is_const(instr->src[0].src)
920 && nir_src_bit_size(instr->src[0].src) == 32
921 && nir_is_same_comp_swizzle(instr->src[0].swizzle,
922 nir_src_num_components(instr->src[0].src))) {
923 op = midgard_alu_op_fmov;
924 }
925
926 /* Midgard can perform certain modifiers on output of an ALU op */
927
928 unsigned outmod = 0;
929 bool is_int = midgard_is_integer_op(op);
930
931 if (midgard_is_integer_out_op(op)) {
932 outmod = midgard_outmod_int_wrap;
933 } else if (instr->op == nir_op_fsat) {
934 outmod = midgard_outmod_sat;
935 } else if (instr->op == nir_op_fsat_signed) {
936 outmod = midgard_outmod_sat_signed;
937 } else if (instr->op == nir_op_fclamp_pos) {
938 outmod = midgard_outmod_pos;
939 }
940
941 /* Fetch unit, quirks, etc information */
942 unsigned opcode_props = alu_opcode_props[op].props;
943 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
944
945 /* Look for floating point mods. We have the mods fsat, fsat_signed,
946 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
947 *
948 * fsat_signed(fpos(x)) = fsat(x)
949 * fsat_signed(fsat(x)) = fsat(x)
950 * fpos(fsat_signed(x)) = fsat(x)
951 * fpos(fsat(x)) = fsat(x)
952 * fsat(fsat_signed(x)) = fsat(x)
953 * fsat(fpos(x)) = fsat(x)
954 *
955 * So by cases any composition of output modifiers is equivalent to
956 * fsat alone.
957 */
958
959 if (!is_int && !(opcode_props & OP_TYPE_CONVERT)) {
960 bool fpos = mir_accept_dest_mod(ctx, &dest, nir_op_fclamp_pos);
961 bool fsat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat);
962 bool ssat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat_signed);
963 bool prior = (outmod != midgard_outmod_none);
964 int count = (int) prior + (int) fpos + (int) ssat + (int) fsat;
965
966 outmod = ((count > 1) || fsat) ? midgard_outmod_sat :
967 fpos ? midgard_outmod_pos :
968 ssat ? midgard_outmod_sat_signed :
969 outmod;
970 }
971
972 midgard_instruction ins = {
973 .type = TAG_ALU_4,
974 .dest = nir_dest_index(dest),
975 .dest_type = nir_op_infos[instr->op].output_type
976 | nir_dest_bit_size(*dest),
977 };
978
979 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
980 ins.src[i] = ~0;
981
982 if (quirk_flipped_r24) {
983 ins.src[0] = ~0;
984 mir_copy_src(&ins, instr, 0, 1, &ins.src_abs[1], &ins.src_neg[1], &ins.src_invert[1], is_int, broadcast_swizzle);
985 } else {
986 for (unsigned i = 0; i < nr_inputs; ++i) {
987 unsigned to = i;
988
989 if (instr->op == nir_op_b32csel) {
990 /* The condition is the first argument; move
991 * the other arguments up one to be a binary
992 * instruction for Midgard with the condition
993 * last */
994
995 if (i == 0)
996 to = 2;
997 else if (flip_src12)
998 to = 2 - i;
999 else
1000 to = i - 1;
1001 } else if (flip_src12) {
1002 to = 1 - to;
1003 }
1004
1005 mir_copy_src(&ins, instr, i, to, &ins.src_abs[to], &ins.src_neg[to], &ins.src_invert[to], is_int, broadcast_swizzle);
1006
1007 /* (!c) ? a : b = c ? b : a */
1008 if (instr->op == nir_op_b32csel && ins.src_invert[2]) {
1009 ins.src_invert[2] = false;
1010 flip_src12 ^= true;
1011 }
1012 }
1013 }
1014
1015 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
1016 /* Lowered to move */
1017 if (instr->op == nir_op_fneg)
1018 ins.src_neg[1] ^= true;
1019
1020 if (instr->op == nir_op_fabs)
1021 ins.src_abs[1] = true;
1022 }
1023
1024 ins.mask = mask_of(nr_components);
1025
1026 midgard_vector_alu alu = {
1027 .op = op,
1028 .reg_mode = reg_mode,
1029 .outmod = outmod,
1030 };
1031
1032 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1033 * components that don't exist. Note modifier => SSA => !reg => no
1034 * writemask, so we don't have to worry about writemasks here.*/
1035
1036 if (!is_ssa)
1037 ins.mask &= instr->dest.write_mask;
1038
1039 ins.alu = alu;
1040
1041 /* Late fixup for emulated instructions */
1042
1043 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1044 /* Presently, our second argument is an inline #0 constant.
1045 * Switch over to an embedded 1.0 constant (that can't fit
1046 * inline, since we're 32-bit, not 16-bit like the inline
1047 * constants) */
1048
1049 ins.has_inline_constant = false;
1050 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1051 ins.src_types[1] = nir_type_float32;
1052 ins.has_constants = true;
1053
1054 if (instr->op == nir_op_b2f32)
1055 ins.constants.f32[0] = 1.0f;
1056 else
1057 ins.constants.i32[0] = 1;
1058
1059 for (unsigned c = 0; c < 16; ++c)
1060 ins.swizzle[1][c] = 0;
1061 } else if (instr->op == nir_op_b2f16) {
1062 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1063 ins.src_types[1] = nir_type_float16;
1064 ins.has_constants = true;
1065 ins.constants.i16[0] = _mesa_float_to_half(1.0);
1066
1067 for (unsigned c = 0; c < 16; ++c)
1068 ins.swizzle[1][c] = 0;
1069 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1070 /* Lots of instructions need a 0 plonked in */
1071 ins.has_inline_constant = false;
1072 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1073 ins.src_types[1] = nir_type_uint32;
1074 ins.has_constants = true;
1075 ins.constants.u32[0] = 0;
1076
1077 for (unsigned c = 0; c < 16; ++c)
1078 ins.swizzle[1][c] = 0;
1079 }
1080
1081 /* Arrange for creation of iandnot/iornot */
1082 if (ins.src_invert[0] && !ins.src_invert[1]) {
1083 mir_flip(&ins);
1084 ins.src_invert[0] = false;
1085 ins.src_invert[1] = true;
1086 }
1087
1088 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1089 /* To avoid duplicating the lookup tables (probably), true LUT
1090 * instructions can only operate as if they were scalars. Lower
1091 * them here by changing the component. */
1092
1093 unsigned orig_mask = ins.mask;
1094
1095 unsigned swizzle_back[MIR_VEC_COMPONENTS];
1096 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
1097
1098 for (int i = 0; i < nr_components; ++i) {
1099 /* Mask the associated component, dropping the
1100 * instruction if needed */
1101
1102 ins.mask = 1 << i;
1103 ins.mask &= orig_mask;
1104
1105 if (!ins.mask)
1106 continue;
1107
1108 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1109 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1110
1111 emit_mir_instruction(ctx, ins);
1112 }
1113 } else {
1114 emit_mir_instruction(ctx, ins);
1115 }
1116 }
1117
1118 #undef ALU_CASE
1119
1120 static void
1121 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1122 {
1123 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1124 unsigned nir_mask = 0;
1125 unsigned dsize = 0;
1126
1127 if (is_read) {
1128 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1129 dsize = nir_dest_bit_size(intr->dest);
1130 } else {
1131 nir_mask = nir_intrinsic_write_mask(intr);
1132 dsize = 32;
1133 }
1134
1135 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1136 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1137 mir_set_bytemask(ins, bytemask);
1138 ins->dest_type = nir_type_uint | dsize;
1139 }
1140
1141 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1142 * optimized) versions of UBO #0 */
1143
1144 static midgard_instruction *
1145 emit_ubo_read(
1146 compiler_context *ctx,
1147 nir_instr *instr,
1148 unsigned dest,
1149 unsigned offset,
1150 nir_src *indirect_offset,
1151 unsigned indirect_shift,
1152 unsigned index)
1153 {
1154 /* TODO: half-floats */
1155
1156 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1157 ins.constants.u32[0] = offset;
1158
1159 if (instr->type == nir_instr_type_intrinsic)
1160 mir_set_intr_mask(instr, &ins, true);
1161
1162 if (indirect_offset) {
1163 ins.src[2] = nir_src_index(ctx, indirect_offset);
1164 ins.src_types[2] = nir_type_uint32;
1165 ins.load_store.arg_2 = (indirect_shift << 5);
1166 } else {
1167 ins.load_store.arg_2 = 0x1E;
1168 }
1169
1170 ins.load_store.arg_1 = index;
1171
1172 return emit_mir_instruction(ctx, ins);
1173 }
1174
1175 /* Globals are like UBOs if you squint. And shared memory is like globals if
1176 * you squint even harder */
1177
1178 static void
1179 emit_global(
1180 compiler_context *ctx,
1181 nir_instr *instr,
1182 bool is_read,
1183 unsigned srcdest,
1184 nir_src *offset,
1185 bool is_shared)
1186 {
1187 /* TODO: types */
1188
1189 midgard_instruction ins;
1190
1191 if (is_read)
1192 ins = m_ld_int4(srcdest, 0);
1193 else
1194 ins = m_st_int4(srcdest, 0);
1195
1196 mir_set_offset(ctx, &ins, offset, is_shared);
1197 mir_set_intr_mask(instr, &ins, is_read);
1198
1199 emit_mir_instruction(ctx, ins);
1200 }
1201
1202 static void
1203 emit_varying_read(
1204 compiler_context *ctx,
1205 unsigned dest, unsigned offset,
1206 unsigned nr_comp, unsigned component,
1207 nir_src *indirect_offset, nir_alu_type type, bool flat)
1208 {
1209 /* XXX: Half-floats? */
1210 /* TODO: swizzle, mask */
1211
1212 midgard_instruction ins = m_ld_vary_32(dest, offset);
1213 ins.mask = mask_of(nr_comp);
1214
1215 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1216 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1217
1218 midgard_varying_parameter p = {
1219 .is_varying = 1,
1220 .interpolation = midgard_interp_default,
1221 .flat = flat,
1222 };
1223
1224 unsigned u;
1225 memcpy(&u, &p, sizeof(p));
1226 ins.load_store.varying_parameters = u;
1227
1228 if (indirect_offset) {
1229 ins.src[2] = nir_src_index(ctx, indirect_offset);
1230 ins.src_types[2] = nir_type_uint32;
1231 } else
1232 ins.load_store.arg_2 = 0x1E;
1233
1234 ins.load_store.arg_1 = 0x9E;
1235
1236 /* Use the type appropriate load */
1237 switch (type) {
1238 case nir_type_uint:
1239 case nir_type_bool:
1240 ins.load_store.op = midgard_op_ld_vary_32u;
1241 break;
1242 case nir_type_int:
1243 ins.load_store.op = midgard_op_ld_vary_32i;
1244 break;
1245 case nir_type_float:
1246 ins.load_store.op = midgard_op_ld_vary_32;
1247 break;
1248 default:
1249 unreachable("Attempted to load unknown type");
1250 break;
1251 }
1252
1253 emit_mir_instruction(ctx, ins);
1254 }
1255
1256 static void
1257 emit_attr_read(
1258 compiler_context *ctx,
1259 unsigned dest, unsigned offset,
1260 unsigned nr_comp, nir_alu_type t)
1261 {
1262 midgard_instruction ins = m_ld_attr_32(dest, offset);
1263 ins.load_store.arg_1 = 0x1E;
1264 ins.load_store.arg_2 = 0x1E;
1265 ins.mask = mask_of(nr_comp);
1266
1267 /* Use the type appropriate load */
1268 switch (t) {
1269 case nir_type_uint:
1270 case nir_type_bool:
1271 ins.load_store.op = midgard_op_ld_attr_32u;
1272 break;
1273 case nir_type_int:
1274 ins.load_store.op = midgard_op_ld_attr_32i;
1275 break;
1276 case nir_type_float:
1277 ins.load_store.op = midgard_op_ld_attr_32;
1278 break;
1279 default:
1280 unreachable("Attempted to load unknown type");
1281 break;
1282 }
1283
1284 emit_mir_instruction(ctx, ins);
1285 }
1286
1287 static void
1288 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1289 unsigned nr_components, unsigned offset)
1290 {
1291 nir_dest nir_dest;
1292
1293 /* Figure out which uniform this is */
1294 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1295 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1296
1297 unsigned dest = nir_dest_index(&nir_dest);
1298
1299 /* Sysvals are prefix uniforms */
1300 unsigned uniform = ((uintptr_t) val) - 1;
1301
1302 /* Emit the read itself -- this is never indirect */
1303 midgard_instruction *ins =
1304 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1305
1306 ins->mask = mask_of(nr_components);
1307 }
1308
1309 static unsigned
1310 compute_builtin_arg(nir_op op)
1311 {
1312 switch (op) {
1313 case nir_intrinsic_load_work_group_id:
1314 return 0x14;
1315 case nir_intrinsic_load_local_invocation_id:
1316 return 0x10;
1317 default:
1318 unreachable("Invalid compute paramater loaded");
1319 }
1320 }
1321
1322 static void
1323 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1324 {
1325 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1326
1327 midgard_instruction *br = ctx->writeout_branch[rt];
1328
1329 assert(!br);
1330
1331 emit_explicit_constant(ctx, src, src);
1332
1333 struct midgard_instruction ins =
1334 v_branch(false, false);
1335
1336 ins.writeout = true;
1337
1338 /* Add dependencies */
1339 ins.src[0] = src;
1340 ins.src_types[0] = nir_type_uint32;
1341 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1342 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1343
1344 /* Emit the branch */
1345 br = emit_mir_instruction(ctx, ins);
1346 schedule_barrier(ctx);
1347 ctx->writeout_branch[rt] = br;
1348
1349 /* Push our current location = current block count - 1 = where we'll
1350 * jump to. Maybe a bit too clever for my own good */
1351
1352 br->branch.target_block = ctx->block_count - 1;
1353 }
1354
1355 static void
1356 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1357 {
1358 unsigned reg = nir_dest_index(&instr->dest);
1359 midgard_instruction ins = m_ld_compute_id(reg, 0);
1360 ins.mask = mask_of(3);
1361 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1362 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1363 emit_mir_instruction(ctx, ins);
1364 }
1365
1366 static unsigned
1367 vertex_builtin_arg(nir_op op)
1368 {
1369 switch (op) {
1370 case nir_intrinsic_load_vertex_id:
1371 return PAN_VERTEX_ID;
1372 case nir_intrinsic_load_instance_id:
1373 return PAN_INSTANCE_ID;
1374 default:
1375 unreachable("Invalid vertex builtin");
1376 }
1377 }
1378
1379 static void
1380 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1381 {
1382 unsigned reg = nir_dest_index(&instr->dest);
1383 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1384 }
1385
1386 static void
1387 emit_control_barrier(compiler_context *ctx)
1388 {
1389 midgard_instruction ins = {
1390 .type = TAG_TEXTURE_4,
1391 .src = { ~0, ~0, ~0, ~0 },
1392 .texture = {
1393 .op = TEXTURE_OP_BARRIER,
1394
1395 /* TODO: optimize */
1396 .barrier_buffer = 1,
1397 .barrier_shared = 1
1398 }
1399 };
1400
1401 emit_mir_instruction(ctx, ins);
1402 }
1403
1404 static const nir_variable *
1405 search_var(struct exec_list *vars, unsigned driver_loc)
1406 {
1407 nir_foreach_variable(var, vars) {
1408 if (var->data.driver_location == driver_loc)
1409 return var;
1410 }
1411
1412 return NULL;
1413 }
1414
1415 static unsigned
1416 mir_get_branch_cond(nir_src *src, bool *invert)
1417 {
1418 /* Wrap it. No swizzle since it's a scalar */
1419
1420 nir_alu_src alu = {
1421 .src = *src
1422 };
1423
1424 *invert = pan_has_source_mod(&alu, nir_op_inot);
1425 return nir_src_index(NULL, &alu.src);
1426 }
1427
1428 static void
1429 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1430 {
1431 unsigned offset = 0, reg;
1432
1433 switch (instr->intrinsic) {
1434 case nir_intrinsic_discard_if:
1435 case nir_intrinsic_discard: {
1436 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1437 struct midgard_instruction discard = v_branch(conditional, false);
1438 discard.branch.target_type = TARGET_DISCARD;
1439
1440 if (conditional) {
1441 discard.src[0] = mir_get_branch_cond(&instr->src[0],
1442 &discard.branch.invert_conditional);
1443 discard.src_types[0] = nir_type_uint32;
1444 }
1445
1446 emit_mir_instruction(ctx, discard);
1447 schedule_barrier(ctx);
1448
1449 break;
1450 }
1451
1452 case nir_intrinsic_load_uniform:
1453 case nir_intrinsic_load_ubo:
1454 case nir_intrinsic_load_global:
1455 case nir_intrinsic_load_shared:
1456 case nir_intrinsic_load_input:
1457 case nir_intrinsic_load_interpolated_input: {
1458 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1459 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1460 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1461 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1462 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1463 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1464
1465 /* Get the base type of the intrinsic */
1466 /* TODO: Infer type? Does it matter? */
1467 nir_alu_type t =
1468 (is_ubo || is_global || is_shared) ? nir_type_uint :
1469 (is_interp) ? nir_type_float :
1470 nir_intrinsic_type(instr);
1471
1472 t = nir_alu_type_get_base_type(t);
1473
1474 if (!(is_ubo || is_global)) {
1475 offset = nir_intrinsic_base(instr);
1476 }
1477
1478 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1479
1480 nir_src *src_offset = nir_get_io_offset_src(instr);
1481
1482 bool direct = nir_src_is_const(*src_offset);
1483 nir_src *indirect_offset = direct ? NULL : src_offset;
1484
1485 if (direct)
1486 offset += nir_src_as_uint(*src_offset);
1487
1488 /* We may need to apply a fractional offset */
1489 int component = (is_flat || is_interp) ?
1490 nir_intrinsic_component(instr) : 0;
1491 reg = nir_dest_index(&instr->dest);
1492
1493 if (is_uniform && !ctx->is_blend) {
1494 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1495 } else if (is_ubo) {
1496 nir_src index = instr->src[0];
1497
1498 /* TODO: Is indirect block number possible? */
1499 assert(nir_src_is_const(index));
1500
1501 uint32_t uindex = nir_src_as_uint(index) + 1;
1502 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1503 } else if (is_global || is_shared) {
1504 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1505 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1506 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1507 } else if (ctx->is_blend) {
1508 /* For blend shaders, load the input color, which is
1509 * preloaded to r0 */
1510
1511 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1512 emit_mir_instruction(ctx, move);
1513 schedule_barrier(ctx);
1514 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1515 emit_attr_read(ctx, reg, offset, nr_comp, t);
1516 } else {
1517 DBG("Unknown load\n");
1518 assert(0);
1519 }
1520
1521 break;
1522 }
1523
1524 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1525 case nir_intrinsic_load_barycentric_pixel:
1526 case nir_intrinsic_load_barycentric_centroid:
1527 break;
1528
1529 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1530
1531 case nir_intrinsic_load_raw_output_pan:
1532 case nir_intrinsic_load_output_u8_as_fp16_pan:
1533 reg = nir_dest_index(&instr->dest);
1534 assert(ctx->is_blend);
1535
1536 /* T720 and below use different blend opcodes with slightly
1537 * different semantics than T760 and up */
1538
1539 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1540 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1541
1542 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1543 ld.load_store.op = old_blend ?
1544 midgard_op_ld_color_buffer_u8_as_fp16_old :
1545 midgard_op_ld_color_buffer_u8_as_fp16;
1546
1547 if (old_blend) {
1548 ld.load_store.address = 1;
1549 ld.load_store.arg_2 = 0x1E;
1550 }
1551
1552 for (unsigned c = 4; c < 16; ++c)
1553 ld.swizzle[0][c] = 0;
1554
1555 ld.dest_type = nir_type_float16;
1556 }
1557
1558 emit_mir_instruction(ctx, ld);
1559 break;
1560
1561 case nir_intrinsic_load_blend_const_color_rgba: {
1562 assert(ctx->is_blend);
1563 reg = nir_dest_index(&instr->dest);
1564
1565 /* Blend constants are embedded directly in the shader and
1566 * patched in, so we use some magic routing */
1567
1568 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1569 ins.has_constants = true;
1570 ins.has_blend_constant = true;
1571 emit_mir_instruction(ctx, ins);
1572 break;
1573 }
1574
1575 case nir_intrinsic_store_zs_output_pan: {
1576 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1577 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1578 MIDGARD_ZS_RT);
1579
1580 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1581
1582 if (!nir_intrinsic_component(instr))
1583 br->writeout_depth = true;
1584 if (nir_intrinsic_component(instr) ||
1585 instr->num_components)
1586 br->writeout_stencil = true;
1587 assert(br->writeout_depth | br->writeout_stencil);
1588 break;
1589 }
1590
1591 case nir_intrinsic_store_output:
1592 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1593
1594 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1595
1596 reg = nir_src_index(ctx, &instr->src[0]);
1597
1598 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1599 const nir_variable *var;
1600 enum midgard_rt_id rt;
1601
1602 var = search_var(&ctx->nir->outputs,
1603 nir_intrinsic_base(instr));
1604 assert(var);
1605 if (var->data.location == FRAG_RESULT_COLOR)
1606 rt = MIDGARD_COLOR_RT0;
1607 else if (var->data.location >= FRAG_RESULT_DATA0)
1608 rt = MIDGARD_COLOR_RT0 + var->data.location -
1609 FRAG_RESULT_DATA0;
1610 else
1611 assert(0);
1612
1613 emit_fragment_store(ctx, reg, rt);
1614 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1615 /* We should have been vectorized, though we don't
1616 * currently check that st_vary is emitted only once
1617 * per slot (this is relevant, since there's not a mask
1618 * parameter available on the store [set to 0 by the
1619 * blob]). We do respect the component by adjusting the
1620 * swizzle. If this is a constant source, we'll need to
1621 * emit that explicitly. */
1622
1623 emit_explicit_constant(ctx, reg, reg);
1624
1625 unsigned dst_component = nir_intrinsic_component(instr);
1626 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1627
1628 midgard_instruction st = m_st_vary_32(reg, offset);
1629 st.load_store.arg_1 = 0x9E;
1630 st.load_store.arg_2 = 0x1E;
1631
1632 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1633 case nir_type_uint:
1634 case nir_type_bool:
1635 st.load_store.op = midgard_op_st_vary_32u;
1636 break;
1637 case nir_type_int:
1638 st.load_store.op = midgard_op_st_vary_32i;
1639 break;
1640 case nir_type_float:
1641 st.load_store.op = midgard_op_st_vary_32;
1642 break;
1643 default:
1644 unreachable("Attempted to store unknown type");
1645 break;
1646 }
1647
1648 /* nir_intrinsic_component(store_intr) encodes the
1649 * destination component start. Source component offset
1650 * adjustment is taken care of in
1651 * install_registers_instr(), when offset_swizzle() is
1652 * called.
1653 */
1654 unsigned src_component = COMPONENT_X;
1655
1656 assert(nr_comp > 0);
1657 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1658 st.swizzle[0][i] = src_component;
1659 if (i >= dst_component && i < dst_component + nr_comp - 1)
1660 src_component++;
1661 }
1662
1663 emit_mir_instruction(ctx, st);
1664 } else {
1665 DBG("Unknown store\n");
1666 assert(0);
1667 }
1668
1669 break;
1670
1671 /* Special case of store_output for lowered blend shaders */
1672 case nir_intrinsic_store_raw_output_pan:
1673 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1674 reg = nir_src_index(ctx, &instr->src[0]);
1675
1676 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1677 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1678 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1679 * of:
1680 *
1681 * imov r0.xyzw, r0.xxxx
1682 */
1683
1684 unsigned expanded = make_compiler_temp(ctx);
1685
1686 midgard_instruction splatter = v_mov(reg, expanded);
1687
1688 for (unsigned c = 0; c < 16; ++c)
1689 splatter.swizzle[1][c] = 0;
1690
1691 emit_mir_instruction(ctx, splatter);
1692 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1693 } else
1694 emit_fragment_store(ctx, reg, ctx->blend_rt);
1695
1696 break;
1697
1698 case nir_intrinsic_store_global:
1699 case nir_intrinsic_store_shared:
1700 reg = nir_src_index(ctx, &instr->src[0]);
1701 emit_explicit_constant(ctx, reg, reg);
1702
1703 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1704 break;
1705
1706 case nir_intrinsic_load_ssbo_address:
1707 emit_sysval_read(ctx, &instr->instr, 1, 0);
1708 break;
1709
1710 case nir_intrinsic_get_buffer_size:
1711 emit_sysval_read(ctx, &instr->instr, 1, 8);
1712 break;
1713
1714 case nir_intrinsic_load_viewport_scale:
1715 case nir_intrinsic_load_viewport_offset:
1716 case nir_intrinsic_load_num_work_groups:
1717 case nir_intrinsic_load_sampler_lod_parameters_pan:
1718 emit_sysval_read(ctx, &instr->instr, 3, 0);
1719 break;
1720
1721 case nir_intrinsic_load_work_group_id:
1722 case nir_intrinsic_load_local_invocation_id:
1723 emit_compute_builtin(ctx, instr);
1724 break;
1725
1726 case nir_intrinsic_load_vertex_id:
1727 case nir_intrinsic_load_instance_id:
1728 emit_vertex_builtin(ctx, instr);
1729 break;
1730
1731 case nir_intrinsic_memory_barrier_buffer:
1732 case nir_intrinsic_memory_barrier_shared:
1733 break;
1734
1735 case nir_intrinsic_control_barrier:
1736 schedule_barrier(ctx);
1737 emit_control_barrier(ctx);
1738 schedule_barrier(ctx);
1739 break;
1740
1741 default:
1742 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1743 assert(0);
1744 break;
1745 }
1746 }
1747
1748 static unsigned
1749 midgard_tex_format(enum glsl_sampler_dim dim)
1750 {
1751 switch (dim) {
1752 case GLSL_SAMPLER_DIM_1D:
1753 case GLSL_SAMPLER_DIM_BUF:
1754 return MALI_TEX_1D;
1755
1756 case GLSL_SAMPLER_DIM_2D:
1757 case GLSL_SAMPLER_DIM_EXTERNAL:
1758 case GLSL_SAMPLER_DIM_RECT:
1759 return MALI_TEX_2D;
1760
1761 case GLSL_SAMPLER_DIM_3D:
1762 return MALI_TEX_3D;
1763
1764 case GLSL_SAMPLER_DIM_CUBE:
1765 return MALI_TEX_CUBE;
1766
1767 default:
1768 DBG("Unknown sampler dim type\n");
1769 assert(0);
1770 return 0;
1771 }
1772 }
1773
1774 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1775 * was successful */
1776
1777 static bool
1778 pan_attach_constant_bias(
1779 compiler_context *ctx,
1780 nir_src lod,
1781 midgard_texture_word *word)
1782 {
1783 /* To attach as constant, it has to *be* constant */
1784
1785 if (!nir_src_is_const(lod))
1786 return false;
1787
1788 float f = nir_src_as_float(lod);
1789
1790 /* Break into fixed-point */
1791 signed lod_int = f;
1792 float lod_frac = f - lod_int;
1793
1794 /* Carry over negative fractions */
1795 if (lod_frac < 0.0) {
1796 lod_int--;
1797 lod_frac += 1.0;
1798 }
1799
1800 /* Encode */
1801 word->bias = float_to_ubyte(lod_frac);
1802 word->bias_int = lod_int;
1803
1804 return true;
1805 }
1806
1807 static void
1808 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1809 unsigned midgard_texop)
1810 {
1811 /* TODO */
1812 //assert (!instr->sampler);
1813
1814 int texture_index = instr->texture_index;
1815 int sampler_index = texture_index;
1816
1817 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1818 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1819
1820 midgard_instruction ins = {
1821 .type = TAG_TEXTURE_4,
1822 .mask = 0xF,
1823 .dest = nir_dest_index(&instr->dest),
1824 .src = { ~0, ~0, ~0, ~0 },
1825 .dest_type = dest_type,
1826 .swizzle = SWIZZLE_IDENTITY_4,
1827 .texture = {
1828 .op = midgard_texop,
1829 .format = midgard_tex_format(instr->sampler_dim),
1830 .texture_handle = texture_index,
1831 .sampler_handle = sampler_index,
1832 .shadow = instr->is_shadow,
1833 }
1834 };
1835
1836 if (instr->is_shadow && !instr->is_new_style_shadow)
1837 for (int i = 0; i < 4; ++i)
1838 ins.swizzle[0][i] = COMPONENT_X;
1839
1840 /* We may need a temporary for the coordinate */
1841
1842 bool needs_temp_coord =
1843 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1844 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1845 (instr->is_shadow);
1846
1847 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1848
1849 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1850 int index = nir_src_index(ctx, &instr->src[i].src);
1851 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1852 unsigned sz = nir_src_bit_size(instr->src[i].src);
1853 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1854
1855 switch (instr->src[i].src_type) {
1856 case nir_tex_src_coord: {
1857 emit_explicit_constant(ctx, index, index);
1858
1859 unsigned coord_mask = mask_of(instr->coord_components);
1860
1861 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1862
1863 if (flip_zw)
1864 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1865
1866 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1867 /* texelFetch is undefined on samplerCube */
1868 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1869
1870 /* For cubemaps, we use a special ld/st op to
1871 * select the face and copy the xy into the
1872 * texture register */
1873
1874 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1875 ld.src[1] = index;
1876 ld.src_types[1] = T;
1877 ld.mask = 0x3; /* xy */
1878 ld.load_store.arg_1 = 0x20;
1879 ld.swizzle[1][3] = COMPONENT_X;
1880 emit_mir_instruction(ctx, ld);
1881
1882 /* xyzw -> xyxx */
1883 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1884 ins.swizzle[1][3] = COMPONENT_X;
1885 } else if (needs_temp_coord) {
1886 /* mov coord_temp, coords */
1887 midgard_instruction mov = v_mov(index, coords);
1888 mov.mask = coord_mask;
1889
1890 if (flip_zw)
1891 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1892
1893 emit_mir_instruction(ctx, mov);
1894 } else {
1895 coords = index;
1896 }
1897
1898 ins.src[1] = coords;
1899 ins.src_types[1] = T;
1900
1901 /* Texelfetch coordinates uses all four elements
1902 * (xyz/index) regardless of texture dimensionality,
1903 * which means it's necessary to zero the unused
1904 * components to keep everything happy */
1905
1906 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1907 /* mov index.zw, #0, or generalized */
1908 midgard_instruction mov =
1909 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1910 mov.has_constants = true;
1911 mov.mask = coord_mask ^ 0xF;
1912 emit_mir_instruction(ctx, mov);
1913 }
1914
1915 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1916 /* Array component in w but NIR wants it in z,
1917 * but if we have a temp coord we already fixed
1918 * that up */
1919
1920 if (nr_components == 3) {
1921 ins.swizzle[1][2] = COMPONENT_Z;
1922 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1923 } else if (nr_components == 2) {
1924 ins.swizzle[1][2] =
1925 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1926 ins.swizzle[1][3] = COMPONENT_X;
1927 } else
1928 unreachable("Invalid texture 2D components");
1929 }
1930
1931 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1932 /* We zeroed */
1933 ins.swizzle[1][2] = COMPONENT_Z;
1934 ins.swizzle[1][3] = COMPONENT_W;
1935 }
1936
1937 break;
1938 }
1939
1940 case nir_tex_src_bias:
1941 case nir_tex_src_lod: {
1942 /* Try as a constant if we can */
1943
1944 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1945 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1946 break;
1947
1948 ins.texture.lod_register = true;
1949 ins.src[2] = index;
1950 ins.src_types[2] = T;
1951
1952 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1953 ins.swizzle[2][c] = COMPONENT_X;
1954
1955 emit_explicit_constant(ctx, index, index);
1956
1957 break;
1958 };
1959
1960 case nir_tex_src_offset: {
1961 ins.texture.offset_register = true;
1962 ins.src[3] = index;
1963 ins.src_types[3] = T;
1964
1965 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1966 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
1967
1968 emit_explicit_constant(ctx, index, index);
1969 break;
1970 };
1971
1972 case nir_tex_src_comparator: {
1973 unsigned comp = COMPONENT_Z;
1974
1975 /* mov coord_temp.foo, coords */
1976 midgard_instruction mov = v_mov(index, coords);
1977 mov.mask = 1 << comp;
1978
1979 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
1980 mov.swizzle[1][i] = COMPONENT_X;
1981
1982 emit_mir_instruction(ctx, mov);
1983 break;
1984 }
1985
1986 default: {
1987 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
1988 assert(0);
1989 }
1990 }
1991 }
1992
1993 emit_mir_instruction(ctx, ins);
1994 }
1995
1996 static void
1997 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1998 {
1999 switch (instr->op) {
2000 case nir_texop_tex:
2001 case nir_texop_txb:
2002 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
2003 break;
2004 case nir_texop_txl:
2005 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
2006 break;
2007 case nir_texop_txf:
2008 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
2009 break;
2010 case nir_texop_txs:
2011 emit_sysval_read(ctx, &instr->instr, 4, 0);
2012 break;
2013 default: {
2014 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
2015 assert(0);
2016 }
2017 }
2018 }
2019
2020 static void
2021 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
2022 {
2023 switch (instr->type) {
2024 case nir_jump_break: {
2025 /* Emit a branch out of the loop */
2026 struct midgard_instruction br = v_branch(false, false);
2027 br.branch.target_type = TARGET_BREAK;
2028 br.branch.target_break = ctx->current_loop_depth;
2029 emit_mir_instruction(ctx, br);
2030 break;
2031 }
2032
2033 default:
2034 DBG("Unknown jump type %d\n", instr->type);
2035 break;
2036 }
2037 }
2038
2039 static void
2040 emit_instr(compiler_context *ctx, struct nir_instr *instr)
2041 {
2042 switch (instr->type) {
2043 case nir_instr_type_load_const:
2044 emit_load_const(ctx, nir_instr_as_load_const(instr));
2045 break;
2046
2047 case nir_instr_type_intrinsic:
2048 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2049 break;
2050
2051 case nir_instr_type_alu:
2052 emit_alu(ctx, nir_instr_as_alu(instr));
2053 break;
2054
2055 case nir_instr_type_tex:
2056 emit_tex(ctx, nir_instr_as_tex(instr));
2057 break;
2058
2059 case nir_instr_type_jump:
2060 emit_jump(ctx, nir_instr_as_jump(instr));
2061 break;
2062
2063 case nir_instr_type_ssa_undef:
2064 /* Spurious */
2065 break;
2066
2067 default:
2068 DBG("Unhandled instruction type\n");
2069 break;
2070 }
2071 }
2072
2073
2074 /* ALU instructions can inline or embed constants, which decreases register
2075 * pressure and saves space. */
2076
2077 #define CONDITIONAL_ATTACH(idx) { \
2078 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2079 \
2080 if (entry) { \
2081 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2082 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2083 } \
2084 }
2085
2086 static void
2087 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2088 {
2089 mir_foreach_instr_in_block(block, alu) {
2090 /* Other instructions cannot inline constants */
2091 if (alu->type != TAG_ALU_4) continue;
2092 if (alu->compact_branch) continue;
2093
2094 /* If there is already a constant here, we can do nothing */
2095 if (alu->has_constants) continue;
2096
2097 CONDITIONAL_ATTACH(0);
2098
2099 if (!alu->has_constants) {
2100 CONDITIONAL_ATTACH(1)
2101 } else if (!alu->inline_constant) {
2102 /* Corner case: _two_ vec4 constants, for instance with a
2103 * csel. For this case, we can only use a constant
2104 * register for one, we'll have to emit a move for the
2105 * other. */
2106
2107 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2108 unsigned scratch = make_compiler_temp(ctx);
2109
2110 if (entry) {
2111 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2112 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2113
2114 /* Set the source */
2115 alu->src[1] = scratch;
2116
2117 /* Inject us -before- the last instruction which set r31 */
2118 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2119 }
2120 }
2121 }
2122 }
2123
2124 /* Midgard supports two types of constants, embedded constants (128-bit) and
2125 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2126 * constants can be demoted to inline constants, for space savings and
2127 * sometimes a performance boost */
2128
2129 static void
2130 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2131 {
2132 mir_foreach_instr_in_block(block, ins) {
2133 if (!ins->has_constants) continue;
2134 if (ins->has_inline_constant) continue;
2135
2136 /* Blend constants must not be inlined by definition */
2137 if (ins->has_blend_constant) continue;
2138
2139 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2140 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2141 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2142
2143 if (!(is_16 || is_32))
2144 continue;
2145
2146 /* src1 cannot be an inline constant due to encoding
2147 * restrictions. So, if possible we try to flip the arguments
2148 * in that case */
2149
2150 int op = ins->alu.op;
2151
2152 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2153 alu_opcode_props[op].props & OP_COMMUTES) {
2154 mir_flip(ins);
2155 }
2156
2157 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2158 /* Component is from the swizzle. Take a nonzero component */
2159 assert(ins->mask);
2160 unsigned first_comp = ffs(ins->mask) - 1;
2161 unsigned component = ins->swizzle[1][first_comp];
2162
2163 /* Scale constant appropriately, if we can legally */
2164 uint16_t scaled_constant = 0;
2165
2166 if (is_16) {
2167 scaled_constant = ins->constants.u16[component];
2168 } else if (midgard_is_integer_op(op)) {
2169 scaled_constant = ins->constants.u32[component];
2170
2171 /* Constant overflow after resize */
2172 if (scaled_constant != ins->constants.u32[component])
2173 continue;
2174 } else {
2175 float original = ins->constants.f32[component];
2176 scaled_constant = _mesa_float_to_half(original);
2177
2178 /* Check for loss of precision. If this is
2179 * mediump, we don't care, but for a highp
2180 * shader, we need to pay attention. NIR
2181 * doesn't yet tell us which mode we're in!
2182 * Practically this prevents most constants
2183 * from being inlined, sadly. */
2184
2185 float fp32 = _mesa_half_to_float(scaled_constant);
2186
2187 if (fp32 != original)
2188 continue;
2189 }
2190
2191 /* Should've been const folded */
2192 if (ins->src_abs[1] || ins->src_neg[1])
2193 continue;
2194
2195 /* Make sure that the constant is not itself a vector
2196 * by checking if all accessed values are the same. */
2197
2198 const midgard_constants *cons = &ins->constants;
2199 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2200
2201 bool is_vector = false;
2202 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2203
2204 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2205 /* We only care if this component is actually used */
2206 if (!(mask & (1 << c)))
2207 continue;
2208
2209 uint32_t test = is_16 ?
2210 cons->u16[ins->swizzle[1][c]] :
2211 cons->u32[ins->swizzle[1][c]];
2212
2213 if (test != value) {
2214 is_vector = true;
2215 break;
2216 }
2217 }
2218
2219 if (is_vector)
2220 continue;
2221
2222 /* Get rid of the embedded constant */
2223 ins->has_constants = false;
2224 ins->src[1] = ~0;
2225 ins->has_inline_constant = true;
2226 ins->inline_constant = scaled_constant;
2227 }
2228 }
2229 }
2230
2231 /* Dead code elimination for branches at the end of a block - only one branch
2232 * per block is legal semantically */
2233
2234 static void
2235 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2236 {
2237 bool branched = false;
2238
2239 mir_foreach_instr_in_block_safe(block, ins) {
2240 if (!midgard_is_branch_unit(ins->unit)) continue;
2241
2242 if (branched)
2243 mir_remove_instruction(ins);
2244
2245 branched = true;
2246 }
2247 }
2248
2249 static unsigned
2250 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2251 {
2252 /* Loop to ourselves */
2253 midgard_instruction *br = ctx->writeout_branch[rt];
2254 struct midgard_instruction ins = v_branch(false, false);
2255 ins.writeout = true;
2256 ins.writeout_depth = br->writeout_depth;
2257 ins.writeout_stencil = br->writeout_stencil;
2258 ins.branch.target_block = ctx->block_count - 1;
2259 ins.constants.u32[0] = br->constants.u32[0];
2260 emit_mir_instruction(ctx, ins);
2261
2262 ctx->current_block->epilogue = true;
2263 schedule_barrier(ctx);
2264 return ins.branch.target_block;
2265 }
2266
2267 static midgard_block *
2268 emit_block(compiler_context *ctx, nir_block *block)
2269 {
2270 midgard_block *this_block = ctx->after_block;
2271 ctx->after_block = NULL;
2272
2273 if (!this_block)
2274 this_block = create_empty_block(ctx);
2275
2276 list_addtail(&this_block->base.link, &ctx->blocks);
2277
2278 this_block->scheduled = false;
2279 ++ctx->block_count;
2280
2281 /* Set up current block */
2282 list_inithead(&this_block->base.instructions);
2283 ctx->current_block = this_block;
2284
2285 nir_foreach_instr(instr, block) {
2286 emit_instr(ctx, instr);
2287 ++ctx->instruction_count;
2288 }
2289
2290 return this_block;
2291 }
2292
2293 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2294
2295 static void
2296 emit_if(struct compiler_context *ctx, nir_if *nif)
2297 {
2298 midgard_block *before_block = ctx->current_block;
2299
2300 /* Speculatively emit the branch, but we can't fill it in until later */
2301 bool inv = false;
2302 EMIT(branch, true, true);
2303 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2304 then_branch->src[0] = mir_get_branch_cond(&nif->condition, &inv);
2305 then_branch->src_types[0] = nir_type_uint32;
2306 then_branch->branch.invert_conditional = !inv;
2307
2308 /* Emit the two subblocks. */
2309 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2310 midgard_block *end_then_block = ctx->current_block;
2311
2312 /* Emit a jump from the end of the then block to the end of the else */
2313 EMIT(branch, false, false);
2314 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2315
2316 /* Emit second block, and check if it's empty */
2317
2318 int else_idx = ctx->block_count;
2319 int count_in = ctx->instruction_count;
2320 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2321 midgard_block *end_else_block = ctx->current_block;
2322 int after_else_idx = ctx->block_count;
2323
2324 /* Now that we have the subblocks emitted, fix up the branches */
2325
2326 assert(then_block);
2327 assert(else_block);
2328
2329 if (ctx->instruction_count == count_in) {
2330 /* The else block is empty, so don't emit an exit jump */
2331 mir_remove_instruction(then_exit);
2332 then_branch->branch.target_block = after_else_idx;
2333 } else {
2334 then_branch->branch.target_block = else_idx;
2335 then_exit->branch.target_block = after_else_idx;
2336 }
2337
2338 /* Wire up the successors */
2339
2340 ctx->after_block = create_empty_block(ctx);
2341
2342 pan_block_add_successor(&before_block->base, &then_block->base);
2343 pan_block_add_successor(&before_block->base, &else_block->base);
2344
2345 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2346 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2347 }
2348
2349 static void
2350 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2351 {
2352 /* Remember where we are */
2353 midgard_block *start_block = ctx->current_block;
2354
2355 /* Allocate a loop number, growing the current inner loop depth */
2356 int loop_idx = ++ctx->current_loop_depth;
2357
2358 /* Get index from before the body so we can loop back later */
2359 int start_idx = ctx->block_count;
2360
2361 /* Emit the body itself */
2362 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2363
2364 /* Branch back to loop back */
2365 struct midgard_instruction br_back = v_branch(false, false);
2366 br_back.branch.target_block = start_idx;
2367 emit_mir_instruction(ctx, br_back);
2368
2369 /* Mark down that branch in the graph. */
2370 pan_block_add_successor(&start_block->base, &loop_block->base);
2371 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2372
2373 /* Find the index of the block about to follow us (note: we don't add
2374 * one; blocks are 0-indexed so we get a fencepost problem) */
2375 int break_block_idx = ctx->block_count;
2376
2377 /* Fix up the break statements we emitted to point to the right place,
2378 * now that we can allocate a block number for them */
2379 ctx->after_block = create_empty_block(ctx);
2380
2381 mir_foreach_block_from(ctx, start_block, _block) {
2382 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2383 if (ins->type != TAG_ALU_4) continue;
2384 if (!ins->compact_branch) continue;
2385
2386 /* We found a branch -- check the type to see if we need to do anything */
2387 if (ins->branch.target_type != TARGET_BREAK) continue;
2388
2389 /* It's a break! Check if it's our break */
2390 if (ins->branch.target_break != loop_idx) continue;
2391
2392 /* Okay, cool, we're breaking out of this loop.
2393 * Rewrite from a break to a goto */
2394
2395 ins->branch.target_type = TARGET_GOTO;
2396 ins->branch.target_block = break_block_idx;
2397
2398 pan_block_add_successor(_block, &ctx->after_block->base);
2399 }
2400 }
2401
2402 /* Now that we've finished emitting the loop, free up the depth again
2403 * so we play nice with recursion amid nested loops */
2404 --ctx->current_loop_depth;
2405
2406 /* Dump loop stats */
2407 ++ctx->loop_count;
2408 }
2409
2410 static midgard_block *
2411 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2412 {
2413 midgard_block *start_block = NULL;
2414
2415 foreach_list_typed(nir_cf_node, node, node, list) {
2416 switch (node->type) {
2417 case nir_cf_node_block: {
2418 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2419
2420 if (!start_block)
2421 start_block = block;
2422
2423 break;
2424 }
2425
2426 case nir_cf_node_if:
2427 emit_if(ctx, nir_cf_node_as_if(node));
2428 break;
2429
2430 case nir_cf_node_loop:
2431 emit_loop(ctx, nir_cf_node_as_loop(node));
2432 break;
2433
2434 case nir_cf_node_function:
2435 assert(0);
2436 break;
2437 }
2438 }
2439
2440 return start_block;
2441 }
2442
2443 /* Due to lookahead, we need to report the first tag executed in the command
2444 * stream and in branch targets. An initial block might be empty, so iterate
2445 * until we find one that 'works' */
2446
2447 static unsigned
2448 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2449 {
2450 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2451
2452 mir_foreach_block_from(ctx, initial_block, _v) {
2453 midgard_block *v = (midgard_block *) _v;
2454 if (v->quadword_count) {
2455 midgard_bundle *initial_bundle =
2456 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2457
2458 return initial_bundle->tag;
2459 }
2460 }
2461
2462 /* Default to a tag 1 which will break from the shader, in case we jump
2463 * to the exit block (i.e. `return` in a compute shader) */
2464
2465 return 1;
2466 }
2467
2468 /* For each fragment writeout instruction, generate a writeout loop to
2469 * associate with it */
2470
2471 static void
2472 mir_add_writeout_loops(compiler_context *ctx)
2473 {
2474 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2475 midgard_instruction *br = ctx->writeout_branch[rt];
2476 if (!br) continue;
2477
2478 unsigned popped = br->branch.target_block;
2479 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2480 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2481 br->branch.target_type = TARGET_GOTO;
2482
2483 /* If we have more RTs, we'll need to restore back after our
2484 * loop terminates */
2485
2486 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2487 midgard_instruction uncond = v_branch(false, false);
2488 uncond.branch.target_block = popped;
2489 uncond.branch.target_type = TARGET_GOTO;
2490 emit_mir_instruction(ctx, uncond);
2491 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2492 schedule_barrier(ctx);
2493 } else {
2494 /* We're last, so we can terminate here */
2495 br->last_writeout = true;
2496 }
2497 }
2498 }
2499
2500 int
2501 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2502 {
2503 struct util_dynarray *compiled = &program->compiled;
2504
2505 midgard_debug = debug_get_option_midgard_debug();
2506
2507 /* TODO: Bound against what? */
2508 compiler_context *ctx = rzalloc(NULL, compiler_context);
2509
2510 ctx->nir = nir;
2511 ctx->stage = nir->info.stage;
2512 ctx->is_blend = is_blend;
2513 ctx->alpha_ref = program->alpha_ref;
2514 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2515 ctx->quirks = midgard_get_quirks(gpu_id);
2516
2517 /* Start off with a safe cutoff, allowing usage of all 16 work
2518 * registers. Later, we'll promote uniform reads to uniform registers
2519 * if we determine it is beneficial to do so */
2520 ctx->uniform_cutoff = 8;
2521
2522 /* Initialize at a global (not block) level hash tables */
2523
2524 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2525 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2526
2527 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2528 * (so we don't accidentally duplicate the epilogue since mesa/st has
2529 * messed with our I/O quite a bit already) */
2530
2531 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2532
2533 if (ctx->stage == MESA_SHADER_VERTEX) {
2534 NIR_PASS_V(nir, nir_lower_viewport_transform);
2535 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2536 }
2537
2538 NIR_PASS_V(nir, nir_lower_var_copies);
2539 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2540 NIR_PASS_V(nir, nir_split_var_copies);
2541 NIR_PASS_V(nir, nir_lower_var_copies);
2542 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2543 NIR_PASS_V(nir, nir_lower_var_copies);
2544 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2545
2546 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2547 NIR_PASS_V(nir, nir_lower_ssbo);
2548 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2549
2550 /* Optimisation passes */
2551
2552 optimise_nir(nir, ctx->quirks);
2553
2554 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2555 nir_print_shader(nir, stdout);
2556 }
2557
2558 /* Assign sysvals and counts, now that we're sure
2559 * (post-optimisation) */
2560
2561 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2562 program->sysval_count = ctx->sysvals.sysval_count;
2563 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2564
2565 nir_foreach_function(func, nir) {
2566 if (!func->impl)
2567 continue;
2568
2569 list_inithead(&ctx->blocks);
2570 ctx->block_count = 0;
2571 ctx->func = func;
2572 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
2573
2574 emit_cf_list(ctx, &func->impl->body);
2575 free(ctx->already_emitted);
2576 break; /* TODO: Multi-function shaders */
2577 }
2578
2579 util_dynarray_init(compiled, NULL);
2580
2581 /* Per-block lowering before opts */
2582
2583 mir_foreach_block(ctx, _block) {
2584 midgard_block *block = (midgard_block *) _block;
2585 inline_alu_constants(ctx, block);
2586 embedded_to_inline_constant(ctx, block);
2587 }
2588 /* MIR-level optimizations */
2589
2590 bool progress = false;
2591
2592 do {
2593 progress = false;
2594 progress |= midgard_opt_dead_code_eliminate(ctx);
2595
2596 mir_foreach_block(ctx, _block) {
2597 midgard_block *block = (midgard_block *) _block;
2598 progress |= midgard_opt_copy_prop(ctx, block);
2599 progress |= midgard_opt_combine_projection(ctx, block);
2600 progress |= midgard_opt_varying_projection(ctx, block);
2601 }
2602 } while (progress);
2603
2604 mir_foreach_block(ctx, _block) {
2605 midgard_block *block = (midgard_block *) _block;
2606 midgard_lower_derivatives(ctx, block);
2607 midgard_cull_dead_branch(ctx, block);
2608 }
2609
2610 if (ctx->stage == MESA_SHADER_FRAGMENT)
2611 mir_add_writeout_loops(ctx);
2612
2613 /* Analyze now that the code is known but before scheduling creates
2614 * pipeline registers which are harder to track */
2615 mir_analyze_helper_terminate(ctx);
2616 mir_analyze_helper_requirements(ctx);
2617
2618 /* Schedule! */
2619 midgard_schedule_program(ctx);
2620 mir_ra(ctx);
2621
2622 /* Now that all the bundles are scheduled and we can calculate block
2623 * sizes, emit actual branch instructions rather than placeholders */
2624
2625 int br_block_idx = 0;
2626
2627 mir_foreach_block(ctx, _block) {
2628 midgard_block *block = (midgard_block *) _block;
2629 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2630 for (int c = 0; c < bundle->instruction_count; ++c) {
2631 midgard_instruction *ins = bundle->instructions[c];
2632
2633 if (!midgard_is_branch_unit(ins->unit)) continue;
2634
2635 /* Parse some basic branch info */
2636 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2637 bool is_conditional = ins->branch.conditional;
2638 bool is_inverted = ins->branch.invert_conditional;
2639 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2640 bool is_writeout = ins->writeout;
2641
2642 /* Determine the block we're jumping to */
2643 int target_number = ins->branch.target_block;
2644
2645 /* Report the destination tag */
2646 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2647
2648 /* Count up the number of quadwords we're
2649 * jumping over = number of quadwords until
2650 * (br_block_idx, target_number) */
2651
2652 int quadword_offset = 0;
2653
2654 if (is_discard) {
2655 /* Ignored */
2656 } else if (target_number > br_block_idx) {
2657 /* Jump forward */
2658
2659 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2660 midgard_block *blk = mir_get_block(ctx, idx);
2661 assert(blk);
2662
2663 quadword_offset += blk->quadword_count;
2664 }
2665 } else {
2666 /* Jump backwards */
2667
2668 for (int idx = br_block_idx; idx >= target_number; --idx) {
2669 midgard_block *blk = mir_get_block(ctx, idx);
2670 assert(blk);
2671
2672 quadword_offset -= blk->quadword_count;
2673 }
2674 }
2675
2676 /* Unconditional extended branches (far jumps)
2677 * have issues, so we always use a conditional
2678 * branch, setting the condition to always for
2679 * unconditional. For compact unconditional
2680 * branches, cond isn't used so it doesn't
2681 * matter what we pick. */
2682
2683 midgard_condition cond =
2684 !is_conditional ? midgard_condition_always :
2685 is_inverted ? midgard_condition_false :
2686 midgard_condition_true;
2687
2688 midgard_jmp_writeout_op op =
2689 is_discard ? midgard_jmp_writeout_op_discard :
2690 is_writeout ? midgard_jmp_writeout_op_writeout :
2691 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2692 midgard_jmp_writeout_op_branch_cond;
2693
2694 if (!is_compact) {
2695 midgard_branch_extended branch =
2696 midgard_create_branch_extended(
2697 cond, op,
2698 dest_tag,
2699 quadword_offset);
2700
2701 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2702 } else if (is_conditional || is_discard) {
2703 midgard_branch_cond branch = {
2704 .op = op,
2705 .dest_tag = dest_tag,
2706 .offset = quadword_offset,
2707 .cond = cond
2708 };
2709
2710 assert(branch.offset == quadword_offset);
2711
2712 memcpy(&ins->br_compact, &branch, sizeof(branch));
2713 } else {
2714 assert(op == midgard_jmp_writeout_op_branch_uncond);
2715
2716 midgard_branch_uncond branch = {
2717 .op = op,
2718 .dest_tag = dest_tag,
2719 .offset = quadword_offset,
2720 .unknown = 1
2721 };
2722
2723 assert(branch.offset == quadword_offset);
2724
2725 memcpy(&ins->br_compact, &branch, sizeof(branch));
2726 }
2727 }
2728 }
2729
2730 ++br_block_idx;
2731 }
2732
2733 /* Emit flat binary from the instruction arrays. Iterate each block in
2734 * sequence. Save instruction boundaries such that lookahead tags can
2735 * be assigned easily */
2736
2737 /* Cache _all_ bundles in source order for lookahead across failed branches */
2738
2739 int bundle_count = 0;
2740 mir_foreach_block(ctx, _block) {
2741 midgard_block *block = (midgard_block *) _block;
2742 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2743 }
2744 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2745 int bundle_idx = 0;
2746 mir_foreach_block(ctx, _block) {
2747 midgard_block *block = (midgard_block *) _block;
2748 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2749 source_order_bundles[bundle_idx++] = bundle;
2750 }
2751 }
2752
2753 int current_bundle = 0;
2754
2755 /* Midgard prefetches instruction types, so during emission we
2756 * need to lookahead. Unless this is the last instruction, in
2757 * which we return 1. */
2758
2759 mir_foreach_block(ctx, _block) {
2760 midgard_block *block = (midgard_block *) _block;
2761 mir_foreach_bundle_in_block(block, bundle) {
2762 int lookahead = 1;
2763
2764 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2765 lookahead = source_order_bundles[current_bundle + 1]->tag;
2766
2767 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2768 ++current_bundle;
2769 }
2770
2771 /* TODO: Free deeper */
2772 //util_dynarray_fini(&block->instructions);
2773 }
2774
2775 free(source_order_bundles);
2776
2777 /* Report the very first tag executed */
2778 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2779
2780 /* Deal with off-by-one related to the fencepost problem */
2781 program->work_register_count = ctx->work_registers + 1;
2782 program->uniform_cutoff = ctx->uniform_cutoff;
2783
2784 program->blend_patch_offset = ctx->blend_constant_offset;
2785 program->tls_size = ctx->tls_size;
2786
2787 if (midgard_debug & MIDGARD_DBG_SHADERS)
2788 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2789
2790 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2791 unsigned nr_bundles = 0, nr_ins = 0;
2792
2793 /* Count instructions and bundles */
2794
2795 mir_foreach_block(ctx, _block) {
2796 midgard_block *block = (midgard_block *) _block;
2797 nr_bundles += util_dynarray_num_elements(
2798 &block->bundles, midgard_bundle);
2799
2800 mir_foreach_bundle_in_block(block, bun)
2801 nr_ins += bun->instruction_count;
2802 }
2803
2804 /* Calculate thread count. There are certain cutoffs by
2805 * register count for thread count */
2806
2807 unsigned nr_registers = program->work_register_count;
2808
2809 unsigned nr_threads =
2810 (nr_registers <= 4) ? 4 :
2811 (nr_registers <= 8) ? 2 :
2812 1;
2813
2814 /* Dump stats */
2815
2816 fprintf(stderr, "shader%d - %s shader: "
2817 "%u inst, %u bundles, %u quadwords, "
2818 "%u registers, %u threads, %u loops, "
2819 "%u:%u spills:fills\n",
2820 SHADER_DB_COUNT++,
2821 gl_shader_stage_name(ctx->stage),
2822 nr_ins, nr_bundles, ctx->quadword_count,
2823 nr_registers, nr_threads,
2824 ctx->loop_count,
2825 ctx->spills, ctx->fills);
2826 }
2827
2828 ralloc_free(ctx);
2829
2830 return 0;
2831 }