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[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 } else { \
121 i.dest = ssa; \
122 i.dest_type = T; \
123 } \
124 return i; \
125 }
126
127 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
128 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
129
130 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
131 * the corresponding Midgard source */
132
133 static midgard_vector_alu_src
134 vector_alu_modifiers(nir_alu_src *src, bool is_int, unsigned broadcast_count,
135 bool half, bool sext)
136 {
137 /* Figure out how many components there are so we can adjust.
138 * Specifically we want to broadcast the last channel so things like
139 * ball2/3 work.
140 */
141
142 if (broadcast_count && src) {
143 uint8_t last_component = src->swizzle[broadcast_count - 1];
144
145 for (unsigned c = broadcast_count; c < NIR_MAX_VEC_COMPONENTS; ++c) {
146 src->swizzle[c] = last_component;
147 }
148 }
149
150 midgard_vector_alu_src alu_src = {
151 .rep_low = 0,
152 .rep_high = 0,
153 .half = half
154 };
155
156 if (is_int) {
157 alu_src.mod = midgard_int_normal;
158
159 /* Sign/zero-extend if needed */
160
161 if (half) {
162 alu_src.mod = sext ?
163 midgard_int_sign_extend
164 : midgard_int_zero_extend;
165 }
166
167 /* These should have been lowered away */
168 if (src)
169 assert(!(src->abs || src->negate));
170 } else {
171 if (src)
172 alu_src.mod = (src->abs << 0) | (src->negate << 1);
173 }
174
175 return alu_src;
176 }
177
178 M_LOAD(ld_attr_32, nir_type_uint32);
179 M_LOAD(ld_vary_32, nir_type_uint32);
180 M_LOAD(ld_ubo_int4, nir_type_uint32);
181 M_LOAD(ld_int4, nir_type_uint32);
182 M_STORE(st_int4, nir_type_uint32);
183 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
184 M_STORE(st_vary_32, nir_type_uint32);
185 M_LOAD(ld_cubemap_coords, nir_type_uint32);
186 M_LOAD(ld_compute_id, nir_type_uint32);
187
188 static midgard_instruction
189 v_branch(bool conditional, bool invert)
190 {
191 midgard_instruction ins = {
192 .type = TAG_ALU_4,
193 .unit = ALU_ENAB_BRANCH,
194 .compact_branch = true,
195 .branch = {
196 .conditional = conditional,
197 .invert_conditional = invert
198 },
199 .dest = ~0,
200 .src = { ~0, ~0, ~0, ~0 },
201 };
202
203 return ins;
204 }
205
206 static midgard_branch_extended
207 midgard_create_branch_extended( midgard_condition cond,
208 midgard_jmp_writeout_op op,
209 unsigned dest_tag,
210 signed quadword_offset)
211 {
212 /* The condition code is actually a LUT describing a function to
213 * combine multiple condition codes. However, we only support a single
214 * condition code at the moment, so we just duplicate over a bunch of
215 * times. */
216
217 uint16_t duplicated_cond =
218 (cond << 14) |
219 (cond << 12) |
220 (cond << 10) |
221 (cond << 8) |
222 (cond << 6) |
223 (cond << 4) |
224 (cond << 2) |
225 (cond << 0);
226
227 midgard_branch_extended branch = {
228 .op = op,
229 .dest_tag = dest_tag,
230 .offset = quadword_offset,
231 .cond = duplicated_cond
232 };
233
234 return branch;
235 }
236
237 static void
238 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
239 {
240 ins->has_constants = true;
241 memcpy(&ins->constants, constants, 16);
242 }
243
244 static int
245 glsl_type_size(const struct glsl_type *type, bool bindless)
246 {
247 return glsl_count_attribute_slots(type, false);
248 }
249
250 /* Lower fdot2 to a vector multiplication followed by channel addition */
251 static void
252 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
253 {
254 if (alu->op != nir_op_fdot2)
255 return;
256
257 b->cursor = nir_before_instr(&alu->instr);
258
259 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
260 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
261
262 nir_ssa_def *product = nir_fmul(b, src0, src1);
263
264 nir_ssa_def *sum = nir_fadd(b,
265 nir_channel(b, product, 0),
266 nir_channel(b, product, 1));
267
268 /* Replace the fdot2 with this sum */
269 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
270 }
271
272 static bool
273 midgard_nir_lower_fdot2(nir_shader *shader)
274 {
275 bool progress = false;
276
277 nir_foreach_function(function, shader) {
278 if (!function->impl) continue;
279
280 nir_builder _b;
281 nir_builder *b = &_b;
282 nir_builder_init(b, function->impl);
283
284 nir_foreach_block(block, function->impl) {
285 nir_foreach_instr_safe(instr, block) {
286 if (instr->type != nir_instr_type_alu) continue;
287
288 nir_alu_instr *alu = nir_instr_as_alu(instr);
289 midgard_nir_lower_fdot2_body(b, alu);
290
291 progress |= true;
292 }
293 }
294
295 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
296
297 }
298
299 return progress;
300 }
301
302 /* Midgard can't write depth and stencil separately. It has to happen in a
303 * single store operation containing both. Let's add a panfrost specific
304 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
305 * one.
306 */
307 static bool
308 midgard_nir_lower_zs_store(nir_shader *nir)
309 {
310 if (nir->info.stage != MESA_SHADER_FRAGMENT)
311 return false;
312
313 nir_variable *z_var = NULL, *s_var = NULL;
314
315 nir_foreach_variable(var, &nir->outputs) {
316 if (var->data.location == FRAG_RESULT_DEPTH)
317 z_var = var;
318 else if (var->data.location == FRAG_RESULT_STENCIL)
319 s_var = var;
320 }
321
322 if (!z_var && !s_var)
323 return false;
324
325 bool progress = false;
326
327 nir_foreach_function(function, nir) {
328 if (!function->impl) continue;
329
330 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
331
332 nir_foreach_block(block, function->impl) {
333 nir_foreach_instr_safe(instr, block) {
334 if (instr->type != nir_instr_type_intrinsic)
335 continue;
336
337 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
338 if (intr->intrinsic != nir_intrinsic_store_output)
339 continue;
340
341 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
342 assert(!z_store);
343 z_store = intr;
344 last_store = intr;
345 }
346
347 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
348 assert(!s_store);
349 s_store = intr;
350 last_store = intr;
351 }
352 }
353 }
354
355 if (!z_store && !s_store) continue;
356
357 nir_builder b;
358 nir_builder_init(&b, function->impl);
359
360 b.cursor = nir_before_instr(&last_store->instr);
361
362 nir_ssa_def *zs_store_src;
363
364 if (z_store && s_store) {
365 nir_ssa_def *srcs[2] = {
366 nir_ssa_for_src(&b, z_store->src[0], 1),
367 nir_ssa_for_src(&b, s_store->src[0], 1),
368 };
369
370 zs_store_src = nir_vec(&b, srcs, 2);
371 } else {
372 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
373 }
374
375 nir_intrinsic_instr *zs_store;
376
377 zs_store = nir_intrinsic_instr_create(b.shader,
378 nir_intrinsic_store_zs_output_pan);
379 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
380 zs_store->num_components = z_store && s_store ? 2 : 1;
381 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
382
383 /* Replace the Z and S store by a ZS store */
384 nir_builder_instr_insert(&b, &zs_store->instr);
385
386 if (z_store)
387 nir_instr_remove(&z_store->instr);
388
389 if (s_store)
390 nir_instr_remove(&s_store->instr);
391
392 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
393 progress = true;
394 }
395
396 return progress;
397 }
398
399 /* Flushes undefined values to zero */
400
401 static void
402 optimise_nir(nir_shader *nir, unsigned quirks)
403 {
404 bool progress;
405 unsigned lower_flrp =
406 (nir->options->lower_flrp16 ? 16 : 0) |
407 (nir->options->lower_flrp32 ? 32 : 0) |
408 (nir->options->lower_flrp64 ? 64 : 0);
409
410 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
411 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
412
413 nir_lower_tex_options lower_tex_options = {
414 .lower_txs_lod = true,
415 .lower_txp = ~0,
416 .lower_tex_without_implicit_lod =
417 (quirks & MIDGARD_EXPLICIT_LOD),
418
419 /* TODO: we have native gradient.. */
420 .lower_txd = true,
421 };
422
423 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
424
425 /* Must lower fdot2 after tex is lowered */
426 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
427
428 /* T720 is broken. */
429
430 if (quirks & MIDGARD_BROKEN_LOD)
431 NIR_PASS_V(nir, midgard_nir_lod_errata);
432
433 do {
434 progress = false;
435
436 NIR_PASS(progress, nir, nir_lower_var_copies);
437 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
438
439 NIR_PASS(progress, nir, nir_copy_prop);
440 NIR_PASS(progress, nir, nir_opt_remove_phis);
441 NIR_PASS(progress, nir, nir_opt_dce);
442 NIR_PASS(progress, nir, nir_opt_dead_cf);
443 NIR_PASS(progress, nir, nir_opt_cse);
444 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
445 NIR_PASS(progress, nir, nir_opt_algebraic);
446 NIR_PASS(progress, nir, nir_opt_constant_folding);
447
448 if (lower_flrp != 0) {
449 bool lower_flrp_progress = false;
450 NIR_PASS(lower_flrp_progress,
451 nir,
452 nir_lower_flrp,
453 lower_flrp,
454 false /* always_precise */,
455 nir->options->lower_ffma);
456 if (lower_flrp_progress) {
457 NIR_PASS(progress, nir,
458 nir_opt_constant_folding);
459 progress = true;
460 }
461
462 /* Nothing should rematerialize any flrps, so we only
463 * need to do this lowering once.
464 */
465 lower_flrp = 0;
466 }
467
468 NIR_PASS(progress, nir, nir_opt_undef);
469 NIR_PASS(progress, nir, nir_undef_to_zero);
470
471 NIR_PASS(progress, nir, nir_opt_loop_unroll,
472 nir_var_shader_in |
473 nir_var_shader_out |
474 nir_var_function_temp);
475
476 NIR_PASS(progress, nir, nir_opt_vectorize);
477 } while (progress);
478
479 /* Must be run at the end to prevent creation of fsin/fcos ops */
480 NIR_PASS(progress, nir, midgard_nir_scale_trig);
481
482 do {
483 progress = false;
484
485 NIR_PASS(progress, nir, nir_opt_dce);
486 NIR_PASS(progress, nir, nir_opt_algebraic);
487 NIR_PASS(progress, nir, nir_opt_constant_folding);
488 NIR_PASS(progress, nir, nir_copy_prop);
489 } while (progress);
490
491 NIR_PASS(progress, nir, nir_opt_algebraic_late);
492
493 /* We implement booleans as 32-bit 0/~0 */
494 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
495
496 /* Now that booleans are lowered, we can run out late opts */
497 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
498
499 /* Lower mods for float ops only. Integer ops don't support modifiers
500 * (saturate doesn't make sense on integers, neg/abs require dedicated
501 * instructions) */
502
503 NIR_PASS(progress, nir, nir_lower_to_source_mods, nir_lower_float_source_mods);
504 NIR_PASS(progress, nir, nir_copy_prop);
505 NIR_PASS(progress, nir, nir_opt_dce);
506
507 /* Take us out of SSA */
508 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
509 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
510
511 /* We are a vector architecture; write combine where possible */
512 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
513 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
514
515 NIR_PASS(progress, nir, nir_opt_dce);
516 }
517
518 /* Do not actually emit a load; instead, cache the constant for inlining */
519
520 static void
521 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
522 {
523 nir_ssa_def def = instr->def;
524
525 midgard_constants *consts = rzalloc(NULL, midgard_constants);
526
527 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
528
529 #define RAW_CONST_COPY(bits) \
530 nir_const_value_to_array(consts->u##bits, instr->value, \
531 instr->def.num_components, u##bits)
532
533 switch (instr->def.bit_size) {
534 case 64:
535 RAW_CONST_COPY(64);
536 break;
537 case 32:
538 RAW_CONST_COPY(32);
539 break;
540 case 16:
541 RAW_CONST_COPY(16);
542 break;
543 case 8:
544 RAW_CONST_COPY(8);
545 break;
546 default:
547 unreachable("Invalid bit_size for load_const instruction\n");
548 }
549
550 /* Shifted for SSA, +1 for off-by-one */
551 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
552 }
553
554 /* Normally constants are embedded implicitly, but for I/O and such we have to
555 * explicitly emit a move with the constant source */
556
557 static void
558 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
559 {
560 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
561
562 if (constant_value) {
563 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
564 attach_constants(ctx, &ins, constant_value, node + 1);
565 emit_mir_instruction(ctx, ins);
566 }
567 }
568
569 static bool
570 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
571 {
572 unsigned comp = src->swizzle[0];
573
574 for (unsigned c = 1; c < nr_components; ++c) {
575 if (src->swizzle[c] != comp)
576 return true;
577 }
578
579 return false;
580 }
581
582 #define ALU_CASE(nir, _op) \
583 case nir_op_##nir: \
584 op = midgard_alu_op_##_op; \
585 assert(src_bitsize == dst_bitsize); \
586 break;
587
588 #define ALU_CASE_BCAST(nir, _op, count) \
589 case nir_op_##nir: \
590 op = midgard_alu_op_##_op; \
591 broadcast_swizzle = count; \
592 assert(src_bitsize == dst_bitsize); \
593 break;
594 static bool
595 nir_is_fzero_constant(nir_src src)
596 {
597 if (!nir_src_is_const(src))
598 return false;
599
600 for (unsigned c = 0; c < nir_src_num_components(src); ++c) {
601 if (nir_src_comp_as_float(src, c) != 0.0)
602 return false;
603 }
604
605 return true;
606 }
607
608 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
609 * special treatment override this anyway. */
610
611 static midgard_reg_mode
612 reg_mode_for_nir(nir_alu_instr *instr)
613 {
614 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
615
616 switch (src_bitsize) {
617 case 8:
618 return midgard_reg_mode_8;
619 case 16:
620 return midgard_reg_mode_16;
621 case 32:
622 return midgard_reg_mode_32;
623 case 64:
624 return midgard_reg_mode_64;
625 default:
626 unreachable("Invalid bit size");
627 }
628 }
629
630 static void
631 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to)
632 {
633 unsigned bits = nir_src_bit_size(instr->src[i].src);
634
635 ins->src[to] = nir_src_index(NULL, &instr->src[i].src);
636 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
637 }
638
639 static void
640 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
641 {
642 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
643 * is handled elsewhere */
644
645 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
646 midgard_emit_derivatives(ctx, instr);
647 return;
648 }
649
650 bool is_ssa = instr->dest.dest.is_ssa;
651
652 unsigned nr_components = nir_dest_num_components(instr->dest.dest);
653 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
654 unsigned op = 0;
655
656 /* Number of components valid to check for the instruction (the rest
657 * will be forced to the last), or 0 to use as-is. Relevant as
658 * ball-type instructions have a channel count in NIR but are all vec4
659 * in Midgard */
660
661 unsigned broadcast_swizzle = 0;
662
663 /* What register mode should we operate in? */
664 midgard_reg_mode reg_mode =
665 reg_mode_for_nir(instr);
666
667 /* Do we need a destination override? Used for inline
668 * type conversion */
669
670 midgard_dest_override dest_override =
671 midgard_dest_override_none;
672
673 /* Should we use a smaller respective source and sign-extend? */
674
675 bool half_1 = false, sext_1 = false;
676 bool half_2 = false, sext_2 = false;
677
678 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
679 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
680
681 switch (instr->op) {
682 ALU_CASE(fadd, fadd);
683 ALU_CASE(fmul, fmul);
684 ALU_CASE(fmin, fmin);
685 ALU_CASE(fmax, fmax);
686 ALU_CASE(imin, imin);
687 ALU_CASE(imax, imax);
688 ALU_CASE(umin, umin);
689 ALU_CASE(umax, umax);
690 ALU_CASE(ffloor, ffloor);
691 ALU_CASE(fround_even, froundeven);
692 ALU_CASE(ftrunc, ftrunc);
693 ALU_CASE(fceil, fceil);
694 ALU_CASE(fdot3, fdot3);
695 ALU_CASE(fdot4, fdot4);
696 ALU_CASE(iadd, iadd);
697 ALU_CASE(isub, isub);
698 ALU_CASE(imul, imul);
699
700 /* Zero shoved as second-arg */
701 ALU_CASE(iabs, iabsdiff);
702
703 ALU_CASE(mov, imov);
704
705 ALU_CASE(feq32, feq);
706 ALU_CASE(fne32, fne);
707 ALU_CASE(flt32, flt);
708 ALU_CASE(ieq32, ieq);
709 ALU_CASE(ine32, ine);
710 ALU_CASE(ilt32, ilt);
711 ALU_CASE(ult32, ult);
712
713 /* We don't have a native b2f32 instruction. Instead, like many
714 * GPUs, we exploit booleans as 0/~0 for false/true, and
715 * correspondingly AND
716 * by 1.0 to do the type conversion. For the moment, prime us
717 * to emit:
718 *
719 * iand [whatever], #0
720 *
721 * At the end of emit_alu (as MIR), we'll fix-up the constant
722 */
723
724 ALU_CASE(b2f32, iand);
725 ALU_CASE(b2i32, iand);
726
727 /* Likewise, we don't have a dedicated f2b32 instruction, but
728 * we can do a "not equal to 0.0" test. */
729
730 ALU_CASE(f2b32, fne);
731 ALU_CASE(i2b32, ine);
732
733 ALU_CASE(frcp, frcp);
734 ALU_CASE(frsq, frsqrt);
735 ALU_CASE(fsqrt, fsqrt);
736 ALU_CASE(fexp2, fexp2);
737 ALU_CASE(flog2, flog2);
738
739 ALU_CASE(f2i64, f2i_rtz);
740 ALU_CASE(f2u64, f2u_rtz);
741 ALU_CASE(i2f64, i2f_rtz);
742 ALU_CASE(u2f64, u2f_rtz);
743
744 ALU_CASE(f2i32, f2i_rtz);
745 ALU_CASE(f2u32, f2u_rtz);
746 ALU_CASE(i2f32, i2f_rtz);
747 ALU_CASE(u2f32, u2f_rtz);
748
749 ALU_CASE(f2i16, f2i_rtz);
750 ALU_CASE(f2u16, f2u_rtz);
751 ALU_CASE(i2f16, i2f_rtz);
752 ALU_CASE(u2f16, u2f_rtz);
753
754 ALU_CASE(fsin, fsin);
755 ALU_CASE(fcos, fcos);
756
757 /* We'll set invert */
758 ALU_CASE(inot, imov);
759 ALU_CASE(iand, iand);
760 ALU_CASE(ior, ior);
761 ALU_CASE(ixor, ixor);
762 ALU_CASE(ishl, ishl);
763 ALU_CASE(ishr, iasr);
764 ALU_CASE(ushr, ilsr);
765
766 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
767 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
768 ALU_CASE(b32all_fequal4, fball_eq);
769
770 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
771 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
772 ALU_CASE(b32any_fnequal4, fbany_neq);
773
774 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
775 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
776 ALU_CASE(b32all_iequal4, iball_eq);
777
778 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
779 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
780 ALU_CASE(b32any_inequal4, ibany_neq);
781
782 /* Source mods will be shoved in later */
783 ALU_CASE(fabs, fmov);
784 ALU_CASE(fneg, fmov);
785 ALU_CASE(fsat, fmov);
786
787 /* For size conversion, we use a move. Ideally though we would squash
788 * these ops together; maybe that has to happen after in NIR as part of
789 * propagation...? An earlier algebraic pass ensured we step down by
790 * only / exactly one size. If stepping down, we use a dest override to
791 * reduce the size; if stepping up, we use a larger-sized move with a
792 * half source and a sign/zero-extension modifier */
793
794 case nir_op_i2i8:
795 case nir_op_i2i16:
796 case nir_op_i2i32:
797 case nir_op_i2i64:
798 /* If we end up upscale, we'll need a sign-extend on the
799 * operand (the second argument) */
800
801 sext_2 = true;
802 /* fallthrough */
803 case nir_op_u2u8:
804 case nir_op_u2u16:
805 case nir_op_u2u32:
806 case nir_op_u2u64:
807 case nir_op_f2f16:
808 case nir_op_f2f32:
809 case nir_op_f2f64: {
810 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
811 instr->op == nir_op_f2f64)
812 op = midgard_alu_op_fmov;
813 else
814 op = midgard_alu_op_imov;
815
816 if (dst_bitsize == (src_bitsize * 2)) {
817 /* Converting up */
818 half_2 = true;
819
820 /* Use a greater register mode */
821 reg_mode++;
822 } else if (src_bitsize == (dst_bitsize * 2)) {
823 /* Converting down */
824 dest_override = midgard_dest_override_lower;
825 }
826
827 break;
828 }
829
830 /* For greater-or-equal, we lower to less-or-equal and flip the
831 * arguments */
832
833 case nir_op_fge:
834 case nir_op_fge32:
835 case nir_op_ige32:
836 case nir_op_uge32: {
837 op =
838 instr->op == nir_op_fge ? midgard_alu_op_fle :
839 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
840 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
841 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
842 0;
843
844 /* Swap via temporary */
845 nir_alu_src temp = instr->src[1];
846 instr->src[1] = instr->src[0];
847 instr->src[0] = temp;
848
849 break;
850 }
851
852 case nir_op_b32csel: {
853 /* Midgard features both fcsel and icsel, depending on
854 * the type of the arguments/output. However, as long
855 * as we're careful we can _always_ use icsel and
856 * _never_ need fcsel, since the latter does additional
857 * floating-point-specific processing whereas the
858 * former just moves bits on the wire. It's not obvious
859 * why these are separate opcodes, save for the ability
860 * to do things like sat/pos/abs/neg for free */
861
862 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
863 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
864
865 /* The condition is the first argument; move the other
866 * arguments up one to be a binary instruction for
867 * Midgard with the condition last */
868
869 nir_alu_src temp = instr->src[2];
870
871 instr->src[2] = instr->src[0];
872 instr->src[0] = instr->src[1];
873 instr->src[1] = temp;
874
875 break;
876 }
877
878 default:
879 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
880 assert(0);
881 return;
882 }
883
884 /* Midgard can perform certain modifiers on output of an ALU op */
885 unsigned outmod;
886
887 if (midgard_is_integer_out_op(op)) {
888 outmod = midgard_outmod_int_wrap;
889 } else {
890 bool sat = instr->dest.saturate || instr->op == nir_op_fsat;
891 outmod = sat ? midgard_outmod_sat : midgard_outmod_none;
892 }
893
894 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
895
896 if (instr->op == nir_op_fmax) {
897 if (nir_is_fzero_constant(instr->src[0].src)) {
898 op = midgard_alu_op_fmov;
899 nr_inputs = 1;
900 outmod = midgard_outmod_pos;
901 instr->src[0] = instr->src[1];
902 } else if (nir_is_fzero_constant(instr->src[1].src)) {
903 op = midgard_alu_op_fmov;
904 nr_inputs = 1;
905 outmod = midgard_outmod_pos;
906 }
907 }
908
909 /* Fetch unit, quirks, etc information */
910 unsigned opcode_props = alu_opcode_props[op].props;
911 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
912
913 midgard_instruction ins = {
914 .type = TAG_ALU_4,
915 .dest = nir_dest_index(&instr->dest.dest),
916 .dest_type = nir_op_infos[instr->op].output_type
917 | nir_dest_bit_size(instr->dest.dest),
918 };
919
920 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
921 ins.src[i] = ~0;
922
923 if (quirk_flipped_r24) {
924 ins.src[0] = ~0;
925 mir_copy_src(&ins, instr, 0, 1);
926 } else {
927 for (unsigned i = 0; i < nr_inputs; ++i)
928 mir_copy_src(&ins, instr, i, quirk_flipped_r24 ? 1 : i);
929 }
930
931 nir_alu_src *nirmods[3] = { NULL };
932
933 if (nr_inputs >= 2) {
934 nirmods[0] = &instr->src[0];
935 nirmods[1] = &instr->src[1];
936 } else if (nr_inputs == 1) {
937 nirmods[quirk_flipped_r24] = &instr->src[0];
938 } else {
939 assert(0);
940 }
941
942 if (nr_inputs == 3)
943 nirmods[2] = &instr->src[2];
944
945 /* These were lowered to a move, so apply the corresponding mod */
946
947 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
948 nir_alu_src *s = nirmods[quirk_flipped_r24];
949
950 if (instr->op == nir_op_fneg)
951 s->negate = !s->negate;
952
953 if (instr->op == nir_op_fabs)
954 s->abs = !s->abs;
955 }
956
957 bool is_int = midgard_is_integer_op(op);
958
959 ins.mask = mask_of(nr_components);
960
961 midgard_vector_alu alu = {
962 .op = op,
963 .reg_mode = reg_mode,
964 .dest_override = dest_override,
965 .outmod = outmod,
966
967 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int, broadcast_swizzle, half_1, sext_1)),
968 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int, broadcast_swizzle, half_2, sext_2)),
969 };
970
971 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
972
973 if (!is_ssa)
974 ins.mask &= instr->dest.write_mask;
975
976 for (unsigned m = 0; m < 3; ++m) {
977 if (!nirmods[m])
978 continue;
979
980 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c)
981 ins.swizzle[m][c] = nirmods[m]->swizzle[c];
982
983 /* Replicate. TODO: remove when vec16 lands */
984 for (unsigned c = NIR_MAX_VEC_COMPONENTS; c < MIR_VEC_COMPONENTS; ++c)
985 ins.swizzle[m][c] = nirmods[m]->swizzle[NIR_MAX_VEC_COMPONENTS - 1];
986 }
987
988 if (nr_inputs == 3) {
989 /* Conditions can't have mods */
990 assert(!nirmods[2]->abs);
991 assert(!nirmods[2]->negate);
992 }
993
994 ins.alu = alu;
995
996 /* Late fixup for emulated instructions */
997
998 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
999 /* Presently, our second argument is an inline #0 constant.
1000 * Switch over to an embedded 1.0 constant (that can't fit
1001 * inline, since we're 32-bit, not 16-bit like the inline
1002 * constants) */
1003
1004 ins.has_inline_constant = false;
1005 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1006 ins.src_types[1] = nir_type_float32;
1007 ins.has_constants = true;
1008
1009 if (instr->op == nir_op_b2f32)
1010 ins.constants.f32[0] = 1.0f;
1011 else
1012 ins.constants.i32[0] = 1;
1013
1014 for (unsigned c = 0; c < 16; ++c)
1015 ins.swizzle[1][c] = 0;
1016 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1017 /* Lots of instructions need a 0 plonked in */
1018 ins.has_inline_constant = false;
1019 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1020 ins.src_types[1] = nir_type_uint32;
1021 ins.has_constants = true;
1022 ins.constants.u32[0] = 0;
1023
1024 for (unsigned c = 0; c < 16; ++c)
1025 ins.swizzle[1][c] = 0;
1026 } else if (instr->op == nir_op_inot) {
1027 ins.invert = true;
1028 }
1029
1030 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1031 /* To avoid duplicating the lookup tables (probably), true LUT
1032 * instructions can only operate as if they were scalars. Lower
1033 * them here by changing the component. */
1034
1035 unsigned orig_mask = ins.mask;
1036
1037 for (int i = 0; i < nr_components; ++i) {
1038 /* Mask the associated component, dropping the
1039 * instruction if needed */
1040
1041 ins.mask = 1 << i;
1042 ins.mask &= orig_mask;
1043
1044 if (!ins.mask)
1045 continue;
1046
1047 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1048 ins.swizzle[0][j] = nirmods[0]->swizzle[i]; /* Pull from the correct component */
1049
1050 emit_mir_instruction(ctx, ins);
1051 }
1052 } else {
1053 emit_mir_instruction(ctx, ins);
1054 }
1055 }
1056
1057 #undef ALU_CASE
1058
1059 static void
1060 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1061 {
1062 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1063 unsigned nir_mask = 0;
1064 unsigned dsize = 0;
1065
1066 if (is_read) {
1067 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1068 dsize = nir_dest_bit_size(intr->dest);
1069 } else {
1070 nir_mask = nir_intrinsic_write_mask(intr);
1071 dsize = 32;
1072 }
1073
1074 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1075 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1076 mir_set_bytemask(ins, bytemask);
1077
1078 if (dsize == 64)
1079 ins->load_64 = true;
1080 }
1081
1082 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1083 * optimized) versions of UBO #0 */
1084
1085 static midgard_instruction *
1086 emit_ubo_read(
1087 compiler_context *ctx,
1088 nir_instr *instr,
1089 unsigned dest,
1090 unsigned offset,
1091 nir_src *indirect_offset,
1092 unsigned indirect_shift,
1093 unsigned index)
1094 {
1095 /* TODO: half-floats */
1096
1097 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1098 ins.constants.u32[0] = offset;
1099
1100 if (instr->type == nir_instr_type_intrinsic)
1101 mir_set_intr_mask(instr, &ins, true);
1102
1103 if (indirect_offset) {
1104 ins.src[2] = nir_src_index(ctx, indirect_offset);
1105 ins.src_types[2] = nir_type_uint32;
1106 ins.load_store.arg_2 = (indirect_shift << 5);
1107 } else {
1108 ins.load_store.arg_2 = 0x1E;
1109 }
1110
1111 ins.load_store.arg_1 = index;
1112
1113 return emit_mir_instruction(ctx, ins);
1114 }
1115
1116 /* Globals are like UBOs if you squint. And shared memory is like globals if
1117 * you squint even harder */
1118
1119 static void
1120 emit_global(
1121 compiler_context *ctx,
1122 nir_instr *instr,
1123 bool is_read,
1124 unsigned srcdest,
1125 nir_src *offset,
1126 bool is_shared)
1127 {
1128 /* TODO: types */
1129
1130 midgard_instruction ins;
1131
1132 if (is_read)
1133 ins = m_ld_int4(srcdest, 0);
1134 else
1135 ins = m_st_int4(srcdest, 0);
1136
1137 mir_set_offset(ctx, &ins, offset, is_shared);
1138 mir_set_intr_mask(instr, &ins, is_read);
1139
1140 emit_mir_instruction(ctx, ins);
1141 }
1142
1143 static void
1144 emit_varying_read(
1145 compiler_context *ctx,
1146 unsigned dest, unsigned offset,
1147 unsigned nr_comp, unsigned component,
1148 nir_src *indirect_offset, nir_alu_type type, bool flat)
1149 {
1150 /* XXX: Half-floats? */
1151 /* TODO: swizzle, mask */
1152
1153 midgard_instruction ins = m_ld_vary_32(dest, offset);
1154 ins.mask = mask_of(nr_comp);
1155
1156 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1157 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1158
1159 midgard_varying_parameter p = {
1160 .is_varying = 1,
1161 .interpolation = midgard_interp_default,
1162 .flat = flat,
1163 };
1164
1165 unsigned u;
1166 memcpy(&u, &p, sizeof(p));
1167 ins.load_store.varying_parameters = u;
1168
1169 if (indirect_offset) {
1170 ins.src[2] = nir_src_index(ctx, indirect_offset);
1171 ins.src_types[2] = nir_type_uint32;
1172 } else
1173 ins.load_store.arg_2 = 0x1E;
1174
1175 ins.load_store.arg_1 = 0x9E;
1176
1177 /* Use the type appropriate load */
1178 switch (type) {
1179 case nir_type_uint:
1180 case nir_type_bool:
1181 ins.load_store.op = midgard_op_ld_vary_32u;
1182 break;
1183 case nir_type_int:
1184 ins.load_store.op = midgard_op_ld_vary_32i;
1185 break;
1186 case nir_type_float:
1187 ins.load_store.op = midgard_op_ld_vary_32;
1188 break;
1189 default:
1190 unreachable("Attempted to load unknown type");
1191 break;
1192 }
1193
1194 emit_mir_instruction(ctx, ins);
1195 }
1196
1197 static void
1198 emit_attr_read(
1199 compiler_context *ctx,
1200 unsigned dest, unsigned offset,
1201 unsigned nr_comp, nir_alu_type t)
1202 {
1203 midgard_instruction ins = m_ld_attr_32(dest, offset);
1204 ins.load_store.arg_1 = 0x1E;
1205 ins.load_store.arg_2 = 0x1E;
1206 ins.mask = mask_of(nr_comp);
1207
1208 /* Use the type appropriate load */
1209 switch (t) {
1210 case nir_type_uint:
1211 case nir_type_bool:
1212 ins.load_store.op = midgard_op_ld_attr_32u;
1213 break;
1214 case nir_type_int:
1215 ins.load_store.op = midgard_op_ld_attr_32i;
1216 break;
1217 case nir_type_float:
1218 ins.load_store.op = midgard_op_ld_attr_32;
1219 break;
1220 default:
1221 unreachable("Attempted to load unknown type");
1222 break;
1223 }
1224
1225 emit_mir_instruction(ctx, ins);
1226 }
1227
1228 static void
1229 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1230 unsigned nr_components, unsigned offset)
1231 {
1232 nir_dest nir_dest;
1233
1234 /* Figure out which uniform this is */
1235 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1236 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1237
1238 unsigned dest = nir_dest_index(&nir_dest);
1239
1240 /* Sysvals are prefix uniforms */
1241 unsigned uniform = ((uintptr_t) val) - 1;
1242
1243 /* Emit the read itself -- this is never indirect */
1244 midgard_instruction *ins =
1245 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1246
1247 ins->mask = mask_of(nr_components);
1248 }
1249
1250 static unsigned
1251 compute_builtin_arg(nir_op op)
1252 {
1253 switch (op) {
1254 case nir_intrinsic_load_work_group_id:
1255 return 0x14;
1256 case nir_intrinsic_load_local_invocation_id:
1257 return 0x10;
1258 default:
1259 unreachable("Invalid compute paramater loaded");
1260 }
1261 }
1262
1263 static void
1264 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1265 {
1266 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1267
1268 midgard_instruction *br = ctx->writeout_branch[rt];
1269
1270 assert(!br);
1271
1272 emit_explicit_constant(ctx, src, src);
1273
1274 struct midgard_instruction ins =
1275 v_branch(false, false);
1276
1277 ins.writeout = true;
1278
1279 /* Add dependencies */
1280 ins.src[0] = src;
1281 ins.src_types[0] = nir_type_uint32;
1282 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1283 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1284
1285 /* Emit the branch */
1286 br = emit_mir_instruction(ctx, ins);
1287 schedule_barrier(ctx);
1288 ctx->writeout_branch[rt] = br;
1289
1290 /* Push our current location = current block count - 1 = where we'll
1291 * jump to. Maybe a bit too clever for my own good */
1292
1293 br->branch.target_block = ctx->block_count - 1;
1294 }
1295
1296 static void
1297 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1298 {
1299 unsigned reg = nir_dest_index(&instr->dest);
1300 midgard_instruction ins = m_ld_compute_id(reg, 0);
1301 ins.mask = mask_of(3);
1302 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1303 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1304 emit_mir_instruction(ctx, ins);
1305 }
1306
1307 static unsigned
1308 vertex_builtin_arg(nir_op op)
1309 {
1310 switch (op) {
1311 case nir_intrinsic_load_vertex_id:
1312 return PAN_VERTEX_ID;
1313 case nir_intrinsic_load_instance_id:
1314 return PAN_INSTANCE_ID;
1315 default:
1316 unreachable("Invalid vertex builtin");
1317 }
1318 }
1319
1320 static void
1321 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1322 {
1323 unsigned reg = nir_dest_index(&instr->dest);
1324 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1325 }
1326
1327 static void
1328 emit_control_barrier(compiler_context *ctx)
1329 {
1330 midgard_instruction ins = {
1331 .type = TAG_TEXTURE_4,
1332 .src = { ~0, ~0, ~0, ~0 },
1333 .texture = {
1334 .op = TEXTURE_OP_BARRIER,
1335
1336 /* TODO: optimize */
1337 .barrier_buffer = 1,
1338 .barrier_shared = 1
1339 }
1340 };
1341
1342 emit_mir_instruction(ctx, ins);
1343 }
1344
1345 static const nir_variable *
1346 search_var(struct exec_list *vars, unsigned driver_loc)
1347 {
1348 nir_foreach_variable(var, vars) {
1349 if (var->data.driver_location == driver_loc)
1350 return var;
1351 }
1352
1353 return NULL;
1354 }
1355
1356 static void
1357 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1358 {
1359 unsigned offset = 0, reg;
1360
1361 switch (instr->intrinsic) {
1362 case nir_intrinsic_discard_if:
1363 case nir_intrinsic_discard: {
1364 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1365 struct midgard_instruction discard = v_branch(conditional, false);
1366 discard.branch.target_type = TARGET_DISCARD;
1367
1368 if (conditional) {
1369 discard.src[0] = nir_src_index(ctx, &instr->src[0]);
1370 discard.src_types[0] = nir_type_uint32;
1371 }
1372
1373 emit_mir_instruction(ctx, discard);
1374 schedule_barrier(ctx);
1375
1376 break;
1377 }
1378
1379 case nir_intrinsic_load_uniform:
1380 case nir_intrinsic_load_ubo:
1381 case nir_intrinsic_load_global:
1382 case nir_intrinsic_load_shared:
1383 case nir_intrinsic_load_input:
1384 case nir_intrinsic_load_interpolated_input: {
1385 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1386 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1387 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1388 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1389 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1390 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1391
1392 /* Get the base type of the intrinsic */
1393 /* TODO: Infer type? Does it matter? */
1394 nir_alu_type t =
1395 (is_ubo || is_global || is_shared) ? nir_type_uint :
1396 (is_interp) ? nir_type_float :
1397 nir_intrinsic_type(instr);
1398
1399 t = nir_alu_type_get_base_type(t);
1400
1401 if (!(is_ubo || is_global)) {
1402 offset = nir_intrinsic_base(instr);
1403 }
1404
1405 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1406
1407 nir_src *src_offset = nir_get_io_offset_src(instr);
1408
1409 bool direct = nir_src_is_const(*src_offset);
1410 nir_src *indirect_offset = direct ? NULL : src_offset;
1411
1412 if (direct)
1413 offset += nir_src_as_uint(*src_offset);
1414
1415 /* We may need to apply a fractional offset */
1416 int component = (is_flat || is_interp) ?
1417 nir_intrinsic_component(instr) : 0;
1418 reg = nir_dest_index(&instr->dest);
1419
1420 if (is_uniform && !ctx->is_blend) {
1421 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1422 } else if (is_ubo) {
1423 nir_src index = instr->src[0];
1424
1425 /* TODO: Is indirect block number possible? */
1426 assert(nir_src_is_const(index));
1427
1428 uint32_t uindex = nir_src_as_uint(index) + 1;
1429 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1430 } else if (is_global || is_shared) {
1431 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1432 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1433 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1434 } else if (ctx->is_blend) {
1435 /* For blend shaders, load the input color, which is
1436 * preloaded to r0 */
1437
1438 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1439 emit_mir_instruction(ctx, move);
1440 schedule_barrier(ctx);
1441 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1442 emit_attr_read(ctx, reg, offset, nr_comp, t);
1443 } else {
1444 DBG("Unknown load\n");
1445 assert(0);
1446 }
1447
1448 break;
1449 }
1450
1451 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1452 case nir_intrinsic_load_barycentric_pixel:
1453 case nir_intrinsic_load_barycentric_centroid:
1454 break;
1455
1456 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1457
1458 case nir_intrinsic_load_raw_output_pan:
1459 case nir_intrinsic_load_output_u8_as_fp16_pan:
1460 reg = nir_dest_index(&instr->dest);
1461 assert(ctx->is_blend);
1462
1463 /* T720 and below use different blend opcodes with slightly
1464 * different semantics than T760 and up */
1465
1466 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1467 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1468
1469 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1470 ld.load_store.op = old_blend ?
1471 midgard_op_ld_color_buffer_u8_as_fp16_old :
1472 midgard_op_ld_color_buffer_u8_as_fp16;
1473
1474 if (old_blend) {
1475 ld.load_store.address = 1;
1476 ld.load_store.arg_2 = 0x1E;
1477 }
1478
1479 for (unsigned c = 2; c < 16; ++c)
1480 ld.swizzle[0][c] = 0;
1481 }
1482
1483 emit_mir_instruction(ctx, ld);
1484 break;
1485
1486 case nir_intrinsic_load_blend_const_color_rgba: {
1487 assert(ctx->is_blend);
1488 reg = nir_dest_index(&instr->dest);
1489
1490 /* Blend constants are embedded directly in the shader and
1491 * patched in, so we use some magic routing */
1492
1493 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1494 ins.has_constants = true;
1495 ins.has_blend_constant = true;
1496 emit_mir_instruction(ctx, ins);
1497 break;
1498 }
1499
1500 case nir_intrinsic_store_zs_output_pan: {
1501 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1502 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1503 MIDGARD_ZS_RT);
1504
1505 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1506
1507 if (!nir_intrinsic_component(instr))
1508 br->writeout_depth = true;
1509 if (nir_intrinsic_component(instr) ||
1510 instr->num_components)
1511 br->writeout_stencil = true;
1512 assert(br->writeout_depth | br->writeout_stencil);
1513 break;
1514 }
1515
1516 case nir_intrinsic_store_output:
1517 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1518
1519 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1520
1521 reg = nir_src_index(ctx, &instr->src[0]);
1522
1523 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1524 const nir_variable *var;
1525 enum midgard_rt_id rt;
1526
1527 var = search_var(&ctx->nir->outputs,
1528 nir_intrinsic_base(instr));
1529 assert(var);
1530 if (var->data.location == FRAG_RESULT_COLOR)
1531 rt = MIDGARD_COLOR_RT0;
1532 else if (var->data.location >= FRAG_RESULT_DATA0)
1533 rt = MIDGARD_COLOR_RT0 + var->data.location -
1534 FRAG_RESULT_DATA0;
1535 else
1536 assert(0);
1537
1538 emit_fragment_store(ctx, reg, rt);
1539 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1540 /* We should have been vectorized, though we don't
1541 * currently check that st_vary is emitted only once
1542 * per slot (this is relevant, since there's not a mask
1543 * parameter available on the store [set to 0 by the
1544 * blob]). We do respect the component by adjusting the
1545 * swizzle. If this is a constant source, we'll need to
1546 * emit that explicitly. */
1547
1548 emit_explicit_constant(ctx, reg, reg);
1549
1550 unsigned dst_component = nir_intrinsic_component(instr);
1551 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1552
1553 midgard_instruction st = m_st_vary_32(reg, offset);
1554 st.load_store.arg_1 = 0x9E;
1555 st.load_store.arg_2 = 0x1E;
1556
1557 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1558 case nir_type_uint:
1559 case nir_type_bool:
1560 st.load_store.op = midgard_op_st_vary_32u;
1561 break;
1562 case nir_type_int:
1563 st.load_store.op = midgard_op_st_vary_32i;
1564 break;
1565 case nir_type_float:
1566 st.load_store.op = midgard_op_st_vary_32;
1567 break;
1568 default:
1569 unreachable("Attempted to store unknown type");
1570 break;
1571 }
1572
1573 /* nir_intrinsic_component(store_intr) encodes the
1574 * destination component start. Source component offset
1575 * adjustment is taken care of in
1576 * install_registers_instr(), when offset_swizzle() is
1577 * called.
1578 */
1579 unsigned src_component = COMPONENT_X;
1580
1581 assert(nr_comp > 0);
1582 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1583 st.swizzle[0][i] = src_component;
1584 if (i >= dst_component && i < dst_component + nr_comp - 1)
1585 src_component++;
1586 }
1587
1588 emit_mir_instruction(ctx, st);
1589 } else {
1590 DBG("Unknown store\n");
1591 assert(0);
1592 }
1593
1594 break;
1595
1596 /* Special case of store_output for lowered blend shaders */
1597 case nir_intrinsic_store_raw_output_pan:
1598 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1599 reg = nir_src_index(ctx, &instr->src[0]);
1600
1601 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1602 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1603 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1604 * of:
1605 *
1606 * imov r0.xyzw, r0.xxxx
1607 */
1608
1609 unsigned expanded = make_compiler_temp(ctx);
1610
1611 midgard_instruction splatter = v_mov(reg, expanded);
1612
1613 for (unsigned c = 0; c < 16; ++c)
1614 splatter.swizzle[1][c] = 0;
1615
1616 emit_mir_instruction(ctx, splatter);
1617 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1618 } else
1619 emit_fragment_store(ctx, reg, ctx->blend_rt);
1620
1621 break;
1622
1623 case nir_intrinsic_store_global:
1624 case nir_intrinsic_store_shared:
1625 reg = nir_src_index(ctx, &instr->src[0]);
1626 emit_explicit_constant(ctx, reg, reg);
1627
1628 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1629 break;
1630
1631 case nir_intrinsic_load_ssbo_address:
1632 emit_sysval_read(ctx, &instr->instr, 1, 0);
1633 break;
1634
1635 case nir_intrinsic_get_buffer_size:
1636 emit_sysval_read(ctx, &instr->instr, 1, 8);
1637 break;
1638
1639 case nir_intrinsic_load_viewport_scale:
1640 case nir_intrinsic_load_viewport_offset:
1641 case nir_intrinsic_load_num_work_groups:
1642 case nir_intrinsic_load_sampler_lod_parameters_pan:
1643 emit_sysval_read(ctx, &instr->instr, 3, 0);
1644 break;
1645
1646 case nir_intrinsic_load_work_group_id:
1647 case nir_intrinsic_load_local_invocation_id:
1648 emit_compute_builtin(ctx, instr);
1649 break;
1650
1651 case nir_intrinsic_load_vertex_id:
1652 case nir_intrinsic_load_instance_id:
1653 emit_vertex_builtin(ctx, instr);
1654 break;
1655
1656 case nir_intrinsic_memory_barrier_buffer:
1657 case nir_intrinsic_memory_barrier_shared:
1658 break;
1659
1660 case nir_intrinsic_control_barrier:
1661 schedule_barrier(ctx);
1662 emit_control_barrier(ctx);
1663 schedule_barrier(ctx);
1664 break;
1665
1666 default:
1667 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1668 assert(0);
1669 break;
1670 }
1671 }
1672
1673 static unsigned
1674 midgard_tex_format(enum glsl_sampler_dim dim)
1675 {
1676 switch (dim) {
1677 case GLSL_SAMPLER_DIM_1D:
1678 case GLSL_SAMPLER_DIM_BUF:
1679 return MALI_TEX_1D;
1680
1681 case GLSL_SAMPLER_DIM_2D:
1682 case GLSL_SAMPLER_DIM_EXTERNAL:
1683 case GLSL_SAMPLER_DIM_RECT:
1684 return MALI_TEX_2D;
1685
1686 case GLSL_SAMPLER_DIM_3D:
1687 return MALI_TEX_3D;
1688
1689 case GLSL_SAMPLER_DIM_CUBE:
1690 return MALI_TEX_CUBE;
1691
1692 default:
1693 DBG("Unknown sampler dim type\n");
1694 assert(0);
1695 return 0;
1696 }
1697 }
1698
1699 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1700 * was successful */
1701
1702 static bool
1703 pan_attach_constant_bias(
1704 compiler_context *ctx,
1705 nir_src lod,
1706 midgard_texture_word *word)
1707 {
1708 /* To attach as constant, it has to *be* constant */
1709
1710 if (!nir_src_is_const(lod))
1711 return false;
1712
1713 float f = nir_src_as_float(lod);
1714
1715 /* Break into fixed-point */
1716 signed lod_int = f;
1717 float lod_frac = f - lod_int;
1718
1719 /* Carry over negative fractions */
1720 if (lod_frac < 0.0) {
1721 lod_int--;
1722 lod_frac += 1.0;
1723 }
1724
1725 /* Encode */
1726 word->bias = float_to_ubyte(lod_frac);
1727 word->bias_int = lod_int;
1728
1729 return true;
1730 }
1731
1732 static void
1733 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1734 unsigned midgard_texop)
1735 {
1736 /* TODO */
1737 //assert (!instr->sampler);
1738
1739 int texture_index = instr->texture_index;
1740 int sampler_index = texture_index;
1741
1742 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1743 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1744
1745 midgard_instruction ins = {
1746 .type = TAG_TEXTURE_4,
1747 .mask = 0xF,
1748 .dest = nir_dest_index(&instr->dest),
1749 .src = { ~0, ~0, ~0, ~0 },
1750 .dest_type = dest_type,
1751 .swizzle = SWIZZLE_IDENTITY_4,
1752 .texture = {
1753 .op = midgard_texop,
1754 .format = midgard_tex_format(instr->sampler_dim),
1755 .texture_handle = texture_index,
1756 .sampler_handle = sampler_index,
1757 .shadow = instr->is_shadow,
1758 }
1759 };
1760
1761 /* We may need a temporary for the coordinate */
1762
1763 bool needs_temp_coord =
1764 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1765 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1766 (instr->is_shadow);
1767
1768 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1769
1770 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1771 int index = nir_src_index(ctx, &instr->src[i].src);
1772 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1773 unsigned sz = nir_src_bit_size(instr->src[i].src);
1774 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1775
1776 switch (instr->src[i].src_type) {
1777 case nir_tex_src_coord: {
1778 emit_explicit_constant(ctx, index, index);
1779
1780 unsigned coord_mask = mask_of(instr->coord_components);
1781
1782 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1783
1784 if (flip_zw)
1785 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1786
1787 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1788 /* texelFetch is undefined on samplerCube */
1789 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1790
1791 /* For cubemaps, we use a special ld/st op to
1792 * select the face and copy the xy into the
1793 * texture register */
1794
1795 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1796 ld.src[1] = index;
1797 ld.src_types[1] = T;
1798 ld.mask = 0x3; /* xy */
1799 ld.load_store.arg_1 = 0x20;
1800 ld.swizzle[1][3] = COMPONENT_X;
1801 emit_mir_instruction(ctx, ld);
1802
1803 /* xyzw -> xyxx */
1804 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1805 ins.swizzle[1][3] = COMPONENT_X;
1806 } else if (needs_temp_coord) {
1807 /* mov coord_temp, coords */
1808 midgard_instruction mov = v_mov(index, coords);
1809 mov.mask = coord_mask;
1810
1811 if (flip_zw)
1812 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1813
1814 emit_mir_instruction(ctx, mov);
1815 } else {
1816 coords = index;
1817 }
1818
1819 ins.src[1] = coords;
1820 ins.src_types[1] = T;
1821
1822 /* Texelfetch coordinates uses all four elements
1823 * (xyz/index) regardless of texture dimensionality,
1824 * which means it's necessary to zero the unused
1825 * components to keep everything happy */
1826
1827 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1828 /* mov index.zw, #0, or generalized */
1829 midgard_instruction mov =
1830 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1831 mov.has_constants = true;
1832 mov.mask = coord_mask ^ 0xF;
1833 emit_mir_instruction(ctx, mov);
1834 }
1835
1836 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1837 /* Array component in w but NIR wants it in z,
1838 * but if we have a temp coord we already fixed
1839 * that up */
1840
1841 if (nr_components == 3) {
1842 ins.swizzle[1][2] = COMPONENT_Z;
1843 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1844 } else if (nr_components == 2) {
1845 ins.swizzle[1][2] =
1846 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1847 ins.swizzle[1][3] = COMPONENT_X;
1848 } else
1849 unreachable("Invalid texture 2D components");
1850 }
1851
1852 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1853 /* We zeroed */
1854 ins.swizzle[1][2] = COMPONENT_Z;
1855 ins.swizzle[1][3] = COMPONENT_W;
1856 }
1857
1858 break;
1859 }
1860
1861 case nir_tex_src_bias:
1862 case nir_tex_src_lod: {
1863 /* Try as a constant if we can */
1864
1865 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1866 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1867 break;
1868
1869 ins.texture.lod_register = true;
1870 ins.src[2] = index;
1871 ins.src_types[2] = T;
1872
1873 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1874 ins.swizzle[2][c] = COMPONENT_X;
1875
1876 emit_explicit_constant(ctx, index, index);
1877
1878 break;
1879 };
1880
1881 case nir_tex_src_offset: {
1882 ins.texture.offset_register = true;
1883 ins.src[3] = index;
1884 ins.src_types[3] = T;
1885
1886 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1887 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
1888
1889 emit_explicit_constant(ctx, index, index);
1890 break;
1891 };
1892
1893 case nir_tex_src_comparator: {
1894 unsigned comp = COMPONENT_Z;
1895
1896 /* mov coord_temp.foo, coords */
1897 midgard_instruction mov = v_mov(index, coords);
1898 mov.mask = 1 << comp;
1899
1900 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
1901 mov.swizzle[1][i] = COMPONENT_X;
1902
1903 emit_mir_instruction(ctx, mov);
1904 break;
1905 }
1906
1907 default: {
1908 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
1909 assert(0);
1910 }
1911 }
1912 }
1913
1914 emit_mir_instruction(ctx, ins);
1915
1916 /* Used for .cont and .last hinting */
1917 ctx->texture_op_count++;
1918 }
1919
1920 static void
1921 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1922 {
1923 switch (instr->op) {
1924 case nir_texop_tex:
1925 case nir_texop_txb:
1926 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
1927 break;
1928 case nir_texop_txl:
1929 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
1930 break;
1931 case nir_texop_txf:
1932 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
1933 break;
1934 case nir_texop_txs:
1935 emit_sysval_read(ctx, &instr->instr, 4, 0);
1936 break;
1937 default: {
1938 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
1939 assert(0);
1940 }
1941 }
1942 }
1943
1944 static void
1945 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1946 {
1947 switch (instr->type) {
1948 case nir_jump_break: {
1949 /* Emit a branch out of the loop */
1950 struct midgard_instruction br = v_branch(false, false);
1951 br.branch.target_type = TARGET_BREAK;
1952 br.branch.target_break = ctx->current_loop_depth;
1953 emit_mir_instruction(ctx, br);
1954 break;
1955 }
1956
1957 default:
1958 DBG("Unknown jump type %d\n", instr->type);
1959 break;
1960 }
1961 }
1962
1963 static void
1964 emit_instr(compiler_context *ctx, struct nir_instr *instr)
1965 {
1966 switch (instr->type) {
1967 case nir_instr_type_load_const:
1968 emit_load_const(ctx, nir_instr_as_load_const(instr));
1969 break;
1970
1971 case nir_instr_type_intrinsic:
1972 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1973 break;
1974
1975 case nir_instr_type_alu:
1976 emit_alu(ctx, nir_instr_as_alu(instr));
1977 break;
1978
1979 case nir_instr_type_tex:
1980 emit_tex(ctx, nir_instr_as_tex(instr));
1981 break;
1982
1983 case nir_instr_type_jump:
1984 emit_jump(ctx, nir_instr_as_jump(instr));
1985 break;
1986
1987 case nir_instr_type_ssa_undef:
1988 /* Spurious */
1989 break;
1990
1991 default:
1992 DBG("Unhandled instruction type\n");
1993 break;
1994 }
1995 }
1996
1997
1998 /* ALU instructions can inline or embed constants, which decreases register
1999 * pressure and saves space. */
2000
2001 #define CONDITIONAL_ATTACH(idx) { \
2002 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2003 \
2004 if (entry) { \
2005 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2006 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2007 } \
2008 }
2009
2010 static void
2011 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2012 {
2013 mir_foreach_instr_in_block(block, alu) {
2014 /* Other instructions cannot inline constants */
2015 if (alu->type != TAG_ALU_4) continue;
2016 if (alu->compact_branch) continue;
2017
2018 /* If there is already a constant here, we can do nothing */
2019 if (alu->has_constants) continue;
2020
2021 CONDITIONAL_ATTACH(0);
2022
2023 if (!alu->has_constants) {
2024 CONDITIONAL_ATTACH(1)
2025 } else if (!alu->inline_constant) {
2026 /* Corner case: _two_ vec4 constants, for instance with a
2027 * csel. For this case, we can only use a constant
2028 * register for one, we'll have to emit a move for the
2029 * other. */
2030
2031 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2032 unsigned scratch = make_compiler_temp(ctx);
2033
2034 if (entry) {
2035 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2036 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2037
2038 /* Set the source */
2039 alu->src[1] = scratch;
2040
2041 /* Inject us -before- the last instruction which set r31 */
2042 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2043 }
2044 }
2045 }
2046 }
2047
2048 /* Midgard supports two types of constants, embedded constants (128-bit) and
2049 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2050 * constants can be demoted to inline constants, for space savings and
2051 * sometimes a performance boost */
2052
2053 static void
2054 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2055 {
2056 mir_foreach_instr_in_block(block, ins) {
2057 if (!ins->has_constants) continue;
2058 if (ins->has_inline_constant) continue;
2059
2060 /* Blend constants must not be inlined by definition */
2061 if (ins->has_blend_constant) continue;
2062
2063 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2064 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2065 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2066
2067 if (!(is_16 || is_32))
2068 continue;
2069
2070 /* src1 cannot be an inline constant due to encoding
2071 * restrictions. So, if possible we try to flip the arguments
2072 * in that case */
2073
2074 int op = ins->alu.op;
2075
2076 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2077 alu_opcode_props[op].props & OP_COMMUTES) {
2078 mir_flip(ins);
2079 }
2080
2081 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2082 /* Extract the source information */
2083
2084 midgard_vector_alu_src *src;
2085 int q = ins->alu.src2;
2086 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
2087 src = m;
2088
2089 /* Component is from the swizzle. Take a nonzero component */
2090 assert(ins->mask);
2091 unsigned first_comp = ffs(ins->mask) - 1;
2092 unsigned component = ins->swizzle[1][first_comp];
2093
2094 /* Scale constant appropriately, if we can legally */
2095 uint16_t scaled_constant = 0;
2096
2097 if (is_16) {
2098 scaled_constant = ins->constants.u16[component];
2099 } else if (midgard_is_integer_op(op)) {
2100 scaled_constant = ins->constants.u32[component];
2101
2102 /* Constant overflow after resize */
2103 if (scaled_constant != ins->constants.u32[component])
2104 continue;
2105 } else {
2106 float original = ins->constants.f32[component];
2107 scaled_constant = _mesa_float_to_half(original);
2108
2109 /* Check for loss of precision. If this is
2110 * mediump, we don't care, but for a highp
2111 * shader, we need to pay attention. NIR
2112 * doesn't yet tell us which mode we're in!
2113 * Practically this prevents most constants
2114 * from being inlined, sadly. */
2115
2116 float fp32 = _mesa_half_to_float(scaled_constant);
2117
2118 if (fp32 != original)
2119 continue;
2120 }
2121
2122 /* We don't know how to handle these with a constant */
2123
2124 if (mir_nontrivial_source2_mod_simple(ins) || src->rep_low || src->rep_high) {
2125 DBG("Bailing inline constant...\n");
2126 continue;
2127 }
2128
2129 /* Make sure that the constant is not itself a vector
2130 * by checking if all accessed values are the same. */
2131
2132 const midgard_constants *cons = &ins->constants;
2133 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2134
2135 bool is_vector = false;
2136 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2137
2138 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2139 /* We only care if this component is actually used */
2140 if (!(mask & (1 << c)))
2141 continue;
2142
2143 uint32_t test = is_16 ?
2144 cons->u16[ins->swizzle[1][c]] :
2145 cons->u32[ins->swizzle[1][c]];
2146
2147 if (test != value) {
2148 is_vector = true;
2149 break;
2150 }
2151 }
2152
2153 if (is_vector)
2154 continue;
2155
2156 /* Get rid of the embedded constant */
2157 ins->has_constants = false;
2158 ins->src[1] = ~0;
2159 ins->has_inline_constant = true;
2160 ins->inline_constant = scaled_constant;
2161 }
2162 }
2163 }
2164
2165 /* Dead code elimination for branches at the end of a block - only one branch
2166 * per block is legal semantically */
2167
2168 static void
2169 midgard_opt_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2170 {
2171 bool branched = false;
2172
2173 mir_foreach_instr_in_block_safe(block, ins) {
2174 if (!midgard_is_branch_unit(ins->unit)) continue;
2175
2176 if (branched)
2177 mir_remove_instruction(ins);
2178
2179 branched = true;
2180 }
2181 }
2182
2183 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2184 * the move can be propagated away entirely */
2185
2186 static bool
2187 mir_compose_float_outmod(midgard_outmod_float *outmod, midgard_outmod_float comp)
2188 {
2189 /* Nothing to do */
2190 if (comp == midgard_outmod_none)
2191 return true;
2192
2193 if (*outmod == midgard_outmod_none) {
2194 *outmod = comp;
2195 return true;
2196 }
2197
2198 /* TODO: Compose rules */
2199 return false;
2200 }
2201
2202 static bool
2203 midgard_opt_pos_propagate(compiler_context *ctx, midgard_block *block)
2204 {
2205 bool progress = false;
2206
2207 mir_foreach_instr_in_block_safe(block, ins) {
2208 if (ins->type != TAG_ALU_4) continue;
2209 if (ins->alu.op != midgard_alu_op_fmov) continue;
2210 if (ins->alu.outmod != midgard_outmod_pos) continue;
2211
2212 /* TODO: Registers? */
2213 unsigned src = ins->src[1];
2214 if (src & PAN_IS_REG) continue;
2215
2216 /* There might be a source modifier, too */
2217 if (mir_nontrivial_source2_mod(ins)) continue;
2218
2219 /* Backpropagate the modifier */
2220 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
2221 if (v->type != TAG_ALU_4) continue;
2222 if (v->dest != src) continue;
2223
2224 /* Can we even take a float outmod? */
2225 if (midgard_is_integer_out_op(v->alu.op)) continue;
2226
2227 midgard_outmod_float temp = v->alu.outmod;
2228 progress |= mir_compose_float_outmod(&temp, ins->alu.outmod);
2229
2230 /* Throw in the towel.. */
2231 if (!progress) break;
2232
2233 /* Otherwise, transfer the modifier */
2234 v->alu.outmod = temp;
2235 ins->alu.outmod = midgard_outmod_none;
2236
2237 break;
2238 }
2239 }
2240
2241 return progress;
2242 }
2243
2244 static unsigned
2245 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2246 {
2247 /* Loop to ourselves */
2248 midgard_instruction *br = ctx->writeout_branch[rt];
2249 struct midgard_instruction ins = v_branch(false, false);
2250 ins.writeout = true;
2251 ins.writeout_depth = br->writeout_depth;
2252 ins.writeout_stencil = br->writeout_stencil;
2253 ins.branch.target_block = ctx->block_count - 1;
2254 ins.constants.u32[0] = br->constants.u32[0];
2255 emit_mir_instruction(ctx, ins);
2256
2257 ctx->current_block->epilogue = true;
2258 schedule_barrier(ctx);
2259 return ins.branch.target_block;
2260 }
2261
2262 static midgard_block *
2263 emit_block(compiler_context *ctx, nir_block *block)
2264 {
2265 midgard_block *this_block = ctx->after_block;
2266 ctx->after_block = NULL;
2267
2268 if (!this_block)
2269 this_block = create_empty_block(ctx);
2270
2271 list_addtail(&this_block->base.link, &ctx->blocks);
2272
2273 this_block->scheduled = false;
2274 ++ctx->block_count;
2275
2276 /* Set up current block */
2277 list_inithead(&this_block->base.instructions);
2278 ctx->current_block = this_block;
2279
2280 nir_foreach_instr(instr, block) {
2281 emit_instr(ctx, instr);
2282 ++ctx->instruction_count;
2283 }
2284
2285 return this_block;
2286 }
2287
2288 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2289
2290 static void
2291 emit_if(struct compiler_context *ctx, nir_if *nif)
2292 {
2293 midgard_block *before_block = ctx->current_block;
2294
2295 /* Speculatively emit the branch, but we can't fill it in until later */
2296 EMIT(branch, true, true);
2297 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2298 then_branch->src[0] = nir_src_index(ctx, &nif->condition);
2299 then_branch->src_types[0] = nir_type_uint32;
2300
2301 /* Emit the two subblocks. */
2302 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2303 midgard_block *end_then_block = ctx->current_block;
2304
2305 /* Emit a jump from the end of the then block to the end of the else */
2306 EMIT(branch, false, false);
2307 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2308
2309 /* Emit second block, and check if it's empty */
2310
2311 int else_idx = ctx->block_count;
2312 int count_in = ctx->instruction_count;
2313 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2314 midgard_block *end_else_block = ctx->current_block;
2315 int after_else_idx = ctx->block_count;
2316
2317 /* Now that we have the subblocks emitted, fix up the branches */
2318
2319 assert(then_block);
2320 assert(else_block);
2321
2322 if (ctx->instruction_count == count_in) {
2323 /* The else block is empty, so don't emit an exit jump */
2324 mir_remove_instruction(then_exit);
2325 then_branch->branch.target_block = after_else_idx;
2326 } else {
2327 then_branch->branch.target_block = else_idx;
2328 then_exit->branch.target_block = after_else_idx;
2329 }
2330
2331 /* Wire up the successors */
2332
2333 ctx->after_block = create_empty_block(ctx);
2334
2335 pan_block_add_successor(&before_block->base, &then_block->base);
2336 pan_block_add_successor(&before_block->base, &else_block->base);
2337
2338 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2339 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2340 }
2341
2342 static void
2343 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2344 {
2345 /* Remember where we are */
2346 midgard_block *start_block = ctx->current_block;
2347
2348 /* Allocate a loop number, growing the current inner loop depth */
2349 int loop_idx = ++ctx->current_loop_depth;
2350
2351 /* Get index from before the body so we can loop back later */
2352 int start_idx = ctx->block_count;
2353
2354 /* Emit the body itself */
2355 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2356
2357 /* Branch back to loop back */
2358 struct midgard_instruction br_back = v_branch(false, false);
2359 br_back.branch.target_block = start_idx;
2360 emit_mir_instruction(ctx, br_back);
2361
2362 /* Mark down that branch in the graph. */
2363 pan_block_add_successor(&start_block->base, &loop_block->base);
2364 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2365
2366 /* Find the index of the block about to follow us (note: we don't add
2367 * one; blocks are 0-indexed so we get a fencepost problem) */
2368 int break_block_idx = ctx->block_count;
2369
2370 /* Fix up the break statements we emitted to point to the right place,
2371 * now that we can allocate a block number for them */
2372 ctx->after_block = create_empty_block(ctx);
2373
2374 mir_foreach_block_from(ctx, start_block, _block) {
2375 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2376 if (ins->type != TAG_ALU_4) continue;
2377 if (!ins->compact_branch) continue;
2378
2379 /* We found a branch -- check the type to see if we need to do anything */
2380 if (ins->branch.target_type != TARGET_BREAK) continue;
2381
2382 /* It's a break! Check if it's our break */
2383 if (ins->branch.target_break != loop_idx) continue;
2384
2385 /* Okay, cool, we're breaking out of this loop.
2386 * Rewrite from a break to a goto */
2387
2388 ins->branch.target_type = TARGET_GOTO;
2389 ins->branch.target_block = break_block_idx;
2390
2391 pan_block_add_successor(_block, &ctx->after_block->base);
2392 }
2393 }
2394
2395 /* Now that we've finished emitting the loop, free up the depth again
2396 * so we play nice with recursion amid nested loops */
2397 --ctx->current_loop_depth;
2398
2399 /* Dump loop stats */
2400 ++ctx->loop_count;
2401 }
2402
2403 static midgard_block *
2404 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2405 {
2406 midgard_block *start_block = NULL;
2407
2408 foreach_list_typed(nir_cf_node, node, node, list) {
2409 switch (node->type) {
2410 case nir_cf_node_block: {
2411 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2412
2413 if (!start_block)
2414 start_block = block;
2415
2416 break;
2417 }
2418
2419 case nir_cf_node_if:
2420 emit_if(ctx, nir_cf_node_as_if(node));
2421 break;
2422
2423 case nir_cf_node_loop:
2424 emit_loop(ctx, nir_cf_node_as_loop(node));
2425 break;
2426
2427 case nir_cf_node_function:
2428 assert(0);
2429 break;
2430 }
2431 }
2432
2433 return start_block;
2434 }
2435
2436 /* Due to lookahead, we need to report the first tag executed in the command
2437 * stream and in branch targets. An initial block might be empty, so iterate
2438 * until we find one that 'works' */
2439
2440 static unsigned
2441 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2442 {
2443 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2444
2445 mir_foreach_block_from(ctx, initial_block, _v) {
2446 midgard_block *v = (midgard_block *) _v;
2447 if (v->quadword_count) {
2448 midgard_bundle *initial_bundle =
2449 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2450
2451 return initial_bundle->tag;
2452 }
2453 }
2454
2455 /* Default to a tag 1 which will break from the shader, in case we jump
2456 * to the exit block (i.e. `return` in a compute shader) */
2457
2458 return 1;
2459 }
2460
2461 /* For each fragment writeout instruction, generate a writeout loop to
2462 * associate with it */
2463
2464 static void
2465 mir_add_writeout_loops(compiler_context *ctx)
2466 {
2467 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2468 midgard_instruction *br = ctx->writeout_branch[rt];
2469 if (!br) continue;
2470
2471 unsigned popped = br->branch.target_block;
2472 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2473 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2474 br->branch.target_type = TARGET_GOTO;
2475
2476 /* If we have more RTs, we'll need to restore back after our
2477 * loop terminates */
2478
2479 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2480 midgard_instruction uncond = v_branch(false, false);
2481 uncond.branch.target_block = popped;
2482 uncond.branch.target_type = TARGET_GOTO;
2483 emit_mir_instruction(ctx, uncond);
2484 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2485 schedule_barrier(ctx);
2486 } else {
2487 /* We're last, so we can terminate here */
2488 br->last_writeout = true;
2489 }
2490 }
2491 }
2492
2493 int
2494 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2495 {
2496 struct util_dynarray *compiled = &program->compiled;
2497
2498 midgard_debug = debug_get_option_midgard_debug();
2499
2500 /* TODO: Bound against what? */
2501 compiler_context *ctx = rzalloc(NULL, compiler_context);
2502
2503 ctx->nir = nir;
2504 ctx->stage = nir->info.stage;
2505 ctx->is_blend = is_blend;
2506 ctx->alpha_ref = program->alpha_ref;
2507 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2508 ctx->quirks = midgard_get_quirks(gpu_id);
2509
2510 /* Start off with a safe cutoff, allowing usage of all 16 work
2511 * registers. Later, we'll promote uniform reads to uniform registers
2512 * if we determine it is beneficial to do so */
2513 ctx->uniform_cutoff = 8;
2514
2515 /* Initialize at a global (not block) level hash tables */
2516
2517 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2518 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2519
2520 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2521 * (so we don't accidentally duplicate the epilogue since mesa/st has
2522 * messed with our I/O quite a bit already) */
2523
2524 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2525
2526 if (ctx->stage == MESA_SHADER_VERTEX) {
2527 NIR_PASS_V(nir, nir_lower_viewport_transform);
2528 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2529 }
2530
2531 NIR_PASS_V(nir, nir_lower_var_copies);
2532 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2533 NIR_PASS_V(nir, nir_split_var_copies);
2534 NIR_PASS_V(nir, nir_lower_var_copies);
2535 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2536 NIR_PASS_V(nir, nir_lower_var_copies);
2537 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2538
2539 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2540 NIR_PASS_V(nir, nir_lower_ssbo);
2541 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2542
2543 /* Optimisation passes */
2544
2545 optimise_nir(nir, ctx->quirks);
2546
2547 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2548 nir_print_shader(nir, stdout);
2549 }
2550
2551 /* Assign sysvals and counts, now that we're sure
2552 * (post-optimisation) */
2553
2554 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2555 program->sysval_count = ctx->sysvals.sysval_count;
2556 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2557
2558 nir_foreach_function(func, nir) {
2559 if (!func->impl)
2560 continue;
2561
2562 list_inithead(&ctx->blocks);
2563 ctx->block_count = 0;
2564 ctx->func = func;
2565
2566 emit_cf_list(ctx, &func->impl->body);
2567 break; /* TODO: Multi-function shaders */
2568 }
2569
2570 util_dynarray_init(compiled, NULL);
2571
2572 /* Per-block lowering before opts */
2573
2574 mir_foreach_block(ctx, _block) {
2575 midgard_block *block = (midgard_block *) _block;
2576 inline_alu_constants(ctx, block);
2577 midgard_opt_promote_fmov(ctx, block);
2578 embedded_to_inline_constant(ctx, block);
2579 }
2580 /* MIR-level optimizations */
2581
2582 bool progress = false;
2583
2584 do {
2585 progress = false;
2586
2587 mir_foreach_block(ctx, _block) {
2588 midgard_block *block = (midgard_block *) _block;
2589 progress |= midgard_opt_pos_propagate(ctx, block);
2590 progress |= midgard_opt_copy_prop(ctx, block);
2591 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2592 progress |= midgard_opt_combine_projection(ctx, block);
2593 progress |= midgard_opt_varying_projection(ctx, block);
2594 progress |= midgard_opt_not_propagate(ctx, block);
2595 progress |= midgard_opt_fuse_src_invert(ctx, block);
2596 progress |= midgard_opt_fuse_dest_invert(ctx, block);
2597 progress |= midgard_opt_csel_invert(ctx, block);
2598 progress |= midgard_opt_drop_cmp_invert(ctx, block);
2599 progress |= midgard_opt_invert_branch(ctx, block);
2600 }
2601 } while (progress);
2602
2603 mir_foreach_block(ctx, _block) {
2604 midgard_block *block = (midgard_block *) _block;
2605 midgard_lower_invert(ctx, block);
2606 midgard_lower_derivatives(ctx, block);
2607 }
2608
2609 /* Nested control-flow can result in dead branches at the end of the
2610 * block. This messes with our analysis and is just dead code, so cull
2611 * them */
2612 mir_foreach_block(ctx, _block) {
2613 midgard_block *block = (midgard_block *) _block;
2614 midgard_opt_cull_dead_branch(ctx, block);
2615 }
2616
2617 /* Ensure we were lowered */
2618 mir_foreach_instr_global(ctx, ins) {
2619 assert(!ins->invert);
2620 }
2621
2622 if (ctx->stage == MESA_SHADER_FRAGMENT)
2623 mir_add_writeout_loops(ctx);
2624
2625 /* Schedule! */
2626 midgard_schedule_program(ctx);
2627 mir_ra(ctx);
2628
2629 /* Now that all the bundles are scheduled and we can calculate block
2630 * sizes, emit actual branch instructions rather than placeholders */
2631
2632 int br_block_idx = 0;
2633
2634 mir_foreach_block(ctx, _block) {
2635 midgard_block *block = (midgard_block *) _block;
2636 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2637 for (int c = 0; c < bundle->instruction_count; ++c) {
2638 midgard_instruction *ins = bundle->instructions[c];
2639
2640 if (!midgard_is_branch_unit(ins->unit)) continue;
2641
2642 /* Parse some basic branch info */
2643 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2644 bool is_conditional = ins->branch.conditional;
2645 bool is_inverted = ins->branch.invert_conditional;
2646 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2647 bool is_writeout = ins->writeout;
2648
2649 /* Determine the block we're jumping to */
2650 int target_number = ins->branch.target_block;
2651
2652 /* Report the destination tag */
2653 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2654
2655 /* Count up the number of quadwords we're
2656 * jumping over = number of quadwords until
2657 * (br_block_idx, target_number) */
2658
2659 int quadword_offset = 0;
2660
2661 if (is_discard) {
2662 /* Ignored */
2663 } else if (target_number > br_block_idx) {
2664 /* Jump forward */
2665
2666 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2667 midgard_block *blk = mir_get_block(ctx, idx);
2668 assert(blk);
2669
2670 quadword_offset += blk->quadword_count;
2671 }
2672 } else {
2673 /* Jump backwards */
2674
2675 for (int idx = br_block_idx; idx >= target_number; --idx) {
2676 midgard_block *blk = mir_get_block(ctx, idx);
2677 assert(blk);
2678
2679 quadword_offset -= blk->quadword_count;
2680 }
2681 }
2682
2683 /* Unconditional extended branches (far jumps)
2684 * have issues, so we always use a conditional
2685 * branch, setting the condition to always for
2686 * unconditional. For compact unconditional
2687 * branches, cond isn't used so it doesn't
2688 * matter what we pick. */
2689
2690 midgard_condition cond =
2691 !is_conditional ? midgard_condition_always :
2692 is_inverted ? midgard_condition_false :
2693 midgard_condition_true;
2694
2695 midgard_jmp_writeout_op op =
2696 is_discard ? midgard_jmp_writeout_op_discard :
2697 is_writeout ? midgard_jmp_writeout_op_writeout :
2698 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2699 midgard_jmp_writeout_op_branch_cond;
2700
2701 if (!is_compact) {
2702 midgard_branch_extended branch =
2703 midgard_create_branch_extended(
2704 cond, op,
2705 dest_tag,
2706 quadword_offset);
2707
2708 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2709 } else if (is_conditional || is_discard) {
2710 midgard_branch_cond branch = {
2711 .op = op,
2712 .dest_tag = dest_tag,
2713 .offset = quadword_offset,
2714 .cond = cond
2715 };
2716
2717 assert(branch.offset == quadword_offset);
2718
2719 memcpy(&ins->br_compact, &branch, sizeof(branch));
2720 } else {
2721 assert(op == midgard_jmp_writeout_op_branch_uncond);
2722
2723 midgard_branch_uncond branch = {
2724 .op = op,
2725 .dest_tag = dest_tag,
2726 .offset = quadword_offset,
2727 .unknown = 1
2728 };
2729
2730 assert(branch.offset == quadword_offset);
2731
2732 memcpy(&ins->br_compact, &branch, sizeof(branch));
2733 }
2734 }
2735 }
2736
2737 ++br_block_idx;
2738 }
2739
2740 /* Emit flat binary from the instruction arrays. Iterate each block in
2741 * sequence. Save instruction boundaries such that lookahead tags can
2742 * be assigned easily */
2743
2744 /* Cache _all_ bundles in source order for lookahead across failed branches */
2745
2746 int bundle_count = 0;
2747 mir_foreach_block(ctx, _block) {
2748 midgard_block *block = (midgard_block *) _block;
2749 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2750 }
2751 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2752 int bundle_idx = 0;
2753 mir_foreach_block(ctx, _block) {
2754 midgard_block *block = (midgard_block *) _block;
2755 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2756 source_order_bundles[bundle_idx++] = bundle;
2757 }
2758 }
2759
2760 int current_bundle = 0;
2761
2762 /* Midgard prefetches instruction types, so during emission we
2763 * need to lookahead. Unless this is the last instruction, in
2764 * which we return 1. */
2765
2766 mir_foreach_block(ctx, _block) {
2767 midgard_block *block = (midgard_block *) _block;
2768 mir_foreach_bundle_in_block(block, bundle) {
2769 int lookahead = 1;
2770
2771 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2772 lookahead = source_order_bundles[current_bundle + 1]->tag;
2773
2774 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2775 ++current_bundle;
2776 }
2777
2778 /* TODO: Free deeper */
2779 //util_dynarray_fini(&block->instructions);
2780 }
2781
2782 free(source_order_bundles);
2783
2784 /* Report the very first tag executed */
2785 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2786
2787 /* Deal with off-by-one related to the fencepost problem */
2788 program->work_register_count = ctx->work_registers + 1;
2789 program->uniform_cutoff = ctx->uniform_cutoff;
2790
2791 program->blend_patch_offset = ctx->blend_constant_offset;
2792 program->tls_size = ctx->tls_size;
2793
2794 if (midgard_debug & MIDGARD_DBG_SHADERS)
2795 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2796
2797 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2798 unsigned nr_bundles = 0, nr_ins = 0;
2799
2800 /* Count instructions and bundles */
2801
2802 mir_foreach_block(ctx, _block) {
2803 midgard_block *block = (midgard_block *) _block;
2804 nr_bundles += util_dynarray_num_elements(
2805 &block->bundles, midgard_bundle);
2806
2807 mir_foreach_bundle_in_block(block, bun)
2808 nr_ins += bun->instruction_count;
2809 }
2810
2811 /* Calculate thread count. There are certain cutoffs by
2812 * register count for thread count */
2813
2814 unsigned nr_registers = program->work_register_count;
2815
2816 unsigned nr_threads =
2817 (nr_registers <= 4) ? 4 :
2818 (nr_registers <= 8) ? 2 :
2819 1;
2820
2821 /* Dump stats */
2822
2823 fprintf(stderr, "shader%d - %s shader: "
2824 "%u inst, %u bundles, %u quadwords, "
2825 "%u registers, %u threads, %u loops, "
2826 "%u:%u spills:fills\n",
2827 SHADER_DB_COUNT++,
2828 gl_shader_stage_name(ctx->stage),
2829 nr_ins, nr_bundles, ctx->quadword_count,
2830 nr_registers, nr_threads,
2831 ctx->loop_count,
2832 ctx->spills, ctx->fills);
2833 }
2834
2835 ralloc_free(ctx);
2836
2837 return 0;
2838 }