2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
50 #include "midgard_quirks.h"
52 #include "disassemble.h"
54 static const struct debug_named_value debug_options
[] = {
55 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
63 unsigned SHADER_DB_COUNT
= 0;
65 int midgard_debug
= 0;
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block
*
72 create_empty_block(compiler_context
*ctx
)
74 midgard_block
*blk
= rzalloc(ctx
, midgard_block
);
76 blk
->base
.predecessors
= _mesa_set_create(blk
,
78 _mesa_key_pointer_equal
);
80 blk
->base
.name
= ctx
->block_source_count
++;
86 schedule_barrier(compiler_context
*ctx
)
88 midgard_block
*temp
= ctx
->after_block
;
89 ctx
->after_block
= create_empty_block(ctx
);
91 list_addtail(&ctx
->after_block
->base
.link
, &ctx
->blocks
);
92 list_inithead(&ctx
->after_block
->base
.instructions
);
93 pan_block_add_successor(&ctx
->current_block
->base
, &ctx
->after_block
->base
);
94 ctx
->current_block
= ctx
->after_block
;
95 ctx
->after_block
= temp
;
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
112 .op = midgard_op_##name, \
119 i.src_types[0] = T; \
127 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
128 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
130 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
131 * the corresponding Midgard source */
133 static midgard_vector_alu_src
134 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
, unsigned broadcast_count
,
135 bool half
, bool sext
)
137 /* Figure out how many components there are so we can adjust.
138 * Specifically we want to broadcast the last channel so things like
142 if (broadcast_count
&& src
) {
143 uint8_t last_component
= src
->swizzle
[broadcast_count
- 1];
145 for (unsigned c
= broadcast_count
; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
146 src
->swizzle
[c
] = last_component
;
150 midgard_vector_alu_src alu_src
= {
157 alu_src
.mod
= midgard_int_normal
;
159 /* Sign/zero-extend if needed */
163 midgard_int_sign_extend
164 : midgard_int_zero_extend
;
167 /* These should have been lowered away */
169 assert(!(src
->abs
|| src
->negate
));
172 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
178 M_LOAD(ld_attr_32
, nir_type_uint32
);
179 M_LOAD(ld_vary_32
, nir_type_uint32
);
180 M_LOAD(ld_ubo_int4
, nir_type_uint32
);
181 M_LOAD(ld_int4
, nir_type_uint32
);
182 M_STORE(st_int4
, nir_type_uint32
);
183 M_LOAD(ld_color_buffer_32u
, nir_type_uint32
);
184 M_STORE(st_vary_32
, nir_type_uint32
);
185 M_LOAD(ld_cubemap_coords
, nir_type_uint32
);
186 M_LOAD(ld_compute_id
, nir_type_uint32
);
188 static midgard_instruction
189 v_branch(bool conditional
, bool invert
)
191 midgard_instruction ins
= {
193 .unit
= ALU_ENAB_BRANCH
,
194 .compact_branch
= true,
196 .conditional
= conditional
,
197 .invert_conditional
= invert
200 .src
= { ~0, ~0, ~0, ~0 },
206 static midgard_branch_extended
207 midgard_create_branch_extended( midgard_condition cond
,
208 midgard_jmp_writeout_op op
,
210 signed quadword_offset
)
212 /* The condition code is actually a LUT describing a function to
213 * combine multiple condition codes. However, we only support a single
214 * condition code at the moment, so we just duplicate over a bunch of
217 uint16_t duplicated_cond
=
227 midgard_branch_extended branch
= {
229 .dest_tag
= dest_tag
,
230 .offset
= quadword_offset
,
231 .cond
= duplicated_cond
238 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
240 ins
->has_constants
= true;
241 memcpy(&ins
->constants
, constants
, 16);
245 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
247 return glsl_count_attribute_slots(type
, false);
250 /* Lower fdot2 to a vector multiplication followed by channel addition */
252 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
254 if (alu
->op
!= nir_op_fdot2
)
257 b
->cursor
= nir_before_instr(&alu
->instr
);
259 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
260 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
262 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
264 nir_ssa_def
*sum
= nir_fadd(b
,
265 nir_channel(b
, product
, 0),
266 nir_channel(b
, product
, 1));
268 /* Replace the fdot2 with this sum */
269 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
273 midgard_nir_lower_fdot2(nir_shader
*shader
)
275 bool progress
= false;
277 nir_foreach_function(function
, shader
) {
278 if (!function
->impl
) continue;
281 nir_builder
*b
= &_b
;
282 nir_builder_init(b
, function
->impl
);
284 nir_foreach_block(block
, function
->impl
) {
285 nir_foreach_instr_safe(instr
, block
) {
286 if (instr
->type
!= nir_instr_type_alu
) continue;
288 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
289 midgard_nir_lower_fdot2_body(b
, alu
);
295 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
302 /* Midgard can't write depth and stencil separately. It has to happen in a
303 * single store operation containing both. Let's add a panfrost specific
304 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
308 midgard_nir_lower_zs_store(nir_shader
*nir
)
310 if (nir
->info
.stage
!= MESA_SHADER_FRAGMENT
)
313 nir_variable
*z_var
= NULL
, *s_var
= NULL
;
315 nir_foreach_variable(var
, &nir
->outputs
) {
316 if (var
->data
.location
== FRAG_RESULT_DEPTH
)
318 else if (var
->data
.location
== FRAG_RESULT_STENCIL
)
322 if (!z_var
&& !s_var
)
325 bool progress
= false;
327 nir_foreach_function(function
, nir
) {
328 if (!function
->impl
) continue;
330 nir_intrinsic_instr
*z_store
= NULL
, *s_store
= NULL
, *last_store
= NULL
;
332 nir_foreach_block(block
, function
->impl
) {
333 nir_foreach_instr_safe(instr
, block
) {
334 if (instr
->type
!= nir_instr_type_intrinsic
)
337 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
338 if (intr
->intrinsic
!= nir_intrinsic_store_output
)
341 if (z_var
&& nir_intrinsic_base(intr
) == z_var
->data
.driver_location
) {
347 if (s_var
&& nir_intrinsic_base(intr
) == s_var
->data
.driver_location
) {
355 if (!z_store
&& !s_store
) continue;
358 nir_builder_init(&b
, function
->impl
);
360 b
.cursor
= nir_before_instr(&last_store
->instr
);
362 nir_ssa_def
*zs_store_src
;
364 if (z_store
&& s_store
) {
365 nir_ssa_def
*srcs
[2] = {
366 nir_ssa_for_src(&b
, z_store
->src
[0], 1),
367 nir_ssa_for_src(&b
, s_store
->src
[0], 1),
370 zs_store_src
= nir_vec(&b
, srcs
, 2);
372 zs_store_src
= nir_ssa_for_src(&b
, last_store
->src
[0], 1);
375 nir_intrinsic_instr
*zs_store
;
377 zs_store
= nir_intrinsic_instr_create(b
.shader
,
378 nir_intrinsic_store_zs_output_pan
);
379 zs_store
->src
[0] = nir_src_for_ssa(zs_store_src
);
380 zs_store
->num_components
= z_store
&& s_store
? 2 : 1;
381 nir_intrinsic_set_component(zs_store
, z_store
? 0 : 1);
383 /* Replace the Z and S store by a ZS store */
384 nir_builder_instr_insert(&b
, &zs_store
->instr
);
387 nir_instr_remove(&z_store
->instr
);
390 nir_instr_remove(&s_store
->instr
);
392 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
399 /* Flushes undefined values to zero */
402 optimise_nir(nir_shader
*nir
, unsigned quirks
)
405 unsigned lower_flrp
=
406 (nir
->options
->lower_flrp16
? 16 : 0) |
407 (nir
->options
->lower_flrp32
? 32 : 0) |
408 (nir
->options
->lower_flrp64
? 64 : 0);
410 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
411 NIR_PASS(progress
, nir
, nir_lower_idiv
, nir_lower_idiv_fast
);
413 nir_lower_tex_options lower_tex_options
= {
414 .lower_txs_lod
= true,
416 .lower_tex_without_implicit_lod
=
417 (quirks
& MIDGARD_EXPLICIT_LOD
),
419 /* TODO: we have native gradient.. */
423 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
425 /* Must lower fdot2 after tex is lowered */
426 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
428 /* T720 is broken. */
430 if (quirks
& MIDGARD_BROKEN_LOD
)
431 NIR_PASS_V(nir
, midgard_nir_lod_errata
);
436 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
437 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
439 NIR_PASS(progress
, nir
, nir_copy_prop
);
440 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
441 NIR_PASS(progress
, nir
, nir_opt_dce
);
442 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
443 NIR_PASS(progress
, nir
, nir_opt_cse
);
444 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
445 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
446 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
448 if (lower_flrp
!= 0) {
449 bool lower_flrp_progress
= false;
450 NIR_PASS(lower_flrp_progress
,
454 false /* always_precise */,
455 nir
->options
->lower_ffma
);
456 if (lower_flrp_progress
) {
457 NIR_PASS(progress
, nir
,
458 nir_opt_constant_folding
);
462 /* Nothing should rematerialize any flrps, so we only
463 * need to do this lowering once.
468 NIR_PASS(progress
, nir
, nir_opt_undef
);
469 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
471 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
474 nir_var_function_temp
);
476 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
479 /* Must be run at the end to prevent creation of fsin/fcos ops */
480 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
485 NIR_PASS(progress
, nir
, nir_opt_dce
);
486 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
487 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
488 NIR_PASS(progress
, nir
, nir_copy_prop
);
491 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
492 NIR_PASS(progress
, nir
, nir_opt_algebraic_distribute_src_mods
);
494 /* We implement booleans as 32-bit 0/~0 */
495 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
497 /* Now that booleans are lowered, we can run out late opts */
498 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
500 NIR_PASS(progress
, nir
, nir_copy_prop
);
501 NIR_PASS(progress
, nir
, nir_opt_dce
);
503 /* Take us out of SSA */
504 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
505 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
507 /* We are a vector architecture; write combine where possible */
508 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
509 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
511 NIR_PASS(progress
, nir
, nir_opt_dce
);
514 /* Do not actually emit a load; instead, cache the constant for inlining */
517 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
519 nir_ssa_def def
= instr
->def
;
521 midgard_constants
*consts
= rzalloc(NULL
, midgard_constants
);
523 assert(instr
->def
.num_components
* instr
->def
.bit_size
<= sizeof(*consts
) * 8);
525 #define RAW_CONST_COPY(bits) \
526 nir_const_value_to_array(consts->u##bits, instr->value, \
527 instr->def.num_components, u##bits)
529 switch (instr
->def
.bit_size
) {
543 unreachable("Invalid bit_size for load_const instruction\n");
546 /* Shifted for SSA, +1 for off-by-one */
547 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (def
.index
<< 1) + 1, consts
);
550 /* Normally constants are embedded implicitly, but for I/O and such we have to
551 * explicitly emit a move with the constant source */
554 emit_explicit_constant(compiler_context
*ctx
, unsigned node
, unsigned to
)
556 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, node
+ 1);
558 if (constant_value
) {
559 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), to
);
560 attach_constants(ctx
, &ins
, constant_value
, node
+ 1);
561 emit_mir_instruction(ctx
, ins
);
566 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
568 unsigned comp
= src
->swizzle
[0];
570 for (unsigned c
= 1; c
< nr_components
; ++c
) {
571 if (src
->swizzle
[c
] != comp
)
578 #define ALU_CASE(nir, _op) \
580 op = midgard_alu_op_##_op; \
581 assert(src_bitsize == dst_bitsize); \
584 #define ALU_CASE_BCAST(nir, _op, count) \
586 op = midgard_alu_op_##_op; \
587 broadcast_swizzle = count; \
588 assert(src_bitsize == dst_bitsize); \
590 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
591 * special treatment override this anyway. */
593 static midgard_reg_mode
594 reg_mode_for_nir(nir_alu_instr
*instr
)
596 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
598 switch (src_bitsize
) {
600 return midgard_reg_mode_8
;
602 return midgard_reg_mode_16
;
604 return midgard_reg_mode_32
;
606 return midgard_reg_mode_64
;
608 unreachable("Invalid bit size");
613 mir_copy_src(midgard_instruction
*ins
, nir_alu_instr
*instr
, unsigned i
, unsigned to
)
615 unsigned bits
= nir_src_bit_size(instr
->src
[i
].src
);
617 ins
->src
[to
] = nir_src_index(NULL
, &instr
->src
[i
].src
);
618 ins
->src_types
[to
] = nir_op_infos
[instr
->op
].input_types
[i
] | bits
;
622 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
624 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
625 * is handled elsewhere */
627 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddy
) {
628 midgard_emit_derivatives(ctx
, instr
);
632 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
634 unsigned nr_components
= nir_dest_num_components(instr
->dest
.dest
);
635 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
638 /* Number of components valid to check for the instruction (the rest
639 * will be forced to the last), or 0 to use as-is. Relevant as
640 * ball-type instructions have a channel count in NIR but are all vec4
643 unsigned broadcast_swizzle
= 0;
645 /* What register mode should we operate in? */
646 midgard_reg_mode reg_mode
=
647 reg_mode_for_nir(instr
);
649 /* Do we need a destination override? Used for inline
652 midgard_dest_override dest_override
=
653 midgard_dest_override_none
;
655 /* Should we use a smaller respective source and sign-extend? */
657 bool half_1
= false, sext_1
= false;
658 bool half_2
= false, sext_2
= false;
660 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
661 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
664 ALU_CASE(fadd
, fadd
);
665 ALU_CASE(fmul
, fmul
);
666 ALU_CASE(fmin
, fmin
);
667 ALU_CASE(fmax
, fmax
);
668 ALU_CASE(imin
, imin
);
669 ALU_CASE(imax
, imax
);
670 ALU_CASE(umin
, umin
);
671 ALU_CASE(umax
, umax
);
672 ALU_CASE(ffloor
, ffloor
);
673 ALU_CASE(fround_even
, froundeven
);
674 ALU_CASE(ftrunc
, ftrunc
);
675 ALU_CASE(fceil
, fceil
);
676 ALU_CASE(fdot3
, fdot3
);
677 ALU_CASE(fdot4
, fdot4
);
678 ALU_CASE(iadd
, iadd
);
679 ALU_CASE(isub
, isub
);
680 ALU_CASE(imul
, imul
);
682 /* Zero shoved as second-arg */
683 ALU_CASE(iabs
, iabsdiff
);
687 ALU_CASE(feq32
, feq
);
688 ALU_CASE(fne32
, fne
);
689 ALU_CASE(flt32
, flt
);
690 ALU_CASE(ieq32
, ieq
);
691 ALU_CASE(ine32
, ine
);
692 ALU_CASE(ilt32
, ilt
);
693 ALU_CASE(ult32
, ult
);
695 /* We don't have a native b2f32 instruction. Instead, like many
696 * GPUs, we exploit booleans as 0/~0 for false/true, and
697 * correspondingly AND
698 * by 1.0 to do the type conversion. For the moment, prime us
701 * iand [whatever], #0
703 * At the end of emit_alu (as MIR), we'll fix-up the constant
706 ALU_CASE(b2f32
, iand
);
707 ALU_CASE(b2i32
, iand
);
709 /* Likewise, we don't have a dedicated f2b32 instruction, but
710 * we can do a "not equal to 0.0" test. */
712 ALU_CASE(f2b32
, fne
);
713 ALU_CASE(i2b32
, ine
);
715 ALU_CASE(frcp
, frcp
);
716 ALU_CASE(frsq
, frsqrt
);
717 ALU_CASE(fsqrt
, fsqrt
);
718 ALU_CASE(fexp2
, fexp2
);
719 ALU_CASE(flog2
, flog2
);
721 ALU_CASE(f2i64
, f2i_rtz
);
722 ALU_CASE(f2u64
, f2u_rtz
);
723 ALU_CASE(i2f64
, i2f_rtz
);
724 ALU_CASE(u2f64
, u2f_rtz
);
726 ALU_CASE(f2i32
, f2i_rtz
);
727 ALU_CASE(f2u32
, f2u_rtz
);
728 ALU_CASE(i2f32
, i2f_rtz
);
729 ALU_CASE(u2f32
, u2f_rtz
);
731 ALU_CASE(f2i16
, f2i_rtz
);
732 ALU_CASE(f2u16
, f2u_rtz
);
733 ALU_CASE(i2f16
, i2f_rtz
);
734 ALU_CASE(u2f16
, u2f_rtz
);
736 ALU_CASE(fsin
, fsin
);
737 ALU_CASE(fcos
, fcos
);
739 /* We'll set invert */
740 ALU_CASE(inot
, imov
);
741 ALU_CASE(iand
, iand
);
743 ALU_CASE(ixor
, ixor
);
744 ALU_CASE(ishl
, ishl
);
745 ALU_CASE(ishr
, iasr
);
746 ALU_CASE(ushr
, ilsr
);
748 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
749 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
750 ALU_CASE(b32all_fequal4
, fball_eq
);
752 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
753 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
754 ALU_CASE(b32any_fnequal4
, fbany_neq
);
756 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
757 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
758 ALU_CASE(b32all_iequal4
, iball_eq
);
760 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
761 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
762 ALU_CASE(b32any_inequal4
, ibany_neq
);
764 /* Source mods will be shoved in later */
765 ALU_CASE(fabs
, fmov
);
766 ALU_CASE(fneg
, fmov
);
767 ALU_CASE(fsat
, fmov
);
769 /* For size conversion, we use a move. Ideally though we would squash
770 * these ops together; maybe that has to happen after in NIR as part of
771 * propagation...? An earlier algebraic pass ensured we step down by
772 * only / exactly one size. If stepping down, we use a dest override to
773 * reduce the size; if stepping up, we use a larger-sized move with a
774 * half source and a sign/zero-extension modifier */
780 /* If we end up upscale, we'll need a sign-extend on the
781 * operand (the second argument) */
792 if (instr
->op
== nir_op_f2f16
|| instr
->op
== nir_op_f2f32
||
793 instr
->op
== nir_op_f2f64
)
794 op
= midgard_alu_op_fmov
;
796 op
= midgard_alu_op_imov
;
798 if (dst_bitsize
== (src_bitsize
* 2)) {
802 /* Use a greater register mode */
804 } else if (src_bitsize
== (dst_bitsize
* 2)) {
805 /* Converting down */
806 dest_override
= midgard_dest_override_lower
;
812 /* For greater-or-equal, we lower to less-or-equal and flip the
820 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
821 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
822 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
823 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
826 /* Swap via temporary */
827 nir_alu_src temp
= instr
->src
[1];
828 instr
->src
[1] = instr
->src
[0];
829 instr
->src
[0] = temp
;
834 case nir_op_b32csel
: {
835 /* Midgard features both fcsel and icsel, depending on
836 * the type of the arguments/output. However, as long
837 * as we're careful we can _always_ use icsel and
838 * _never_ need fcsel, since the latter does additional
839 * floating-point-specific processing whereas the
840 * former just moves bits on the wire. It's not obvious
841 * why these are separate opcodes, save for the ability
842 * to do things like sat/pos/abs/neg for free */
844 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
845 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
847 /* The condition is the first argument; move the other
848 * arguments up one to be a binary instruction for
849 * Midgard with the condition last */
851 nir_alu_src temp
= instr
->src
[2];
853 instr
->src
[2] = instr
->src
[0];
854 instr
->src
[0] = instr
->src
[1];
855 instr
->src
[1] = temp
;
861 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
866 /* Midgard can perform certain modifiers on output of an ALU op */
869 if (midgard_is_integer_out_op(op
)) {
870 outmod
= midgard_outmod_int_wrap
;
872 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
873 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
877 /* Fetch unit, quirks, etc information */
878 unsigned opcode_props
= alu_opcode_props
[op
].props
;
879 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
881 midgard_instruction ins
= {
883 .dest
= nir_dest_index(&instr
->dest
.dest
),
884 .dest_type
= nir_op_infos
[instr
->op
].output_type
885 | nir_dest_bit_size(instr
->dest
.dest
),
888 for (unsigned i
= nr_inputs
; i
< ARRAY_SIZE(ins
.src
); ++i
)
891 if (quirk_flipped_r24
) {
893 mir_copy_src(&ins
, instr
, 0, 1);
895 for (unsigned i
= 0; i
< nr_inputs
; ++i
)
896 mir_copy_src(&ins
, instr
, i
, quirk_flipped_r24
? 1 : i
);
899 nir_alu_src
*nirmods
[3] = { NULL
};
901 if (nr_inputs
>= 2) {
902 nirmods
[0] = &instr
->src
[0];
903 nirmods
[1] = &instr
->src
[1];
904 } else if (nr_inputs
== 1) {
905 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
911 nirmods
[2] = &instr
->src
[2];
913 /* These were lowered to a move, so apply the corresponding mod */
915 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
916 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
918 if (instr
->op
== nir_op_fneg
)
919 s
->negate
= !s
->negate
;
921 if (instr
->op
== nir_op_fabs
)
925 bool is_int
= midgard_is_integer_op(op
);
927 ins
.mask
= mask_of(nr_components
);
929 midgard_vector_alu alu
= {
931 .reg_mode
= reg_mode
,
932 .dest_override
= dest_override
,
935 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, sext_1
)),
936 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
, broadcast_swizzle
, half_2
, sext_2
)),
939 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
942 ins
.mask
&= instr
->dest
.write_mask
;
944 for (unsigned m
= 0; m
< 3; ++m
) {
948 for (unsigned c
= 0; c
< NIR_MAX_VEC_COMPONENTS
; ++c
)
949 ins
.swizzle
[m
][c
] = nirmods
[m
]->swizzle
[c
];
951 /* Replicate. TODO: remove when vec16 lands */
952 for (unsigned c
= NIR_MAX_VEC_COMPONENTS
; c
< MIR_VEC_COMPONENTS
; ++c
)
953 ins
.swizzle
[m
][c
] = nirmods
[m
]->swizzle
[NIR_MAX_VEC_COMPONENTS
- 1];
956 if (nr_inputs
== 3) {
957 /* Conditions can't have mods */
958 assert(!nirmods
[2]->abs
);
959 assert(!nirmods
[2]->negate
);
964 /* Late fixup for emulated instructions */
966 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
967 /* Presently, our second argument is an inline #0 constant.
968 * Switch over to an embedded 1.0 constant (that can't fit
969 * inline, since we're 32-bit, not 16-bit like the inline
972 ins
.has_inline_constant
= false;
973 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
974 ins
.src_types
[1] = nir_type_float32
;
975 ins
.has_constants
= true;
977 if (instr
->op
== nir_op_b2f32
)
978 ins
.constants
.f32
[0] = 1.0f
;
980 ins
.constants
.i32
[0] = 1;
982 for (unsigned c
= 0; c
< 16; ++c
)
983 ins
.swizzle
[1][c
] = 0;
984 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
985 /* Lots of instructions need a 0 plonked in */
986 ins
.has_inline_constant
= false;
987 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
988 ins
.src_types
[1] = nir_type_uint32
;
989 ins
.has_constants
= true;
990 ins
.constants
.u32
[0] = 0;
992 for (unsigned c
= 0; c
< 16; ++c
)
993 ins
.swizzle
[1][c
] = 0;
994 } else if (instr
->op
== nir_op_inot
) {
998 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
999 /* To avoid duplicating the lookup tables (probably), true LUT
1000 * instructions can only operate as if they were scalars. Lower
1001 * them here by changing the component. */
1003 unsigned orig_mask
= ins
.mask
;
1005 for (int i
= 0; i
< nr_components
; ++i
) {
1006 /* Mask the associated component, dropping the
1007 * instruction if needed */
1010 ins
.mask
&= orig_mask
;
1015 for (unsigned j
= 0; j
< MIR_VEC_COMPONENTS
; ++j
)
1016 ins
.swizzle
[0][j
] = nirmods
[0]->swizzle
[i
]; /* Pull from the correct component */
1018 emit_mir_instruction(ctx
, ins
);
1021 emit_mir_instruction(ctx
, ins
);
1028 mir_set_intr_mask(nir_instr
*instr
, midgard_instruction
*ins
, bool is_read
)
1030 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
1031 unsigned nir_mask
= 0;
1035 nir_mask
= mask_of(nir_intrinsic_dest_components(intr
));
1036 dsize
= nir_dest_bit_size(intr
->dest
);
1038 nir_mask
= nir_intrinsic_write_mask(intr
);
1042 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1043 unsigned bytemask
= pan_to_bytemask(dsize
, nir_mask
);
1044 mir_set_bytemask(ins
, bytemask
);
1047 ins
->load_64
= true;
1050 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1051 * optimized) versions of UBO #0 */
1053 static midgard_instruction
*
1055 compiler_context
*ctx
,
1059 nir_src
*indirect_offset
,
1060 unsigned indirect_shift
,
1063 /* TODO: half-floats */
1065 midgard_instruction ins
= m_ld_ubo_int4(dest
, 0);
1066 ins
.constants
.u32
[0] = offset
;
1068 if (instr
->type
== nir_instr_type_intrinsic
)
1069 mir_set_intr_mask(instr
, &ins
, true);
1071 if (indirect_offset
) {
1072 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1073 ins
.src_types
[2] = nir_type_uint32
;
1074 ins
.load_store
.arg_2
= (indirect_shift
<< 5);
1076 ins
.load_store
.arg_2
= 0x1E;
1079 ins
.load_store
.arg_1
= index
;
1081 return emit_mir_instruction(ctx
, ins
);
1084 /* Globals are like UBOs if you squint. And shared memory is like globals if
1085 * you squint even harder */
1089 compiler_context
*ctx
,
1098 midgard_instruction ins
;
1101 ins
= m_ld_int4(srcdest
, 0);
1103 ins
= m_st_int4(srcdest
, 0);
1105 mir_set_offset(ctx
, &ins
, offset
, is_shared
);
1106 mir_set_intr_mask(instr
, &ins
, is_read
);
1108 emit_mir_instruction(ctx
, ins
);
1113 compiler_context
*ctx
,
1114 unsigned dest
, unsigned offset
,
1115 unsigned nr_comp
, unsigned component
,
1116 nir_src
*indirect_offset
, nir_alu_type type
, bool flat
)
1118 /* XXX: Half-floats? */
1119 /* TODO: swizzle, mask */
1121 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1122 ins
.mask
= mask_of(nr_comp
);
1124 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
.swizzle
[0]); ++i
)
1125 ins
.swizzle
[0][i
] = MIN2(i
+ component
, COMPONENT_W
);
1127 midgard_varying_parameter p
= {
1129 .interpolation
= midgard_interp_default
,
1134 memcpy(&u
, &p
, sizeof(p
));
1135 ins
.load_store
.varying_parameters
= u
;
1137 if (indirect_offset
) {
1138 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1139 ins
.src_types
[2] = nir_type_uint32
;
1141 ins
.load_store
.arg_2
= 0x1E;
1143 ins
.load_store
.arg_1
= 0x9E;
1145 /* Use the type appropriate load */
1149 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1152 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1154 case nir_type_float
:
1155 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1158 unreachable("Attempted to load unknown type");
1162 emit_mir_instruction(ctx
, ins
);
1167 compiler_context
*ctx
,
1168 unsigned dest
, unsigned offset
,
1169 unsigned nr_comp
, nir_alu_type t
)
1171 midgard_instruction ins
= m_ld_attr_32(dest
, offset
);
1172 ins
.load_store
.arg_1
= 0x1E;
1173 ins
.load_store
.arg_2
= 0x1E;
1174 ins
.mask
= mask_of(nr_comp
);
1176 /* Use the type appropriate load */
1180 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1183 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1185 case nir_type_float
:
1186 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1189 unreachable("Attempted to load unknown type");
1193 emit_mir_instruction(ctx
, ins
);
1197 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
,
1198 unsigned nr_components
, unsigned offset
)
1202 /* Figure out which uniform this is */
1203 int sysval
= panfrost_sysval_for_instr(instr
, &nir_dest
);
1204 void *val
= _mesa_hash_table_u64_search(ctx
->sysvals
.sysval_to_id
, sysval
);
1206 unsigned dest
= nir_dest_index(&nir_dest
);
1208 /* Sysvals are prefix uniforms */
1209 unsigned uniform
= ((uintptr_t) val
) - 1;
1211 /* Emit the read itself -- this is never indirect */
1212 midgard_instruction
*ins
=
1213 emit_ubo_read(ctx
, instr
, dest
, (uniform
* 16) + offset
, NULL
, 0, 0);
1215 ins
->mask
= mask_of(nr_components
);
1219 compute_builtin_arg(nir_op op
)
1222 case nir_intrinsic_load_work_group_id
:
1224 case nir_intrinsic_load_local_invocation_id
:
1227 unreachable("Invalid compute paramater loaded");
1232 emit_fragment_store(compiler_context
*ctx
, unsigned src
, enum midgard_rt_id rt
)
1234 assert(rt
< ARRAY_SIZE(ctx
->writeout_branch
));
1236 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
1240 emit_explicit_constant(ctx
, src
, src
);
1242 struct midgard_instruction ins
=
1243 v_branch(false, false);
1245 ins
.writeout
= true;
1247 /* Add dependencies */
1249 ins
.src_types
[0] = nir_type_uint32
;
1250 ins
.constants
.u32
[0] = rt
== MIDGARD_ZS_RT
?
1251 0xFF : (rt
- MIDGARD_COLOR_RT0
) * 0x100;
1253 /* Emit the branch */
1254 br
= emit_mir_instruction(ctx
, ins
);
1255 schedule_barrier(ctx
);
1256 ctx
->writeout_branch
[rt
] = br
;
1258 /* Push our current location = current block count - 1 = where we'll
1259 * jump to. Maybe a bit too clever for my own good */
1261 br
->branch
.target_block
= ctx
->block_count
- 1;
1265 emit_compute_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1267 unsigned reg
= nir_dest_index(&instr
->dest
);
1268 midgard_instruction ins
= m_ld_compute_id(reg
, 0);
1269 ins
.mask
= mask_of(3);
1270 ins
.swizzle
[0][3] = COMPONENT_X
; /* xyzx */
1271 ins
.load_store
.arg_1
= compute_builtin_arg(instr
->intrinsic
);
1272 emit_mir_instruction(ctx
, ins
);
1276 vertex_builtin_arg(nir_op op
)
1279 case nir_intrinsic_load_vertex_id
:
1280 return PAN_VERTEX_ID
;
1281 case nir_intrinsic_load_instance_id
:
1282 return PAN_INSTANCE_ID
;
1284 unreachable("Invalid vertex builtin");
1289 emit_vertex_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1291 unsigned reg
= nir_dest_index(&instr
->dest
);
1292 emit_attr_read(ctx
, reg
, vertex_builtin_arg(instr
->intrinsic
), 1, nir_type_int
);
1296 emit_control_barrier(compiler_context
*ctx
)
1298 midgard_instruction ins
= {
1299 .type
= TAG_TEXTURE_4
,
1300 .src
= { ~0, ~0, ~0, ~0 },
1302 .op
= TEXTURE_OP_BARRIER
,
1304 /* TODO: optimize */
1305 .barrier_buffer
= 1,
1310 emit_mir_instruction(ctx
, ins
);
1313 static const nir_variable
*
1314 search_var(struct exec_list
*vars
, unsigned driver_loc
)
1316 nir_foreach_variable(var
, vars
) {
1317 if (var
->data
.driver_location
== driver_loc
)
1325 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1327 unsigned offset
= 0, reg
;
1329 switch (instr
->intrinsic
) {
1330 case nir_intrinsic_discard_if
:
1331 case nir_intrinsic_discard
: {
1332 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1333 struct midgard_instruction discard
= v_branch(conditional
, false);
1334 discard
.branch
.target_type
= TARGET_DISCARD
;
1337 discard
.src
[0] = nir_src_index(ctx
, &instr
->src
[0]);
1338 discard
.src_types
[0] = nir_type_uint32
;
1341 emit_mir_instruction(ctx
, discard
);
1342 schedule_barrier(ctx
);
1347 case nir_intrinsic_load_uniform
:
1348 case nir_intrinsic_load_ubo
:
1349 case nir_intrinsic_load_global
:
1350 case nir_intrinsic_load_shared
:
1351 case nir_intrinsic_load_input
:
1352 case nir_intrinsic_load_interpolated_input
: {
1353 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1354 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1355 bool is_global
= instr
->intrinsic
== nir_intrinsic_load_global
;
1356 bool is_shared
= instr
->intrinsic
== nir_intrinsic_load_shared
;
1357 bool is_flat
= instr
->intrinsic
== nir_intrinsic_load_input
;
1358 bool is_interp
= instr
->intrinsic
== nir_intrinsic_load_interpolated_input
;
1360 /* Get the base type of the intrinsic */
1361 /* TODO: Infer type? Does it matter? */
1363 (is_ubo
|| is_global
|| is_shared
) ? nir_type_uint
:
1364 (is_interp
) ? nir_type_float
:
1365 nir_intrinsic_type(instr
);
1367 t
= nir_alu_type_get_base_type(t
);
1369 if (!(is_ubo
|| is_global
)) {
1370 offset
= nir_intrinsic_base(instr
);
1373 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1375 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1377 bool direct
= nir_src_is_const(*src_offset
);
1378 nir_src
*indirect_offset
= direct
? NULL
: src_offset
;
1381 offset
+= nir_src_as_uint(*src_offset
);
1383 /* We may need to apply a fractional offset */
1384 int component
= (is_flat
|| is_interp
) ?
1385 nir_intrinsic_component(instr
) : 0;
1386 reg
= nir_dest_index(&instr
->dest
);
1388 if (is_uniform
&& !ctx
->is_blend
) {
1389 emit_ubo_read(ctx
, &instr
->instr
, reg
, (ctx
->sysvals
.sysval_count
+ offset
) * 16, indirect_offset
, 4, 0);
1390 } else if (is_ubo
) {
1391 nir_src index
= instr
->src
[0];
1393 /* TODO: Is indirect block number possible? */
1394 assert(nir_src_is_const(index
));
1396 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1397 emit_ubo_read(ctx
, &instr
->instr
, reg
, offset
, indirect_offset
, 0, uindex
);
1398 } else if (is_global
|| is_shared
) {
1399 emit_global(ctx
, &instr
->instr
, true, reg
, src_offset
, is_shared
);
1400 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1401 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, indirect_offset
, t
, is_flat
);
1402 } else if (ctx
->is_blend
) {
1403 /* For blend shaders, load the input color, which is
1404 * preloaded to r0 */
1406 midgard_instruction move
= v_mov(SSA_FIXED_REGISTER(0), reg
);
1407 emit_mir_instruction(ctx
, move
);
1408 schedule_barrier(ctx
);
1409 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1410 emit_attr_read(ctx
, reg
, offset
, nr_comp
, t
);
1412 DBG("Unknown load\n");
1419 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1420 case nir_intrinsic_load_barycentric_pixel
:
1421 case nir_intrinsic_load_barycentric_centroid
:
1424 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1426 case nir_intrinsic_load_raw_output_pan
:
1427 case nir_intrinsic_load_output_u8_as_fp16_pan
:
1428 reg
= nir_dest_index(&instr
->dest
);
1429 assert(ctx
->is_blend
);
1431 /* T720 and below use different blend opcodes with slightly
1432 * different semantics than T760 and up */
1434 midgard_instruction ld
= m_ld_color_buffer_32u(reg
, 0);
1435 bool old_blend
= ctx
->quirks
& MIDGARD_OLD_BLEND
;
1437 if (instr
->intrinsic
== nir_intrinsic_load_output_u8_as_fp16_pan
) {
1438 ld
.load_store
.op
= old_blend
?
1439 midgard_op_ld_color_buffer_u8_as_fp16_old
:
1440 midgard_op_ld_color_buffer_u8_as_fp16
;
1443 ld
.load_store
.address
= 1;
1444 ld
.load_store
.arg_2
= 0x1E;
1447 for (unsigned c
= 2; c
< 16; ++c
)
1448 ld
.swizzle
[0][c
] = 0;
1451 emit_mir_instruction(ctx
, ld
);
1454 case nir_intrinsic_load_blend_const_color_rgba
: {
1455 assert(ctx
->is_blend
);
1456 reg
= nir_dest_index(&instr
->dest
);
1458 /* Blend constants are embedded directly in the shader and
1459 * patched in, so we use some magic routing */
1461 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), reg
);
1462 ins
.has_constants
= true;
1463 ins
.has_blend_constant
= true;
1464 emit_mir_instruction(ctx
, ins
);
1468 case nir_intrinsic_store_zs_output_pan
: {
1469 assert(ctx
->stage
== MESA_SHADER_FRAGMENT
);
1470 emit_fragment_store(ctx
, nir_src_index(ctx
, &instr
->src
[0]),
1473 midgard_instruction
*br
= ctx
->writeout_branch
[MIDGARD_ZS_RT
];
1475 if (!nir_intrinsic_component(instr
))
1476 br
->writeout_depth
= true;
1477 if (nir_intrinsic_component(instr
) ||
1478 instr
->num_components
)
1479 br
->writeout_stencil
= true;
1480 assert(br
->writeout_depth
| br
->writeout_stencil
);
1484 case nir_intrinsic_store_output
:
1485 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1487 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1489 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1491 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1492 const nir_variable
*var
;
1493 enum midgard_rt_id rt
;
1495 var
= search_var(&ctx
->nir
->outputs
,
1496 nir_intrinsic_base(instr
));
1498 if (var
->data
.location
== FRAG_RESULT_COLOR
)
1499 rt
= MIDGARD_COLOR_RT0
;
1500 else if (var
->data
.location
>= FRAG_RESULT_DATA0
)
1501 rt
= MIDGARD_COLOR_RT0
+ var
->data
.location
-
1506 emit_fragment_store(ctx
, reg
, rt
);
1507 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1508 /* We should have been vectorized, though we don't
1509 * currently check that st_vary is emitted only once
1510 * per slot (this is relevant, since there's not a mask
1511 * parameter available on the store [set to 0 by the
1512 * blob]). We do respect the component by adjusting the
1513 * swizzle. If this is a constant source, we'll need to
1514 * emit that explicitly. */
1516 emit_explicit_constant(ctx
, reg
, reg
);
1518 unsigned dst_component
= nir_intrinsic_component(instr
);
1519 unsigned nr_comp
= nir_src_num_components(instr
->src
[0]);
1521 midgard_instruction st
= m_st_vary_32(reg
, offset
);
1522 st
.load_store
.arg_1
= 0x9E;
1523 st
.load_store
.arg_2
= 0x1E;
1525 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr
))) {
1528 st
.load_store
.op
= midgard_op_st_vary_32u
;
1531 st
.load_store
.op
= midgard_op_st_vary_32i
;
1533 case nir_type_float
:
1534 st
.load_store
.op
= midgard_op_st_vary_32
;
1537 unreachable("Attempted to store unknown type");
1541 /* nir_intrinsic_component(store_intr) encodes the
1542 * destination component start. Source component offset
1543 * adjustment is taken care of in
1544 * install_registers_instr(), when offset_swizzle() is
1547 unsigned src_component
= COMPONENT_X
;
1549 assert(nr_comp
> 0);
1550 for (unsigned i
= 0; i
< ARRAY_SIZE(st
.swizzle
); ++i
) {
1551 st
.swizzle
[0][i
] = src_component
;
1552 if (i
>= dst_component
&& i
< dst_component
+ nr_comp
- 1)
1556 emit_mir_instruction(ctx
, st
);
1558 DBG("Unknown store\n");
1564 /* Special case of store_output for lowered blend shaders */
1565 case nir_intrinsic_store_raw_output_pan
:
1566 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1567 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1569 if (ctx
->quirks
& MIDGARD_OLD_BLEND
) {
1570 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1571 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1574 * imov r0.xyzw, r0.xxxx
1577 unsigned expanded
= make_compiler_temp(ctx
);
1579 midgard_instruction splatter
= v_mov(reg
, expanded
);
1581 for (unsigned c
= 0; c
< 16; ++c
)
1582 splatter
.swizzle
[1][c
] = 0;
1584 emit_mir_instruction(ctx
, splatter
);
1585 emit_fragment_store(ctx
, expanded
, ctx
->blend_rt
);
1587 emit_fragment_store(ctx
, reg
, ctx
->blend_rt
);
1591 case nir_intrinsic_store_global
:
1592 case nir_intrinsic_store_shared
:
1593 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1594 emit_explicit_constant(ctx
, reg
, reg
);
1596 emit_global(ctx
, &instr
->instr
, false, reg
, &instr
->src
[1], instr
->intrinsic
== nir_intrinsic_store_shared
);
1599 case nir_intrinsic_load_ssbo_address
:
1600 emit_sysval_read(ctx
, &instr
->instr
, 1, 0);
1603 case nir_intrinsic_get_buffer_size
:
1604 emit_sysval_read(ctx
, &instr
->instr
, 1, 8);
1607 case nir_intrinsic_load_viewport_scale
:
1608 case nir_intrinsic_load_viewport_offset
:
1609 case nir_intrinsic_load_num_work_groups
:
1610 case nir_intrinsic_load_sampler_lod_parameters_pan
:
1611 emit_sysval_read(ctx
, &instr
->instr
, 3, 0);
1614 case nir_intrinsic_load_work_group_id
:
1615 case nir_intrinsic_load_local_invocation_id
:
1616 emit_compute_builtin(ctx
, instr
);
1619 case nir_intrinsic_load_vertex_id
:
1620 case nir_intrinsic_load_instance_id
:
1621 emit_vertex_builtin(ctx
, instr
);
1624 case nir_intrinsic_memory_barrier_buffer
:
1625 case nir_intrinsic_memory_barrier_shared
:
1628 case nir_intrinsic_control_barrier
:
1629 schedule_barrier(ctx
);
1630 emit_control_barrier(ctx
);
1631 schedule_barrier(ctx
);
1635 fprintf(stderr
, "Unhandled intrinsic %s\n", nir_intrinsic_infos
[instr
->intrinsic
].name
);
1642 midgard_tex_format(enum glsl_sampler_dim dim
)
1645 case GLSL_SAMPLER_DIM_1D
:
1646 case GLSL_SAMPLER_DIM_BUF
:
1649 case GLSL_SAMPLER_DIM_2D
:
1650 case GLSL_SAMPLER_DIM_EXTERNAL
:
1651 case GLSL_SAMPLER_DIM_RECT
:
1654 case GLSL_SAMPLER_DIM_3D
:
1657 case GLSL_SAMPLER_DIM_CUBE
:
1658 return MALI_TEX_CUBE
;
1661 DBG("Unknown sampler dim type\n");
1667 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1671 pan_attach_constant_bias(
1672 compiler_context
*ctx
,
1674 midgard_texture_word
*word
)
1676 /* To attach as constant, it has to *be* constant */
1678 if (!nir_src_is_const(lod
))
1681 float f
= nir_src_as_float(lod
);
1683 /* Break into fixed-point */
1685 float lod_frac
= f
- lod_int
;
1687 /* Carry over negative fractions */
1688 if (lod_frac
< 0.0) {
1694 word
->bias
= float_to_ubyte(lod_frac
);
1695 word
->bias_int
= lod_int
;
1701 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1702 unsigned midgard_texop
)
1705 //assert (!instr->sampler);
1707 int texture_index
= instr
->texture_index
;
1708 int sampler_index
= texture_index
;
1710 nir_alu_type dest_base
= nir_alu_type_get_base_type(instr
->dest_type
);
1711 nir_alu_type dest_type
= dest_base
| nir_dest_bit_size(instr
->dest
);
1713 midgard_instruction ins
= {
1714 .type
= TAG_TEXTURE_4
,
1716 .dest
= nir_dest_index(&instr
->dest
),
1717 .src
= { ~0, ~0, ~0, ~0 },
1718 .dest_type
= dest_type
,
1719 .swizzle
= SWIZZLE_IDENTITY_4
,
1721 .op
= midgard_texop
,
1722 .format
= midgard_tex_format(instr
->sampler_dim
),
1723 .texture_handle
= texture_index
,
1724 .sampler_handle
= sampler_index
,
1725 .shadow
= instr
->is_shadow
,
1729 if (instr
->is_shadow
&& !instr
->is_new_style_shadow
)
1730 for (int i
= 0; i
< 4; ++i
)
1731 ins
.swizzle
[0][i
] = COMPONENT_X
;
1733 /* We may need a temporary for the coordinate */
1735 bool needs_temp_coord
=
1736 (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) ||
1737 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) ||
1740 unsigned coords
= needs_temp_coord
? make_compiler_temp_reg(ctx
) : 0;
1742 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1743 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1744 unsigned nr_components
= nir_src_num_components(instr
->src
[i
].src
);
1745 unsigned sz
= nir_src_bit_size(instr
->src
[i
].src
);
1746 nir_alu_type T
= nir_tex_instr_src_type(instr
, i
) | sz
;
1748 switch (instr
->src
[i
].src_type
) {
1749 case nir_tex_src_coord
: {
1750 emit_explicit_constant(ctx
, index
, index
);
1752 unsigned coord_mask
= mask_of(instr
->coord_components
);
1754 bool flip_zw
= (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) && (coord_mask
& (1 << COMPONENT_Z
));
1757 coord_mask
^= ((1 << COMPONENT_Z
) | (1 << COMPONENT_W
));
1759 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1760 /* texelFetch is undefined on samplerCube */
1761 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
1763 /* For cubemaps, we use a special ld/st op to
1764 * select the face and copy the xy into the
1765 * texture register */
1767 midgard_instruction ld
= m_ld_cubemap_coords(coords
, 0);
1769 ld
.src_types
[1] = T
;
1770 ld
.mask
= 0x3; /* xy */
1771 ld
.load_store
.arg_1
= 0x20;
1772 ld
.swizzle
[1][3] = COMPONENT_X
;
1773 emit_mir_instruction(ctx
, ld
);
1776 ins
.swizzle
[1][2] = instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
1777 ins
.swizzle
[1][3] = COMPONENT_X
;
1778 } else if (needs_temp_coord
) {
1779 /* mov coord_temp, coords */
1780 midgard_instruction mov
= v_mov(index
, coords
);
1781 mov
.mask
= coord_mask
;
1784 mov
.swizzle
[1][COMPONENT_W
] = COMPONENT_Z
;
1786 emit_mir_instruction(ctx
, mov
);
1791 ins
.src
[1] = coords
;
1792 ins
.src_types
[1] = T
;
1794 /* Texelfetch coordinates uses all four elements
1795 * (xyz/index) regardless of texture dimensionality,
1796 * which means it's necessary to zero the unused
1797 * components to keep everything happy */
1799 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1800 /* mov index.zw, #0, or generalized */
1801 midgard_instruction mov
=
1802 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), coords
);
1803 mov
.has_constants
= true;
1804 mov
.mask
= coord_mask
^ 0xF;
1805 emit_mir_instruction(ctx
, mov
);
1808 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) {
1809 /* Array component in w but NIR wants it in z,
1810 * but if we have a temp coord we already fixed
1813 if (nr_components
== 3) {
1814 ins
.swizzle
[1][2] = COMPONENT_Z
;
1815 ins
.swizzle
[1][3] = needs_temp_coord
? COMPONENT_W
: COMPONENT_Z
;
1816 } else if (nr_components
== 2) {
1818 instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
1819 ins
.swizzle
[1][3] = COMPONENT_X
;
1821 unreachable("Invalid texture 2D components");
1824 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1826 ins
.swizzle
[1][2] = COMPONENT_Z
;
1827 ins
.swizzle
[1][3] = COMPONENT_W
;
1833 case nir_tex_src_bias
:
1834 case nir_tex_src_lod
: {
1835 /* Try as a constant if we can */
1837 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
1838 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
1841 ins
.texture
.lod_register
= true;
1843 ins
.src_types
[2] = T
;
1845 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
1846 ins
.swizzle
[2][c
] = COMPONENT_X
;
1848 emit_explicit_constant(ctx
, index
, index
);
1853 case nir_tex_src_offset
: {
1854 ins
.texture
.offset_register
= true;
1856 ins
.src_types
[3] = T
;
1858 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
1859 ins
.swizzle
[3][c
] = (c
> COMPONENT_Z
) ? 0 : c
;
1861 emit_explicit_constant(ctx
, index
, index
);
1865 case nir_tex_src_comparator
: {
1866 unsigned comp
= COMPONENT_Z
;
1868 /* mov coord_temp.foo, coords */
1869 midgard_instruction mov
= v_mov(index
, coords
);
1870 mov
.mask
= 1 << comp
;
1872 for (unsigned i
= 0; i
< MIR_VEC_COMPONENTS
; ++i
)
1873 mov
.swizzle
[1][i
] = COMPONENT_X
;
1875 emit_mir_instruction(ctx
, mov
);
1880 fprintf(stderr
, "Unknown texture source type: %d\n", instr
->src
[i
].src_type
);
1886 emit_mir_instruction(ctx
, ins
);
1890 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1892 switch (instr
->op
) {
1895 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
1898 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
1901 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
1904 emit_sysval_read(ctx
, &instr
->instr
, 4, 0);
1907 fprintf(stderr
, "Unhandled texture op: %d\n", instr
->op
);
1914 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1916 switch (instr
->type
) {
1917 case nir_jump_break
: {
1918 /* Emit a branch out of the loop */
1919 struct midgard_instruction br
= v_branch(false, false);
1920 br
.branch
.target_type
= TARGET_BREAK
;
1921 br
.branch
.target_break
= ctx
->current_loop_depth
;
1922 emit_mir_instruction(ctx
, br
);
1927 DBG("Unknown jump type %d\n", instr
->type
);
1933 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1935 switch (instr
->type
) {
1936 case nir_instr_type_load_const
:
1937 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1940 case nir_instr_type_intrinsic
:
1941 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1944 case nir_instr_type_alu
:
1945 emit_alu(ctx
, nir_instr_as_alu(instr
));
1948 case nir_instr_type_tex
:
1949 emit_tex(ctx
, nir_instr_as_tex(instr
));
1952 case nir_instr_type_jump
:
1953 emit_jump(ctx
, nir_instr_as_jump(instr
));
1956 case nir_instr_type_ssa_undef
:
1961 DBG("Unhandled instruction type\n");
1967 /* ALU instructions can inline or embed constants, which decreases register
1968 * pressure and saves space. */
1970 #define CONDITIONAL_ATTACH(idx) { \
1971 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
1974 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
1975 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1980 inline_alu_constants(compiler_context
*ctx
, midgard_block
*block
)
1982 mir_foreach_instr_in_block(block
, alu
) {
1983 /* Other instructions cannot inline constants */
1984 if (alu
->type
!= TAG_ALU_4
) continue;
1985 if (alu
->compact_branch
) continue;
1987 /* If there is already a constant here, we can do nothing */
1988 if (alu
->has_constants
) continue;
1990 CONDITIONAL_ATTACH(0);
1992 if (!alu
->has_constants
) {
1993 CONDITIONAL_ATTACH(1)
1994 } else if (!alu
->inline_constant
) {
1995 /* Corner case: _two_ vec4 constants, for instance with a
1996 * csel. For this case, we can only use a constant
1997 * register for one, we'll have to emit a move for the
2000 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->src
[1] + 1);
2001 unsigned scratch
= make_compiler_temp(ctx
);
2004 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), scratch
);
2005 attach_constants(ctx
, &ins
, entry
, alu
->src
[1] + 1);
2007 /* Set the source */
2008 alu
->src
[1] = scratch
;
2010 /* Inject us -before- the last instruction which set r31 */
2011 mir_insert_instruction_before(ctx
, mir_prev_op(alu
), ins
);
2017 /* Midgard supports two types of constants, embedded constants (128-bit) and
2018 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2019 * constants can be demoted to inline constants, for space savings and
2020 * sometimes a performance boost */
2023 embedded_to_inline_constant(compiler_context
*ctx
, midgard_block
*block
)
2025 mir_foreach_instr_in_block(block
, ins
) {
2026 if (!ins
->has_constants
) continue;
2027 if (ins
->has_inline_constant
) continue;
2029 /* Blend constants must not be inlined by definition */
2030 if (ins
->has_blend_constant
) continue;
2032 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2033 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
2034 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
2036 if (!(is_16
|| is_32
))
2039 /* src1 cannot be an inline constant due to encoding
2040 * restrictions. So, if possible we try to flip the arguments
2043 int op
= ins
->alu
.op
;
2045 if (ins
->src
[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
) &&
2046 alu_opcode_props
[op
].props
& OP_COMMUTES
) {
2050 if (ins
->src
[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2051 /* Extract the source information */
2053 midgard_vector_alu_src
*src
;
2054 int q
= ins
->alu
.src2
;
2055 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2058 /* Component is from the swizzle. Take a nonzero component */
2060 unsigned first_comp
= ffs(ins
->mask
) - 1;
2061 unsigned component
= ins
->swizzle
[1][first_comp
];
2063 /* Scale constant appropriately, if we can legally */
2064 uint16_t scaled_constant
= 0;
2067 scaled_constant
= ins
->constants
.u16
[component
];
2068 } else if (midgard_is_integer_op(op
)) {
2069 scaled_constant
= ins
->constants
.u32
[component
];
2071 /* Constant overflow after resize */
2072 if (scaled_constant
!= ins
->constants
.u32
[component
])
2075 float original
= ins
->constants
.f32
[component
];
2076 scaled_constant
= _mesa_float_to_half(original
);
2078 /* Check for loss of precision. If this is
2079 * mediump, we don't care, but for a highp
2080 * shader, we need to pay attention. NIR
2081 * doesn't yet tell us which mode we're in!
2082 * Practically this prevents most constants
2083 * from being inlined, sadly. */
2085 float fp32
= _mesa_half_to_float(scaled_constant
);
2087 if (fp32
!= original
)
2091 /* We don't know how to handle these with a constant */
2093 if (mir_nontrivial_source2_mod_simple(ins
) || src
->rep_low
|| src
->rep_high
) {
2094 DBG("Bailing inline constant...\n");
2098 /* Make sure that the constant is not itself a vector
2099 * by checking if all accessed values are the same. */
2101 const midgard_constants
*cons
= &ins
->constants
;
2102 uint32_t value
= is_16
? cons
->u16
[component
] : cons
->u32
[component
];
2104 bool is_vector
= false;
2105 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
2107 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
) {
2108 /* We only care if this component is actually used */
2109 if (!(mask
& (1 << c
)))
2112 uint32_t test
= is_16
?
2113 cons
->u16
[ins
->swizzle
[1][c
]] :
2114 cons
->u32
[ins
->swizzle
[1][c
]];
2116 if (test
!= value
) {
2125 /* Get rid of the embedded constant */
2126 ins
->has_constants
= false;
2128 ins
->has_inline_constant
= true;
2129 ins
->inline_constant
= scaled_constant
;
2134 /* Dead code elimination for branches at the end of a block - only one branch
2135 * per block is legal semantically */
2138 midgard_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
2140 bool branched
= false;
2142 mir_foreach_instr_in_block_safe(block
, ins
) {
2143 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2146 mir_remove_instruction(ins
);
2153 emit_fragment_epilogue(compiler_context
*ctx
, unsigned rt
)
2155 /* Loop to ourselves */
2156 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
2157 struct midgard_instruction ins
= v_branch(false, false);
2158 ins
.writeout
= true;
2159 ins
.writeout_depth
= br
->writeout_depth
;
2160 ins
.writeout_stencil
= br
->writeout_stencil
;
2161 ins
.branch
.target_block
= ctx
->block_count
- 1;
2162 ins
.constants
.u32
[0] = br
->constants
.u32
[0];
2163 emit_mir_instruction(ctx
, ins
);
2165 ctx
->current_block
->epilogue
= true;
2166 schedule_barrier(ctx
);
2167 return ins
.branch
.target_block
;
2170 static midgard_block
*
2171 emit_block(compiler_context
*ctx
, nir_block
*block
)
2173 midgard_block
*this_block
= ctx
->after_block
;
2174 ctx
->after_block
= NULL
;
2177 this_block
= create_empty_block(ctx
);
2179 list_addtail(&this_block
->base
.link
, &ctx
->blocks
);
2181 this_block
->scheduled
= false;
2184 /* Set up current block */
2185 list_inithead(&this_block
->base
.instructions
);
2186 ctx
->current_block
= this_block
;
2188 nir_foreach_instr(instr
, block
) {
2189 emit_instr(ctx
, instr
);
2190 ++ctx
->instruction_count
;
2196 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2199 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2201 midgard_block
*before_block
= ctx
->current_block
;
2203 /* Speculatively emit the branch, but we can't fill it in until later */
2204 EMIT(branch
, true, true);
2205 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2206 then_branch
->src
[0] = nir_src_index(ctx
, &nif
->condition
);
2207 then_branch
->src_types
[0] = nir_type_uint32
;
2209 /* Emit the two subblocks. */
2210 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2211 midgard_block
*end_then_block
= ctx
->current_block
;
2213 /* Emit a jump from the end of the then block to the end of the else */
2214 EMIT(branch
, false, false);
2215 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2217 /* Emit second block, and check if it's empty */
2219 int else_idx
= ctx
->block_count
;
2220 int count_in
= ctx
->instruction_count
;
2221 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2222 midgard_block
*end_else_block
= ctx
->current_block
;
2223 int after_else_idx
= ctx
->block_count
;
2225 /* Now that we have the subblocks emitted, fix up the branches */
2230 if (ctx
->instruction_count
== count_in
) {
2231 /* The else block is empty, so don't emit an exit jump */
2232 mir_remove_instruction(then_exit
);
2233 then_branch
->branch
.target_block
= after_else_idx
;
2235 then_branch
->branch
.target_block
= else_idx
;
2236 then_exit
->branch
.target_block
= after_else_idx
;
2239 /* Wire up the successors */
2241 ctx
->after_block
= create_empty_block(ctx
);
2243 pan_block_add_successor(&before_block
->base
, &then_block
->base
);
2244 pan_block_add_successor(&before_block
->base
, &else_block
->base
);
2246 pan_block_add_successor(&end_then_block
->base
, &ctx
->after_block
->base
);
2247 pan_block_add_successor(&end_else_block
->base
, &ctx
->after_block
->base
);
2251 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2253 /* Remember where we are */
2254 midgard_block
*start_block
= ctx
->current_block
;
2256 /* Allocate a loop number, growing the current inner loop depth */
2257 int loop_idx
= ++ctx
->current_loop_depth
;
2259 /* Get index from before the body so we can loop back later */
2260 int start_idx
= ctx
->block_count
;
2262 /* Emit the body itself */
2263 midgard_block
*loop_block
= emit_cf_list(ctx
, &nloop
->body
);
2265 /* Branch back to loop back */
2266 struct midgard_instruction br_back
= v_branch(false, false);
2267 br_back
.branch
.target_block
= start_idx
;
2268 emit_mir_instruction(ctx
, br_back
);
2270 /* Mark down that branch in the graph. */
2271 pan_block_add_successor(&start_block
->base
, &loop_block
->base
);
2272 pan_block_add_successor(&ctx
->current_block
->base
, &loop_block
->base
);
2274 /* Find the index of the block about to follow us (note: we don't add
2275 * one; blocks are 0-indexed so we get a fencepost problem) */
2276 int break_block_idx
= ctx
->block_count
;
2278 /* Fix up the break statements we emitted to point to the right place,
2279 * now that we can allocate a block number for them */
2280 ctx
->after_block
= create_empty_block(ctx
);
2282 mir_foreach_block_from(ctx
, start_block
, _block
) {
2283 mir_foreach_instr_in_block(((midgard_block
*) _block
), ins
) {
2284 if (ins
->type
!= TAG_ALU_4
) continue;
2285 if (!ins
->compact_branch
) continue;
2287 /* We found a branch -- check the type to see if we need to do anything */
2288 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2290 /* It's a break! Check if it's our break */
2291 if (ins
->branch
.target_break
!= loop_idx
) continue;
2293 /* Okay, cool, we're breaking out of this loop.
2294 * Rewrite from a break to a goto */
2296 ins
->branch
.target_type
= TARGET_GOTO
;
2297 ins
->branch
.target_block
= break_block_idx
;
2299 pan_block_add_successor(_block
, &ctx
->after_block
->base
);
2303 /* Now that we've finished emitting the loop, free up the depth again
2304 * so we play nice with recursion amid nested loops */
2305 --ctx
->current_loop_depth
;
2307 /* Dump loop stats */
2311 static midgard_block
*
2312 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2314 midgard_block
*start_block
= NULL
;
2316 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2317 switch (node
->type
) {
2318 case nir_cf_node_block
: {
2319 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2322 start_block
= block
;
2327 case nir_cf_node_if
:
2328 emit_if(ctx
, nir_cf_node_as_if(node
));
2331 case nir_cf_node_loop
:
2332 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2335 case nir_cf_node_function
:
2344 /* Due to lookahead, we need to report the first tag executed in the command
2345 * stream and in branch targets. An initial block might be empty, so iterate
2346 * until we find one that 'works' */
2349 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2351 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2353 mir_foreach_block_from(ctx
, initial_block
, _v
) {
2354 midgard_block
*v
= (midgard_block
*) _v
;
2355 if (v
->quadword_count
) {
2356 midgard_bundle
*initial_bundle
=
2357 util_dynarray_element(&v
->bundles
, midgard_bundle
, 0);
2359 return initial_bundle
->tag
;
2363 /* Default to a tag 1 which will break from the shader, in case we jump
2364 * to the exit block (i.e. `return` in a compute shader) */
2369 /* For each fragment writeout instruction, generate a writeout loop to
2370 * associate with it */
2373 mir_add_writeout_loops(compiler_context
*ctx
)
2375 for (unsigned rt
= 0; rt
< ARRAY_SIZE(ctx
->writeout_branch
); ++rt
) {
2376 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
2379 unsigned popped
= br
->branch
.target_block
;
2380 pan_block_add_successor(&(mir_get_block(ctx
, popped
- 1)->base
), &ctx
->current_block
->base
);
2381 br
->branch
.target_block
= emit_fragment_epilogue(ctx
, rt
);
2382 br
->branch
.target_type
= TARGET_GOTO
;
2384 /* If we have more RTs, we'll need to restore back after our
2385 * loop terminates */
2387 if ((rt
+ 1) < ARRAY_SIZE(ctx
->writeout_branch
) && ctx
->writeout_branch
[rt
+ 1]) {
2388 midgard_instruction uncond
= v_branch(false, false);
2389 uncond
.branch
.target_block
= popped
;
2390 uncond
.branch
.target_type
= TARGET_GOTO
;
2391 emit_mir_instruction(ctx
, uncond
);
2392 pan_block_add_successor(&ctx
->current_block
->base
, &(mir_get_block(ctx
, popped
)->base
));
2393 schedule_barrier(ctx
);
2395 /* We're last, so we can terminate here */
2396 br
->last_writeout
= true;
2402 midgard_compile_shader_nir(nir_shader
*nir
, panfrost_program
*program
, bool is_blend
, unsigned blend_rt
, unsigned gpu_id
, bool shaderdb
)
2404 struct util_dynarray
*compiled
= &program
->compiled
;
2406 midgard_debug
= debug_get_option_midgard_debug();
2408 /* TODO: Bound against what? */
2409 compiler_context
*ctx
= rzalloc(NULL
, compiler_context
);
2412 ctx
->stage
= nir
->info
.stage
;
2413 ctx
->is_blend
= is_blend
;
2414 ctx
->alpha_ref
= program
->alpha_ref
;
2415 ctx
->blend_rt
= MIDGARD_COLOR_RT0
+ blend_rt
;
2416 ctx
->quirks
= midgard_get_quirks(gpu_id
);
2418 /* Start off with a safe cutoff, allowing usage of all 16 work
2419 * registers. Later, we'll promote uniform reads to uniform registers
2420 * if we determine it is beneficial to do so */
2421 ctx
->uniform_cutoff
= 8;
2423 /* Initialize at a global (not block) level hash tables */
2425 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2426 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2428 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2429 * (so we don't accidentally duplicate the epilogue since mesa/st has
2430 * messed with our I/O quite a bit already) */
2432 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2434 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2435 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2436 NIR_PASS_V(nir
, nir_lower_point_size
, 1.0, 1024.0);
2439 NIR_PASS_V(nir
, nir_lower_var_copies
);
2440 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2441 NIR_PASS_V(nir
, nir_split_var_copies
);
2442 NIR_PASS_V(nir
, nir_lower_var_copies
);
2443 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2444 NIR_PASS_V(nir
, nir_lower_var_copies
);
2445 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2447 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2448 NIR_PASS_V(nir
, nir_lower_ssbo
);
2449 NIR_PASS_V(nir
, midgard_nir_lower_zs_store
);
2451 /* Optimisation passes */
2453 optimise_nir(nir
, ctx
->quirks
);
2455 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2456 nir_print_shader(nir
, stdout
);
2459 /* Assign sysvals and counts, now that we're sure
2460 * (post-optimisation) */
2462 panfrost_nir_assign_sysvals(&ctx
->sysvals
, nir
);
2463 program
->sysval_count
= ctx
->sysvals
.sysval_count
;
2464 memcpy(program
->sysvals
, ctx
->sysvals
.sysvals
, sizeof(ctx
->sysvals
.sysvals
[0]) * ctx
->sysvals
.sysval_count
);
2466 nir_foreach_function(func
, nir
) {
2470 list_inithead(&ctx
->blocks
);
2471 ctx
->block_count
= 0;
2474 emit_cf_list(ctx
, &func
->impl
->body
);
2475 break; /* TODO: Multi-function shaders */
2478 util_dynarray_init(compiled
, NULL
);
2480 /* Per-block lowering before opts */
2482 mir_foreach_block(ctx
, _block
) {
2483 midgard_block
*block
= (midgard_block
*) _block
;
2484 inline_alu_constants(ctx
, block
);
2485 midgard_opt_promote_fmov(ctx
, block
);
2486 embedded_to_inline_constant(ctx
, block
);
2488 /* MIR-level optimizations */
2490 bool progress
= false;
2495 mir_foreach_block(ctx
, _block
) {
2496 midgard_block
*block
= (midgard_block
*) _block
;
2497 progress
|= midgard_opt_copy_prop(ctx
, block
);
2498 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2499 progress
|= midgard_opt_combine_projection(ctx
, block
);
2500 progress
|= midgard_opt_varying_projection(ctx
, block
);
2501 progress
|= midgard_opt_not_propagate(ctx
, block
);
2502 progress
|= midgard_opt_fuse_src_invert(ctx
, block
);
2503 progress
|= midgard_opt_fuse_dest_invert(ctx
, block
);
2504 progress
|= midgard_opt_csel_invert(ctx
, block
);
2505 progress
|= midgard_opt_drop_cmp_invert(ctx
, block
);
2506 progress
|= midgard_opt_invert_branch(ctx
, block
);
2510 mir_foreach_block(ctx
, _block
) {
2511 midgard_block
*block
= (midgard_block
*) _block
;
2512 midgard_lower_invert(ctx
, block
);
2513 midgard_lower_derivatives(ctx
, block
);
2516 /* Nested control-flow can result in dead branches at the end of the
2517 * block. This messes with our analysis and is just dead code, so cull
2519 mir_foreach_block(ctx
, _block
) {
2520 midgard_block
*block
= (midgard_block
*) _block
;
2521 midgard_cull_dead_branch(ctx
, block
);
2524 /* Ensure we were lowered */
2525 mir_foreach_instr_global(ctx
, ins
) {
2526 assert(!ins
->invert
);
2529 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
2530 mir_add_writeout_loops(ctx
);
2532 /* Analyze now that the code is known but before scheduling creates
2533 * pipeline registers which are harder to track */
2534 mir_analyze_helper_terminate(ctx
);
2535 mir_analyze_helper_requirements(ctx
);
2538 midgard_schedule_program(ctx
);
2541 /* Now that all the bundles are scheduled and we can calculate block
2542 * sizes, emit actual branch instructions rather than placeholders */
2544 int br_block_idx
= 0;
2546 mir_foreach_block(ctx
, _block
) {
2547 midgard_block
*block
= (midgard_block
*) _block
;
2548 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2549 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2550 midgard_instruction
*ins
= bundle
->instructions
[c
];
2552 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2554 /* Parse some basic branch info */
2555 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2556 bool is_conditional
= ins
->branch
.conditional
;
2557 bool is_inverted
= ins
->branch
.invert_conditional
;
2558 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2559 bool is_writeout
= ins
->writeout
;
2561 /* Determine the block we're jumping to */
2562 int target_number
= ins
->branch
.target_block
;
2564 /* Report the destination tag */
2565 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2567 /* Count up the number of quadwords we're
2568 * jumping over = number of quadwords until
2569 * (br_block_idx, target_number) */
2571 int quadword_offset
= 0;
2575 } else if (target_number
> br_block_idx
) {
2578 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2579 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2582 quadword_offset
+= blk
->quadword_count
;
2585 /* Jump backwards */
2587 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2588 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2591 quadword_offset
-= blk
->quadword_count
;
2595 /* Unconditional extended branches (far jumps)
2596 * have issues, so we always use a conditional
2597 * branch, setting the condition to always for
2598 * unconditional. For compact unconditional
2599 * branches, cond isn't used so it doesn't
2600 * matter what we pick. */
2602 midgard_condition cond
=
2603 !is_conditional
? midgard_condition_always
:
2604 is_inverted
? midgard_condition_false
:
2605 midgard_condition_true
;
2607 midgard_jmp_writeout_op op
=
2608 is_discard
? midgard_jmp_writeout_op_discard
:
2609 is_writeout
? midgard_jmp_writeout_op_writeout
:
2610 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2611 midgard_jmp_writeout_op_branch_cond
;
2614 midgard_branch_extended branch
=
2615 midgard_create_branch_extended(
2620 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2621 } else if (is_conditional
|| is_discard
) {
2622 midgard_branch_cond branch
= {
2624 .dest_tag
= dest_tag
,
2625 .offset
= quadword_offset
,
2629 assert(branch
.offset
== quadword_offset
);
2631 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2633 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2635 midgard_branch_uncond branch
= {
2637 .dest_tag
= dest_tag
,
2638 .offset
= quadword_offset
,
2642 assert(branch
.offset
== quadword_offset
);
2644 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2652 /* Emit flat binary from the instruction arrays. Iterate each block in
2653 * sequence. Save instruction boundaries such that lookahead tags can
2654 * be assigned easily */
2656 /* Cache _all_ bundles in source order for lookahead across failed branches */
2658 int bundle_count
= 0;
2659 mir_foreach_block(ctx
, _block
) {
2660 midgard_block
*block
= (midgard_block
*) _block
;
2661 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2663 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2665 mir_foreach_block(ctx
, _block
) {
2666 midgard_block
*block
= (midgard_block
*) _block
;
2667 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2668 source_order_bundles
[bundle_idx
++] = bundle
;
2672 int current_bundle
= 0;
2674 /* Midgard prefetches instruction types, so during emission we
2675 * need to lookahead. Unless this is the last instruction, in
2676 * which we return 1. */
2678 mir_foreach_block(ctx
, _block
) {
2679 midgard_block
*block
= (midgard_block
*) _block
;
2680 mir_foreach_bundle_in_block(block
, bundle
) {
2683 if (!bundle
->last_writeout
&& (current_bundle
+ 1 < bundle_count
))
2684 lookahead
= source_order_bundles
[current_bundle
+ 1]->tag
;
2686 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2690 /* TODO: Free deeper */
2691 //util_dynarray_fini(&block->instructions);
2694 free(source_order_bundles
);
2696 /* Report the very first tag executed */
2697 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2699 /* Deal with off-by-one related to the fencepost problem */
2700 program
->work_register_count
= ctx
->work_registers
+ 1;
2701 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2703 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2704 program
->tls_size
= ctx
->tls_size
;
2706 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2707 disassemble_midgard(stdout
, program
->compiled
.data
, program
->compiled
.size
, gpu_id
, ctx
->stage
);
2709 if (midgard_debug
& MIDGARD_DBG_SHADERDB
|| shaderdb
) {
2710 unsigned nr_bundles
= 0, nr_ins
= 0;
2712 /* Count instructions and bundles */
2714 mir_foreach_block(ctx
, _block
) {
2715 midgard_block
*block
= (midgard_block
*) _block
;
2716 nr_bundles
+= util_dynarray_num_elements(
2717 &block
->bundles
, midgard_bundle
);
2719 mir_foreach_bundle_in_block(block
, bun
)
2720 nr_ins
+= bun
->instruction_count
;
2723 /* Calculate thread count. There are certain cutoffs by
2724 * register count for thread count */
2726 unsigned nr_registers
= program
->work_register_count
;
2728 unsigned nr_threads
=
2729 (nr_registers
<= 4) ? 4 :
2730 (nr_registers
<= 8) ? 2 :
2735 fprintf(stderr
, "shader%d - %s shader: "
2736 "%u inst, %u bundles, %u quadwords, "
2737 "%u registers, %u threads, %u loops, "
2738 "%u:%u spills:fills\n",
2740 gl_shader_stage_name(ctx
->stage
),
2741 nr_ins
, nr_bundles
, ctx
->quadword_count
,
2742 nr_registers
, nr_threads
,
2744 ctx
->spills
, ctx
->fills
);