projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
pan/mdg: Fold roundmode into applicable instructions
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 i.dest_type = T; \
121 } else { \
122 i.dest = ssa; \
123 i.dest_type = T; \
124 } \
125 return i; \
126 }
127
128 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
129 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
130
131 M_LOAD(ld_attr_32, nir_type_uint32);
132 M_LOAD(ld_vary_32, nir_type_uint32);
133 M_LOAD(ld_ubo_int4, nir_type_uint32);
134 M_LOAD(ld_int4, nir_type_uint32);
135 M_STORE(st_int4, nir_type_uint32);
136 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
137 M_STORE(st_vary_32, nir_type_uint32);
138 M_LOAD(ld_cubemap_coords, nir_type_uint32);
139 M_LOAD(ld_compute_id, nir_type_uint32);
140
141 static midgard_instruction
142 v_branch(bool conditional, bool invert)
143 {
144 midgard_instruction ins = {
145 .type = TAG_ALU_4,
146 .unit = ALU_ENAB_BRANCH,
147 .compact_branch = true,
148 .branch = {
149 .conditional = conditional,
150 .invert_conditional = invert
151 },
152 .dest = ~0,
153 .src = { ~0, ~0, ~0, ~0 },
154 };
155
156 return ins;
157 }
158
159 static midgard_branch_extended
160 midgard_create_branch_extended( midgard_condition cond,
161 midgard_jmp_writeout_op op,
162 unsigned dest_tag,
163 signed quadword_offset)
164 {
165 /* The condition code is actually a LUT describing a function to
166 * combine multiple condition codes. However, we only support a single
167 * condition code at the moment, so we just duplicate over a bunch of
168 * times. */
169
170 uint16_t duplicated_cond =
171 (cond << 14) |
172 (cond << 12) |
173 (cond << 10) |
174 (cond << 8) |
175 (cond << 6) |
176 (cond << 4) |
177 (cond << 2) |
178 (cond << 0);
179
180 midgard_branch_extended branch = {
181 .op = op,
182 .dest_tag = dest_tag,
183 .offset = quadword_offset,
184 .cond = duplicated_cond
185 };
186
187 return branch;
188 }
189
190 static void
191 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
192 {
193 ins->has_constants = true;
194 memcpy(&ins->constants, constants, 16);
195 }
196
197 static int
198 glsl_type_size(const struct glsl_type *type, bool bindless)
199 {
200 return glsl_count_attribute_slots(type, false);
201 }
202
203 /* Lower fdot2 to a vector multiplication followed by channel addition */
204 static void
205 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
206 {
207 if (alu->op != nir_op_fdot2)
208 return;
209
210 b->cursor = nir_before_instr(&alu->instr);
211
212 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
213 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
214
215 nir_ssa_def *product = nir_fmul(b, src0, src1);
216
217 nir_ssa_def *sum = nir_fadd(b,
218 nir_channel(b, product, 0),
219 nir_channel(b, product, 1));
220
221 /* Replace the fdot2 with this sum */
222 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
223 }
224
225 static bool
226 midgard_nir_lower_fdot2(nir_shader *shader)
227 {
228 bool progress = false;
229
230 nir_foreach_function(function, shader) {
231 if (!function->impl) continue;
232
233 nir_builder _b;
234 nir_builder *b = &_b;
235 nir_builder_init(b, function->impl);
236
237 nir_foreach_block(block, function->impl) {
238 nir_foreach_instr_safe(instr, block) {
239 if (instr->type != nir_instr_type_alu) continue;
240
241 nir_alu_instr *alu = nir_instr_as_alu(instr);
242 midgard_nir_lower_fdot2_body(b, alu);
243
244 progress |= true;
245 }
246 }
247
248 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
249
250 }
251
252 return progress;
253 }
254
255 /* Midgard can't write depth and stencil separately. It has to happen in a
256 * single store operation containing both. Let's add a panfrost specific
257 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
258 * one.
259 */
260 static bool
261 midgard_nir_lower_zs_store(nir_shader *nir)
262 {
263 if (nir->info.stage != MESA_SHADER_FRAGMENT)
264 return false;
265
266 nir_variable *z_var = NULL, *s_var = NULL;
267
268 nir_foreach_variable(var, &nir->outputs) {
269 if (var->data.location == FRAG_RESULT_DEPTH)
270 z_var = var;
271 else if (var->data.location == FRAG_RESULT_STENCIL)
272 s_var = var;
273 }
274
275 if (!z_var && !s_var)
276 return false;
277
278 bool progress = false;
279
280 nir_foreach_function(function, nir) {
281 if (!function->impl) continue;
282
283 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
284
285 nir_foreach_block(block, function->impl) {
286 nir_foreach_instr_safe(instr, block) {
287 if (instr->type != nir_instr_type_intrinsic)
288 continue;
289
290 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
291 if (intr->intrinsic != nir_intrinsic_store_output)
292 continue;
293
294 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
295 assert(!z_store);
296 z_store = intr;
297 last_store = intr;
298 }
299
300 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
301 assert(!s_store);
302 s_store = intr;
303 last_store = intr;
304 }
305 }
306 }
307
308 if (!z_store && !s_store) continue;
309
310 nir_builder b;
311 nir_builder_init(&b, function->impl);
312
313 b.cursor = nir_before_instr(&last_store->instr);
314
315 nir_ssa_def *zs_store_src;
316
317 if (z_store && s_store) {
318 nir_ssa_def *srcs[2] = {
319 nir_ssa_for_src(&b, z_store->src[0], 1),
320 nir_ssa_for_src(&b, s_store->src[0], 1),
321 };
322
323 zs_store_src = nir_vec(&b, srcs, 2);
324 } else {
325 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
326 }
327
328 nir_intrinsic_instr *zs_store;
329
330 zs_store = nir_intrinsic_instr_create(b.shader,
331 nir_intrinsic_store_zs_output_pan);
332 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
333 zs_store->num_components = z_store && s_store ? 2 : 1;
334 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
335
336 /* Replace the Z and S store by a ZS store */
337 nir_builder_instr_insert(&b, &zs_store->instr);
338
339 if (z_store)
340 nir_instr_remove(&z_store->instr);
341
342 if (s_store)
343 nir_instr_remove(&s_store->instr);
344
345 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
346 progress = true;
347 }
348
349 return progress;
350 }
351
352 /* Flushes undefined values to zero */
353
354 static void
355 optimise_nir(nir_shader *nir, unsigned quirks, bool is_blend)
356 {
357 bool progress;
358 unsigned lower_flrp =
359 (nir->options->lower_flrp16 ? 16 : 0) |
360 (nir->options->lower_flrp32 ? 32 : 0) |
361 (nir->options->lower_flrp64 ? 64 : 0);
362
363 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
364 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
365
366 nir_lower_tex_options lower_tex_options = {
367 .lower_txs_lod = true,
368 .lower_txp = ~0,
369 .lower_tex_without_implicit_lod =
370 (quirks & MIDGARD_EXPLICIT_LOD),
371
372 /* TODO: we have native gradient.. */
373 .lower_txd = true,
374 };
375
376 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
377
378 /* Must lower fdot2 after tex is lowered */
379 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
380
381 /* T720 is broken. */
382
383 if (quirks & MIDGARD_BROKEN_LOD)
384 NIR_PASS_V(nir, midgard_nir_lod_errata);
385
386 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_early);
387
388 if (!is_blend)
389 NIR_PASS(progress, nir, nir_fuse_io_16);
390
391 do {
392 progress = false;
393
394 NIR_PASS(progress, nir, nir_lower_var_copies);
395 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
396
397 NIR_PASS(progress, nir, nir_copy_prop);
398 NIR_PASS(progress, nir, nir_opt_remove_phis);
399 NIR_PASS(progress, nir, nir_opt_dce);
400 NIR_PASS(progress, nir, nir_opt_dead_cf);
401 NIR_PASS(progress, nir, nir_opt_cse);
402 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
403 NIR_PASS(progress, nir, nir_opt_algebraic);
404 NIR_PASS(progress, nir, nir_opt_constant_folding);
405
406 if (lower_flrp != 0) {
407 bool lower_flrp_progress = false;
408 NIR_PASS(lower_flrp_progress,
409 nir,
410 nir_lower_flrp,
411 lower_flrp,
412 false /* always_precise */,
413 nir->options->lower_ffma);
414 if (lower_flrp_progress) {
415 NIR_PASS(progress, nir,
416 nir_opt_constant_folding);
417 progress = true;
418 }
419
420 /* Nothing should rematerialize any flrps, so we only
421 * need to do this lowering once.
422 */
423 lower_flrp = 0;
424 }
425
426 NIR_PASS(progress, nir, nir_opt_undef);
427 NIR_PASS(progress, nir, nir_undef_to_zero);
428
429 NIR_PASS(progress, nir, nir_opt_loop_unroll,
430 nir_var_shader_in |
431 nir_var_shader_out |
432 nir_var_function_temp);
433
434 NIR_PASS(progress, nir, nir_opt_vectorize);
435 } while (progress);
436
437 /* Must be run at the end to prevent creation of fsin/fcos ops */
438 NIR_PASS(progress, nir, midgard_nir_scale_trig);
439
440 do {
441 progress = false;
442
443 NIR_PASS(progress, nir, nir_opt_dce);
444 NIR_PASS(progress, nir, nir_opt_algebraic);
445 NIR_PASS(progress, nir, nir_opt_constant_folding);
446 NIR_PASS(progress, nir, nir_copy_prop);
447 } while (progress);
448
449 NIR_PASS(progress, nir, nir_opt_algebraic_late);
450 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
451
452 /* We implement booleans as 32-bit 0/~0 */
453 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
454
455 /* Now that booleans are lowered, we can run out late opts */
456 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
457 NIR_PASS(progress, nir, midgard_nir_cancel_inot);
458
459 NIR_PASS(progress, nir, nir_copy_prop);
460 NIR_PASS(progress, nir, nir_opt_dce);
461
462 /* Take us out of SSA */
463 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
464 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
465
466 /* We are a vector architecture; write combine where possible */
467 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
468 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
469
470 NIR_PASS(progress, nir, nir_opt_dce);
471 }
472
473 /* Do not actually emit a load; instead, cache the constant for inlining */
474
475 static void
476 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
477 {
478 nir_ssa_def def = instr->def;
479
480 midgard_constants *consts = rzalloc(NULL, midgard_constants);
481
482 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
483
484 #define RAW_CONST_COPY(bits) \
485 nir_const_value_to_array(consts->u##bits, instr->value, \
486 instr->def.num_components, u##bits)
487
488 switch (instr->def.bit_size) {
489 case 64:
490 RAW_CONST_COPY(64);
491 break;
492 case 32:
493 RAW_CONST_COPY(32);
494 break;
495 case 16:
496 RAW_CONST_COPY(16);
497 break;
498 case 8:
499 RAW_CONST_COPY(8);
500 break;
501 default:
502 unreachable("Invalid bit_size for load_const instruction\n");
503 }
504
505 /* Shifted for SSA, +1 for off-by-one */
506 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
507 }
508
509 /* Normally constants are embedded implicitly, but for I/O and such we have to
510 * explicitly emit a move with the constant source */
511
512 static void
513 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
514 {
515 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
516
517 if (constant_value) {
518 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
519 attach_constants(ctx, &ins, constant_value, node + 1);
520 emit_mir_instruction(ctx, ins);
521 }
522 }
523
524 static bool
525 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
526 {
527 unsigned comp = src->swizzle[0];
528
529 for (unsigned c = 1; c < nr_components; ++c) {
530 if (src->swizzle[c] != comp)
531 return true;
532 }
533
534 return false;
535 }
536
537 #define ALU_CASE(nir, _op) \
538 case nir_op_##nir: \
539 op = midgard_alu_op_##_op; \
540 assert(src_bitsize == dst_bitsize); \
541 break;
542
543 #define ALU_CASE_RTZ(nir, _op) \
544 case nir_op_##nir: \
545 op = midgard_alu_op_##_op; \
546 roundmode = MIDGARD_RTZ; \
547 assert(src_bitsize == dst_bitsize); \
548 break;
549
550 #define ALU_CHECK_CMP(sext) \
551 assert(src_bitsize == 16 || src_bitsize == 32); \
552 assert(dst_bitsize == 16 || dst_bitsize == 32); \
553
554 #define ALU_CASE_BCAST(nir, _op, count) \
555 case nir_op_##nir: \
556 op = midgard_alu_op_##_op; \
557 broadcast_swizzle = count; \
558 ALU_CHECK_CMP(true); \
559 break;
560
561 #define ALU_CASE_CMP(nir, _op, sext) \
562 case nir_op_##nir: \
563 op = midgard_alu_op_##_op; \
564 ALU_CHECK_CMP(sext); \
565 break;
566
567 /* Analyze the sizes of the dest and inputs to determine reg mode. */
568
569 static midgard_reg_mode
570 reg_mode_for_nir(nir_alu_instr *instr)
571 {
572 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
573 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
574 unsigned max_bitsize = MAX2(src_bitsize, dst_bitsize);
575
576 /* We don't have fp16 LUTs, so we'll want to emit code like:
577 *
578 * vlut.fsinr hr0, hr0
579 *
580 * where both input and output are 16-bit but the operation is carried
581 * out in 32-bit
582 */
583
584 switch (instr->op) {
585 case nir_op_fsqrt:
586 case nir_op_frcp:
587 case nir_op_frsq:
588 case nir_op_fsin:
589 case nir_op_fcos:
590 case nir_op_fexp2:
591 case nir_op_flog2:
592 max_bitsize = MAX2(max_bitsize, 32);
593 break;
594
595 /* These get lowered to moves */
596 case nir_op_pack_32_4x8:
597 max_bitsize = 8;
598 break;
599 case nir_op_pack_32_2x16:
600 max_bitsize = 16;
601 break;
602 default:
603 break;
604 }
605
606
607 switch (max_bitsize) {
608 /* Use 16 pipe for 8 since we don't support vec16 yet */
609 case 8:
610 case 16:
611 return midgard_reg_mode_16;
612 case 32:
613 return midgard_reg_mode_32;
614 case 64:
615 return midgard_reg_mode_64;
616 default:
617 unreachable("Invalid bit size");
618 }
619 }
620
621 /* Compare mir_lower_invert */
622 static bool
623 nir_accepts_inot(nir_op op, unsigned src)
624 {
625 switch (op) {
626 case nir_op_ior:
627 case nir_op_iand: /* TODO: b2f16 */
628 case nir_op_ixor:
629 return true;
630 case nir_op_b32csel:
631 /* Only the condition */
632 return (src == 0);
633 default:
634 return false;
635 }
636 }
637
638 static bool
639 mir_accept_dest_mod(compiler_context *ctx, nir_dest **dest, nir_op op)
640 {
641 if (pan_has_dest_mod(dest, op)) {
642 assert((*dest)->is_ssa);
643 BITSET_SET(ctx->already_emitted, (*dest)->ssa.index);
644 return true;
645 }
646
647 return false;
648 }
649
650 static void
651 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool *not, enum midgard_roundmode *roundmode, bool is_int, unsigned bcast_count)
652 {
653 nir_alu_src src = instr->src[i];
654
655 if (!is_int) {
656 if (pan_has_source_mod(&src, nir_op_fneg))
657 *neg = !(*neg);
658
659 if (pan_has_source_mod(&src, nir_op_fabs))
660 *abs = true;
661 }
662
663 if (nir_accepts_inot(instr->op, i) && pan_has_source_mod(&src, nir_op_inot))
664 *not = true;
665
666 if (roundmode) {
667 if (pan_has_source_mod(&src, nir_op_fround_even))
668 *roundmode = MIDGARD_RTE;
669
670 if (pan_has_source_mod(&src, nir_op_ftrunc))
671 *roundmode = MIDGARD_RTZ;
672
673 if (pan_has_source_mod(&src, nir_op_ffloor))
674 *roundmode = MIDGARD_RTN;
675
676 if (pan_has_source_mod(&src, nir_op_fceil))
677 *roundmode = MIDGARD_RTP;
678 }
679
680 unsigned bits = nir_src_bit_size(src.src);
681
682 ins->src[to] = nir_src_index(NULL, &src.src);
683 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
684
685 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
686 ins->swizzle[to][c] = src.swizzle[
687 (!bcast_count || c < bcast_count) ? c :
688 (bcast_count - 1)];
689 }
690 }
691
692 /* Midgard features both fcsel and icsel, depending on whether you want int or
693 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
694 * we should emit an int or float csel depending on what modifiers could be
695 * placed. In the absense of modifiers, this is probably arbitrary. */
696
697 static bool
698 mir_is_bcsel_float(nir_alu_instr *instr)
699 {
700 nir_op intmods[] = {
701 nir_op_i2i8, nir_op_i2i16,
702 nir_op_i2i32, nir_op_i2i64
703 };
704
705 nir_op floatmods[] = {
706 nir_op_fabs, nir_op_fneg,
707 nir_op_f2f16, nir_op_f2f32,
708 nir_op_f2f64
709 };
710
711 nir_op floatdestmods[] = {
712 nir_op_fsat, nir_op_fsat_signed, nir_op_fclamp_pos,
713 nir_op_f2f16, nir_op_f2f32
714 };
715
716 signed score = 0;
717
718 for (unsigned i = 1; i < 3; ++i) {
719 nir_alu_src s = instr->src[i];
720 for (unsigned q = 0; q < ARRAY_SIZE(intmods); ++q) {
721 if (pan_has_source_mod(&s, intmods[q]))
722 score--;
723 }
724 }
725
726 for (unsigned i = 1; i < 3; ++i) {
727 nir_alu_src s = instr->src[i];
728 for (unsigned q = 0; q < ARRAY_SIZE(floatmods); ++q) {
729 if (pan_has_source_mod(&s, floatmods[q]))
730 score++;
731 }
732 }
733
734 for (unsigned q = 0; q < ARRAY_SIZE(floatdestmods); ++q) {
735 nir_dest *dest = &instr->dest.dest;
736 if (pan_has_dest_mod(&dest, floatdestmods[q]))
737 score++;
738 }
739
740 return (score > 0);
741 }
742
743 static void
744 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
745 {
746 nir_dest *dest = &instr->dest.dest;
747
748 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index))
749 return;
750
751 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
752 * is handled elsewhere */
753
754 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
755 midgard_emit_derivatives(ctx, instr);
756 return;
757 }
758
759 bool is_ssa = dest->is_ssa;
760
761 unsigned nr_components = nir_dest_num_components(*dest);
762 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
763 unsigned op = 0;
764
765 /* Number of components valid to check for the instruction (the rest
766 * will be forced to the last), or 0 to use as-is. Relevant as
767 * ball-type instructions have a channel count in NIR but are all vec4
768 * in Midgard */
769
770 unsigned broadcast_swizzle = 0;
771
772 /* What register mode should we operate in? */
773 midgard_reg_mode reg_mode =
774 reg_mode_for_nir(instr);
775
776 /* Should we swap arguments? */
777 bool flip_src12 = false;
778
779 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
780 unsigned dst_bitsize = nir_dest_bit_size(*dest);
781
782 enum midgard_roundmode roundmode = MIDGARD_RTE;
783
784 switch (instr->op) {
785 ALU_CASE(fadd, fadd);
786 ALU_CASE(fmul, fmul);
787 ALU_CASE(fmin, fmin);
788 ALU_CASE(fmax, fmax);
789 ALU_CASE(imin, imin);
790 ALU_CASE(imax, imax);
791 ALU_CASE(umin, umin);
792 ALU_CASE(umax, umax);
793 ALU_CASE(ffloor, ffloor);
794 ALU_CASE(fround_even, froundeven);
795 ALU_CASE(ftrunc, ftrunc);
796 ALU_CASE(fceil, fceil);
797 ALU_CASE(fdot3, fdot3);
798 ALU_CASE(fdot4, fdot4);
799 ALU_CASE(iadd, iadd);
800 ALU_CASE(isub, isub);
801 ALU_CASE(imul, imul);
802
803 /* Zero shoved as second-arg */
804 ALU_CASE(iabs, iabsdiff);
805
806 ALU_CASE(mov, imov);
807
808 ALU_CASE_CMP(feq32, feq, false);
809 ALU_CASE_CMP(fne32, fne, false);
810 ALU_CASE_CMP(flt32, flt, false);
811 ALU_CASE_CMP(ieq32, ieq, true);
812 ALU_CASE_CMP(ine32, ine, true);
813 ALU_CASE_CMP(ilt32, ilt, true);
814 ALU_CASE_CMP(ult32, ult, false);
815
816 /* We don't have a native b2f32 instruction. Instead, like many
817 * GPUs, we exploit booleans as 0/~0 for false/true, and
818 * correspondingly AND
819 * by 1.0 to do the type conversion. For the moment, prime us
820 * to emit:
821 *
822 * iand [whatever], #0
823 *
824 * At the end of emit_alu (as MIR), we'll fix-up the constant
825 */
826
827 ALU_CASE_CMP(b2f32, iand, true);
828 ALU_CASE_CMP(b2f16, iand, true);
829 ALU_CASE_CMP(b2i32, iand, true);
830
831 /* Likewise, we don't have a dedicated f2b32 instruction, but
832 * we can do a "not equal to 0.0" test. */
833
834 ALU_CASE_CMP(f2b32, fne, false);
835 ALU_CASE_CMP(i2b32, ine, true);
836
837 ALU_CASE(frcp, frcp);
838 ALU_CASE(frsq, frsqrt);
839 ALU_CASE(fsqrt, fsqrt);
840 ALU_CASE(fexp2, fexp2);
841 ALU_CASE(flog2, flog2);
842
843 ALU_CASE_RTZ(f2i64, f2i_rte);
844 ALU_CASE_RTZ(f2u64, f2u_rte);
845 ALU_CASE_RTZ(i2f64, i2f_rte);
846 ALU_CASE_RTZ(u2f64, u2f_rte);
847
848 ALU_CASE_RTZ(f2i32, f2i_rte);
849 ALU_CASE_RTZ(f2u32, f2u_rte);
850 ALU_CASE_RTZ(i2f32, i2f_rte);
851 ALU_CASE_RTZ(u2f32, u2f_rte);
852
853 ALU_CASE_RTZ(f2i16, f2i_rte);
854 ALU_CASE_RTZ(f2u16, f2u_rte);
855 ALU_CASE_RTZ(i2f16, i2f_rte);
856 ALU_CASE_RTZ(u2f16, u2f_rte);
857
858 ALU_CASE(fsin, fsin);
859 ALU_CASE(fcos, fcos);
860
861 /* We'll get 0 in the second arg, so:
862 * ~a = ~(a | 0) = nor(a, 0) */
863 ALU_CASE(inot, inor);
864 ALU_CASE(iand, iand);
865 ALU_CASE(ior, ior);
866 ALU_CASE(ixor, ixor);
867 ALU_CASE(ishl, ishl);
868 ALU_CASE(ishr, iasr);
869 ALU_CASE(ushr, ilsr);
870
871 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
872 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
873 ALU_CASE_CMP(b32all_fequal4, fball_eq, true);
874
875 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
876 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
877 ALU_CASE_CMP(b32any_fnequal4, fbany_neq, true);
878
879 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
880 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
881 ALU_CASE_CMP(b32all_iequal4, iball_eq, true);
882
883 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
884 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
885 ALU_CASE_CMP(b32any_inequal4, ibany_neq, true);
886
887 /* Source mods will be shoved in later */
888 ALU_CASE(fabs, fmov);
889 ALU_CASE(fneg, fmov);
890 ALU_CASE(fsat, fmov);
891 ALU_CASE(fsat_signed, fmov);
892 ALU_CASE(fclamp_pos, fmov);
893
894 /* For size conversion, we use a move. Ideally though we would squash
895 * these ops together; maybe that has to happen after in NIR as part of
896 * propagation...? An earlier algebraic pass ensured we step down by
897 * only / exactly one size. If stepping down, we use a dest override to
898 * reduce the size; if stepping up, we use a larger-sized move with a
899 * half source and a sign/zero-extension modifier */
900
901 case nir_op_i2i8:
902 case nir_op_i2i16:
903 case nir_op_i2i32:
904 case nir_op_i2i64:
905 case nir_op_u2u8:
906 case nir_op_u2u16:
907 case nir_op_u2u32:
908 case nir_op_u2u64:
909 case nir_op_f2f16:
910 case nir_op_f2f32:
911 case nir_op_f2f64: {
912 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
913 instr->op == nir_op_f2f64)
914 op = midgard_alu_op_fmov;
915 else
916 op = midgard_alu_op_imov;
917
918 break;
919 }
920
921 /* For greater-or-equal, we lower to less-or-equal and flip the
922 * arguments */
923
924 case nir_op_fge:
925 case nir_op_fge32:
926 case nir_op_ige32:
927 case nir_op_uge32: {
928 op =
929 instr->op == nir_op_fge ? midgard_alu_op_fle :
930 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
931 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
932 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
933 0;
934
935 flip_src12 = true;
936 ALU_CHECK_CMP(false);
937 break;
938 }
939
940 case nir_op_b32csel: {
941 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
942 bool is_float = mir_is_bcsel_float(instr);
943 op = is_float ?
944 (mixed ? midgard_alu_op_fcsel_v : midgard_alu_op_fcsel) :
945 (mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel);
946
947 break;
948 }
949
950 case nir_op_unpack_32_2x16:
951 case nir_op_unpack_32_4x8:
952 case nir_op_pack_32_2x16:
953 case nir_op_pack_32_4x8: {
954 op = midgard_alu_op_imov;
955 break;
956 }
957
958 default:
959 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
960 assert(0);
961 return;
962 }
963
964 /* Promote imov to fmov if it might help inline a constant */
965 if (op == midgard_alu_op_imov && nir_src_is_const(instr->src[0].src)
966 && nir_src_bit_size(instr->src[0].src) == 32
967 && nir_is_same_comp_swizzle(instr->src[0].swizzle,
968 nir_src_num_components(instr->src[0].src))) {
969 op = midgard_alu_op_fmov;
970 }
971
972 /* Midgard can perform certain modifiers on output of an ALU op */
973
974 unsigned outmod = 0;
975 bool is_int = midgard_is_integer_op(op);
976
977 if (midgard_is_integer_out_op(op)) {
978 outmod = midgard_outmod_int_wrap;
979 } else if (instr->op == nir_op_fsat) {
980 outmod = midgard_outmod_sat;
981 } else if (instr->op == nir_op_fsat_signed) {
982 outmod = midgard_outmod_sat_signed;
983 } else if (instr->op == nir_op_fclamp_pos) {
984 outmod = midgard_outmod_pos;
985 }
986
987 /* Fetch unit, quirks, etc information */
988 unsigned opcode_props = alu_opcode_props[op].props;
989 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
990
991 /* Look for floating point mods. We have the mods fsat, fsat_signed,
992 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
993 *
994 * fsat_signed(fpos(x)) = fsat(x)
995 * fsat_signed(fsat(x)) = fsat(x)
996 * fpos(fsat_signed(x)) = fsat(x)
997 * fpos(fsat(x)) = fsat(x)
998 * fsat(fsat_signed(x)) = fsat(x)
999 * fsat(fpos(x)) = fsat(x)
1000 *
1001 * So by cases any composition of output modifiers is equivalent to
1002 * fsat alone.
1003 */
1004
1005 if (!is_int && !(opcode_props & OP_TYPE_CONVERT)) {
1006 bool fpos = mir_accept_dest_mod(ctx, &dest, nir_op_fclamp_pos);
1007 bool fsat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat);
1008 bool ssat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat_signed);
1009 bool prior = (outmod != midgard_outmod_none);
1010 int count = (int) prior + (int) fpos + (int) ssat + (int) fsat;
1011
1012 outmod = ((count > 1) || fsat) ? midgard_outmod_sat :
1013 fpos ? midgard_outmod_pos :
1014 ssat ? midgard_outmod_sat_signed :
1015 outmod;
1016 }
1017
1018 midgard_instruction ins = {
1019 .type = TAG_ALU_4,
1020 .dest = nir_dest_index(dest),
1021 .dest_type = nir_op_infos[instr->op].output_type
1022 | nir_dest_bit_size(*dest),
1023 .roundmode = roundmode,
1024 };
1025
1026 enum midgard_roundmode *roundptr = (opcode_props & MIDGARD_ROUNDS) ?
1027 &ins.roundmode : NULL;
1028
1029 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
1030 ins.src[i] = ~0;
1031
1032 if (quirk_flipped_r24) {
1033 ins.src[0] = ~0;
1034 mir_copy_src(&ins, instr, 0, 1, &ins.src_abs[1], &ins.src_neg[1], &ins.src_invert[1], roundptr, is_int, broadcast_swizzle);
1035 } else {
1036 for (unsigned i = 0; i < nr_inputs; ++i) {
1037 unsigned to = i;
1038
1039 if (instr->op == nir_op_b32csel) {
1040 /* The condition is the first argument; move
1041 * the other arguments up one to be a binary
1042 * instruction for Midgard with the condition
1043 * last */
1044
1045 if (i == 0)
1046 to = 2;
1047 else if (flip_src12)
1048 to = 2 - i;
1049 else
1050 to = i - 1;
1051 } else if (flip_src12) {
1052 to = 1 - to;
1053 }
1054
1055 mir_copy_src(&ins, instr, i, to, &ins.src_abs[to], &ins.src_neg[to], &ins.src_invert[to], roundptr, is_int, broadcast_swizzle);
1056
1057 /* (!c) ? a : b = c ? b : a */
1058 if (instr->op == nir_op_b32csel && ins.src_invert[2]) {
1059 ins.src_invert[2] = false;
1060 flip_src12 ^= true;
1061 }
1062 }
1063 }
1064
1065 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
1066 /* Lowered to move */
1067 if (instr->op == nir_op_fneg)
1068 ins.src_neg[1] ^= true;
1069
1070 if (instr->op == nir_op_fabs)
1071 ins.src_abs[1] = true;
1072 }
1073
1074 ins.mask = mask_of(nr_components);
1075
1076 midgard_vector_alu alu = {
1077 .op = op,
1078 .reg_mode = reg_mode,
1079 .outmod = outmod,
1080 };
1081
1082 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1083 * components that don't exist. Note modifier => SSA => !reg => no
1084 * writemask, so we don't have to worry about writemasks here.*/
1085
1086 if (!is_ssa)
1087 ins.mask &= instr->dest.write_mask;
1088
1089 ins.alu = alu;
1090
1091 /* Late fixup for emulated instructions */
1092
1093 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1094 /* Presently, our second argument is an inline #0 constant.
1095 * Switch over to an embedded 1.0 constant (that can't fit
1096 * inline, since we're 32-bit, not 16-bit like the inline
1097 * constants) */
1098
1099 ins.has_inline_constant = false;
1100 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1101 ins.src_types[1] = nir_type_float32;
1102 ins.has_constants = true;
1103
1104 if (instr->op == nir_op_b2f32)
1105 ins.constants.f32[0] = 1.0f;
1106 else
1107 ins.constants.i32[0] = 1;
1108
1109 for (unsigned c = 0; c < 16; ++c)
1110 ins.swizzle[1][c] = 0;
1111 } else if (instr->op == nir_op_b2f16) {
1112 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1113 ins.src_types[1] = nir_type_float16;
1114 ins.has_constants = true;
1115 ins.constants.i16[0] = _mesa_float_to_half(1.0);
1116
1117 for (unsigned c = 0; c < 16; ++c)
1118 ins.swizzle[1][c] = 0;
1119 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1120 /* Lots of instructions need a 0 plonked in */
1121 ins.has_inline_constant = false;
1122 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1123 ins.src_types[1] = nir_type_uint32;
1124 ins.has_constants = true;
1125 ins.constants.u32[0] = 0;
1126
1127 for (unsigned c = 0; c < 16; ++c)
1128 ins.swizzle[1][c] = 0;
1129 } else if (instr->op == nir_op_pack_32_2x16) {
1130 ins.dest_type = nir_type_uint16;
1131 ins.mask = mask_of(nr_components * 2);
1132 ins.is_pack = true;
1133 } else if (instr->op == nir_op_pack_32_4x8) {
1134 ins.dest_type = nir_type_uint8;
1135 ins.mask = mask_of(nr_components * 4);
1136 ins.is_pack = true;
1137 } else if (instr->op == nir_op_unpack_32_2x16) {
1138 ins.dest_type = nir_type_uint32;
1139 ins.mask = mask_of(nr_components >> 1);
1140 ins.is_pack = true;
1141 } else if (instr->op == nir_op_unpack_32_4x8) {
1142 ins.dest_type = nir_type_uint32;
1143 ins.mask = mask_of(nr_components >> 2);
1144 ins.is_pack = true;
1145 }
1146
1147 /* Arrange for creation of iandnot/iornot */
1148 if (ins.src_invert[0] && !ins.src_invert[1]) {
1149 mir_flip(&ins);
1150 ins.src_invert[0] = false;
1151 ins.src_invert[1] = true;
1152 }
1153
1154 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1155 /* To avoid duplicating the lookup tables (probably), true LUT
1156 * instructions can only operate as if they were scalars. Lower
1157 * them here by changing the component. */
1158
1159 unsigned orig_mask = ins.mask;
1160
1161 unsigned swizzle_back[MIR_VEC_COMPONENTS];
1162 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
1163
1164 for (int i = 0; i < nr_components; ++i) {
1165 /* Mask the associated component, dropping the
1166 * instruction if needed */
1167
1168 ins.mask = 1 << i;
1169 ins.mask &= orig_mask;
1170
1171 if (!ins.mask)
1172 continue;
1173
1174 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1175 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1176
1177 emit_mir_instruction(ctx, ins);
1178 }
1179 } else {
1180 emit_mir_instruction(ctx, ins);
1181 }
1182 }
1183
1184 #undef ALU_CASE
1185
1186 static void
1187 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1188 {
1189 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1190 unsigned nir_mask = 0;
1191 unsigned dsize = 0;
1192
1193 if (is_read) {
1194 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1195 dsize = nir_dest_bit_size(intr->dest);
1196 } else {
1197 nir_mask = nir_intrinsic_write_mask(intr);
1198 dsize = 32;
1199 }
1200
1201 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1202 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1203 mir_set_bytemask(ins, bytemask);
1204 ins->dest_type = nir_type_uint | dsize;
1205 }
1206
1207 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1208 * optimized) versions of UBO #0 */
1209
1210 static midgard_instruction *
1211 emit_ubo_read(
1212 compiler_context *ctx,
1213 nir_instr *instr,
1214 unsigned dest,
1215 unsigned offset,
1216 nir_src *indirect_offset,
1217 unsigned indirect_shift,
1218 unsigned index)
1219 {
1220 /* TODO: half-floats */
1221
1222 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1223 ins.constants.u32[0] = offset;
1224
1225 if (instr->type == nir_instr_type_intrinsic)
1226 mir_set_intr_mask(instr, &ins, true);
1227
1228 if (indirect_offset) {
1229 ins.src[2] = nir_src_index(ctx, indirect_offset);
1230 ins.src_types[2] = nir_type_uint32;
1231 ins.load_store.arg_2 = (indirect_shift << 5);
1232 } else {
1233 ins.load_store.arg_2 = 0x1E;
1234 }
1235
1236 ins.load_store.arg_1 = index;
1237
1238 return emit_mir_instruction(ctx, ins);
1239 }
1240
1241 /* Globals are like UBOs if you squint. And shared memory is like globals if
1242 * you squint even harder */
1243
1244 static void
1245 emit_global(
1246 compiler_context *ctx,
1247 nir_instr *instr,
1248 bool is_read,
1249 unsigned srcdest,
1250 nir_src *offset,
1251 bool is_shared)
1252 {
1253 /* TODO: types */
1254
1255 midgard_instruction ins;
1256
1257 if (is_read)
1258 ins = m_ld_int4(srcdest, 0);
1259 else
1260 ins = m_st_int4(srcdest, 0);
1261
1262 mir_set_offset(ctx, &ins, offset, is_shared);
1263 mir_set_intr_mask(instr, &ins, is_read);
1264
1265 emit_mir_instruction(ctx, ins);
1266 }
1267
1268 static void
1269 emit_varying_read(
1270 compiler_context *ctx,
1271 unsigned dest, unsigned offset,
1272 unsigned nr_comp, unsigned component,
1273 nir_src *indirect_offset, nir_alu_type type, bool flat)
1274 {
1275 /* XXX: Half-floats? */
1276 /* TODO: swizzle, mask */
1277
1278 midgard_instruction ins = m_ld_vary_32(dest, offset);
1279 ins.mask = mask_of(nr_comp);
1280
1281 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1282 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1283
1284 midgard_varying_parameter p = {
1285 .is_varying = 1,
1286 .interpolation = midgard_interp_default,
1287 .flat = flat,
1288 };
1289
1290 unsigned u;
1291 memcpy(&u, &p, sizeof(p));
1292 ins.load_store.varying_parameters = u;
1293
1294 if (indirect_offset) {
1295 ins.src[2] = nir_src_index(ctx, indirect_offset);
1296 ins.src_types[2] = nir_type_uint32;
1297 } else
1298 ins.load_store.arg_2 = 0x1E;
1299
1300 ins.load_store.arg_1 = 0x9E;
1301
1302 /* Use the type appropriate load */
1303 switch (type) {
1304 case nir_type_uint32:
1305 case nir_type_bool32:
1306 ins.load_store.op = midgard_op_ld_vary_32u;
1307 break;
1308 case nir_type_int32:
1309 ins.load_store.op = midgard_op_ld_vary_32i;
1310 break;
1311 case nir_type_float32:
1312 ins.load_store.op = midgard_op_ld_vary_32;
1313 break;
1314 case nir_type_float16:
1315 ins.load_store.op = midgard_op_ld_vary_16;
1316 break;
1317 default:
1318 unreachable("Attempted to load unknown type");
1319 break;
1320 }
1321
1322 emit_mir_instruction(ctx, ins);
1323 }
1324
1325 static void
1326 emit_attr_read(
1327 compiler_context *ctx,
1328 unsigned dest, unsigned offset,
1329 unsigned nr_comp, nir_alu_type t)
1330 {
1331 midgard_instruction ins = m_ld_attr_32(dest, offset);
1332 ins.load_store.arg_1 = 0x1E;
1333 ins.load_store.arg_2 = 0x1E;
1334 ins.mask = mask_of(nr_comp);
1335
1336 /* Use the type appropriate load */
1337 switch (t) {
1338 case nir_type_uint:
1339 case nir_type_bool:
1340 ins.load_store.op = midgard_op_ld_attr_32u;
1341 break;
1342 case nir_type_int:
1343 ins.load_store.op = midgard_op_ld_attr_32i;
1344 break;
1345 case nir_type_float:
1346 ins.load_store.op = midgard_op_ld_attr_32;
1347 break;
1348 default:
1349 unreachable("Attempted to load unknown type");
1350 break;
1351 }
1352
1353 emit_mir_instruction(ctx, ins);
1354 }
1355
1356 static void
1357 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1358 unsigned nr_components, unsigned offset)
1359 {
1360 nir_dest nir_dest;
1361
1362 /* Figure out which uniform this is */
1363 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1364 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1365
1366 unsigned dest = nir_dest_index(&nir_dest);
1367
1368 /* Sysvals are prefix uniforms */
1369 unsigned uniform = ((uintptr_t) val) - 1;
1370
1371 /* Emit the read itself -- this is never indirect */
1372 midgard_instruction *ins =
1373 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1374
1375 ins->mask = mask_of(nr_components);
1376 }
1377
1378 static unsigned
1379 compute_builtin_arg(nir_op op)
1380 {
1381 switch (op) {
1382 case nir_intrinsic_load_work_group_id:
1383 return 0x14;
1384 case nir_intrinsic_load_local_invocation_id:
1385 return 0x10;
1386 default:
1387 unreachable("Invalid compute paramater loaded");
1388 }
1389 }
1390
1391 static void
1392 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1393 {
1394 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1395
1396 midgard_instruction *br = ctx->writeout_branch[rt];
1397
1398 assert(!br);
1399
1400 emit_explicit_constant(ctx, src, src);
1401
1402 struct midgard_instruction ins =
1403 v_branch(false, false);
1404
1405 ins.writeout = true;
1406
1407 /* Add dependencies */
1408 ins.src[0] = src;
1409 ins.src_types[0] = nir_type_uint32;
1410 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1411 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1412
1413 /* Emit the branch */
1414 br = emit_mir_instruction(ctx, ins);
1415 schedule_barrier(ctx);
1416 ctx->writeout_branch[rt] = br;
1417
1418 /* Push our current location = current block count - 1 = where we'll
1419 * jump to. Maybe a bit too clever for my own good */
1420
1421 br->branch.target_block = ctx->block_count - 1;
1422 }
1423
1424 static void
1425 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1426 {
1427 unsigned reg = nir_dest_index(&instr->dest);
1428 midgard_instruction ins = m_ld_compute_id(reg, 0);
1429 ins.mask = mask_of(3);
1430 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1431 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1432 emit_mir_instruction(ctx, ins);
1433 }
1434
1435 static unsigned
1436 vertex_builtin_arg(nir_op op)
1437 {
1438 switch (op) {
1439 case nir_intrinsic_load_vertex_id:
1440 return PAN_VERTEX_ID;
1441 case nir_intrinsic_load_instance_id:
1442 return PAN_INSTANCE_ID;
1443 default:
1444 unreachable("Invalid vertex builtin");
1445 }
1446 }
1447
1448 static void
1449 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1450 {
1451 unsigned reg = nir_dest_index(&instr->dest);
1452 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1453 }
1454
1455 static void
1456 emit_control_barrier(compiler_context *ctx)
1457 {
1458 midgard_instruction ins = {
1459 .type = TAG_TEXTURE_4,
1460 .dest = ~0,
1461 .src = { ~0, ~0, ~0, ~0 },
1462 .texture = {
1463 .op = TEXTURE_OP_BARRIER,
1464
1465 /* TODO: optimize */
1466 .out_of_order = MIDGARD_BARRIER_BUFFER |
1467 MIDGARD_BARRIER_SHARED ,
1468 }
1469 };
1470
1471 emit_mir_instruction(ctx, ins);
1472 }
1473
1474 static const nir_variable *
1475 search_var(struct exec_list *vars, unsigned driver_loc)
1476 {
1477 nir_foreach_variable(var, vars) {
1478 if (var->data.driver_location == driver_loc)
1479 return var;
1480 }
1481
1482 return NULL;
1483 }
1484
1485 static unsigned
1486 mir_get_branch_cond(nir_src *src, bool *invert)
1487 {
1488 /* Wrap it. No swizzle since it's a scalar */
1489
1490 nir_alu_src alu = {
1491 .src = *src
1492 };
1493
1494 *invert = pan_has_source_mod(&alu, nir_op_inot);
1495 return nir_src_index(NULL, &alu.src);
1496 }
1497
1498 static void
1499 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1500 {
1501 unsigned offset = 0, reg;
1502
1503 switch (instr->intrinsic) {
1504 case nir_intrinsic_discard_if:
1505 case nir_intrinsic_discard: {
1506 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1507 struct midgard_instruction discard = v_branch(conditional, false);
1508 discard.branch.target_type = TARGET_DISCARD;
1509
1510 if (conditional) {
1511 discard.src[0] = mir_get_branch_cond(&instr->src[0],
1512 &discard.branch.invert_conditional);
1513 discard.src_types[0] = nir_type_uint32;
1514 }
1515
1516 emit_mir_instruction(ctx, discard);
1517 schedule_barrier(ctx);
1518
1519 break;
1520 }
1521
1522 case nir_intrinsic_load_uniform:
1523 case nir_intrinsic_load_ubo:
1524 case nir_intrinsic_load_global:
1525 case nir_intrinsic_load_shared:
1526 case nir_intrinsic_load_input:
1527 case nir_intrinsic_load_interpolated_input: {
1528 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1529 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1530 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1531 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1532 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1533 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1534
1535 /* Get the base type of the intrinsic */
1536 /* TODO: Infer type? Does it matter? */
1537 nir_alu_type t =
1538 (is_ubo || is_global || is_shared) ? nir_type_uint :
1539 (is_interp) ? nir_type_float :
1540 nir_intrinsic_type(instr);
1541
1542 t = nir_alu_type_get_base_type(t);
1543
1544 if (!(is_ubo || is_global)) {
1545 offset = nir_intrinsic_base(instr);
1546 }
1547
1548 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1549
1550 nir_src *src_offset = nir_get_io_offset_src(instr);
1551
1552 bool direct = nir_src_is_const(*src_offset);
1553 nir_src *indirect_offset = direct ? NULL : src_offset;
1554
1555 if (direct)
1556 offset += nir_src_as_uint(*src_offset);
1557
1558 /* We may need to apply a fractional offset */
1559 int component = (is_flat || is_interp) ?
1560 nir_intrinsic_component(instr) : 0;
1561 reg = nir_dest_index(&instr->dest);
1562
1563 if (is_uniform && !ctx->is_blend) {
1564 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1565 } else if (is_ubo) {
1566 nir_src index = instr->src[0];
1567
1568 /* TODO: Is indirect block number possible? */
1569 assert(nir_src_is_const(index));
1570
1571 uint32_t uindex = nir_src_as_uint(index) + 1;
1572 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1573 } else if (is_global || is_shared) {
1574 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1575 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1576 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t | nir_dest_bit_size(instr->dest), is_flat);
1577 } else if (ctx->is_blend) {
1578 /* For blend shaders, load the input color, which is
1579 * preloaded to r0 */
1580
1581 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1582 emit_mir_instruction(ctx, move);
1583 schedule_barrier(ctx);
1584 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1585 emit_attr_read(ctx, reg, offset, nr_comp, t);
1586 } else {
1587 DBG("Unknown load\n");
1588 assert(0);
1589 }
1590
1591 break;
1592 }
1593
1594 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1595 case nir_intrinsic_load_barycentric_pixel:
1596 case nir_intrinsic_load_barycentric_centroid:
1597 break;
1598
1599 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1600
1601 case nir_intrinsic_load_raw_output_pan:
1602 case nir_intrinsic_load_output_u8_as_fp16_pan:
1603 reg = nir_dest_index(&instr->dest);
1604 assert(ctx->is_blend);
1605
1606 /* T720 and below use different blend opcodes with slightly
1607 * different semantics than T760 and up */
1608
1609 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1610 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1611
1612 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1613 ld.load_store.op = old_blend ?
1614 midgard_op_ld_color_buffer_as_fp16_old :
1615 midgard_op_ld_color_buffer_as_fp16;
1616
1617 for (unsigned c = 4; c < 16; ++c)
1618 ld.swizzle[0][c] = 0;
1619
1620 ld.dest_type = nir_type_float16;
1621
1622 if (old_blend) {
1623 ld.load_store.address = 1;
1624 ld.load_store.arg_2 = 0x1E;
1625 }
1626 } else if (old_blend) {
1627 ld.load_store.op = midgard_op_ld_color_buffer_32u_old;
1628 ld.load_store.address = 16;
1629 ld.load_store.arg_2 = 0x1E;
1630 }
1631
1632 emit_mir_instruction(ctx, ld);
1633 break;
1634
1635 case nir_intrinsic_load_blend_const_color_rgba: {
1636 assert(ctx->is_blend);
1637 reg = nir_dest_index(&instr->dest);
1638
1639 /* Blend constants are embedded directly in the shader and
1640 * patched in, so we use some magic routing */
1641
1642 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1643 ins.has_constants = true;
1644 ins.has_blend_constant = true;
1645 emit_mir_instruction(ctx, ins);
1646 break;
1647 }
1648
1649 case nir_intrinsic_store_zs_output_pan: {
1650 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1651 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1652 MIDGARD_ZS_RT);
1653
1654 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1655
1656 if (!nir_intrinsic_component(instr))
1657 br->writeout_depth = true;
1658 if (nir_intrinsic_component(instr) ||
1659 instr->num_components)
1660 br->writeout_stencil = true;
1661 assert(br->writeout_depth | br->writeout_stencil);
1662 break;
1663 }
1664
1665 case nir_intrinsic_store_output:
1666 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1667
1668 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1669
1670 reg = nir_src_index(ctx, &instr->src[0]);
1671
1672 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1673 const nir_variable *var;
1674 enum midgard_rt_id rt;
1675
1676 var = search_var(&ctx->nir->outputs,
1677 nir_intrinsic_base(instr));
1678 assert(var);
1679 if (var->data.location == FRAG_RESULT_COLOR)
1680 rt = MIDGARD_COLOR_RT0;
1681 else if (var->data.location >= FRAG_RESULT_DATA0)
1682 rt = MIDGARD_COLOR_RT0 + var->data.location -
1683 FRAG_RESULT_DATA0;
1684 else
1685 assert(0);
1686
1687 emit_fragment_store(ctx, reg, rt);
1688 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1689 /* We should have been vectorized, though we don't
1690 * currently check that st_vary is emitted only once
1691 * per slot (this is relevant, since there's not a mask
1692 * parameter available on the store [set to 0 by the
1693 * blob]). We do respect the component by adjusting the
1694 * swizzle. If this is a constant source, we'll need to
1695 * emit that explicitly. */
1696
1697 emit_explicit_constant(ctx, reg, reg);
1698
1699 unsigned dst_component = nir_intrinsic_component(instr);
1700 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1701
1702 midgard_instruction st = m_st_vary_32(reg, offset);
1703 st.load_store.arg_1 = 0x9E;
1704 st.load_store.arg_2 = 0x1E;
1705
1706 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1707 case nir_type_uint:
1708 case nir_type_bool:
1709 st.load_store.op = midgard_op_st_vary_32u;
1710 break;
1711 case nir_type_int:
1712 st.load_store.op = midgard_op_st_vary_32i;
1713 break;
1714 case nir_type_float:
1715 st.load_store.op = midgard_op_st_vary_32;
1716 break;
1717 default:
1718 unreachable("Attempted to store unknown type");
1719 break;
1720 }
1721
1722 /* nir_intrinsic_component(store_intr) encodes the
1723 * destination component start. Source component offset
1724 * adjustment is taken care of in
1725 * install_registers_instr(), when offset_swizzle() is
1726 * called.
1727 */
1728 unsigned src_component = COMPONENT_X;
1729
1730 assert(nr_comp > 0);
1731 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1732 st.swizzle[0][i] = src_component;
1733 if (i >= dst_component && i < dst_component + nr_comp - 1)
1734 src_component++;
1735 }
1736
1737 emit_mir_instruction(ctx, st);
1738 } else {
1739 DBG("Unknown store\n");
1740 assert(0);
1741 }
1742
1743 break;
1744
1745 /* Special case of store_output for lowered blend shaders */
1746 case nir_intrinsic_store_raw_output_pan:
1747 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1748 reg = nir_src_index(ctx, &instr->src[0]);
1749 emit_fragment_store(ctx, reg, ctx->blend_rt);
1750 break;
1751
1752 case nir_intrinsic_store_global:
1753 case nir_intrinsic_store_shared:
1754 reg = nir_src_index(ctx, &instr->src[0]);
1755 emit_explicit_constant(ctx, reg, reg);
1756
1757 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1758 break;
1759
1760 case nir_intrinsic_load_ssbo_address:
1761 emit_sysval_read(ctx, &instr->instr, 1, 0);
1762 break;
1763
1764 case nir_intrinsic_get_buffer_size:
1765 emit_sysval_read(ctx, &instr->instr, 1, 8);
1766 break;
1767
1768 case nir_intrinsic_load_viewport_scale:
1769 case nir_intrinsic_load_viewport_offset:
1770 case nir_intrinsic_load_num_work_groups:
1771 case nir_intrinsic_load_sampler_lod_parameters_pan:
1772 emit_sysval_read(ctx, &instr->instr, 3, 0);
1773 break;
1774
1775 case nir_intrinsic_load_work_group_id:
1776 case nir_intrinsic_load_local_invocation_id:
1777 emit_compute_builtin(ctx, instr);
1778 break;
1779
1780 case nir_intrinsic_load_vertex_id:
1781 case nir_intrinsic_load_instance_id:
1782 emit_vertex_builtin(ctx, instr);
1783 break;
1784
1785 case nir_intrinsic_memory_barrier_buffer:
1786 case nir_intrinsic_memory_barrier_shared:
1787 break;
1788
1789 case nir_intrinsic_control_barrier:
1790 schedule_barrier(ctx);
1791 emit_control_barrier(ctx);
1792 schedule_barrier(ctx);
1793 break;
1794
1795 default:
1796 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1797 assert(0);
1798 break;
1799 }
1800 }
1801
1802 static unsigned
1803 midgard_tex_format(enum glsl_sampler_dim dim)
1804 {
1805 switch (dim) {
1806 case GLSL_SAMPLER_DIM_1D:
1807 case GLSL_SAMPLER_DIM_BUF:
1808 return MALI_TEX_1D;
1809
1810 case GLSL_SAMPLER_DIM_2D:
1811 case GLSL_SAMPLER_DIM_EXTERNAL:
1812 case GLSL_SAMPLER_DIM_RECT:
1813 return MALI_TEX_2D;
1814
1815 case GLSL_SAMPLER_DIM_3D:
1816 return MALI_TEX_3D;
1817
1818 case GLSL_SAMPLER_DIM_CUBE:
1819 return MALI_TEX_CUBE;
1820
1821 default:
1822 DBG("Unknown sampler dim type\n");
1823 assert(0);
1824 return 0;
1825 }
1826 }
1827
1828 /* Tries to attach an explicit LOD or bias as a constant. Returns whether this
1829 * was successful */
1830
1831 static bool
1832 pan_attach_constant_bias(
1833 compiler_context *ctx,
1834 nir_src lod,
1835 midgard_texture_word *word)
1836 {
1837 /* To attach as constant, it has to *be* constant */
1838
1839 if (!nir_src_is_const(lod))
1840 return false;
1841
1842 float f = nir_src_as_float(lod);
1843
1844 /* Break into fixed-point */
1845 signed lod_int = f;
1846 float lod_frac = f - lod_int;
1847
1848 /* Carry over negative fractions */
1849 if (lod_frac < 0.0) {
1850 lod_int--;
1851 lod_frac += 1.0;
1852 }
1853
1854 /* Encode */
1855 word->bias = float_to_ubyte(lod_frac);
1856 word->bias_int = lod_int;
1857
1858 return true;
1859 }
1860
1861 static void
1862 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1863 unsigned midgard_texop)
1864 {
1865 /* TODO */
1866 //assert (!instr->sampler);
1867
1868 int texture_index = instr->texture_index;
1869 int sampler_index = texture_index;
1870
1871 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1872 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1873
1874 midgard_instruction ins = {
1875 .type = TAG_TEXTURE_4,
1876 .mask = 0xF,
1877 .dest = nir_dest_index(&instr->dest),
1878 .src = { ~0, ~0, ~0, ~0 },
1879 .dest_type = dest_type,
1880 .swizzle = SWIZZLE_IDENTITY_4,
1881 .texture = {
1882 .op = midgard_texop,
1883 .format = midgard_tex_format(instr->sampler_dim),
1884 .texture_handle = texture_index,
1885 .sampler_handle = sampler_index,
1886 .shadow = instr->is_shadow,
1887 }
1888 };
1889
1890 if (instr->is_shadow && !instr->is_new_style_shadow)
1891 for (int i = 0; i < 4; ++i)
1892 ins.swizzle[0][i] = COMPONENT_X;
1893
1894 /* We may need a temporary for the coordinate */
1895
1896 bool needs_temp_coord =
1897 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1898 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1899 (instr->is_shadow);
1900
1901 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1902
1903 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1904 int index = nir_src_index(ctx, &instr->src[i].src);
1905 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1906 unsigned sz = nir_src_bit_size(instr->src[i].src);
1907 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1908
1909 switch (instr->src[i].src_type) {
1910 case nir_tex_src_coord: {
1911 emit_explicit_constant(ctx, index, index);
1912
1913 unsigned coord_mask = mask_of(instr->coord_components);
1914
1915 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1916
1917 if (flip_zw)
1918 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1919
1920 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1921 /* texelFetch is undefined on samplerCube */
1922 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1923
1924 /* For cubemaps, we use a special ld/st op to
1925 * select the face and copy the xy into the
1926 * texture register */
1927
1928 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1929 ld.src[1] = index;
1930 ld.src_types[1] = T;
1931 ld.mask = 0x3; /* xy */
1932 ld.load_store.arg_1 = 0x20;
1933 ld.swizzle[1][3] = COMPONENT_X;
1934 emit_mir_instruction(ctx, ld);
1935
1936 /* xyzw -> xyxx */
1937 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1938 ins.swizzle[1][3] = COMPONENT_X;
1939 } else if (needs_temp_coord) {
1940 /* mov coord_temp, coords */
1941 midgard_instruction mov = v_mov(index, coords);
1942 mov.mask = coord_mask;
1943
1944 if (flip_zw)
1945 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1946
1947 emit_mir_instruction(ctx, mov);
1948 } else {
1949 coords = index;
1950 }
1951
1952 ins.src[1] = coords;
1953 ins.src_types[1] = T;
1954
1955 /* Texelfetch coordinates uses all four elements
1956 * (xyz/index) regardless of texture dimensionality,
1957 * which means it's necessary to zero the unused
1958 * components to keep everything happy */
1959
1960 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1961 /* mov index.zw, #0, or generalized */
1962 midgard_instruction mov =
1963 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1964 mov.has_constants = true;
1965 mov.mask = coord_mask ^ 0xF;
1966 emit_mir_instruction(ctx, mov);
1967 }
1968
1969 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1970 /* Array component in w but NIR wants it in z,
1971 * but if we have a temp coord we already fixed
1972 * that up */
1973
1974 if (nr_components == 3) {
1975 ins.swizzle[1][2] = COMPONENT_Z;
1976 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1977 } else if (nr_components == 2) {
1978 ins.swizzle[1][2] =
1979 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1980 ins.swizzle[1][3] = COMPONENT_X;
1981 } else
1982 unreachable("Invalid texture 2D components");
1983 }
1984
1985 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1986 /* We zeroed */
1987 ins.swizzle[1][2] = COMPONENT_Z;
1988 ins.swizzle[1][3] = COMPONENT_W;
1989 }
1990
1991 break;
1992 }
1993
1994 case nir_tex_src_bias:
1995 case nir_tex_src_lod: {
1996 /* Try as a constant if we can */
1997
1998 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1999 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
2000 break;
2001
2002 ins.texture.lod_register = true;
2003 ins.src[2] = index;
2004 ins.src_types[2] = T;
2005
2006 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2007 ins.swizzle[2][c] = COMPONENT_X;
2008
2009 emit_explicit_constant(ctx, index, index);
2010
2011 break;
2012 };
2013
2014 case nir_tex_src_offset: {
2015 ins.texture.offset_register = true;
2016 ins.src[3] = index;
2017 ins.src_types[3] = T;
2018
2019 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2020 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
2021
2022 emit_explicit_constant(ctx, index, index);
2023 break;
2024 };
2025
2026 case nir_tex_src_comparator: {
2027 unsigned comp = COMPONENT_Z;
2028
2029 /* mov coord_temp.foo, coords */
2030 midgard_instruction mov = v_mov(index, coords);
2031 mov.mask = 1 << comp;
2032
2033 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
2034 mov.swizzle[1][i] = COMPONENT_X;
2035
2036 emit_mir_instruction(ctx, mov);
2037 break;
2038 }
2039
2040 default: {
2041 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
2042 assert(0);
2043 }
2044 }
2045 }
2046
2047 emit_mir_instruction(ctx, ins);
2048 }
2049
2050 static void
2051 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
2052 {
2053 switch (instr->op) {
2054 case nir_texop_tex:
2055 case nir_texop_txb:
2056 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
2057 break;
2058 case nir_texop_txl:
2059 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
2060 break;
2061 case nir_texop_txf:
2062 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
2063 break;
2064 case nir_texop_txs:
2065 emit_sysval_read(ctx, &instr->instr, 4, 0);
2066 break;
2067 default: {
2068 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
2069 assert(0);
2070 }
2071 }
2072 }
2073
2074 static void
2075 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
2076 {
2077 switch (instr->type) {
2078 case nir_jump_break: {
2079 /* Emit a branch out of the loop */
2080 struct midgard_instruction br = v_branch(false, false);
2081 br.branch.target_type = TARGET_BREAK;
2082 br.branch.target_break = ctx->current_loop_depth;
2083 emit_mir_instruction(ctx, br);
2084 break;
2085 }
2086
2087 default:
2088 DBG("Unknown jump type %d\n", instr->type);
2089 break;
2090 }
2091 }
2092
2093 static void
2094 emit_instr(compiler_context *ctx, struct nir_instr *instr)
2095 {
2096 switch (instr->type) {
2097 case nir_instr_type_load_const:
2098 emit_load_const(ctx, nir_instr_as_load_const(instr));
2099 break;
2100
2101 case nir_instr_type_intrinsic:
2102 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2103 break;
2104
2105 case nir_instr_type_alu:
2106 emit_alu(ctx, nir_instr_as_alu(instr));
2107 break;
2108
2109 case nir_instr_type_tex:
2110 emit_tex(ctx, nir_instr_as_tex(instr));
2111 break;
2112
2113 case nir_instr_type_jump:
2114 emit_jump(ctx, nir_instr_as_jump(instr));
2115 break;
2116
2117 case nir_instr_type_ssa_undef:
2118 /* Spurious */
2119 break;
2120
2121 default:
2122 DBG("Unhandled instruction type\n");
2123 break;
2124 }
2125 }
2126
2127
2128 /* ALU instructions can inline or embed constants, which decreases register
2129 * pressure and saves space. */
2130
2131 #define CONDITIONAL_ATTACH(idx) { \
2132 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2133 \
2134 if (entry) { \
2135 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2136 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2137 } \
2138 }
2139
2140 static void
2141 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2142 {
2143 mir_foreach_instr_in_block(block, alu) {
2144 /* Other instructions cannot inline constants */
2145 if (alu->type != TAG_ALU_4) continue;
2146 if (alu->compact_branch) continue;
2147
2148 /* If there is already a constant here, we can do nothing */
2149 if (alu->has_constants) continue;
2150
2151 CONDITIONAL_ATTACH(0);
2152
2153 if (!alu->has_constants) {
2154 CONDITIONAL_ATTACH(1)
2155 } else if (!alu->inline_constant) {
2156 /* Corner case: _two_ vec4 constants, for instance with a
2157 * csel. For this case, we can only use a constant
2158 * register for one, we'll have to emit a move for the
2159 * other. */
2160
2161 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2162 unsigned scratch = make_compiler_temp(ctx);
2163
2164 if (entry) {
2165 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2166 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2167
2168 /* Set the source */
2169 alu->src[1] = scratch;
2170
2171 /* Inject us -before- the last instruction which set r31 */
2172 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2173 }
2174 }
2175 }
2176 }
2177
2178 /* Midgard supports two types of constants, embedded constants (128-bit) and
2179 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2180 * constants can be demoted to inline constants, for space savings and
2181 * sometimes a performance boost */
2182
2183 static void
2184 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2185 {
2186 mir_foreach_instr_in_block(block, ins) {
2187 if (!ins->has_constants) continue;
2188 if (ins->has_inline_constant) continue;
2189
2190 /* Blend constants must not be inlined by definition */
2191 if (ins->has_blend_constant) continue;
2192
2193 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2194 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2195 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2196
2197 if (!(is_16 || is_32))
2198 continue;
2199
2200 /* src1 cannot be an inline constant due to encoding
2201 * restrictions. So, if possible we try to flip the arguments
2202 * in that case */
2203
2204 int op = ins->alu.op;
2205
2206 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2207 alu_opcode_props[op].props & OP_COMMUTES) {
2208 mir_flip(ins);
2209 }
2210
2211 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2212 /* Component is from the swizzle. Take a nonzero component */
2213 assert(ins->mask);
2214 unsigned first_comp = ffs(ins->mask) - 1;
2215 unsigned component = ins->swizzle[1][first_comp];
2216
2217 /* Scale constant appropriately, if we can legally */
2218 uint16_t scaled_constant = 0;
2219
2220 if (is_16) {
2221 scaled_constant = ins->constants.u16[component];
2222 } else if (midgard_is_integer_op(op)) {
2223 scaled_constant = ins->constants.u32[component];
2224
2225 /* Constant overflow after resize */
2226 if (scaled_constant != ins->constants.u32[component])
2227 continue;
2228 } else {
2229 float original = ins->constants.f32[component];
2230 scaled_constant = _mesa_float_to_half(original);
2231
2232 /* Check for loss of precision. If this is
2233 * mediump, we don't care, but for a highp
2234 * shader, we need to pay attention. NIR
2235 * doesn't yet tell us which mode we're in!
2236 * Practically this prevents most constants
2237 * from being inlined, sadly. */
2238
2239 float fp32 = _mesa_half_to_float(scaled_constant);
2240
2241 if (fp32 != original)
2242 continue;
2243 }
2244
2245 /* Should've been const folded */
2246 if (ins->src_abs[1] || ins->src_neg[1])
2247 continue;
2248
2249 /* Make sure that the constant is not itself a vector
2250 * by checking if all accessed values are the same. */
2251
2252 const midgard_constants *cons = &ins->constants;
2253 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2254
2255 bool is_vector = false;
2256 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2257
2258 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2259 /* We only care if this component is actually used */
2260 if (!(mask & (1 << c)))
2261 continue;
2262
2263 uint32_t test = is_16 ?
2264 cons->u16[ins->swizzle[1][c]] :
2265 cons->u32[ins->swizzle[1][c]];
2266
2267 if (test != value) {
2268 is_vector = true;
2269 break;
2270 }
2271 }
2272
2273 if (is_vector)
2274 continue;
2275
2276 /* Get rid of the embedded constant */
2277 ins->has_constants = false;
2278 ins->src[1] = ~0;
2279 ins->has_inline_constant = true;
2280 ins->inline_constant = scaled_constant;
2281 }
2282 }
2283 }
2284
2285 /* Dead code elimination for branches at the end of a block - only one branch
2286 * per block is legal semantically */
2287
2288 static void
2289 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2290 {
2291 bool branched = false;
2292
2293 mir_foreach_instr_in_block_safe(block, ins) {
2294 if (!midgard_is_branch_unit(ins->unit)) continue;
2295
2296 if (branched)
2297 mir_remove_instruction(ins);
2298
2299 branched = true;
2300 }
2301 }
2302
2303 static unsigned
2304 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2305 {
2306 /* Loop to ourselves */
2307 midgard_instruction *br = ctx->writeout_branch[rt];
2308 struct midgard_instruction ins = v_branch(false, false);
2309 ins.writeout = true;
2310 ins.writeout_depth = br->writeout_depth;
2311 ins.writeout_stencil = br->writeout_stencil;
2312 ins.branch.target_block = ctx->block_count - 1;
2313 ins.constants.u32[0] = br->constants.u32[0];
2314 emit_mir_instruction(ctx, ins);
2315
2316 ctx->current_block->epilogue = true;
2317 schedule_barrier(ctx);
2318 return ins.branch.target_block;
2319 }
2320
2321 static midgard_block *
2322 emit_block(compiler_context *ctx, nir_block *block)
2323 {
2324 midgard_block *this_block = ctx->after_block;
2325 ctx->after_block = NULL;
2326
2327 if (!this_block)
2328 this_block = create_empty_block(ctx);
2329
2330 list_addtail(&this_block->base.link, &ctx->blocks);
2331
2332 this_block->scheduled = false;
2333 ++ctx->block_count;
2334
2335 /* Set up current block */
2336 list_inithead(&this_block->base.instructions);
2337 ctx->current_block = this_block;
2338
2339 nir_foreach_instr(instr, block) {
2340 emit_instr(ctx, instr);
2341 ++ctx->instruction_count;
2342 }
2343
2344 return this_block;
2345 }
2346
2347 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2348
2349 static void
2350 emit_if(struct compiler_context *ctx, nir_if *nif)
2351 {
2352 midgard_block *before_block = ctx->current_block;
2353
2354 /* Speculatively emit the branch, but we can't fill it in until later */
2355 bool inv = false;
2356 EMIT(branch, true, true);
2357 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2358 then_branch->src[0] = mir_get_branch_cond(&nif->condition, &inv);
2359 then_branch->src_types[0] = nir_type_uint32;
2360 then_branch->branch.invert_conditional = !inv;
2361
2362 /* Emit the two subblocks. */
2363 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2364 midgard_block *end_then_block = ctx->current_block;
2365
2366 /* Emit a jump from the end of the then block to the end of the else */
2367 EMIT(branch, false, false);
2368 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2369
2370 /* Emit second block, and check if it's empty */
2371
2372 int else_idx = ctx->block_count;
2373 int count_in = ctx->instruction_count;
2374 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2375 midgard_block *end_else_block = ctx->current_block;
2376 int after_else_idx = ctx->block_count;
2377
2378 /* Now that we have the subblocks emitted, fix up the branches */
2379
2380 assert(then_block);
2381 assert(else_block);
2382
2383 if (ctx->instruction_count == count_in) {
2384 /* The else block is empty, so don't emit an exit jump */
2385 mir_remove_instruction(then_exit);
2386 then_branch->branch.target_block = after_else_idx;
2387 } else {
2388 then_branch->branch.target_block = else_idx;
2389 then_exit->branch.target_block = after_else_idx;
2390 }
2391
2392 /* Wire up the successors */
2393
2394 ctx->after_block = create_empty_block(ctx);
2395
2396 pan_block_add_successor(&before_block->base, &then_block->base);
2397 pan_block_add_successor(&before_block->base, &else_block->base);
2398
2399 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2400 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2401 }
2402
2403 static void
2404 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2405 {
2406 /* Remember where we are */
2407 midgard_block *start_block = ctx->current_block;
2408
2409 /* Allocate a loop number, growing the current inner loop depth */
2410 int loop_idx = ++ctx->current_loop_depth;
2411
2412 /* Get index from before the body so we can loop back later */
2413 int start_idx = ctx->block_count;
2414
2415 /* Emit the body itself */
2416 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2417
2418 /* Branch back to loop back */
2419 struct midgard_instruction br_back = v_branch(false, false);
2420 br_back.branch.target_block = start_idx;
2421 emit_mir_instruction(ctx, br_back);
2422
2423 /* Mark down that branch in the graph. */
2424 pan_block_add_successor(&start_block->base, &loop_block->base);
2425 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2426
2427 /* Find the index of the block about to follow us (note: we don't add
2428 * one; blocks are 0-indexed so we get a fencepost problem) */
2429 int break_block_idx = ctx->block_count;
2430
2431 /* Fix up the break statements we emitted to point to the right place,
2432 * now that we can allocate a block number for them */
2433 ctx->after_block = create_empty_block(ctx);
2434
2435 mir_foreach_block_from(ctx, start_block, _block) {
2436 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2437 if (ins->type != TAG_ALU_4) continue;
2438 if (!ins->compact_branch) continue;
2439
2440 /* We found a branch -- check the type to see if we need to do anything */
2441 if (ins->branch.target_type != TARGET_BREAK) continue;
2442
2443 /* It's a break! Check if it's our break */
2444 if (ins->branch.target_break != loop_idx) continue;
2445
2446 /* Okay, cool, we're breaking out of this loop.
2447 * Rewrite from a break to a goto */
2448
2449 ins->branch.target_type = TARGET_GOTO;
2450 ins->branch.target_block = break_block_idx;
2451
2452 pan_block_add_successor(_block, &ctx->after_block->base);
2453 }
2454 }
2455
2456 /* Now that we've finished emitting the loop, free up the depth again
2457 * so we play nice with recursion amid nested loops */
2458 --ctx->current_loop_depth;
2459
2460 /* Dump loop stats */
2461 ++ctx->loop_count;
2462 }
2463
2464 static midgard_block *
2465 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2466 {
2467 midgard_block *start_block = NULL;
2468
2469 foreach_list_typed(nir_cf_node, node, node, list) {
2470 switch (node->type) {
2471 case nir_cf_node_block: {
2472 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2473
2474 if (!start_block)
2475 start_block = block;
2476
2477 break;
2478 }
2479
2480 case nir_cf_node_if:
2481 emit_if(ctx, nir_cf_node_as_if(node));
2482 break;
2483
2484 case nir_cf_node_loop:
2485 emit_loop(ctx, nir_cf_node_as_loop(node));
2486 break;
2487
2488 case nir_cf_node_function:
2489 assert(0);
2490 break;
2491 }
2492 }
2493
2494 return start_block;
2495 }
2496
2497 /* Due to lookahead, we need to report the first tag executed in the command
2498 * stream and in branch targets. An initial block might be empty, so iterate
2499 * until we find one that 'works' */
2500
2501 static unsigned
2502 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2503 {
2504 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2505
2506 mir_foreach_block_from(ctx, initial_block, _v) {
2507 midgard_block *v = (midgard_block *) _v;
2508 if (v->quadword_count) {
2509 midgard_bundle *initial_bundle =
2510 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2511
2512 return initial_bundle->tag;
2513 }
2514 }
2515
2516 /* Default to a tag 1 which will break from the shader, in case we jump
2517 * to the exit block (i.e. `return` in a compute shader) */
2518
2519 return 1;
2520 }
2521
2522 /* For each fragment writeout instruction, generate a writeout loop to
2523 * associate with it */
2524
2525 static void
2526 mir_add_writeout_loops(compiler_context *ctx)
2527 {
2528 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2529 midgard_instruction *br = ctx->writeout_branch[rt];
2530 if (!br) continue;
2531
2532 unsigned popped = br->branch.target_block;
2533 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2534 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2535 br->branch.target_type = TARGET_GOTO;
2536
2537 /* If we have more RTs, we'll need to restore back after our
2538 * loop terminates */
2539
2540 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2541 midgard_instruction uncond = v_branch(false, false);
2542 uncond.branch.target_block = popped;
2543 uncond.branch.target_type = TARGET_GOTO;
2544 emit_mir_instruction(ctx, uncond);
2545 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2546 schedule_barrier(ctx);
2547 } else {
2548 /* We're last, so we can terminate here */
2549 br->last_writeout = true;
2550 }
2551 }
2552 }
2553
2554 int
2555 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2556 {
2557 struct util_dynarray *compiled = &program->compiled;
2558
2559 midgard_debug = debug_get_option_midgard_debug();
2560
2561 /* TODO: Bound against what? */
2562 compiler_context *ctx = rzalloc(NULL, compiler_context);
2563
2564 ctx->nir = nir;
2565 ctx->stage = nir->info.stage;
2566 ctx->is_blend = is_blend;
2567 ctx->alpha_ref = program->alpha_ref;
2568 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2569 ctx->quirks = midgard_get_quirks(gpu_id);
2570
2571 /* Start off with a safe cutoff, allowing usage of all 16 work
2572 * registers. Later, we'll promote uniform reads to uniform registers
2573 * if we determine it is beneficial to do so */
2574 ctx->uniform_cutoff = 8;
2575
2576 /* Initialize at a global (not block) level hash tables */
2577
2578 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2579 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2580
2581 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2582 * (so we don't accidentally duplicate the epilogue since mesa/st has
2583 * messed with our I/O quite a bit already) */
2584
2585 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2586
2587 if (ctx->stage == MESA_SHADER_VERTEX) {
2588 NIR_PASS_V(nir, nir_lower_viewport_transform);
2589 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2590 }
2591
2592 NIR_PASS_V(nir, nir_lower_var_copies);
2593 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2594 NIR_PASS_V(nir, nir_split_var_copies);
2595 NIR_PASS_V(nir, nir_lower_var_copies);
2596 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2597 NIR_PASS_V(nir, nir_lower_var_copies);
2598 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2599
2600 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2601 NIR_PASS_V(nir, nir_lower_ssbo);
2602 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2603
2604 /* Optimisation passes */
2605
2606 optimise_nir(nir, ctx->quirks, is_blend);
2607
2608 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2609 nir_print_shader(nir, stdout);
2610 }
2611
2612 /* Assign sysvals and counts, now that we're sure
2613 * (post-optimisation) */
2614
2615 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2616 program->sysval_count = ctx->sysvals.sysval_count;
2617 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2618
2619 nir_foreach_function(func, nir) {
2620 if (!func->impl)
2621 continue;
2622
2623 list_inithead(&ctx->blocks);
2624 ctx->block_count = 0;
2625 ctx->func = func;
2626 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
2627
2628 emit_cf_list(ctx, &func->impl->body);
2629 free(ctx->already_emitted);
2630 break; /* TODO: Multi-function shaders */
2631 }
2632
2633 util_dynarray_init(compiled, NULL);
2634
2635 /* Per-block lowering before opts */
2636
2637 mir_foreach_block(ctx, _block) {
2638 midgard_block *block = (midgard_block *) _block;
2639 inline_alu_constants(ctx, block);
2640 embedded_to_inline_constant(ctx, block);
2641 }
2642 /* MIR-level optimizations */
2643
2644 bool progress = false;
2645
2646 do {
2647 progress = false;
2648 progress |= midgard_opt_dead_code_eliminate(ctx);
2649
2650 mir_foreach_block(ctx, _block) {
2651 midgard_block *block = (midgard_block *) _block;
2652 progress |= midgard_opt_copy_prop(ctx, block);
2653 progress |= midgard_opt_combine_projection(ctx, block);
2654 progress |= midgard_opt_varying_projection(ctx, block);
2655 }
2656 } while (progress);
2657
2658 mir_foreach_block(ctx, _block) {
2659 midgard_block *block = (midgard_block *) _block;
2660 midgard_lower_derivatives(ctx, block);
2661 midgard_cull_dead_branch(ctx, block);
2662 }
2663
2664 if (ctx->stage == MESA_SHADER_FRAGMENT)
2665 mir_add_writeout_loops(ctx);
2666
2667 /* Analyze now that the code is known but before scheduling creates
2668 * pipeline registers which are harder to track */
2669 mir_analyze_helper_terminate(ctx);
2670 mir_analyze_helper_requirements(ctx);
2671
2672 /* Schedule! */
2673 midgard_schedule_program(ctx);
2674 mir_ra(ctx);
2675
2676 /* Now that all the bundles are scheduled and we can calculate block
2677 * sizes, emit actual branch instructions rather than placeholders */
2678
2679 int br_block_idx = 0;
2680
2681 mir_foreach_block(ctx, _block) {
2682 midgard_block *block = (midgard_block *) _block;
2683 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2684 for (int c = 0; c < bundle->instruction_count; ++c) {
2685 midgard_instruction *ins = bundle->instructions[c];
2686
2687 if (!midgard_is_branch_unit(ins->unit)) continue;
2688
2689 /* Parse some basic branch info */
2690 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2691 bool is_conditional = ins->branch.conditional;
2692 bool is_inverted = ins->branch.invert_conditional;
2693 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2694 bool is_writeout = ins->writeout;
2695
2696 /* Determine the block we're jumping to */
2697 int target_number = ins->branch.target_block;
2698
2699 /* Report the destination tag */
2700 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2701
2702 /* Count up the number of quadwords we're
2703 * jumping over = number of quadwords until
2704 * (br_block_idx, target_number) */
2705
2706 int quadword_offset = 0;
2707
2708 if (is_discard) {
2709 /* Ignored */
2710 } else if (target_number > br_block_idx) {
2711 /* Jump forward */
2712
2713 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2714 midgard_block *blk = mir_get_block(ctx, idx);
2715 assert(blk);
2716
2717 quadword_offset += blk->quadword_count;
2718 }
2719 } else {
2720 /* Jump backwards */
2721
2722 for (int idx = br_block_idx; idx >= target_number; --idx) {
2723 midgard_block *blk = mir_get_block(ctx, idx);
2724 assert(blk);
2725
2726 quadword_offset -= blk->quadword_count;
2727 }
2728 }
2729
2730 /* Unconditional extended branches (far jumps)
2731 * have issues, so we always use a conditional
2732 * branch, setting the condition to always for
2733 * unconditional. For compact unconditional
2734 * branches, cond isn't used so it doesn't
2735 * matter what we pick. */
2736
2737 midgard_condition cond =
2738 !is_conditional ? midgard_condition_always :
2739 is_inverted ? midgard_condition_false :
2740 midgard_condition_true;
2741
2742 midgard_jmp_writeout_op op =
2743 is_discard ? midgard_jmp_writeout_op_discard :
2744 is_writeout ? midgard_jmp_writeout_op_writeout :
2745 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2746 midgard_jmp_writeout_op_branch_cond;
2747
2748 if (!is_compact) {
2749 midgard_branch_extended branch =
2750 midgard_create_branch_extended(
2751 cond, op,
2752 dest_tag,
2753 quadword_offset);
2754
2755 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2756 } else if (is_conditional || is_discard) {
2757 midgard_branch_cond branch = {
2758 .op = op,
2759 .dest_tag = dest_tag,
2760 .offset = quadword_offset,
2761 .cond = cond
2762 };
2763
2764 assert(branch.offset == quadword_offset);
2765
2766 memcpy(&ins->br_compact, &branch, sizeof(branch));
2767 } else {
2768 assert(op == midgard_jmp_writeout_op_branch_uncond);
2769
2770 midgard_branch_uncond branch = {
2771 .op = op,
2772 .dest_tag = dest_tag,
2773 .offset = quadword_offset,
2774 .unknown = 1
2775 };
2776
2777 assert(branch.offset == quadword_offset);
2778
2779 memcpy(&ins->br_compact, &branch, sizeof(branch));
2780 }
2781 }
2782 }
2783
2784 ++br_block_idx;
2785 }
2786
2787 /* Emit flat binary from the instruction arrays. Iterate each block in
2788 * sequence. Save instruction boundaries such that lookahead tags can
2789 * be assigned easily */
2790
2791 /* Cache _all_ bundles in source order for lookahead across failed branches */
2792
2793 int bundle_count = 0;
2794 mir_foreach_block(ctx, _block) {
2795 midgard_block *block = (midgard_block *) _block;
2796 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2797 }
2798 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2799 int bundle_idx = 0;
2800 mir_foreach_block(ctx, _block) {
2801 midgard_block *block = (midgard_block *) _block;
2802 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2803 source_order_bundles[bundle_idx++] = bundle;
2804 }
2805 }
2806
2807 int current_bundle = 0;
2808
2809 /* Midgard prefetches instruction types, so during emission we
2810 * need to lookahead. Unless this is the last instruction, in
2811 * which we return 1. */
2812
2813 mir_foreach_block(ctx, _block) {
2814 midgard_block *block = (midgard_block *) _block;
2815 mir_foreach_bundle_in_block(block, bundle) {
2816 int lookahead = 1;
2817
2818 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2819 lookahead = source_order_bundles[current_bundle + 1]->tag;
2820
2821 emit_binary_bundle(ctx, block, bundle, compiled, lookahead);
2822 ++current_bundle;
2823 }
2824
2825 /* TODO: Free deeper */
2826 //util_dynarray_fini(&block->instructions);
2827 }
2828
2829 free(source_order_bundles);
2830
2831 /* Report the very first tag executed */
2832 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2833
2834 /* Deal with off-by-one related to the fencepost problem */
2835 program->work_register_count = ctx->work_registers + 1;
2836 program->uniform_cutoff = ctx->uniform_cutoff;
2837
2838 program->blend_patch_offset = ctx->blend_constant_offset;
2839 program->tls_size = ctx->tls_size;
2840
2841 if (midgard_debug & MIDGARD_DBG_SHADERS)
2842 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2843
2844 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2845 unsigned nr_bundles = 0, nr_ins = 0;
2846
2847 /* Count instructions and bundles */
2848
2849 mir_foreach_block(ctx, _block) {
2850 midgard_block *block = (midgard_block *) _block;
2851 nr_bundles += util_dynarray_num_elements(
2852 &block->bundles, midgard_bundle);
2853
2854 mir_foreach_bundle_in_block(block, bun)
2855 nr_ins += bun->instruction_count;
2856 }
2857
2858 /* Calculate thread count. There are certain cutoffs by
2859 * register count for thread count */
2860
2861 unsigned nr_registers = program->work_register_count;
2862
2863 unsigned nr_threads =
2864 (nr_registers <= 4) ? 4 :
2865 (nr_registers <= 8) ? 2 :
2866 1;
2867
2868 /* Dump stats */
2869
2870 fprintf(stderr, "shader%d - %s shader: "
2871 "%u inst, %u bundles, %u quadwords, "
2872 "%u registers, %u threads, %u loops, "
2873 "%u:%u spills:fills\n",
2874 SHADER_DB_COUNT++,
2875 ctx->is_blend ? "PAN_SHADER_BLEND" :
2876 gl_shader_stage_name(ctx->stage),
2877 nr_ins, nr_bundles, ctx->quadword_count,
2878 nr_registers, nr_threads,
2879 ctx->loop_count,
2880 ctx->spills, ctx->fills);
2881 }
2882
2883 ralloc_free(ctx);
2884
2885 return 0;
2886 }