src/panfrost/midgard/midgard_emit.c

   1 /*
   2  * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #include "compiler.h"
  25 #include "midgard_ops.h"
  26 #include "midgard_quirks.h"
  27
  28 static midgard_int_mod
  29 mir_get_imod(bool shift, nir_alu_type T, bool half, bool scalar)
  30 {
  31         if (!half) {
  32                 assert(!shift);
  33                 /* Sign-extension, really... */
  34                 return scalar ? 0 : midgard_int_normal;
  35         }
  36
  37         if (shift)
  38                 return midgard_int_shift;
  39
  40         if (nir_alu_type_get_base_type(T) == nir_type_int)
  41                 return midgard_int_sign_extend;
  42         else
  43                 return midgard_int_zero_extend;
  44 }
  45
  46 static unsigned
  47 mir_pack_mod(midgard_instruction *ins, unsigned i, bool scalar)
  48 {
  49         bool integer = midgard_is_integer_op(ins->op);
  50         unsigned base_size = (8 << ins->alu.reg_mode);
  51         unsigned sz = nir_alu_type_get_type_size(ins->src_types[i]);
  52         bool half = (sz == (base_size >> 1));
  53
  54         return integer ?
  55                 mir_get_imod(ins->src_shift[i], ins->src_types[i], half, scalar) :
  56                 ((ins->src_abs[i] << 0) |
  57                  ((ins->src_neg[i] << 1)));
  58 }
  59
  60 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
  61  * use scalar ALU instructions, for functional or performance reasons. To do
  62  * this, we just demote vector ALU payloads to scalar. */
  63
  64 static int
  65 component_from_mask(unsigned mask)
  66 {
  67         for (int c = 0; c < 8; ++c) {
  68                 if (mask & (1 << c))
  69                         return c;
  70         }
  71
  72         assert(0);
  73         return 0;
  74 }
  75
  76 static unsigned
  77 mir_pack_scalar_source(unsigned mod, bool is_full, unsigned component)
  78 {
  79         midgard_scalar_alu_src s = {
  80                 .mod = mod,
  81                 .full = is_full,
  82                 .component = component << (is_full ? 1 : 0)
  83         };
  84
  85         unsigned o;
  86         memcpy(&o, &s, sizeof(s));
  87
  88         return o & ((1 << 6) - 1);
  89 }
  90
  91 static midgard_scalar_alu
  92 vector_to_scalar_alu(midgard_vector_alu v, midgard_instruction *ins)
  93 {
  94         bool is_full = nir_alu_type_get_type_size(ins->dest_type) == 32;
  95
  96         bool half_0 = nir_alu_type_get_type_size(ins->src_types[0]) == 16;
  97         bool half_1 = nir_alu_type_get_type_size(ins->src_types[1]) == 16;
  98         unsigned comp = component_from_mask(ins->mask);
  99
 100         unsigned packed_src[2] = {
 101                 mir_pack_scalar_source(mir_pack_mod(ins, 0, true), !half_0, ins->swizzle[0][comp]),
 102                 mir_pack_scalar_source(mir_pack_mod(ins, 1, true), !half_1, ins->swizzle[1][comp])
 103         };
 104
 105         /* The output component is from the mask */
 106         midgard_scalar_alu s = {
 107                 .op = v.op,
 108                 .src1 = packed_src[0],
 109                 .src2 = packed_src[1],
 110                 .unknown = 0,
 111                 .outmod = v.outmod,
 112                 .output_full = is_full,
 113                 .output_component = comp
 114         };
 115
 116         /* Full components are physically spaced out */
 117         if (is_full) {
 118                 assert(s.output_component < 4);
 119                 s.output_component <<= 1;
 120         }
 121
 122         /* Inline constant is passed along rather than trying to extract it
 123          * from v */
 124
 125         if (ins->has_inline_constant) {
 126                 uint16_t imm = 0;
 127                 int lower_11 = ins->inline_constant & ((1 << 12) - 1);
 128                 imm |= (lower_11 >> 9) & 3;
 129                 imm |= (lower_11 >> 6) & 4;
 130                 imm |= (lower_11 >> 2) & 0x38;
 131                 imm |= (lower_11 & 63) << 6;
 132
 133                 s.src2 = imm;
 134         }
 135
 136         return s;
 137 }
 138
 139 /* 64-bit swizzles are super easy since there are 2 components of 2 components
 140  * in an 8-bit field ... lots of duplication to go around!
 141  *
 142  * Swizzles of 32-bit vectors accessed from 64-bit instructions are a little
 143  * funny -- pack them *as if* they were native 64-bit, using rep_* flags to
 144  * flag upper. For instance, xy would become 64-bit XY but that's just xyzw
 145  * native. Likewise, zz would become 64-bit XX with rep* so it would be xyxy
 146  * with rep. Pretty nifty, huh? */
 147
 148 static unsigned
 149 mir_pack_swizzle_64(unsigned *swizzle, unsigned max_component)
 150 {
 151         unsigned packed = 0;
 152
 153         for (unsigned i = 0; i < 2; ++i) {
 154                 assert(swizzle[i] <= max_component);
 155
 156                 unsigned a = (swizzle[i] & 1) ?
 157                         (COMPONENT_W << 2) | COMPONENT_Z :
 158                         (COMPONENT_Y << 2) | COMPONENT_X;
 159
 160                 packed |= a << (i * 4);
 161         }
 162
 163         return packed;
 164 }
 165
 166 static void
 167 mir_pack_mask_alu(midgard_instruction *ins)
 168 {
 169         unsigned effective = ins->mask;
 170
 171         /* If we have a destination override, we need to figure out whether to
 172          * override to the lower or upper half, shifting the effective mask in
 173          * the latter, so AAAA.... becomes AAAA */
 174
 175         unsigned inst_size = 8 << ins->alu.reg_mode;
 176         signed upper_shift = mir_upper_override(ins, inst_size);
 177
 178         if (upper_shift >= 0) {
 179                 effective >>= upper_shift;
 180                 ins->alu.dest_override = upper_shift ?
 181                         midgard_dest_override_upper :
 182                         midgard_dest_override_lower;
 183         } else {
 184                 ins->alu.dest_override = midgard_dest_override_none;
 185         }
 186
 187         if (ins->alu.reg_mode == midgard_reg_mode_32)
 188                 ins->alu.mask = expand_writemask(effective, 2);
 189         else if (ins->alu.reg_mode == midgard_reg_mode_64)
 190                 ins->alu.mask = expand_writemask(effective, 1);
 191         else
 192                 ins->alu.mask = effective;
 193 }
 194
 195 static unsigned
 196 mir_pack_swizzle(unsigned mask, unsigned *swizzle,
 197                 nir_alu_type T, midgard_reg_mode reg_mode,
 198                 bool op_channeled, bool *rep_low, bool *rep_high)
 199 {
 200         unsigned packed = 0;
 201         unsigned sz = nir_alu_type_get_type_size(T);
 202
 203         if (reg_mode == midgard_reg_mode_64) {
 204                 assert(sz == 64 || sz == 32);
 205                 unsigned components = (sz == 32) ? 4 : 2;
 206
 207                 packed = mir_pack_swizzle_64(swizzle, components);
 208
 209                 if (sz == 32) {
 210                         bool lo = swizzle[0] >= COMPONENT_Z;
 211                         bool hi = swizzle[1] >= COMPONENT_Z;
 212
 213                         if (mask & 0x1) {
 214                                 /* We can't mix halves... */
 215                                 if (mask & 2)
 216                                         assert(lo == hi);
 217
 218                                 *rep_low = lo;
 219                         } else {
 220                                 *rep_low = hi;
 221                         }
 222                 } else if (sz < 32) {
 223                         unreachable("Cannot encode 8/16 swizzle in 64-bit");
 224                 }
 225         } else {
 226                 /* For 32-bit, swizzle packing is stupid-simple. For 16-bit,
 227                  * the strategy is to check whether the nibble we're on is
 228                  * upper or lower. We need all components to be on the same
 229                  * "side"; that much is enforced by the ISA and should have
 230                  * been lowered. TODO: 8-bit packing. TODO: vec8 */
 231
 232                 unsigned first = mask ? ffs(mask) - 1 : 0;
 233                 bool upper = swizzle[first] > 3;
 234
 235                 if (upper && mask)
 236                         assert(sz <= 16);
 237
 238                 bool dest_up = !op_channeled && (first >= 4);
 239
 240                 for (unsigned c = (dest_up ? 4 : 0); c < (dest_up ? 8 : 4); ++c) {
 241                         unsigned v = swizzle[c];
 242
 243                         bool t_upper = v > 3;
 244
 245                         /* Ensure we're doing something sane */
 246
 247                         if (mask & (1 << c)) {
 248                                 assert(t_upper == upper);
 249                                 assert(v <= 7);
 250                         }
 251
 252                         /* Use the non upper part */
 253                         v &= 0x3;
 254
 255                         packed |= v << (2 * (c % 4));
 256                 }
 257
 258
 259                 /* Replicate for now.. should really pick a side for
 260                  * dot products */
 261
 262                 if (reg_mode == midgard_reg_mode_16 && sz == 16) {
 263                         *rep_low = !upper;
 264                         *rep_high = upper;
 265                 } else if (reg_mode == midgard_reg_mode_16 && sz == 8) {
 266                         *rep_low = upper;
 267                         *rep_high = upper;
 268                 } else if (reg_mode == midgard_reg_mode_32) {
 269                         *rep_low = upper;
 270                 } else {
 271                         unreachable("Unhandled reg mode");
 272                 }
 273         }
 274
 275         return packed;
 276 }
 277
 278 static void
 279 mir_pack_vector_srcs(midgard_instruction *ins)
 280 {
 281         bool channeled = GET_CHANNEL_COUNT(alu_opcode_props[ins->op].props);
 282
 283         midgard_reg_mode mode = ins->alu.reg_mode;
 284         unsigned base_size = (8 << mode);
 285
 286         for (unsigned i = 0; i < 2; ++i) {
 287                 if (ins->has_inline_constant && (i == 1))
 288                         continue;
 289
 290                 if (ins->src[i] == ~0)
 291                         continue;
 292
 293                 bool rep_lo = false, rep_hi = false;
 294                 unsigned sz = nir_alu_type_get_type_size(ins->src_types[i]);
 295                 bool half = (sz == (base_size >> 1));
 296
 297                 assert((sz == base_size) || half);
 298
 299                 unsigned swizzle = mir_pack_swizzle(ins->mask, ins->swizzle[i],
 300                                 ins->src_types[i], ins->alu.reg_mode,
 301                                 channeled, &rep_lo, &rep_hi);
 302
 303                 midgard_vector_alu_src pack = {
 304                         .mod = mir_pack_mod(ins, i, false),
 305                         .rep_low = rep_lo,
 306                         .rep_high = rep_hi,
 307                         .half = half,
 308                         .swizzle = swizzle
 309                 };
 310
 311                 unsigned p = vector_alu_srco_unsigned(pack);
 312
 313                 if (i == 0)
 314                         ins->alu.src1 = p;
 315                 else
 316                         ins->alu.src2 = p;
 317         }
 318 }
 319
 320 static void
 321 mir_pack_swizzle_ldst(midgard_instruction *ins)
 322 {
 323         /* TODO: non-32-bit, non-vec4 */
 324         for (unsigned c = 0; c < 4; ++c) {
 325                 unsigned v = ins->swizzle[0][c];
 326
 327                 /* Check vec4 */
 328                 assert(v <= 3);
 329
 330                 ins->load_store.swizzle |= v << (2 * c);
 331         }
 332
 333         /* TODO: arg_1/2 */
 334 }
 335
 336 static void
 337 mir_pack_swizzle_tex(midgard_instruction *ins)
 338 {
 339         for (unsigned i = 0; i < 2; ++i) {
 340                 unsigned packed = 0;
 341
 342                 for (unsigned c = 0; c < 4; ++c) {
 343                         unsigned v = ins->swizzle[i][c];
 344
 345                         /* Check vec4 */
 346                         assert(v <= 3);
 347
 348                         packed |= v << (2 * c);
 349                 }
 350
 351                 if (i == 0)
 352                         ins->texture.swizzle = packed;
 353                 else
 354                         ins->texture.in_reg_swizzle = packed;
 355         }
 356
 357         /* TODO: bias component */
 358 }
 359
 360 /* Up to 3 { ALU, LDST } bundles can execute in parallel with a texture op.
 361  * Given a texture op, lookahead to see how many such bundles we can flag for
 362  * OoO execution */
 363
 364 static bool
 365 mir_can_run_ooo(midgard_block *block, midgard_bundle *bundle,
 366                 unsigned dependency)
 367 {
 368         /* Don't read out of bounds */
 369         if (bundle >= (midgard_bundle *) ((char *) block->bundles.data + block->bundles.size))
 370                 return false;
 371
 372         /* Texture ops can't execute with other texture ops */
 373         if (!IS_ALU(bundle->tag) && bundle->tag != TAG_LOAD_STORE_4)
 374                 return false;
 375
 376         /* Ensure there is no read-after-write dependency */
 377
 378         for (unsigned i = 0; i < bundle->instruction_count; ++i) {
 379                 midgard_instruction *ins = bundle->instructions[i];
 380
 381                 mir_foreach_src(ins, s) {
 382                         if (ins->src[s] == dependency)
 383                                 return false;
 384                 }
 385         }
 386
 387         /* Otherwise, we're okay */
 388         return true;
 389 }
 390
 391 static void
 392 mir_pack_tex_ooo(midgard_block *block, midgard_bundle *bundle, midgard_instruction *ins)
 393 {
 394         unsigned count = 0;
 395
 396         for (count = 0; count < 3; ++count) {
 397                 if (!mir_can_run_ooo(block, bundle + count + 1, ins->dest))
 398                         break;
 399         }
 400
 401         ins->texture.out_of_order = count;
 402 }
 403
 404 /* Load store masks are 4-bits. Load/store ops pack for that. vec4 is the
 405  * natural mask width; vec8 is constrained to be in pairs, vec2 is duplicated. TODO: 8-bit?
 406  */
 407
 408 static void
 409 mir_pack_ldst_mask(midgard_instruction *ins)
 410 {
 411         unsigned sz = nir_alu_type_get_type_size(ins->dest_type);
 412         unsigned packed = ins->mask;
 413
 414         if (sz == 64) {
 415                 packed = ((ins->mask & 0x2) ? (0x8 | 0x4) : 0) |
 416                          ((ins->mask & 0x1) ? (0x2 | 0x1) : 0);
 417         } else if (sz == 16) {
 418                 packed = 0;
 419
 420                 for (unsigned i = 0; i < 4; ++i) {
 421                         /* Make sure we're duplicated */
 422                         bool u = (ins->mask & (1 << (2*i + 0))) != 0;
 423                         bool v = (ins->mask & (1 << (2*i + 1))) != 0;
 424                         assert(u == v);
 425
 426                         packed |= (u << i);
 427                 }
 428         } else {
 429                 assert(sz == 32);
 430         }
 431
 432         ins->load_store.mask = packed;
 433 }
 434
 435 static void
 436 mir_lower_inverts(midgard_instruction *ins)
 437 {
 438         bool inv[3] = {
 439                 ins->src_invert[0],
 440                 ins->src_invert[1],
 441                 ins->src_invert[2]
 442         };
 443
 444         switch (ins->op) {
 445         case midgard_alu_op_iand:
 446                 /* a & ~b = iandnot(a, b) */
 447                 /* ~a & ~b = ~(a | b) = inor(a, b) */
 448
 449                 if (inv[0] && inv[1])
 450                         ins->op = midgard_alu_op_inor;
 451                 else if (inv[1])
 452                         ins->op = midgard_alu_op_iandnot;
 453
 454                 break;
 455         case midgard_alu_op_ior:
 456                 /*  a | ~b = iornot(a, b) */
 457                 /* ~a | ~b = ~(a & b) = inand(a, b) */
 458
 459                 if (inv[0] && inv[1])
 460                         ins->op = midgard_alu_op_inand;
 461                 else if (inv[1])
 462                         ins->op = midgard_alu_op_iornot;
 463
 464                 break;
 465
 466         case midgard_alu_op_ixor:
 467                 /* ~a ^ b = a ^ ~b = ~(a ^ b) = inxor(a, b) */
 468                 /* ~a ^ ~b = a ^ b */
 469
 470                 if (inv[0] ^ inv[1])
 471                         ins->op = midgard_alu_op_inxor;
 472
 473                 break;
 474
 475         default:
 476                 break;
 477         }
 478 }
 479
 480 /* Opcodes with ROUNDS are the base (rte/0) type so we can just add */
 481
 482 static void
 483 mir_lower_roundmode(midgard_instruction *ins)
 484 {
 485         if (alu_opcode_props[ins->op].props & MIDGARD_ROUNDS) {
 486                 assert(ins->roundmode <= 0x3);
 487                 ins->op += ins->roundmode;
 488         }
 489 }
 490
 491 static void
 492 emit_alu_bundle(compiler_context *ctx,
 493                 midgard_bundle *bundle,
 494                 struct util_dynarray *emission,
 495                 unsigned lookahead)
 496 {
 497         /* Emit the control word */
 498         util_dynarray_append(emission, uint32_t, bundle->control | lookahead);
 499
 500         /* Next up, emit register words */
 501         for (unsigned i = 0; i < bundle->instruction_count; ++i) {
 502                 midgard_instruction *ins = bundle->instructions[i];
 503
 504                 /* Check if this instruction has registers */
 505                 if (ins->compact_branch) continue;
 506
 507                 /* Otherwise, just emit the registers */
 508                 uint16_t reg_word = 0;
 509                 memcpy(&reg_word, &ins->registers, sizeof(uint16_t));
 510                 util_dynarray_append(emission, uint16_t, reg_word);
 511         }
 512
 513         /* Now, we emit the body itself */
 514         for (unsigned i = 0; i < bundle->instruction_count; ++i) {
 515                 midgard_instruction *ins = bundle->instructions[i];
 516
 517                 /* Where is this body */
 518                 unsigned size = 0;
 519                 void *source = NULL;
 520
 521                 midgard_vector_alu source_alu;
 522
 523                 /* In case we demote to a scalar */
 524                 midgard_scalar_alu scalarized;
 525
 526                 if (!ins->compact_branch) {
 527                         mir_lower_inverts(ins);
 528                         mir_lower_roundmode(ins);
 529                 }
 530
 531                 if (ins->unit & UNITS_ANY_VECTOR) {
 532                         mir_pack_mask_alu(ins);
 533                         mir_pack_vector_srcs(ins);
 534                         size = sizeof(midgard_vector_alu);
 535                         source_alu = ins->alu;
 536                         source_alu.op = ins->op;
 537                         source = &source_alu;
 538                 } else if (ins->unit == ALU_ENAB_BR_COMPACT) {
 539                         size = sizeof(midgard_branch_cond);
 540                         source = &ins->br_compact;
 541                 } else if (ins->compact_branch) { /* misnomer */
 542                         size = sizeof(midgard_branch_extended);
 543                         source = &ins->branch_extended;
 544                 } else {
 545                         size = sizeof(midgard_scalar_alu);
 546                         source_alu = ins->alu;
 547                         source_alu.op = ins->op;
 548                         scalarized = vector_to_scalar_alu(source_alu, ins);
 549                         source = &scalarized;
 550                 }
 551
 552                 memcpy(util_dynarray_grow_bytes(emission, size, 1), source, size);
 553         }
 554
 555         /* Emit padding (all zero) */
 556         memset(util_dynarray_grow_bytes(emission, bundle->padding, 1), 0, bundle->padding);
 557
 558         /* Tack on constants */
 559
 560         if (bundle->has_embedded_constants)
 561                 util_dynarray_append(emission, midgard_constants, bundle->constants);
 562 }
 563
 564 /* Shift applied to the immediate used as an offset. Probably this is papering
 565  * over some other semantic distinction else well, but it unifies things in the
 566  * compiler so I don't mind. */
 567
 568 static unsigned
 569 mir_ldst_imm_shift(midgard_load_store_op op)
 570 {
 571         if (OP_IS_UBO_READ(op))
 572                 return 3;
 573         else
 574                 return 1;
 575 }
 576
 577 static enum mali_sampler_type
 578 midgard_sampler_type(nir_alu_type t) {
 579         switch (nir_alu_type_get_base_type(t))
 580         {
 581         case nir_type_float:
 582                 return MALI_SAMPLER_FLOAT;
 583         case nir_type_int:
 584                 return MALI_SAMPLER_SIGNED;
 585         case nir_type_uint:
 586                 return MALI_SAMPLER_UNSIGNED;
 587         default:
 588                 unreachable("Unknown sampler type");
 589         }
 590 }
 591
 592 /* After everything is scheduled, emit whole bundles at a time */
 593
 594 void
 595 emit_binary_bundle(compiler_context *ctx,
 596                    midgard_block *block,
 597                    midgard_bundle *bundle,
 598                    struct util_dynarray *emission,
 599                    int next_tag)
 600 {
 601         int lookahead = next_tag << 4;
 602
 603         switch (bundle->tag) {
 604         case TAG_ALU_4:
 605         case TAG_ALU_8:
 606         case TAG_ALU_12:
 607         case TAG_ALU_16:
 608         case TAG_ALU_4 + 4:
 609         case TAG_ALU_8 + 4:
 610         case TAG_ALU_12 + 4:
 611         case TAG_ALU_16 + 4:
 612                 emit_alu_bundle(ctx, bundle, emission, lookahead);
 613                 break;
 614
 615         case TAG_LOAD_STORE_4: {
 616                 /* One or two composing instructions */
 617
 618                 uint64_t current64, next64 = LDST_NOP;
 619
 620                 /* Copy masks */
 621
 622                 for (unsigned i = 0; i < bundle->instruction_count; ++i) {
 623                         mir_pack_ldst_mask(bundle->instructions[i]);
 624
 625                         mir_pack_swizzle_ldst(bundle->instructions[i]);
 626
 627                         /* Apply a constant offset */
 628                         unsigned offset = bundle->instructions[i]->constants.u32[0];
 629
 630                         if (offset) {
 631                                 unsigned shift = mir_ldst_imm_shift(bundle->instructions[i]->load_store.op);
 632                                 unsigned upper_shift = 10 - shift;
 633
 634                                 bundle->instructions[i]->load_store.varying_parameters |= (offset & ((1 << upper_shift) - 1)) << shift;
 635                                 bundle->instructions[i]->load_store.address |= (offset >> upper_shift);
 636                         }
 637                 }
 638
 639                 memcpy(&current64, &bundle->instructions[0]->load_store, sizeof(current64));
 640
 641                 if (bundle->instruction_count == 2)
 642                         memcpy(&next64, &bundle->instructions[1]->load_store, sizeof(next64));
 643
 644                 midgard_load_store instruction = {
 645                         .type = bundle->tag,
 646                         .next_type = next_tag,
 647                         .word1 = current64,
 648                         .word2 = next64
 649                 };
 650
 651                 util_dynarray_append(emission, midgard_load_store, instruction);
 652
 653                 break;
 654         }
 655
 656         case TAG_TEXTURE_4:
 657         case TAG_TEXTURE_4_VTX:
 658         case TAG_TEXTURE_4_BARRIER: {
 659                 /* Texture instructions are easy, since there is no pipelining
 660                  * nor VLIW to worry about. We may need to set .cont/.last
 661                  * flags. */
 662
 663                 midgard_instruction *ins = bundle->instructions[0];
 664
 665                 ins->texture.type = bundle->tag;
 666                 ins->texture.next_type = next_tag;
 667
 668                 /* Nothing else to pack for barriers */
 669                 if (ins->texture.op == TEXTURE_OP_BARRIER) {
 670                         ins->texture.cont = ins->texture.last = 1;
 671                         util_dynarray_append(emission, midgard_texture_word, ins->texture);
 672                         return;
 673                 }
 674
 675                 signed override = mir_upper_override(ins, 32);
 676
 677                 ins->texture.mask = override > 0 ?
 678                         ins->mask >> override :
 679                         ins->mask;
 680
 681                 mir_pack_swizzle_tex(ins);
 682
 683                 if (!(ctx->quirks & MIDGARD_NO_OOO))
 684                         mir_pack_tex_ooo(block, bundle, ins);
 685
 686                 unsigned osz = nir_alu_type_get_type_size(ins->dest_type);
 687                 unsigned isz = nir_alu_type_get_type_size(ins->src_types[1]);
 688
 689                 assert(osz == 32 || osz == 16);
 690                 assert(isz == 32 || isz == 16);
 691
 692                 ins->texture.out_full = (osz == 32);
 693                 ins->texture.out_upper = override > 0;
 694                 ins->texture.in_reg_full = (isz == 32);
 695                 ins->texture.sampler_type = midgard_sampler_type(ins->dest_type);
 696
 697                 if (mir_op_computes_derivatives(ctx->stage, ins->texture.op)) {
 698                         ins->texture.cont = !ins->helper_terminate;
 699                         ins->texture.last = ins->helper_terminate || ins->helper_execute;
 700                 } else {
 701                         ins->texture.cont = ins->texture.last = 1;
 702                 }
 703
 704                 util_dynarray_append(emission, midgard_texture_word, ins->texture);
 705                 break;
 706         }
 707
 708         default:
 709                 unreachable("Unknown midgard instruction type\n");
 710         }
 711 }