src/panfrost/midgard/midgard_emit.c

   1 /*
   2  * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #include "compiler.h"
  25 #include "midgard_ops.h"
  26
  27 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
  28  * use scalar ALU instructions, for functional or performance reasons. To do
  29  * this, we just demote vector ALU payloads to scalar. */
  30
  31 static int
  32 component_from_mask(unsigned mask)
  33 {
  34         for (int c = 0; c < 8; ++c) {
  35                 if (mask & (1 << c))
  36                         return c;
  37         }
  38
  39         assert(0);
  40         return 0;
  41 }
  42
  43 static unsigned
  44 vector_to_scalar_source(unsigned u, bool is_int, bool is_full,
  45                 unsigned component)
  46 {
  47         midgard_vector_alu_src v;
  48         memcpy(&v, &u, sizeof(v));
  49
  50         /* TODO: Integers */
  51
  52         midgard_scalar_alu_src s = { 0 };
  53
  54         if (is_full) {
  55                 /* For a 32-bit op, just check the source half flag */
  56                 s.full = !v.half;
  57         } else if (!v.half) {
  58                 /* For a 16-bit op that's not subdivided, never full */
  59                 s.full = false;
  60         } else {
  61                 /* We can't do 8-bit scalar, abort! */
  62                 assert(0);
  63         }
  64
  65         /* Component indexing takes size into account */
  66
  67         if (s.full)
  68                 s.component = component << 1;
  69         else
  70                 s.component = component;
  71
  72         if (is_int) {
  73                 /* TODO */
  74         } else {
  75                 s.abs = v.mod & MIDGARD_FLOAT_MOD_ABS;
  76                 s.negate = v.mod & MIDGARD_FLOAT_MOD_NEG;
  77         }
  78
  79         unsigned o;
  80         memcpy(&o, &s, sizeof(s));
  81
  82         return o & ((1 << 6) - 1);
  83 }
  84
  85 static midgard_scalar_alu
  86 vector_to_scalar_alu(midgard_vector_alu v, midgard_instruction *ins)
  87 {
  88         bool is_int = midgard_is_integer_op(v.op);
  89         bool is_full = v.reg_mode == midgard_reg_mode_32;
  90         bool is_inline_constant = ins->has_inline_constant;
  91
  92         unsigned comp = component_from_mask(ins->mask);
  93
  94         /* The output component is from the mask */
  95         midgard_scalar_alu s = {
  96                 .op = v.op,
  97                 .src1 = vector_to_scalar_source(v.src1, is_int, is_full, ins->swizzle[0][comp]),
  98                 .src2 = !is_inline_constant ? vector_to_scalar_source(v.src2, is_int, is_full, ins->swizzle[1][comp]) : 0,
  99                 .unknown = 0,
 100                 .outmod = v.outmod,
 101                 .output_full = is_full,
 102                 .output_component = comp
 103         };
 104
 105         /* Full components are physically spaced out */
 106         if (is_full) {
 107                 assert(s.output_component < 4);
 108                 s.output_component <<= 1;
 109         }
 110
 111         /* Inline constant is passed along rather than trying to extract it
 112          * from v */
 113
 114         if (ins->has_inline_constant) {
 115                 uint16_t imm = 0;
 116                 int lower_11 = ins->inline_constant & ((1 << 12) - 1);
 117                 imm |= (lower_11 >> 9) & 3;
 118                 imm |= (lower_11 >> 6) & 4;
 119                 imm |= (lower_11 >> 2) & 0x38;
 120                 imm |= (lower_11 & 63) << 6;
 121
 122                 s.src2 = imm;
 123         }
 124
 125         return s;
 126 }
 127
 128 /* 64-bit swizzles are super easy since there are 2 components of 2 components
 129  * in an 8-bit field ... lots of duplication to go around!
 130  *
 131  * Swizzles of 32-bit vectors accessed from 64-bit instructions are a little
 132  * funny -- pack them *as if* they were native 64-bit, using rep_* flags to
 133  * flag upper. For instance, xy would become 64-bit XY but that's just xyzw
 134  * native. Likewise, zz would become 64-bit XX with rep* so it would be xyxy
 135  * with rep. Pretty nifty, huh? */
 136
 137 static unsigned
 138 mir_pack_swizzle_64(unsigned *swizzle, unsigned max_component)
 139 {
 140         unsigned packed = 0;
 141
 142         for (unsigned i = 0; i < 2; ++i) {
 143                 assert(swizzle[i] <= max_component);
 144
 145                 unsigned a = swizzle[i] & 1 ?
 146                         (COMPONENT_W << 2) | COMPONENT_Z :
 147                         (COMPONENT_Y << 2) | COMPONENT_X;
 148
 149                 packed |= a << (i * 4);
 150         }
 151
 152         return packed;
 153 }
 154
 155 static void
 156 mir_pack_swizzle_alu(midgard_instruction *ins)
 157 {
 158         midgard_vector_alu_src src[] = {
 159                 vector_alu_from_unsigned(ins->alu.src1),
 160                 vector_alu_from_unsigned(ins->alu.src2)
 161         };
 162
 163         for (unsigned i = 0; i < 2; ++i) {
 164                 unsigned packed = 0;
 165
 166                 if (ins->alu.reg_mode == midgard_reg_mode_64) {
 167                         midgard_reg_mode mode = mir_srcsize(ins, i);
 168                         unsigned components = 16 / mir_bytes_for_mode(mode);
 169
 170                         packed = mir_pack_swizzle_64(ins->swizzle[i], components);
 171
 172                         if (mode == midgard_reg_mode_32) {
 173                                 src[i].rep_low |= (ins->swizzle[i][0] >= COMPONENT_Z);
 174                                 src[i].rep_high |= (ins->swizzle[i][1] >= COMPONENT_Z);
 175                         } else if (mode < midgard_reg_mode_32) {
 176                                 unreachable("Cannot encode 8/16 swizzle in 64-bit");
 177                         }
 178                 } else {
 179                         /* For 32-bit, swizzle packing is stupid-simple. For 16-bit,
 180                          * the strategy is to check whether the nibble we're on is
 181                          * upper or lower. We need all components to be on the same
 182                          * "side"; that much is enforced by the ISA and should have
 183                          * been lowered. TODO: 8-bit packing. TODO: vec8 */
 184
 185                         unsigned first = ins->mask ? ffs(ins->mask) - 1 : 0;
 186                         bool upper = ins->swizzle[i][first] > 3;
 187
 188                         if (upper && ins->mask)
 189                                 assert(mir_srcsize(ins, i) <= midgard_reg_mode_16);
 190
 191                         for (unsigned c = 0; c < 4; ++c) {
 192                                 unsigned v = ins->swizzle[i][c];
 193
 194                                 bool t_upper = v > 3;
 195
 196                                 /* Ensure we're doing something sane */
 197
 198                                 if (ins->mask & (1 << c)) {
 199                                         assert(t_upper == upper);
 200                                         assert(v <= 7);
 201                                 }
 202
 203                                 /* Use the non upper part */
 204                                 v &= 0x3;
 205
 206                                 packed |= v << (2 * c);
 207                         }
 208
 209                         src[i].rep_high = upper;
 210                 }
 211
 212                 src[i].swizzle = packed;
 213         }
 214
 215         ins->alu.src1 = vector_alu_srco_unsigned(src[0]);
 216
 217         if (!ins->has_inline_constant)
 218                 ins->alu.src2 = vector_alu_srco_unsigned(src[1]);
 219 }
 220
 221 static void
 222 mir_pack_swizzle_ldst(midgard_instruction *ins)
 223 {
 224         /* TODO: non-32-bit, non-vec4 */
 225         for (unsigned c = 0; c < 4; ++c) {
 226                 unsigned v = ins->swizzle[0][c];
 227
 228                 /* Check vec4 */
 229                 assert(v <= 3);
 230
 231                 ins->load_store.swizzle |= v << (2 * c);
 232         }
 233
 234         /* TODO: arg_1/2 */
 235 }
 236
 237 static void
 238 mir_pack_swizzle_tex(midgard_instruction *ins)
 239 {
 240         for (unsigned i = 0; i < 2; ++i) {
 241                 unsigned packed = 0;
 242
 243                 for (unsigned c = 0; c < 4; ++c) {
 244                         unsigned v = ins->swizzle[i][c];
 245
 246                         /* Check vec4 */
 247                         assert(v <= 3);
 248
 249                         packed |= v << (2 * c);
 250                 }
 251
 252                 if (i == 0)
 253                         ins->texture.swizzle = packed;
 254                 else
 255                         ins->texture.in_reg_swizzle = packed;
 256         }
 257
 258         /* TODO: bias component */
 259 }
 260
 261 /* Load store masks are 4-bits. Load/store ops pack for that. vec4 is the
 262  * natural mask width; vec8 is constrained to be in pairs, vec2 is duplicated. TODO: 8-bit?
 263  */
 264
 265 static void
 266 mir_pack_ldst_mask(midgard_instruction *ins)
 267 {
 268         midgard_reg_mode mode = mir_typesize(ins);
 269         unsigned packed = ins->mask;
 270
 271         if (mode == midgard_reg_mode_64) {
 272                 packed = ((ins->mask & 0x2) ? (0x8 | 0x4) : 0) |
 273                          ((ins->mask & 0x1) ? (0x2 | 0x1) : 0);
 274         } else if (mode == midgard_reg_mode_16) {
 275                 packed = 0;
 276
 277                 for (unsigned i = 0; i < 4; ++i) {
 278                         /* Make sure we're duplicated */
 279                         bool u = (ins->mask & (1 << (2*i + 0))) != 0;
 280                         bool v = (ins->mask & (1 << (2*i + 1))) != 0;
 281                         assert(u == v);
 282
 283                         packed |= (u << i);
 284                 }
 285         }
 286
 287         ins->load_store.mask = packed;
 288 }
 289
 290 static void
 291 emit_alu_bundle(compiler_context *ctx,
 292                 midgard_bundle *bundle,
 293                 struct util_dynarray *emission,
 294                 unsigned lookahead)
 295 {
 296         /* Emit the control word */
 297         util_dynarray_append(emission, uint32_t, bundle->control | lookahead);
 298
 299         /* Next up, emit register words */
 300         for (unsigned i = 0; i < bundle->instruction_count; ++i) {
 301                 midgard_instruction *ins = bundle->instructions[i];
 302
 303                 /* Check if this instruction has registers */
 304                 if (ins->compact_branch || ins->prepacked_branch) continue;
 305
 306                 /* Otherwise, just emit the registers */
 307                 uint16_t reg_word = 0;
 308                 memcpy(&reg_word, &ins->registers, sizeof(uint16_t));
 309                 util_dynarray_append(emission, uint16_t, reg_word);
 310         }
 311
 312         /* Now, we emit the body itself */
 313         for (unsigned i = 0; i < bundle->instruction_count; ++i) {
 314                 midgard_instruction *ins = bundle->instructions[i];
 315
 316                 /* Where is this body */
 317                 unsigned size = 0;
 318                 void *source = NULL;
 319
 320                 /* In case we demote to a scalar */
 321                 midgard_scalar_alu scalarized;
 322
 323                 if (ins->unit & UNITS_ANY_VECTOR) {
 324                         if (ins->alu.reg_mode == midgard_reg_mode_64)
 325                                 ins->alu.mask = expand_writemask(ins->mask, 2);
 326                         else if (ins->alu.reg_mode == midgard_reg_mode_32)
 327                                 ins->alu.mask = expand_writemask(ins->mask, 4);
 328                         else
 329                                 ins->alu.mask = ins->mask;
 330
 331                         mir_pack_swizzle_alu(ins);
 332                         size = sizeof(midgard_vector_alu);
 333                         source = &ins->alu;
 334                 } else if (ins->unit == ALU_ENAB_BR_COMPACT) {
 335                         size = sizeof(midgard_branch_cond);
 336                         source = &ins->br_compact;
 337                 } else if (ins->compact_branch) { /* misnomer */
 338                         size = sizeof(midgard_branch_extended);
 339                         source = &ins->branch_extended;
 340                 } else {
 341                         size = sizeof(midgard_scalar_alu);
 342                         scalarized = vector_to_scalar_alu(ins->alu, ins);
 343                         source = &scalarized;
 344                 }
 345
 346                 memcpy(util_dynarray_grow_bytes(emission, 1, size), source, size);
 347         }
 348
 349         /* Emit padding (all zero) */
 350         memset(util_dynarray_grow_bytes(emission, 1, bundle->padding), 0, bundle->padding);
 351
 352         /* Tack on constants */
 353
 354         if (bundle->has_embedded_constants) {
 355                 util_dynarray_append(emission, float, bundle->constants[0]);
 356                 util_dynarray_append(emission, float, bundle->constants[1]);
 357                 util_dynarray_append(emission, float, bundle->constants[2]);
 358                 util_dynarray_append(emission, float, bundle->constants[3]);
 359         }
 360 }
 361
 362 /* After everything is scheduled, emit whole bundles at a time */
 363
 364 void
 365 emit_binary_bundle(compiler_context *ctx,
 366                    midgard_bundle *bundle,
 367                    struct util_dynarray *emission,
 368                    int next_tag)
 369 {
 370         int lookahead = next_tag << 4;
 371
 372         switch (bundle->tag) {
 373         case TAG_ALU_4:
 374         case TAG_ALU_8:
 375         case TAG_ALU_12:
 376         case TAG_ALU_16:
 377                 emit_alu_bundle(ctx, bundle, emission, lookahead);
 378                 break;
 379
 380         case TAG_LOAD_STORE_4: {
 381                 /* One or two composing instructions */
 382
 383                 uint64_t current64, next64 = LDST_NOP;
 384
 385                 /* Copy masks */
 386
 387                 for (unsigned i = 0; i < bundle->instruction_count; ++i) {
 388                         mir_pack_ldst_mask(bundle->instructions[i]);
 389
 390                         mir_pack_swizzle_ldst(bundle->instructions[i]);
 391                 }
 392
 393                 memcpy(&current64, &bundle->instructions[0]->load_store, sizeof(current64));
 394
 395                 if (bundle->instruction_count == 2)
 396                         memcpy(&next64, &bundle->instructions[1]->load_store, sizeof(next64));
 397
 398                 midgard_load_store instruction = {
 399                         .type = bundle->tag,
 400                         .next_type = next_tag,
 401                         .word1 = current64,
 402                         .word2 = next64
 403                 };
 404
 405                 util_dynarray_append(emission, midgard_load_store, instruction);
 406
 407                 break;
 408         }
 409
 410         case TAG_TEXTURE_4:
 411         case TAG_TEXTURE_4_VTX: {
 412                 /* Texture instructions are easy, since there is no pipelining
 413                  * nor VLIW to worry about. We may need to set .cont/.last
 414                  * flags. */
 415
 416                 midgard_instruction *ins = bundle->instructions[0];
 417
 418                 ins->texture.type = bundle->tag;
 419                 ins->texture.next_type = next_tag;
 420                 ins->texture.mask = ins->mask;
 421                 mir_pack_swizzle_tex(ins);
 422
 423                 ctx->texture_op_count--;
 424
 425                 if (mir_op_computes_derivatives(ins->texture.op)) {
 426                         bool continues = ctx->texture_op_count > 0;
 427
 428                         /* Control flow complicates helper invocation
 429                          * lifespans, so for now just keep helper threads
 430                          * around indefinitely with loops. TODO: Proper
 431                          * analysis */
 432                         continues |= ctx->loop_count > 0;
 433
 434                         ins->texture.cont = continues;
 435                         ins->texture.last = !continues;
 436                 } else {
 437                         ins->texture.cont = ins->texture.last = 1;
 438                 }
 439
 440                 util_dynarray_append(emission, midgard_texture_word, ins->texture);
 441                 break;
 442         }
 443
 444         default:
 445                 unreachable("Unknown midgard instruction type\n");
 446         }
 447 }