2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 * Copyright (C) 2019 Collabora, Ltd.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 #include "midgard_ops.h"
27 #include "util/register_allocate.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
31 /* For work registers, we can subdivide in various ways. So we create
32 * classes for the various sizes and conflict accordingly, keeping in
33 * mind that physical registers are divided along 128-bit boundaries.
34 * The important part is that 128-bit boundaries are not crossed.
36 * For each 128-bit register, we can subdivide to 32-bits 10 ways
43 * For each 64-bit register, we can subdivide similarly to 16-bit
44 * (TODO: half-float RA, not that we support fp16 yet)
47 #define WORK_STRIDE 10
49 /* We have overlapping register classes for special registers, handled via
56 /* Prepacked masks/swizzles for virtual register types */
57 static unsigned reg_type_to_mask
[WORK_STRIDE
] = {
59 0x7, 0x7 << 1, /* xyz */
60 0x3, 0x3 << 1, 0x3 << 2, /* xy */
61 0x1, 0x1 << 1, 0x1 << 2, 0x1 << 3 /* x */
65 /* Physical register: 0-31 */
68 /* Byte offset into the physical register: 0-15 */
71 /* Number of bytes in a component of this register */
75 /* Shift up by reg_offset and horizontally by dst_offset. */
78 offset_swizzle(unsigned *swizzle
, unsigned reg_offset
, unsigned srcsize
, unsigned dst_offset
)
80 unsigned out
[MIR_VEC_COMPONENTS
];
82 signed reg_comp
= reg_offset
/ srcsize
;
83 signed dst_comp
= dst_offset
/ srcsize
;
85 unsigned max_component
= (16 / srcsize
) - 1;
87 assert(reg_comp
* srcsize
== reg_offset
);
88 assert(dst_comp
* srcsize
== dst_offset
);
90 for (signed c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
) {
91 signed comp
= MAX2(c
- dst_comp
, 0);
92 out
[c
] = MIN2(swizzle
[comp
] + reg_comp
, max_component
);
95 memcpy(swizzle
, out
, sizeof(out
));
98 /* Helper to return the default phys_reg for a given register */
100 static struct phys_reg
101 default_phys_reg(int reg
, midgard_reg_mode size
)
103 struct phys_reg r
= {
106 .size
= mir_bytes_for_mode(size
)
112 /* Determine which physical register, swizzle, and mask a virtual
113 * register corresponds to */
115 static struct phys_reg
116 index_to_reg(compiler_context
*ctx
, struct ra_graph
*g
, unsigned reg
, midgard_reg_mode size
)
118 /* Check for special cases */
120 return default_phys_reg(REGISTER_UNUSED
, size
);
121 else if (reg
>= SSA_FIXED_MINIMUM
)
122 return default_phys_reg(SSA_REG_FROM_FIXED(reg
), size
);
124 return default_phys_reg(REGISTER_UNUSED
, size
);
126 /* Special cases aside, we pick the underlying register */
127 int virt
= ra_get_node_reg(g
, reg
);
129 /* Divide out the register and classification */
130 int phys
= virt
/ WORK_STRIDE
;
131 int type
= virt
% WORK_STRIDE
;
133 /* Apply shadow registers */
135 if (phys
>= SHADOW_R28
&& phys
<= SHADOW_R29
)
136 phys
+= 28 - SHADOW_R28
;
137 else if (phys
== SHADOW_R0
)
140 unsigned bytes
= mir_bytes_for_mode(size
);
142 struct phys_reg r
= {
144 .offset
= __builtin_ctz(reg_type_to_mask
[type
]) * bytes
,
148 /* Report that we actually use this register, and return it */
151 ctx
->work_registers
= MAX2(ctx
->work_registers
, phys
);
156 /* This routine creates a register set. Should be called infrequently since
157 * it's slow and can be cached. For legibility, variables are named in terms of
158 * work registers, although it is also used to create the register set for
159 * special register allocation */
162 add_shadow_conflicts (struct ra_regs
*regs
, unsigned base
, unsigned shadow
, unsigned shadow_count
)
164 for (unsigned a
= 0; a
< WORK_STRIDE
; ++a
) {
165 unsigned reg_a
= (WORK_STRIDE
* base
) + a
;
167 for (unsigned b
= 0; b
< shadow_count
; ++b
) {
168 unsigned reg_b
= (WORK_STRIDE
* shadow
) + b
;
170 ra_add_reg_conflict(regs
, reg_a
, reg_b
);
171 ra_add_reg_conflict(regs
, reg_b
, reg_a
);
176 static struct ra_regs
*
177 create_register_set(unsigned work_count
, unsigned *classes
)
179 int virtual_count
= 32 * WORK_STRIDE
;
181 /* First, initialize the RA */
182 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, virtual_count
, true);
184 for (unsigned c
= 0; c
< (NR_REG_CLASSES
- 1); ++c
) {
185 int work_vec4
= ra_alloc_reg_class(regs
);
186 int work_vec3
= ra_alloc_reg_class(regs
);
187 int work_vec2
= ra_alloc_reg_class(regs
);
188 int work_vec1
= ra_alloc_reg_class(regs
);
190 classes
[4*c
+ 0] = work_vec1
;
191 classes
[4*c
+ 1] = work_vec2
;
192 classes
[4*c
+ 2] = work_vec3
;
193 classes
[4*c
+ 3] = work_vec4
;
195 /* Special register classes have other register counts */
197 (c
== REG_CLASS_WORK
) ? work_count
: 2;
200 (c
== REG_CLASS_LDST
) ? 26 :
201 (c
== REG_CLASS_TEXR
) ? 28 :
202 (c
== REG_CLASS_TEXW
) ? SHADOW_R28
:
205 /* Add the full set of work registers */
206 for (unsigned i
= first_reg
; i
< (first_reg
+ count
); ++i
) {
207 int base
= WORK_STRIDE
* i
;
209 /* Build a full set of subdivisions */
210 ra_class_add_reg(regs
, work_vec4
, base
);
211 ra_class_add_reg(regs
, work_vec3
, base
+ 1);
212 ra_class_add_reg(regs
, work_vec3
, base
+ 2);
213 ra_class_add_reg(regs
, work_vec2
, base
+ 3);
214 ra_class_add_reg(regs
, work_vec2
, base
+ 4);
215 ra_class_add_reg(regs
, work_vec2
, base
+ 5);
216 ra_class_add_reg(regs
, work_vec1
, base
+ 6);
217 ra_class_add_reg(regs
, work_vec1
, base
+ 7);
218 ra_class_add_reg(regs
, work_vec1
, base
+ 8);
219 ra_class_add_reg(regs
, work_vec1
, base
+ 9);
221 for (unsigned a
= 0; a
< 10; ++a
) {
222 unsigned mask1
= reg_type_to_mask
[a
];
224 for (unsigned b
= 0; b
< 10; ++b
) {
225 unsigned mask2
= reg_type_to_mask
[b
];
228 ra_add_reg_conflict(regs
,
235 int fragc
= ra_alloc_reg_class(regs
);
237 classes
[4*REG_CLASS_FRAGC
+ 0] = fragc
;
238 classes
[4*REG_CLASS_FRAGC
+ 1] = fragc
;
239 classes
[4*REG_CLASS_FRAGC
+ 2] = fragc
;
240 classes
[4*REG_CLASS_FRAGC
+ 3] = fragc
;
241 ra_class_add_reg(regs
, fragc
, WORK_STRIDE
* SHADOW_R0
);
243 /* We have duplicate classes */
244 add_shadow_conflicts(regs
, 0, SHADOW_R0
, 1);
245 add_shadow_conflicts(regs
, 28, SHADOW_R28
, WORK_STRIDE
);
246 add_shadow_conflicts(regs
, 29, SHADOW_R29
, WORK_STRIDE
);
248 /* We're done setting up */
249 ra_set_finalize(regs
, NULL
);
254 /* This routine gets a precomputed register set off the screen if it's able, or
255 * otherwise it computes one on the fly */
257 static struct ra_regs
*
258 get_register_set(struct midgard_screen
*screen
, unsigned work_count
, unsigned **classes
)
261 assert(work_count
>= 8);
262 assert(work_count
<= 16);
265 unsigned index
= work_count
- 8;
267 /* Find the reg set */
268 struct ra_regs
*cached
= screen
->regs
[index
];
271 assert(screen
->reg_classes
[index
]);
272 *classes
= screen
->reg_classes
[index
];
276 /* Otherwise, create one */
277 struct ra_regs
*created
= create_register_set(work_count
, screen
->reg_classes
[index
]);
279 /* Cache it and use it */
280 screen
->regs
[index
] = created
;
282 *classes
= screen
->reg_classes
[index
];
286 /* Assign a (special) class, ensuring that it is compatible with whatever class
290 set_class(unsigned *classes
, unsigned node
, unsigned class)
292 /* Check that we're even a node */
293 if (node
>= SSA_FIXED_MINIMUM
)
296 /* First 4 are work, next 4 are load/store.. */
297 unsigned current_class
= classes
[node
] >> 2;
300 if (class == current_class
)
303 /* If we're changing, we haven't assigned a special class */
304 assert(current_class
== REG_CLASS_WORK
);
306 classes
[node
] &= 0x3;
307 classes
[node
] |= (class << 2);
311 force_vec4(unsigned *classes
, unsigned node
)
313 if (node
>= SSA_FIXED_MINIMUM
)
317 classes
[node
] |= 0x3;
320 /* Special register classes impose special constraints on who can read their
321 * values, so check that */
324 check_read_class(unsigned *classes
, unsigned tag
, unsigned node
)
326 /* Non-nodes are implicitly ok */
327 if (node
>= SSA_FIXED_MINIMUM
)
330 unsigned current_class
= classes
[node
] >> 2;
332 switch (current_class
) {
334 return (tag
== TAG_LOAD_STORE_4
);
336 return (tag
== TAG_TEXTURE_4
);
338 return (tag
!= TAG_LOAD_STORE_4
);
342 unreachable("Invalid class");
347 check_write_class(unsigned *classes
, unsigned tag
, unsigned node
)
349 /* Non-nodes are implicitly ok */
350 if (node
>= SSA_FIXED_MINIMUM
)
353 unsigned current_class
= classes
[node
] >> 2;
355 switch (current_class
) {
359 return (tag
== TAG_TEXTURE_4
);
362 return IS_ALU(tag
) || (tag
== TAG_LOAD_STORE_4
);
364 unreachable("Invalid class");
368 /* Prepass before RA to ensure special class restrictions are met. The idea is
369 * to create a bit field of types of instructions that read a particular index.
370 * Later, we'll add moves as appropriate and rewrite to specialize by type. */
373 mark_node_class (unsigned *bitfield
, unsigned node
)
375 if (node
< SSA_FIXED_MINIMUM
)
376 BITSET_SET(bitfield
, node
);
380 mir_lower_special_reads(compiler_context
*ctx
)
382 size_t sz
= BITSET_WORDS(ctx
->temp_count
) * sizeof(BITSET_WORD
);
384 /* Bitfields for the various types of registers we could have. aluw can
385 * be written by either ALU or load/store */
387 unsigned *alur
= calloc(sz
, 1);
388 unsigned *aluw
= calloc(sz
, 1);
389 unsigned *brar
= calloc(sz
, 1);
390 unsigned *ldst
= calloc(sz
, 1);
391 unsigned *texr
= calloc(sz
, 1);
392 unsigned *texw
= calloc(sz
, 1);
394 /* Pass #1 is analysis, a linear scan to fill out the bitfields */
396 mir_foreach_instr_global(ctx
, ins
) {
399 mark_node_class(aluw
, ins
->dest
);
400 mark_node_class(alur
, ins
->src
[0]);
401 mark_node_class(alur
, ins
->src
[1]);
402 mark_node_class(alur
, ins
->src
[2]);
404 if (ins
->compact_branch
&& ins
->writeout
)
405 mark_node_class(brar
, ins
->src
[0]);
409 case TAG_LOAD_STORE_4
:
410 mark_node_class(aluw
, ins
->dest
);
411 mark_node_class(ldst
, ins
->src
[0]);
412 mark_node_class(ldst
, ins
->src
[1]);
413 mark_node_class(ldst
, ins
->src
[2]);
417 mark_node_class(texr
, ins
->src
[0]);
418 mark_node_class(texr
, ins
->src
[1]);
419 mark_node_class(texr
, ins
->src
[2]);
420 mark_node_class(texw
, ins
->dest
);
425 /* Pass #2 is lowering now that we've analyzed all the classes.
426 * Conceptually, if an index is only marked for a single type of use,
427 * there is nothing to lower. If it is marked for different uses, we
428 * split up based on the number of types of uses. To do so, we divide
429 * into N distinct classes of use (where N>1 by definition), emit N-1
430 * moves from the index to copies of the index, and finally rewrite N-1
431 * of the types of uses to use the corresponding move */
433 unsigned spill_idx
= ctx
->temp_count
;
435 for (unsigned i
= 0; i
< ctx
->temp_count
; ++i
) {
436 bool is_alur
= BITSET_TEST(alur
, i
);
437 bool is_aluw
= BITSET_TEST(aluw
, i
);
438 bool is_brar
= BITSET_TEST(brar
, i
);
439 bool is_ldst
= BITSET_TEST(ldst
, i
);
440 bool is_texr
= BITSET_TEST(texr
, i
);
441 bool is_texw
= BITSET_TEST(texw
, i
);
443 /* Analyse to check how many distinct uses there are. ALU ops
444 * (alur) can read the results of the texture pipeline (texw)
445 * but not ldst or texr. Load/store ops (ldst) cannot read
446 * anything but load/store inputs. Texture pipeline cannot read
447 * anything but texture inputs. TODO: Simplify. */
450 (is_alur
&& (is_ldst
|| is_texr
)) ||
451 (is_ldst
&& (is_alur
|| is_texr
|| is_texw
)) ||
452 (is_texr
&& (is_alur
|| is_ldst
|| is_texw
)) ||
453 (is_texw
&& (is_aluw
|| is_ldst
|| is_texr
)) ||
454 (is_brar
&& is_texw
);
459 /* Use the index as-is as the work copy. Emit copies for
462 unsigned classes
[] = { TAG_LOAD_STORE_4
, TAG_TEXTURE_4
, TAG_TEXTURE_4
, TAG_ALU_4
};
463 bool collisions
[] = { is_ldst
, is_texr
, is_texw
&& is_aluw
, is_brar
};
465 for (unsigned j
= 0; j
< ARRAY_SIZE(collisions
); ++j
) {
466 if (!collisions
[j
]) continue;
468 /* When the hazard is from reading, we move and rewrite
469 * sources (typical case). When it's from writing, we
470 * flip the move and rewrite destinations (obscure,
471 * only from control flow -- impossible in SSA) */
473 bool hazard_write
= (j
== 2);
475 unsigned idx
= spill_idx
++;
477 midgard_instruction m
= hazard_write
?
478 v_mov(idx
, i
) : v_mov(i
, idx
);
480 /* Insert move before each read/write, depending on the
481 * hazard we're trying to account for */
483 mir_foreach_instr_global_safe(ctx
, pre_use
) {
484 if (pre_use
->type
!= classes
[j
])
488 if (pre_use
->dest
!= i
)
491 if (!mir_has_arg(pre_use
, i
))
496 midgard_instruction
*use
= mir_next_op(pre_use
);
498 mir_insert_instruction_before(ctx
, use
, m
);
499 mir_rewrite_index_dst_single(pre_use
, i
, idx
);
503 m
.mask
= mir_from_bytemask(mir_bytemask_of_read_components(pre_use
, i
), midgard_reg_mode_32
);
504 mir_insert_instruction_before(ctx
, pre_use
, m
);
505 mir_rewrite_index_src_single(pre_use
, i
, idx
);
519 /* We register allocate after scheduling, so we need to ensure instructions
520 * executing in parallel within a segment of a bundle don't clobber each
521 * other's registers. This is mostly a non-issue thanks to scheduling, but
522 * there are edge cases. In particular, after a register is written in a
523 * segment, it interferes with anything reading. */
526 mir_compute_segment_interference(
527 compiler_context
*ctx
,
533 for (unsigned j
= pivot
; j
< i
; ++j
) {
534 mir_foreach_src(bun
->instructions
[j
], s
) {
535 if (bun
->instructions
[j
]->src
[s
] >= ctx
->temp_count
)
538 for (unsigned q
= pivot
; q
< i
; ++q
) {
539 if (bun
->instructions
[q
]->dest
>= ctx
->temp_count
)
542 /* See dEQP-GLES2.functional.shaders.return.output_write_in_func_dynamic_fragment */
545 if (!(bun
->instructions
[j
]->unit
== UNIT_SMUL
&& bun
->instructions
[q
]->unit
== UNIT_VLUT
))
549 ra_add_node_interference(l
, bun
->instructions
[q
]->dest
, bun
->instructions
[j
]->src
[s
]);
556 mir_compute_bundle_interference(
557 compiler_context
*ctx
,
561 if (!IS_ALU(bun
->tag
))
564 bool old
= bun
->instructions
[0]->unit
>= UNIT_VADD
;
567 for (unsigned i
= 1; i
< bun
->instruction_count
; ++i
) {
568 bool new = bun
->instructions
[i
]->unit
>= UNIT_VADD
;
571 mir_compute_segment_interference(ctx
, l
, bun
, 0, i
);
577 mir_compute_segment_interference(ctx
, l
, bun
, pivot
, bun
->instruction_count
);
581 mir_compute_interference(
582 compiler_context
*ctx
,
585 /* First, we need liveness information to be computed per block */
586 mir_compute_liveness(ctx
);
588 /* Now that every block has live_in/live_out computed, we can determine
589 * interference by walking each block linearly. Take live_out at the
590 * end of each block and walk the block backwards. */
592 mir_foreach_block(ctx
, blk
) {
593 uint16_t *live
= mem_dup(blk
->live_out
, ctx
->temp_count
* sizeof(uint16_t));
595 mir_foreach_instr_in_block_rev(blk
, ins
) {
596 /* Mark all registers live after the instruction as
597 * interfering with the destination */
599 unsigned dest
= ins
->dest
;
601 if (dest
< ctx
->temp_count
) {
602 for (unsigned i
= 0; i
< ctx
->temp_count
; ++i
)
604 ra_add_node_interference(g
, dest
, i
);
608 mir_liveness_ins_update(live
, ins
, ctx
->temp_count
);
611 mir_foreach_bundle_in_block(blk
, bun
)
612 mir_compute_bundle_interference(ctx
, g
, bun
);
618 /* This routine performs the actual register allocation. It should be succeeded
619 * by install_registers */
622 allocate_registers(compiler_context
*ctx
, bool *spilled
)
624 /* The number of vec4 work registers available depends on when the
625 * uniforms start, so compute that first */
626 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
627 unsigned *classes
= NULL
;
628 struct ra_regs
*regs
= get_register_set(ctx
->screen
, work_count
, &classes
);
630 assert(regs
!= NULL
);
631 assert(classes
!= NULL
);
633 /* No register allocation to do with no SSA */
635 if (!ctx
->temp_count
)
638 /* Let's actually do register allocation */
639 int nodes
= ctx
->temp_count
;
640 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
642 /* Register class (as known to the Mesa register allocator) is actually
643 * the product of both semantic class (work, load/store, texture..) and
644 * size (vec2/vec3..). First, we'll go through and determine the
645 * minimum size needed to hold values */
647 unsigned *found_class
= calloc(sizeof(unsigned), ctx
->temp_count
);
649 mir_foreach_instr_global(ctx
, ins
) {
650 if (ins
->dest
>= SSA_FIXED_MINIMUM
) continue;
652 /* 0 for x, 1 for xy, 2 for xyz, 3 for xyzw */
653 int class = util_logbase2(ins
->mask
);
655 /* Use the largest class if there's ambiguity, this
656 * handles partial writes */
658 int dest
= ins
->dest
;
659 found_class
[dest
] = MAX2(found_class
[dest
], class);
662 /* Next, we'll determine semantic class. We default to zero (work).
663 * But, if we're used with a special operation, that will force us to a
664 * particular class. Each node must be assigned to exactly one class; a
665 * prepass before RA should have lowered what-would-have-been
666 * multiclass nodes into a series of moves to break it up into multiple
669 mir_foreach_instr_global(ctx
, ins
) {
670 /* Check if this operation imposes any classes */
672 if (ins
->type
== TAG_LOAD_STORE_4
) {
673 bool force_vec4_only
= OP_IS_VEC4_ONLY(ins
->load_store
.op
);
675 set_class(found_class
, ins
->src
[0], REG_CLASS_LDST
);
676 set_class(found_class
, ins
->src
[1], REG_CLASS_LDST
);
677 set_class(found_class
, ins
->src
[2], REG_CLASS_LDST
);
679 if (force_vec4_only
) {
680 force_vec4(found_class
, ins
->dest
);
681 force_vec4(found_class
, ins
->src
[0]);
682 force_vec4(found_class
, ins
->src
[1]);
683 force_vec4(found_class
, ins
->src
[2]);
685 } else if (ins
->type
== TAG_TEXTURE_4
) {
686 set_class(found_class
, ins
->dest
, REG_CLASS_TEXW
);
687 set_class(found_class
, ins
->src
[0], REG_CLASS_TEXR
);
688 set_class(found_class
, ins
->src
[1], REG_CLASS_TEXR
);
689 set_class(found_class
, ins
->src
[2], REG_CLASS_TEXR
);
693 /* Check that the semantics of the class are respected */
694 mir_foreach_instr_global(ctx
, ins
) {
695 assert(check_write_class(found_class
, ins
->type
, ins
->dest
));
696 assert(check_read_class(found_class
, ins
->type
, ins
->src
[0]));
697 assert(check_read_class(found_class
, ins
->type
, ins
->src
[1]));
698 assert(check_read_class(found_class
, ins
->type
, ins
->src
[2]));
701 /* Mark writeout to r0 */
702 mir_foreach_instr_global(ctx
, ins
) {
703 if (ins
->compact_branch
&& ins
->writeout
)
704 set_class(found_class
, ins
->src
[0], REG_CLASS_FRAGC
);
707 for (unsigned i
= 0; i
< ctx
->temp_count
; ++i
) {
708 unsigned class = found_class
[i
];
709 ra_set_node_class(g
, i
, classes
[class]);
712 mir_compute_interference(ctx
, g
);
714 if (!ra_allocate(g
)) {
720 /* Whether we were successful or not, report the graph so we can
721 * compute spill nodes */
726 /* Once registers have been decided via register allocation
727 * (allocate_registers), we need to rewrite the MIR to use registers instead of
731 install_registers_instr(
732 compiler_context
*ctx
,
734 midgard_instruction
*ins
)
741 if (ins
->compact_branch
)
744 struct phys_reg src1
= index_to_reg(ctx
, g
, ins
->src
[0], mir_srcsize(ins
, 0));
745 struct phys_reg src2
= index_to_reg(ctx
, g
, ins
->src
[1], mir_srcsize(ins
, 1));
746 struct phys_reg dest
= index_to_reg(ctx
, g
, ins
->dest
, mir_typesize(ins
));
748 mir_set_bytemask(ins
, mir_bytemask(ins
) << dest
.offset
);
750 unsigned dest_offset
=
751 GET_CHANNEL_COUNT(alu_opcode_props
[ins
->alu
.op
].props
) ? 0 :
754 offset_swizzle(ins
->swizzle
[0], src1
.offset
, src1
.size
, dest_offset
);
756 ins
->registers
.src1_reg
= src1
.reg
;
758 ins
->registers
.src2_imm
= ins
->has_inline_constant
;
760 if (ins
->has_inline_constant
) {
761 /* Encode inline 16-bit constant. See disassembler for
762 * where the algorithm is from */
764 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
766 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
767 uint16_t imm
= ((lower_11
>> 8) & 0x7) |
768 ((lower_11
& 0xFF) << 3);
770 ins
->alu
.src2
= imm
<< 2;
772 midgard_vector_alu_src mod2
=
773 vector_alu_from_unsigned(ins
->alu
.src2
);
774 offset_swizzle(ins
->swizzle
[1], src2
.offset
, src2
.size
, dest_offset
);
775 ins
->alu
.src2
= vector_alu_srco_unsigned(mod2
);
777 ins
->registers
.src2_reg
= src2
.reg
;
780 ins
->registers
.out_reg
= dest
.reg
;
784 case TAG_LOAD_STORE_4
: {
785 /* Which physical register we read off depends on
786 * whether we are loading or storing -- think about the
787 * logical dataflow */
789 bool encodes_src
= OP_IS_STORE(ins
->load_store
.op
);
792 struct phys_reg src
= index_to_reg(ctx
, g
, ins
->src
[0], mir_srcsize(ins
, 0));
793 assert(src
.reg
== 26 || src
.reg
== 27);
795 ins
->load_store
.reg
= src
.reg
- 26;
796 offset_swizzle(ins
->swizzle
[0], src
.offset
, src
.size
, 0);
798 struct phys_reg dst
= index_to_reg(ctx
, g
, ins
->dest
, mir_typesize(ins
));
800 ins
->load_store
.reg
= dst
.reg
;
801 offset_swizzle(ins
->swizzle
[0], 0, 4, dst
.offset
);
802 mir_set_bytemask(ins
, mir_bytemask(ins
) << dst
.offset
);
805 /* We also follow up by actual arguments */
807 unsigned src2
= ins
->src
[1];
808 unsigned src3
= ins
->src
[2];
811 struct phys_reg src
= index_to_reg(ctx
, g
, src2
, mir_srcsize(ins
, 1));
812 unsigned component
= src
.offset
/ src
.size
;
813 assert(component
* src
.size
== src
.offset
);
814 ins
->load_store
.arg_1
|= midgard_ldst_reg(src
.reg
, component
);
818 struct phys_reg src
= index_to_reg(ctx
, g
, src3
, mir_srcsize(ins
, 2));
819 unsigned component
= src
.offset
/ src
.size
;
820 assert(component
* src
.size
== src
.offset
);
821 ins
->load_store
.arg_2
|= midgard_ldst_reg(src
.reg
, component
);
827 case TAG_TEXTURE_4
: {
828 /* Grab RA results */
829 struct phys_reg dest
= index_to_reg(ctx
, g
, ins
->dest
, mir_typesize(ins
));
830 struct phys_reg coord
= index_to_reg(ctx
, g
, ins
->src
[1], mir_srcsize(ins
, 1));
831 struct phys_reg lod
= index_to_reg(ctx
, g
, ins
->src
[2], mir_srcsize(ins
, 2));
833 assert(dest
.reg
== 28 || dest
.reg
== 29);
834 assert(coord
.reg
== 28 || coord
.reg
== 29);
836 /* First, install the texture coordinate */
837 ins
->texture
.in_reg_full
= 1;
838 ins
->texture
.in_reg_upper
= 0;
839 ins
->texture
.in_reg_select
= coord
.reg
- 28;
840 offset_swizzle(ins
->swizzle
[1], coord
.offset
, coord
.size
, 0);
842 /* Next, install the destination */
843 ins
->texture
.out_full
= 1;
844 ins
->texture
.out_upper
= 0;
845 ins
->texture
.out_reg_select
= dest
.reg
- 28;
846 offset_swizzle(ins
->swizzle
[0], 0, 4, dest
.offset
);
847 mir_set_bytemask(ins
, mir_bytemask(ins
) << dest
.offset
);
849 /* If there is a register LOD/bias, use it */
850 if (ins
->src
[2] != ~0) {
851 assert(!(lod
.offset
& 3));
852 midgard_tex_register_select sel
= {
855 .component
= lod
.offset
/ 4
859 memcpy(&packed
, &sel
, sizeof(packed
));
860 ins
->texture
.bias
= packed
;
872 install_registers(compiler_context
*ctx
, struct ra_graph
*g
)
874 mir_foreach_instr_global(ctx
, ins
)
875 install_registers_instr(ctx
, g
, ins
);