src/panfrost/midgard/midgard_ra.c

   1 /*
   2  * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  * Copyright (C) 2019 Collabora, Ltd.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  */
  24
  25 #include "compiler.h"
  26 #include "midgard_ops.h"
  27 #include "util/u_math.h"
  28 #include "util/u_memory.h"
  29 #include "lcra.h"
  30
  31 struct phys_reg {
  32         /* Physical register: 0-31 */
  33         unsigned reg;
  34
  35         /* Byte offset into the physical register: 0-15 */
  36         unsigned offset;
  37
  38         /* Number of bytes in a component of this register */
  39         unsigned size;
  40 };
  41
  42 /* Shift up by reg_offset and horizontally by dst_offset. */
  43
  44 static void
  45 offset_swizzle(unsigned *swizzle, unsigned reg_offset, unsigned srcsize, unsigned dst_offset)
  46 {
  47         unsigned out[MIR_VEC_COMPONENTS];
  48
  49         signed reg_comp = reg_offset / srcsize;
  50         signed dst_comp = dst_offset / srcsize;
  51
  52         unsigned max_component = (16 / srcsize) - 1;
  53
  54         assert(reg_comp * srcsize == reg_offset);
  55         assert(dst_comp * srcsize == dst_offset);
  56
  57         for (signed c = 0; c < MIR_VEC_COMPONENTS; ++c) {
  58                 signed comp = MAX2(c - dst_comp, 0);
  59                 out[c] = MIN2(swizzle[comp] + reg_comp, max_component);
  60         }
  61
  62         memcpy(swizzle, out, sizeof(out));
  63 }
  64
  65 /* Helper to return the default phys_reg for a given register */
  66
  67 static struct phys_reg
  68 default_phys_reg(int reg, midgard_reg_mode size)
  69 {
  70         struct phys_reg r = {
  71                 .reg = reg,
  72                 .offset = 0,
  73                 .size = mir_bytes_for_mode(size)
  74         };
  75
  76         return r;
  77 }
  78
  79 /* Determine which physical register, swizzle, and mask a virtual
  80  * register corresponds to */
  81
  82 static struct phys_reg
  83 index_to_reg(compiler_context *ctx, struct lcra_state *l, unsigned reg, midgard_reg_mode size)
  84 {
  85         /* Check for special cases */
  86         if (reg == ~0)
  87                 return default_phys_reg(REGISTER_UNUSED, size);
  88         else if (reg >= SSA_FIXED_MINIMUM)
  89                 return default_phys_reg(SSA_REG_FROM_FIXED(reg), size);
  90         else if (!l)
  91                 return default_phys_reg(REGISTER_UNUSED, size);
  92
  93         struct phys_reg r = {
  94                 .reg = l->solutions[reg] / 16,
  95                 .offset = l->solutions[reg] & 0xF,
  96                 .size = mir_bytes_for_mode(size)
  97         };
  98
  99         /* Report that we actually use this register, and return it */
 100
 101         if (r.reg < 16)
 102                 ctx->work_registers = MAX2(ctx->work_registers, r.reg);
 103
 104         return r;
 105 }
 106
 107 static void
 108 set_class(unsigned *classes, unsigned node, unsigned class)
 109 {
 110         if (node < SSA_FIXED_MINIMUM && class != classes[node]) {
 111                 assert(classes[node] == REG_CLASS_WORK);
 112                 classes[node] = class;
 113         }
 114 }
 115
 116 /* Special register classes impose special constraints on who can read their
 117  * values, so check that */
 118
 119 static bool
 120 check_read_class(unsigned *classes, unsigned tag, unsigned node)
 121 {
 122         /* Non-nodes are implicitly ok */
 123         if (node >= SSA_FIXED_MINIMUM)
 124                 return true;
 125
 126         switch (classes[node]) {
 127         case REG_CLASS_LDST:
 128                 return (tag == TAG_LOAD_STORE_4);
 129         case REG_CLASS_TEXR:
 130                 return (tag == TAG_TEXTURE_4);
 131         case REG_CLASS_TEXW:
 132                 return (tag != TAG_LOAD_STORE_4);
 133         case REG_CLASS_WORK:
 134                 return IS_ALU(tag);
 135         default:
 136                 unreachable("Invalid class");
 137         }
 138 }
 139
 140 static bool
 141 check_write_class(unsigned *classes, unsigned tag, unsigned node)
 142 {
 143         /* Non-nodes are implicitly ok */
 144         if (node >= SSA_FIXED_MINIMUM)
 145                 return true;
 146
 147         switch (classes[node]) {
 148         case REG_CLASS_TEXR:
 149                 return true;
 150         case REG_CLASS_TEXW:
 151                 return (tag == TAG_TEXTURE_4);
 152         case REG_CLASS_LDST:
 153         case REG_CLASS_WORK:
 154                 return IS_ALU(tag) || (tag == TAG_LOAD_STORE_4);
 155         default:
 156                 unreachable("Invalid class");
 157         }
 158 }
 159
 160 /* Prepass before RA to ensure special class restrictions are met. The idea is
 161  * to create a bit field of types of instructions that read a particular index.
 162  * Later, we'll add moves as appropriate and rewrite to specialize by type. */
 163
 164 static void
 165 mark_node_class (unsigned *bitfield, unsigned node)
 166 {
 167         if (node < SSA_FIXED_MINIMUM)
 168                 BITSET_SET(bitfield, node);
 169 }
 170
 171 void
 172 mir_lower_special_reads(compiler_context *ctx)
 173 {
 174         size_t sz = BITSET_WORDS(ctx->temp_count) * sizeof(BITSET_WORD);
 175
 176         /* Bitfields for the various types of registers we could have. aluw can
 177          * be written by either ALU or load/store */
 178
 179         unsigned *alur = calloc(sz, 1);
 180         unsigned *aluw = calloc(sz, 1);
 181         unsigned *brar = calloc(sz, 1);
 182         unsigned *ldst = calloc(sz, 1);
 183         unsigned *texr = calloc(sz, 1);
 184         unsigned *texw = calloc(sz, 1);
 185
 186         /* Pass #1 is analysis, a linear scan to fill out the bitfields */
 187
 188         mir_foreach_instr_global(ctx, ins) {
 189                 switch (ins->type) {
 190                 case TAG_ALU_4:
 191                         mark_node_class(aluw, ins->dest);
 192                         mark_node_class(alur, ins->src[0]);
 193                         mark_node_class(alur, ins->src[1]);
 194                         mark_node_class(alur, ins->src[2]);
 195
 196                         if (ins->compact_branch && ins->writeout)
 197                                 mark_node_class(brar, ins->src[0]);
 198
 199                         break;
 200
 201                 case TAG_LOAD_STORE_4:
 202                         mark_node_class(aluw, ins->dest);
 203                         mark_node_class(ldst, ins->src[0]);
 204                         mark_node_class(ldst, ins->src[1]);
 205                         mark_node_class(ldst, ins->src[2]);
 206                         break;
 207
 208                 case TAG_TEXTURE_4:
 209                         mark_node_class(texr, ins->src[0]);
 210                         mark_node_class(texr, ins->src[1]);
 211                         mark_node_class(texr, ins->src[2]);
 212                         mark_node_class(texw, ins->dest);
 213                         break;
 214                 }
 215         }
 216
 217         /* Pass #2 is lowering now that we've analyzed all the classes.
 218          * Conceptually, if an index is only marked for a single type of use,
 219          * there is nothing to lower. If it is marked for different uses, we
 220          * split up based on the number of types of uses. To do so, we divide
 221          * into N distinct classes of use (where N>1 by definition), emit N-1
 222          * moves from the index to copies of the index, and finally rewrite N-1
 223          * of the types of uses to use the corresponding move */
 224
 225         unsigned spill_idx = ctx->temp_count;
 226
 227         for (unsigned i = 0; i < ctx->temp_count; ++i) {
 228                 bool is_alur = BITSET_TEST(alur, i);
 229                 bool is_aluw = BITSET_TEST(aluw, i);
 230                 bool is_brar = BITSET_TEST(brar, i);
 231                 bool is_ldst = BITSET_TEST(ldst, i);
 232                 bool is_texr = BITSET_TEST(texr, i);
 233                 bool is_texw = BITSET_TEST(texw, i);
 234
 235                 /* Analyse to check how many distinct uses there are. ALU ops
 236                  * (alur) can read the results of the texture pipeline (texw)
 237                  * but not ldst or texr. Load/store ops (ldst) cannot read
 238                  * anything but load/store inputs. Texture pipeline cannot read
 239                  * anything but texture inputs. TODO: Simplify.  */
 240
 241                 bool collision =
 242                         (is_alur && (is_ldst || is_texr)) ||
 243                         (is_ldst && (is_alur || is_texr || is_texw)) ||
 244                         (is_texr && (is_alur || is_ldst || is_texw)) ||
 245                         (is_texw && (is_aluw || is_ldst || is_texr)) ||
 246                         (is_brar && is_texw);
 247
 248                 if (!collision)
 249                         continue;
 250
 251                 /* Use the index as-is as the work copy. Emit copies for
 252                  * special uses */
 253
 254                 unsigned classes[] = { TAG_LOAD_STORE_4, TAG_TEXTURE_4, TAG_TEXTURE_4, TAG_ALU_4};
 255                 bool collisions[] = { is_ldst, is_texr, is_texw && is_aluw, is_brar };
 256
 257                 for (unsigned j = 0; j < ARRAY_SIZE(collisions); ++j) {
 258                         if (!collisions[j]) continue;
 259
 260                         /* When the hazard is from reading, we move and rewrite
 261                          * sources (typical case). When it's from writing, we
 262                          * flip the move and rewrite destinations (obscure,
 263                          * only from control flow -- impossible in SSA) */
 264
 265                         bool hazard_write = (j == 2);
 266
 267                         unsigned idx = spill_idx++;
 268
 269                         midgard_instruction m = hazard_write ?
 270                                 v_mov(idx, i) : v_mov(i, idx);
 271
 272                         /* Insert move before each read/write, depending on the
 273                          * hazard we're trying to account for */
 274
 275                         mir_foreach_instr_global_safe(ctx, pre_use) {
 276                                 if (pre_use->type != classes[j])
 277                                         continue;
 278
 279                                 if (hazard_write) {
 280                                         if (pre_use->dest != i)
 281                                                 continue;
 282                                 } else {
 283                                         if (!mir_has_arg(pre_use, i))
 284                                                 continue;
 285                                 }
 286
 287                                 if (hazard_write) {
 288                                         midgard_instruction *use = mir_next_op(pre_use);
 289                                         assert(use);
 290                                         mir_insert_instruction_before(ctx, use, m);
 291                                         mir_rewrite_index_dst_single(pre_use, i, idx);
 292                                 } else {
 293                                         idx = spill_idx++;
 294                                         m = v_mov(i, idx);
 295                                         m.mask = mir_from_bytemask(mir_bytemask_of_read_components(pre_use, i), midgard_reg_mode_32);
 296                                         mir_insert_instruction_before(ctx, pre_use, m);
 297                                         mir_rewrite_index_src_single(pre_use, i, idx);
 298                                 }
 299                         }
 300                 }
 301         }
 302
 303         free(alur);
 304         free(aluw);
 305         free(brar);
 306         free(ldst);
 307         free(texr);
 308         free(texw);
 309 }
 310
 311 /* We register allocate after scheduling, so we need to ensure instructions
 312  * executing in parallel within a segment of a bundle don't clobber each
 313  * other's registers. This is mostly a non-issue thanks to scheduling, but
 314  * there are edge cases. In particular, after a register is written in a
 315  * segment, it interferes with anything reading. */
 316
 317 static void
 318 mir_compute_segment_interference(
 319                 compiler_context *ctx,
 320                 struct lcra_state *l,
 321                 midgard_bundle *bun,
 322                 unsigned pivot,
 323                 unsigned i)
 324 {
 325         for (unsigned j = pivot; j < i; ++j) {
 326                 mir_foreach_src(bun->instructions[j], s) {
 327                         if (bun->instructions[j]->src[s] >= ctx->temp_count)
 328                                 continue;
 329
 330                         for (unsigned q = pivot; q < i; ++q) {
 331                                 if (bun->instructions[q]->dest >= ctx->temp_count)
 332                                         continue;
 333
 334                                 /* See dEQP-GLES2.functional.shaders.return.output_write_in_func_dynamic_fragment */
 335
 336                                 if (q >= j) {
 337                                         if (!(bun->instructions[j]->unit == UNIT_SMUL && bun->instructions[q]->unit == UNIT_VLUT))
 338                                                 continue;
 339                                 }
 340
 341                                 unsigned mask = mir_bytemask(bun->instructions[q]);
 342                                 unsigned rmask = mir_bytemask_of_read_components(bun->instructions[j], bun->instructions[j]->src[s]);
 343                                 lcra_add_node_interference(l, bun->instructions[q]->dest, mask, bun->instructions[j]->src[s], rmask);
 344                         }
 345                 }
 346         }
 347 }
 348
 349 static void
 350 mir_compute_bundle_interference(
 351                 compiler_context *ctx,
 352                 struct lcra_state *l,
 353                 midgard_bundle *bun)
 354 {
 355         if (!IS_ALU(bun->tag))
 356                 return;
 357
 358         bool old = bun->instructions[0]->unit >= UNIT_VADD;
 359         unsigned pivot = 0;
 360
 361         for (unsigned i = 1; i < bun->instruction_count; ++i) {
 362                 bool new = bun->instructions[i]->unit >= UNIT_VADD;
 363
 364                 if (old != new) {
 365                         mir_compute_segment_interference(ctx, l, bun, 0, i);
 366                         pivot = i;
 367                         break;
 368                 }
 369         }
 370
 371         mir_compute_segment_interference(ctx, l, bun, pivot, bun->instruction_count);
 372 }
 373
 374 static void
 375 mir_compute_interference(
 376                 compiler_context *ctx,
 377                 struct lcra_state *l)
 378 {
 379         /* First, we need liveness information to be computed per block */
 380         mir_compute_liveness(ctx);
 381
 382         /* Now that every block has live_in/live_out computed, we can determine
 383          * interference by walking each block linearly. Take live_out at the
 384          * end of each block and walk the block backwards. */
 385
 386         mir_foreach_block(ctx, blk) {
 387                 uint16_t *live = mem_dup(blk->live_out, ctx->temp_count * sizeof(uint16_t));
 388
 389                 mir_foreach_instr_in_block_rev(blk, ins) {
 390                         /* Mark all registers live after the instruction as
 391                          * interfering with the destination */
 392
 393                         unsigned dest = ins->dest;
 394
 395                         if (dest < ctx->temp_count) {
 396                                 for (unsigned i = 0; i < ctx->temp_count; ++i)
 397                                         if (live[i]) {
 398                                                 unsigned mask = mir_bytemask(ins);
 399                                                 lcra_add_node_interference(l, dest, mask, i, live[i]);
 400                                         }
 401                         }
 402
 403                         /* Update live_in */
 404                         mir_liveness_ins_update(live, ins, ctx->temp_count);
 405                 }
 406
 407                 mir_foreach_bundle_in_block(blk, bun)
 408                         mir_compute_bundle_interference(ctx, l, bun);
 409
 410                 free(live);
 411         }
 412 }
 413
 414 /* This routine performs the actual register allocation. It should be succeeded
 415  * by install_registers */
 416
 417 struct lcra_state *
 418 allocate_registers(compiler_context *ctx, bool *spilled)
 419 {
 420         /* The number of vec4 work registers available depends on when the
 421          * uniforms start, so compute that first */
 422         int work_count = 16 - MAX2((ctx->uniform_cutoff - 8), 0);
 423
 424        /* No register allocation to do with no SSA */
 425
 426         if (!ctx->temp_count)
 427                 return NULL;
 428
 429         struct lcra_state *l = lcra_alloc_equations(ctx->temp_count, 1, 8, 16, 5);
 430
 431         /* Starts of classes, in bytes */
 432         l->class_start[REG_CLASS_WORK]  = 16 * 0;
 433         l->class_start[REG_CLASS_LDST]  = 16 * 26;
 434         l->class_start[REG_CLASS_TEXR]  = 16 * 28;
 435         l->class_start[REG_CLASS_TEXW]  = 16 * 28;
 436
 437         l->class_size[REG_CLASS_WORK] = 16 * work_count;
 438         l->class_size[REG_CLASS_LDST]  = 16 * 2;
 439         l->class_size[REG_CLASS_TEXR]  = 16 * 2;
 440         l->class_size[REG_CLASS_TEXW]  = 16 * 2;
 441
 442         lcra_set_disjoint_class(l, REG_CLASS_TEXR, REG_CLASS_TEXW);
 443
 444         unsigned *found_class = calloc(sizeof(unsigned), ctx->temp_count);
 445
 446         mir_foreach_instr_global(ctx, ins) {
 447                 if (ins->dest >= SSA_FIXED_MINIMUM) continue;
 448
 449                 /* 0 for x, 1 for xy, 2 for xyz, 3 for xyzw */
 450                 int class = util_logbase2(ins->mask);
 451
 452                 /* Use the largest class if there's ambiguity, this
 453                  * handles partial writes */
 454
 455                 int dest = ins->dest;
 456                 found_class[dest] = MAX2(found_class[dest], class);
 457
 458                 lcra_set_alignment(l, dest, 2); /* (1 << 2) = 4 */
 459
 460                 /* XXX: Ensure swizzles align the right way with more LCRA constraints? */
 461                 if (ins->type == TAG_ALU_4 && ins->alu.reg_mode != midgard_reg_mode_32)
 462                         lcra_set_alignment(l, dest, 3); /* (1 << 3) = 8 */
 463         }
 464
 465         for (unsigned i = 0; i < ctx->temp_count; ++i)
 466                 lcra_restrict_range(l, i, (found_class[i] + 1) * 4);
 467
 468         free(found_class);
 469
 470         /* Next, we'll determine semantic class. We default to zero (work).
 471          * But, if we're used with a special operation, that will force us to a
 472          * particular class. Each node must be assigned to exactly one class; a
 473          * prepass before RA should have lowered what-would-have-been
 474          * multiclass nodes into a series of moves to break it up into multiple
 475          * nodes (TODO) */
 476
 477         mir_foreach_instr_global(ctx, ins) {
 478                 /* Check if this operation imposes any classes */
 479
 480                 if (ins->type == TAG_LOAD_STORE_4) {
 481                         set_class(l->class, ins->src[0], REG_CLASS_LDST);
 482                         set_class(l->class, ins->src[1], REG_CLASS_LDST);
 483                         set_class(l->class, ins->src[2], REG_CLASS_LDST);
 484
 485                         if (OP_IS_VEC4_ONLY(ins->load_store.op))
 486                                 lcra_restrict_range(l, ins->dest, 16);
 487                 } else if (ins->type == TAG_TEXTURE_4) {
 488                         set_class(l->class, ins->dest, REG_CLASS_TEXW);
 489                         set_class(l->class, ins->src[0], REG_CLASS_TEXR);
 490                         set_class(l->class, ins->src[1], REG_CLASS_TEXR);
 491                         set_class(l->class, ins->src[2], REG_CLASS_TEXR);
 492                 }
 493         }
 494
 495         /* Check that the semantics of the class are respected */
 496         mir_foreach_instr_global(ctx, ins) {
 497                 assert(check_write_class(l->class, ins->type, ins->dest));
 498                 assert(check_read_class(l->class, ins->type, ins->src[0]));
 499                 assert(check_read_class(l->class, ins->type, ins->src[1]));
 500                 assert(check_read_class(l->class, ins->type, ins->src[2]));
 501         }
 502
 503         /* Mark writeout to r0 */
 504         mir_foreach_instr_global(ctx, ins) {
 505                 if (ins->compact_branch && ins->writeout && ins->src[0] < ctx->temp_count)
 506                         l->solutions[ins->src[0]] = 0;
 507         }
 508
 509         mir_compute_interference(ctx, l);
 510
 511         *spilled = !lcra_solve(l);
 512         return l;
 513 }
 514
 515 /* Once registers have been decided via register allocation
 516  * (allocate_registers), we need to rewrite the MIR to use registers instead of
 517  * indices */
 518
 519 static void
 520 install_registers_instr(
 521         compiler_context *ctx,
 522         struct lcra_state *l,
 523         midgard_instruction *ins)
 524 {
 525         switch (ins->type) {
 526         case TAG_ALU_4:
 527         case TAG_ALU_8:
 528         case TAG_ALU_12:
 529         case TAG_ALU_16: {
 530                  if (ins->compact_branch)
 531                          return;
 532
 533                 struct phys_reg src1 = index_to_reg(ctx, l, ins->src[0], mir_srcsize(ins, 0));
 534                 struct phys_reg src2 = index_to_reg(ctx, l, ins->src[1], mir_srcsize(ins, 1));
 535                 struct phys_reg dest = index_to_reg(ctx, l, ins->dest, mir_typesize(ins));
 536
 537                 mir_set_bytemask(ins, mir_bytemask(ins) << dest.offset);
 538
 539                 unsigned dest_offset =
 540                         GET_CHANNEL_COUNT(alu_opcode_props[ins->alu.op].props) ? 0 :
 541                         dest.offset;
 542
 543                 offset_swizzle(ins->swizzle[0], src1.offset, src1.size, dest_offset);
 544
 545                 ins->registers.src1_reg = src1.reg;
 546
 547                 ins->registers.src2_imm = ins->has_inline_constant;
 548
 549                 if (ins->has_inline_constant) {
 550                         /* Encode inline 16-bit constant. See disassembler for
 551                          * where the algorithm is from */
 552
 553                         ins->registers.src2_reg = ins->inline_constant >> 11;
 554
 555                         int lower_11 = ins->inline_constant & ((1 << 12) - 1);
 556                         uint16_t imm = ((lower_11 >> 8) & 0x7) |
 557                                        ((lower_11 & 0xFF) << 3);
 558
 559                         ins->alu.src2 = imm << 2;
 560                 } else {
 561                         midgard_vector_alu_src mod2 =
 562                                 vector_alu_from_unsigned(ins->alu.src2);
 563                         offset_swizzle(ins->swizzle[1], src2.offset, src2.size, dest_offset);
 564                         ins->alu.src2 = vector_alu_srco_unsigned(mod2);
 565
 566                         ins->registers.src2_reg = src2.reg;
 567                 }
 568
 569                 ins->registers.out_reg = dest.reg;
 570                 break;
 571         }
 572
 573         case TAG_LOAD_STORE_4: {
 574                 /* Which physical register we read off depends on
 575                  * whether we are loading or storing -- think about the
 576                  * logical dataflow */
 577
 578                 bool encodes_src = OP_IS_STORE(ins->load_store.op);
 579
 580                 if (encodes_src) {
 581                         struct phys_reg src = index_to_reg(ctx, l, ins->src[0], mir_srcsize(ins, 0));
 582                         assert(src.reg == 26 || src.reg == 27);
 583
 584                         ins->load_store.reg = src.reg - 26;
 585                         offset_swizzle(ins->swizzle[0], src.offset, src.size, 0);
 586                } else {
 587                         struct phys_reg dst = index_to_reg(ctx, l, ins->dest, mir_typesize(ins));
 588
 589                         ins->load_store.reg = dst.reg;
 590                         offset_swizzle(ins->swizzle[0], 0, 4, dst.offset);
 591                         mir_set_bytemask(ins, mir_bytemask(ins) << dst.offset);
 592                 }
 593
 594                 /* We also follow up by actual arguments */
 595
 596                 unsigned src2 = ins->src[1];
 597                 unsigned src3 = ins->src[2];
 598
 599                 if (src2 != ~0) {
 600                         struct phys_reg src = index_to_reg(ctx, l, src2, mir_srcsize(ins, 1));
 601                         unsigned component = src.offset / src.size;
 602                         assert(component * src.size == src.offset);
 603                         ins->load_store.arg_1 |= midgard_ldst_reg(src.reg, component);
 604                 }
 605
 606                 if (src3 != ~0) {
 607                         struct phys_reg src = index_to_reg(ctx, l, src3, mir_srcsize(ins, 2));
 608                         unsigned component = src.offset / src.size;
 609                         assert(component * src.size == src.offset);
 610                         ins->load_store.arg_2 |= midgard_ldst_reg(src.reg, component);
 611                 }
 612
 613                 break;
 614         }
 615
 616         case TAG_TEXTURE_4: {
 617                 /* Grab RA results */
 618                 struct phys_reg dest = index_to_reg(ctx, l, ins->dest, mir_typesize(ins));
 619                 struct phys_reg coord = index_to_reg(ctx, l, ins->src[1], mir_srcsize(ins, 1));
 620                 struct phys_reg lod = index_to_reg(ctx, l, ins->src[2], mir_srcsize(ins, 2));
 621
 622                 assert(dest.reg == 28 || dest.reg == 29);
 623                 assert(coord.reg == 28 || coord.reg == 29);
 624
 625                 /* First, install the texture coordinate */
 626                 ins->texture.in_reg_full = 1;
 627                 ins->texture.in_reg_upper = 0;
 628                 ins->texture.in_reg_select = coord.reg - 28;
 629                 offset_swizzle(ins->swizzle[1], coord.offset, coord.size, 0);
 630
 631                 /* Next, install the destination */
 632                 ins->texture.out_full = 1;
 633                 ins->texture.out_upper = 0;
 634                 ins->texture.out_reg_select = dest.reg - 28;
 635                 offset_swizzle(ins->swizzle[0], 0, 4, dest.offset);
 636                 mir_set_bytemask(ins, mir_bytemask(ins) << dest.offset);
 637
 638                 /* If there is a register LOD/bias, use it */
 639                 if (ins->src[2] != ~0) {
 640                         assert(!(lod.offset & 3));
 641                         midgard_tex_register_select sel = {
 642                                 .select = lod.reg,
 643                                 .full = 1,
 644                                 .component = lod.offset / 4
 645                         };
 646
 647                         uint8_t packed;
 648                         memcpy(&packed, &sel, sizeof(packed));
 649                         ins->texture.bias = packed;
 650                 }
 651
 652                 break;
 653         }
 654
 655         default:
 656                 break;
 657         }
 658 }
 659
 660 void
 661 install_registers(compiler_context *ctx, struct lcra_state *l)
 662 {
 663         mir_foreach_instr_global(ctx, ins)
 664                 install_registers_instr(ctx, l, ins);
 665 }