src/panfrost/midgard/midgard_ra.c

   1 /*
   2  * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  * Copyright (C) 2019 Collabora, Ltd.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  */
  24
  25 #include "compiler.h"
  26 #include "midgard_ops.h"
  27 #include "util/u_math.h"
  28 #include "util/u_memory.h"
  29 #include "midgard_quirks.h"
  30
  31 struct phys_reg {
  32         /* Physical register: 0-31 */
  33         unsigned reg;
  34
  35         /* Byte offset into the physical register: 0-15 */
  36         unsigned offset;
  37
  38         /* Number of bytes in a component of this register */
  39         unsigned size;
  40 };
  41
  42 /* Shift up by reg_offset and horizontally by dst_offset. */
  43
  44 static void
  45 offset_swizzle(unsigned *swizzle, unsigned reg_offset, unsigned srcsize, unsigned dstsize, unsigned dst_offset)
  46 {
  47         unsigned out[MIR_VEC_COMPONENTS];
  48
  49         signed reg_comp = reg_offset / srcsize;
  50         signed dst_comp = dst_offset / dstsize;
  51
  52         unsigned max_component = (16 / srcsize) - 1;
  53
  54         assert(reg_comp * srcsize == reg_offset);
  55         assert(dst_comp * dstsize == dst_offset);
  56
  57         for (signed c = 0; c < MIR_VEC_COMPONENTS; ++c) {
  58                 signed comp = MAX2(c - dst_comp, 0);
  59                 out[c] = MIN2(swizzle[comp] + reg_comp, max_component);
  60         }
  61
  62         memcpy(swizzle, out, sizeof(out));
  63 }
  64
  65 /* Helper to return the default phys_reg for a given register */
  66
  67 static struct phys_reg
  68 default_phys_reg(int reg, unsigned size)
  69 {
  70         struct phys_reg r = {
  71                 .reg = reg,
  72                 .offset = 0,
  73                 .size = size
  74         };
  75
  76         return r;
  77 }
  78
  79 /* Determine which physical register, swizzle, and mask a virtual
  80  * register corresponds to */
  81
  82 static struct phys_reg
  83 index_to_reg(compiler_context *ctx, struct lcra_state *l, unsigned reg, unsigned size)
  84 {
  85         /* Check for special cases */
  86         if (reg == ~0)
  87                 return default_phys_reg(REGISTER_UNUSED, size);
  88         else if (reg >= SSA_FIXED_MINIMUM)
  89                 return default_phys_reg(SSA_REG_FROM_FIXED(reg), size);
  90         else if (!l)
  91                 return default_phys_reg(REGISTER_UNUSED, size);
  92
  93         struct phys_reg r = {
  94                 .reg = l->solutions[reg] / 16,
  95                 .offset = l->solutions[reg] & 0xF,
  96                 .size = size
  97         };
  98
  99         /* Report that we actually use this register, and return it */
 100
 101         if (r.reg < 16)
 102                 ctx->work_registers = MAX2(ctx->work_registers, r.reg);
 103
 104         return r;
 105 }
 106
 107 static void
 108 set_class(unsigned *classes, unsigned node, unsigned class)
 109 {
 110         if (node < SSA_FIXED_MINIMUM && class != classes[node]) {
 111                 assert(classes[node] == REG_CLASS_WORK);
 112                 classes[node] = class;
 113         }
 114 }
 115
 116 /* Special register classes impose special constraints on who can read their
 117  * values, so check that */
 118
 119 static bool
 120 check_read_class(unsigned *classes, unsigned tag, unsigned node)
 121 {
 122         /* Non-nodes are implicitly ok */
 123         if (node >= SSA_FIXED_MINIMUM)
 124                 return true;
 125
 126         switch (classes[node]) {
 127         case REG_CLASS_LDST:
 128                 return (tag == TAG_LOAD_STORE_4);
 129         case REG_CLASS_TEXR:
 130                 return (tag == TAG_TEXTURE_4);
 131         case REG_CLASS_TEXW:
 132                 return (tag != TAG_LOAD_STORE_4);
 133         case REG_CLASS_WORK:
 134                 return IS_ALU(tag);
 135         default:
 136                 unreachable("Invalid class");
 137         }
 138 }
 139
 140 static bool
 141 check_write_class(unsigned *classes, unsigned tag, unsigned node)
 142 {
 143         /* Non-nodes are implicitly ok */
 144         if (node >= SSA_FIXED_MINIMUM)
 145                 return true;
 146
 147         switch (classes[node]) {
 148         case REG_CLASS_TEXR:
 149                 return true;
 150         case REG_CLASS_TEXW:
 151                 return (tag == TAG_TEXTURE_4);
 152         case REG_CLASS_LDST:
 153         case REG_CLASS_WORK:
 154                 return IS_ALU(tag) || (tag == TAG_LOAD_STORE_4);
 155         default:
 156                 unreachable("Invalid class");
 157         }
 158 }
 159
 160 /* Prepass before RA to ensure special class restrictions are met. The idea is
 161  * to create a bit field of types of instructions that read a particular index.
 162  * Later, we'll add moves as appropriate and rewrite to specialize by type. */
 163
 164 static void
 165 mark_node_class (unsigned *bitfield, unsigned node)
 166 {
 167         if (node < SSA_FIXED_MINIMUM)
 168                 BITSET_SET(bitfield, node);
 169 }
 170
 171 void
 172 mir_lower_special_reads(compiler_context *ctx)
 173 {
 174         size_t sz = BITSET_WORDS(ctx->temp_count) * sizeof(BITSET_WORD);
 175
 176         /* Bitfields for the various types of registers we could have. aluw can
 177          * be written by either ALU or load/store */
 178
 179         unsigned *alur = calloc(sz, 1);
 180         unsigned *aluw = calloc(sz, 1);
 181         unsigned *brar = calloc(sz, 1);
 182         unsigned *ldst = calloc(sz, 1);
 183         unsigned *texr = calloc(sz, 1);
 184         unsigned *texw = calloc(sz, 1);
 185
 186         /* Pass #1 is analysis, a linear scan to fill out the bitfields */
 187
 188         mir_foreach_instr_global(ctx, ins) {
 189                 switch (ins->type) {
 190                 case TAG_ALU_4:
 191                         mark_node_class(aluw, ins->dest);
 192                         mark_node_class(alur, ins->src[0]);
 193                         mark_node_class(alur, ins->src[1]);
 194                         mark_node_class(alur, ins->src[2]);
 195
 196                         if (ins->compact_branch && ins->writeout)
 197                                 mark_node_class(brar, ins->src[0]);
 198
 199                         break;
 200
 201                 case TAG_LOAD_STORE_4:
 202                         mark_node_class(aluw, ins->dest);
 203                         mark_node_class(ldst, ins->src[0]);
 204                         mark_node_class(ldst, ins->src[1]);
 205                         mark_node_class(ldst, ins->src[2]);
 206                         break;
 207
 208                 case TAG_TEXTURE_4:
 209                         mark_node_class(texr, ins->src[0]);
 210                         mark_node_class(texr, ins->src[1]);
 211                         mark_node_class(texr, ins->src[2]);
 212                         mark_node_class(texw, ins->dest);
 213                         break;
 214                 }
 215         }
 216
 217         /* Pass #2 is lowering now that we've analyzed all the classes.
 218          * Conceptually, if an index is only marked for a single type of use,
 219          * there is nothing to lower. If it is marked for different uses, we
 220          * split up based on the number of types of uses. To do so, we divide
 221          * into N distinct classes of use (where N>1 by definition), emit N-1
 222          * moves from the index to copies of the index, and finally rewrite N-1
 223          * of the types of uses to use the corresponding move */
 224
 225         unsigned spill_idx = ctx->temp_count;
 226
 227         for (unsigned i = 0; i < ctx->temp_count; ++i) {
 228                 bool is_alur = BITSET_TEST(alur, i);
 229                 bool is_aluw = BITSET_TEST(aluw, i);
 230                 bool is_brar = BITSET_TEST(brar, i);
 231                 bool is_ldst = BITSET_TEST(ldst, i);
 232                 bool is_texr = BITSET_TEST(texr, i);
 233                 bool is_texw = BITSET_TEST(texw, i);
 234
 235                 /* Analyse to check how many distinct uses there are. ALU ops
 236                  * (alur) can read the results of the texture pipeline (texw)
 237                  * but not ldst or texr. Load/store ops (ldst) cannot read
 238                  * anything but load/store inputs. Texture pipeline cannot read
 239                  * anything but texture inputs. TODO: Simplify.  */
 240
 241                 bool collision =
 242                         (is_alur && (is_ldst || is_texr)) ||
 243                         (is_ldst && (is_alur || is_texr || is_texw)) ||
 244                         (is_texr && (is_alur || is_ldst || is_texw)) ||
 245                         (is_texw && (is_aluw || is_ldst || is_texr)) ||
 246                         (is_brar && is_texw);
 247
 248                 if (!collision)
 249                         continue;
 250
 251                 /* Use the index as-is as the work copy. Emit copies for
 252                  * special uses */
 253
 254                 unsigned classes[] = { TAG_LOAD_STORE_4, TAG_TEXTURE_4, TAG_TEXTURE_4, TAG_ALU_4};
 255                 bool collisions[] = { is_ldst, is_texr, is_texw && is_aluw, is_brar };
 256
 257                 for (unsigned j = 0; j < ARRAY_SIZE(collisions); ++j) {
 258                         if (!collisions[j]) continue;
 259
 260                         /* When the hazard is from reading, we move and rewrite
 261                          * sources (typical case). When it's from writing, we
 262                          * flip the move and rewrite destinations (obscure,
 263                          * only from control flow -- impossible in SSA) */
 264
 265                         bool hazard_write = (j == 2);
 266
 267                         unsigned idx = spill_idx++;
 268
 269                         midgard_instruction m = hazard_write ?
 270                                 v_mov(idx, i) : v_mov(i, idx);
 271
 272                         /* Insert move before each read/write, depending on the
 273                          * hazard we're trying to account for */
 274
 275                         mir_foreach_instr_global_safe(ctx, pre_use) {
 276                                 if (pre_use->type != classes[j])
 277                                         continue;
 278
 279                                 if (hazard_write) {
 280                                         if (pre_use->dest != i)
 281                                                 continue;
 282                                 } else {
 283                                         if (!mir_has_arg(pre_use, i))
 284                                                 continue;
 285                                 }
 286
 287                                 if (hazard_write) {
 288                                         midgard_instruction *use = mir_next_op(pre_use);
 289                                         assert(use);
 290                                         mir_insert_instruction_before(ctx, use, m);
 291                                         mir_rewrite_index_dst_single(pre_use, i, idx);
 292                                 } else {
 293                                         idx = spill_idx++;
 294                                         m = v_mov(i, idx);
 295                                         m.mask = mir_from_bytemask(mir_bytemask_of_read_components(pre_use, i), 32);
 296                                         mir_insert_instruction_before(ctx, pre_use, m);
 297                                         mir_rewrite_index_src_single(pre_use, i, idx);
 298                                 }
 299                         }
 300                 }
 301         }
 302
 303         free(alur);
 304         free(aluw);
 305         free(brar);
 306         free(ldst);
 307         free(texr);
 308         free(texw);
 309 }
 310
 311 /* We register allocate after scheduling, so we need to ensure instructions
 312  * executing in parallel within a segment of a bundle don't clobber each
 313  * other's registers. This is mostly a non-issue thanks to scheduling, but
 314  * there are edge cases. In particular, after a register is written in a
 315  * segment, it interferes with anything reading. */
 316
 317 static void
 318 mir_compute_segment_interference(
 319                 compiler_context *ctx,
 320                 struct lcra_state *l,
 321                 midgard_bundle *bun,
 322                 unsigned pivot,
 323                 unsigned i)
 324 {
 325         for (unsigned j = pivot; j < i; ++j) {
 326                 mir_foreach_src(bun->instructions[j], s) {
 327                         if (bun->instructions[j]->src[s] >= ctx->temp_count)
 328                                 continue;
 329
 330                         for (unsigned q = pivot; q < i; ++q) {
 331                                 if (bun->instructions[q]->dest >= ctx->temp_count)
 332                                         continue;
 333
 334                                 /* See dEQP-GLES2.functional.shaders.return.output_write_in_func_dynamic_fragment */
 335
 336                                 if (q >= j) {
 337                                         if (!(bun->instructions[j]->unit == UNIT_SMUL && bun->instructions[q]->unit == UNIT_VLUT))
 338                                                 continue;
 339                                 }
 340
 341                                 unsigned mask = mir_bytemask(bun->instructions[q]);
 342                                 unsigned rmask = mir_bytemask_of_read_components(bun->instructions[j], bun->instructions[j]->src[s]);
 343                                 lcra_add_node_interference(l, bun->instructions[q]->dest, mask, bun->instructions[j]->src[s], rmask);
 344                         }
 345                 }
 346         }
 347 }
 348
 349 static void
 350 mir_compute_bundle_interference(
 351                 compiler_context *ctx,
 352                 struct lcra_state *l,
 353                 midgard_bundle *bun)
 354 {
 355         if (!IS_ALU(bun->tag))
 356                 return;
 357
 358         bool old = bun->instructions[0]->unit >= UNIT_VADD;
 359         unsigned pivot = 0;
 360
 361         for (unsigned i = 1; i < bun->instruction_count; ++i) {
 362                 bool new = bun->instructions[i]->unit >= UNIT_VADD;
 363
 364                 if (old != new) {
 365                         mir_compute_segment_interference(ctx, l, bun, 0, i);
 366                         pivot = i;
 367                         break;
 368                 }
 369         }
 370
 371         mir_compute_segment_interference(ctx, l, bun, pivot, bun->instruction_count);
 372 }
 373
 374 static void
 375 mir_compute_interference(
 376                 compiler_context *ctx,
 377                 struct lcra_state *l)
 378 {
 379         /* First, we need liveness information to be computed per block */
 380         mir_compute_liveness(ctx);
 381
 382         /* We need to force r1.w live throughout a blend shader */
 383
 384         if (ctx->is_blend) {
 385                 unsigned r1w = ~0;
 386
 387                 mir_foreach_block(ctx, _block) {
 388                         midgard_block *block = (midgard_block *) _block;
 389                         mir_foreach_instr_in_block_rev(block, ins) {
 390                                 if (ins->writeout)
 391                                         r1w = ins->src[2];
 392                         }
 393
 394                         if (r1w != ~0)
 395                                 break;
 396                 }
 397
 398                 mir_foreach_instr_global(ctx, ins) {
 399                         if (ins->dest < ctx->temp_count)
 400                                 lcra_add_node_interference(l, ins->dest, mir_bytemask(ins), r1w, 0xF);
 401                 }
 402         }
 403
 404         /* Now that every block has live_in/live_out computed, we can determine
 405          * interference by walking each block linearly. Take live_out at the
 406          * end of each block and walk the block backwards. */
 407
 408         mir_foreach_block(ctx, _blk) {
 409                 midgard_block *blk = (midgard_block *) _blk;
 410                 uint16_t *live = mem_dup(_blk->live_out, ctx->temp_count * sizeof(uint16_t));
 411
 412                 mir_foreach_instr_in_block_rev(blk, ins) {
 413                         /* Mark all registers live after the instruction as
 414                          * interfering with the destination */
 415
 416                         unsigned dest = ins->dest;
 417
 418                         if (dest < ctx->temp_count) {
 419                                 for (unsigned i = 0; i < ctx->temp_count; ++i)
 420                                         if (live[i]) {
 421                                                 unsigned mask = mir_bytemask(ins);
 422                                                 lcra_add_node_interference(l, dest, mask, i, live[i]);
 423                                         }
 424                         }
 425
 426                         /* Update live_in */
 427                         mir_liveness_ins_update(live, ins, ctx->temp_count);
 428                 }
 429
 430                 mir_foreach_bundle_in_block(blk, bun)
 431                         mir_compute_bundle_interference(ctx, l, bun);
 432
 433                 free(live);
 434         }
 435 }
 436
 437 /* This routine performs the actual register allocation. It should be succeeded
 438  * by install_registers */
 439
 440 static struct lcra_state *
 441 allocate_registers(compiler_context *ctx, bool *spilled)
 442 {
 443         /* The number of vec4 work registers available depends on when the
 444          * uniforms start, so compute that first */
 445         int work_count = 16 - MAX2((ctx->uniform_cutoff - 8), 0);
 446
 447        /* No register allocation to do with no SSA */
 448
 449         if (!ctx->temp_count)
 450                 return NULL;
 451
 452         struct lcra_state *l = lcra_alloc_equations(ctx->temp_count, 1, 8, 16, 5);
 453
 454         /* Starts of classes, in bytes */
 455         l->class_start[REG_CLASS_WORK]  = 16 * 0;
 456         l->class_start[REG_CLASS_LDST]  = 16 * 26;
 457         l->class_start[REG_CLASS_TEXR]  = 16 * 28;
 458         l->class_start[REG_CLASS_TEXW]  = 16 * 28;
 459
 460         l->class_size[REG_CLASS_WORK] = 16 * work_count;
 461         l->class_size[REG_CLASS_LDST]  = 16 * 2;
 462         l->class_size[REG_CLASS_TEXR]  = 16 * 2;
 463         l->class_size[REG_CLASS_TEXW]  = 16 * 2;
 464
 465         lcra_set_disjoint_class(l, REG_CLASS_TEXR, REG_CLASS_TEXW);
 466
 467         /* To save space on T*20, we don't have real texture registers.
 468          * Instead, tex inputs reuse the load/store pipeline registers, and
 469          * tex outputs use work r0/r1. Note we still use TEXR/TEXW classes,
 470          * noting that this handles interferences and sizes correctly. */
 471
 472         if (ctx->quirks & MIDGARD_INTERPIPE_REG_ALIASING) {
 473                 l->class_start[REG_CLASS_TEXR] = l->class_start[REG_CLASS_LDST];
 474                 l->class_start[REG_CLASS_TEXW] = l->class_start[REG_CLASS_WORK];
 475         }
 476
 477         unsigned *found_class = calloc(sizeof(unsigned), ctx->temp_count);
 478         unsigned *min_alignment = calloc(sizeof(unsigned), ctx->temp_count);
 479
 480         mir_foreach_instr_global(ctx, ins) {
 481                 /* Swizzles of 32-bit sources on 64-bit instructions need to be
 482                  * aligned to either bottom (xy) or top (zw). More general
 483                  * swizzle lowering should happen prior to scheduling (TODO),
 484                  * but once we get RA we shouldn't disrupt this further. Align
 485                  * sources of 64-bit instructions. */
 486
 487                 if (ins->type == TAG_ALU_4 && ins->alu.reg_mode == midgard_reg_mode_64) {
 488                         mir_foreach_src(ins, v) {
 489                                 unsigned s = ins->src[v];
 490
 491                                 if (s < ctx->temp_count)
 492                                         min_alignment[s] = 3;
 493                         }
 494                 }
 495
 496                 if (ins->type == TAG_LOAD_STORE_4 && OP_HAS_ADDRESS(ins->load_store.op)) {
 497                         mir_foreach_src(ins, v) {
 498                                 unsigned s = ins->src[v];
 499                                 unsigned size = nir_alu_type_get_type_size(ins->src_types[v]);
 500
 501                                 if (s < ctx->temp_count)
 502                                         min_alignment[s] = (size == 64) ? 3 : 2;
 503                         }
 504                 }
 505
 506                 if (ins->dest >= SSA_FIXED_MINIMUM) continue;
 507
 508                 /* 0 for x, 1 for xy, 2 for xyz, 3 for xyzw */
 509                 int class = util_logbase2(ins->mask);
 510
 511                 /* Use the largest class if there's ambiguity, this
 512                  * handles partial writes */
 513
 514                 int dest = ins->dest;
 515                 found_class[dest] = MAX2(found_class[dest], class);
 516
 517                 /* XXX: Ensure swizzles align the right way with more LCRA constraints? */
 518                 if (ins->type == TAG_ALU_4 && ins->alu.reg_mode != midgard_reg_mode_32)
 519                         min_alignment[dest] = 3; /* (1 << 3) = 8 */
 520
 521                 if (ins->type == TAG_LOAD_STORE_4 && ins->load_64)
 522                         min_alignment[dest] = 3;
 523
 524                 /* We don't have a swizzle for the conditional and we don't
 525                  * want to muck with the conditional itself, so just force
 526                  * alignment for now */
 527
 528                 if (ins->type == TAG_ALU_4 && OP_IS_CSEL_V(ins->alu.op))
 529                         min_alignment[dest] = 4; /* 1 << 4= 16-byte = vec4 */
 530
 531         }
 532
 533         for (unsigned i = 0; i < ctx->temp_count; ++i) {
 534                 lcra_set_alignment(l, i, min_alignment[i] ? min_alignment[i] : 2);
 535                 lcra_restrict_range(l, i, (found_class[i] + 1) * 4);
 536         }
 537
 538         free(found_class);
 539         free(min_alignment);
 540
 541         /* Next, we'll determine semantic class. We default to zero (work).
 542          * But, if we're used with a special operation, that will force us to a
 543          * particular class. Each node must be assigned to exactly one class; a
 544          * prepass before RA should have lowered what-would-have-been
 545          * multiclass nodes into a series of moves to break it up into multiple
 546          * nodes (TODO) */
 547
 548         mir_foreach_instr_global(ctx, ins) {
 549                 /* Check if this operation imposes any classes */
 550
 551                 if (ins->type == TAG_LOAD_STORE_4) {
 552                         set_class(l->class, ins->src[0], REG_CLASS_LDST);
 553                         set_class(l->class, ins->src[1], REG_CLASS_LDST);
 554                         set_class(l->class, ins->src[2], REG_CLASS_LDST);
 555
 556                         if (OP_IS_VEC4_ONLY(ins->load_store.op)) {
 557                                 lcra_restrict_range(l, ins->dest, 16);
 558                                 lcra_restrict_range(l, ins->src[0], 16);
 559                                 lcra_restrict_range(l, ins->src[1], 16);
 560                                 lcra_restrict_range(l, ins->src[2], 16);
 561                         }
 562                 } else if (ins->type == TAG_TEXTURE_4) {
 563                         set_class(l->class, ins->dest, REG_CLASS_TEXW);
 564                         set_class(l->class, ins->src[0], REG_CLASS_TEXR);
 565                         set_class(l->class, ins->src[1], REG_CLASS_TEXR);
 566                         set_class(l->class, ins->src[2], REG_CLASS_TEXR);
 567                         set_class(l->class, ins->src[3], REG_CLASS_TEXR);
 568                 }
 569         }
 570
 571         /* Check that the semantics of the class are respected */
 572         mir_foreach_instr_global(ctx, ins) {
 573                 assert(check_write_class(l->class, ins->type, ins->dest));
 574                 assert(check_read_class(l->class, ins->type, ins->src[0]));
 575                 assert(check_read_class(l->class, ins->type, ins->src[1]));
 576                 assert(check_read_class(l->class, ins->type, ins->src[2]));
 577         }
 578
 579         /* Mark writeout to r0, render target to r1.z, unknown to r1.w */
 580         mir_foreach_instr_global(ctx, ins) {
 581                 if (!(ins->compact_branch && ins->writeout)) continue;
 582
 583                 if (ins->src[0] < ctx->temp_count) {
 584                         if (ins->writeout_depth)
 585                                 l->solutions[ins->src[0]] = (16 * 1) + COMPONENT_X * 4;
 586                         else if (ins->writeout_stencil)
 587                                 l->solutions[ins->src[0]] = (16 * 1) + COMPONENT_Y * 4;
 588                         else
 589                                 l->solutions[ins->src[0]] = 0;
 590                 }
 591
 592                 if (ins->src[1] < ctx->temp_count)
 593                         l->solutions[ins->src[1]] = (16 * 1) + COMPONENT_Z * 4;
 594
 595                 if (ins->src[2] < ctx->temp_count)
 596                         l->solutions[ins->src[2]] = (16 * 1) + COMPONENT_W * 4;
 597         }
 598
 599         mir_compute_interference(ctx, l);
 600
 601         *spilled = !lcra_solve(l);
 602         return l;
 603 }
 604
 605
 606 /* Once registers have been decided via register allocation
 607  * (allocate_registers), we need to rewrite the MIR to use registers instead of
 608  * indices */
 609
 610 static void
 611 install_registers_instr(
 612         compiler_context *ctx,
 613         struct lcra_state *l,
 614         midgard_instruction *ins)
 615 {
 616         unsigned src_size[MIR_SRC_COUNT];
 617
 618         for (unsigned i = 0; i < MIR_SRC_COUNT; ++i)
 619                 src_size[i] = MAX2(nir_alu_type_get_type_size(ins->src_types[i]) / 8, 1);
 620
 621         unsigned dest_size = MAX2(nir_alu_type_get_type_size(ins->dest_type) / 8, 1);
 622
 623         switch (ins->type) {
 624         case TAG_ALU_4:
 625         case TAG_ALU_8:
 626         case TAG_ALU_12:
 627         case TAG_ALU_16: {
 628                  if (ins->compact_branch)
 629                          return;
 630
 631                 struct phys_reg src1 = index_to_reg(ctx, l, ins->src[0], src_size[0]);
 632                 struct phys_reg src2 = index_to_reg(ctx, l, ins->src[1], src_size[1]);
 633                 struct phys_reg dest = index_to_reg(ctx, l, ins->dest, dest_size);
 634
 635                 mir_set_bytemask(ins, mir_bytemask(ins) << dest.offset);
 636
 637                 unsigned dest_offset =
 638                         GET_CHANNEL_COUNT(alu_opcode_props[ins->alu.op].props) ? 0 :
 639                         dest.offset;
 640
 641                 offset_swizzle(ins->swizzle[0], src1.offset, src1.size, dest.size, dest_offset);
 642
 643                 ins->registers.src1_reg = src1.reg;
 644
 645                 ins->registers.src2_imm = ins->has_inline_constant;
 646
 647                 if (ins->has_inline_constant) {
 648                         /* Encode inline 16-bit constant. See disassembler for
 649                          * where the algorithm is from */
 650
 651                         ins->registers.src2_reg = ins->inline_constant >> 11;
 652
 653                         int lower_11 = ins->inline_constant & ((1 << 12) - 1);
 654                         uint16_t imm = ((lower_11 >> 8) & 0x7) |
 655                                        ((lower_11 & 0xFF) << 3);
 656
 657                         ins->alu.src2 = imm << 2;
 658                 } else {
 659                         midgard_vector_alu_src mod2 =
 660                                 vector_alu_from_unsigned(ins->alu.src2);
 661                         offset_swizzle(ins->swizzle[1], src2.offset, src2.size, dest.size, dest_offset);
 662                         ins->alu.src2 = vector_alu_srco_unsigned(mod2);
 663
 664                         ins->registers.src2_reg = src2.reg;
 665                 }
 666
 667                 ins->registers.out_reg = dest.reg;
 668                 break;
 669         }
 670
 671         case TAG_LOAD_STORE_4: {
 672                 /* Which physical register we read off depends on
 673                  * whether we are loading or storing -- think about the
 674                  * logical dataflow */
 675
 676                 bool encodes_src = OP_IS_STORE(ins->load_store.op);
 677
 678                 if (encodes_src) {
 679                         struct phys_reg src = index_to_reg(ctx, l, ins->src[0], src_size[0]);
 680                         assert(src.reg == 26 || src.reg == 27);
 681
 682                         ins->load_store.reg = src.reg - 26;
 683                         offset_swizzle(ins->swizzle[0], src.offset, src.size, 1, 0);
 684                } else {
 685                         struct phys_reg dst = index_to_reg(ctx, l, ins->dest, dest_size);
 686
 687                         ins->load_store.reg = dst.reg;
 688                         offset_swizzle(ins->swizzle[0], 0, 4, dst.size, dst.offset);
 689                         mir_set_bytemask(ins, mir_bytemask(ins) << dst.offset);
 690                 }
 691
 692                 /* We also follow up by actual arguments */
 693
 694                 unsigned src2 = ins->src[1];
 695                 unsigned src3 = ins->src[2];
 696
 697                 if (src2 != ~0) {
 698                         struct phys_reg src = index_to_reg(ctx, l, src2, 4);
 699                         unsigned component = src.offset / src.size;
 700                         assert(component * src.size == src.offset);
 701                         ins->load_store.arg_1 |= midgard_ldst_reg(src.reg, component);
 702                 }
 703
 704                 if (src3 != ~0) {
 705                         struct phys_reg src = index_to_reg(ctx, l, src3, 4);
 706                         unsigned component = src.offset / src.size;
 707                         assert(component * src.size == src.offset);
 708                         ins->load_store.arg_2 |= midgard_ldst_reg(src.reg, component);
 709                 }
 710
 711                 break;
 712         }
 713
 714         case TAG_TEXTURE_4: {
 715                 if (ins->texture.op == TEXTURE_OP_BARRIER)
 716                         break;
 717
 718                 /* Grab RA results */
 719                 struct phys_reg dest = index_to_reg(ctx, l, ins->dest, dest_size);
 720                 struct phys_reg coord = index_to_reg(ctx, l, ins->src[1], src_size[1]);
 721                 struct phys_reg lod = index_to_reg(ctx, l, ins->src[2], src_size[2]);
 722                 struct phys_reg offset = index_to_reg(ctx, l, ins->src[3], src_size[3]);
 723
 724                 /* First, install the texture coordinate */
 725                 ins->texture.in_reg_full = 1;
 726                 ins->texture.in_reg_upper = 0;
 727                 ins->texture.in_reg_select = coord.reg & 1;
 728                 offset_swizzle(ins->swizzle[1], coord.offset, coord.size, dest.size, 0);
 729
 730                 /* Next, install the destination */
 731                 ins->texture.out_full = 1;
 732                 ins->texture.out_upper = 0;
 733                 ins->texture.out_reg_select = dest.reg & 1;
 734                 offset_swizzle(ins->swizzle[0], 0, 4, dest.size, dest.offset);
 735                 mir_set_bytemask(ins, mir_bytemask(ins) << dest.offset);
 736
 737                 /* If there is a register LOD/bias, use it */
 738                 if (ins->src[2] != ~0) {
 739                         assert(!(lod.offset & 3));
 740                         midgard_tex_register_select sel = {
 741                                 .select = lod.reg & 1,
 742                                 .full = 1,
 743                                 .component = lod.offset / 4
 744                         };
 745
 746                         uint8_t packed;
 747                         memcpy(&packed, &sel, sizeof(packed));
 748                         ins->texture.bias = packed;
 749                 }
 750
 751                 /* If there is an offset register, install it */
 752                 if (ins->src[3] != ~0) {
 753                         unsigned x = offset.offset / 4;
 754                         unsigned y = x + 1;
 755                         unsigned z = x + 2;
 756
 757                         /* Check range, TODO: half-registers */
 758                         assert(z < 4);
 759
 760                         ins->texture.offset =
 761                                 (1)                   | /* full */
 762                                 (offset.reg & 1) << 1 | /* select */
 763                                 (0 << 2)              | /* upper */
 764                                 (x << 3)              | /* swizzle */
 765                                 (y << 5)              | /* swizzle */
 766                                 (z << 7);               /* swizzle */
 767                 }
 768
 769                 break;
 770         }
 771
 772         default:
 773                 break;
 774         }
 775 }
 776
 777 static void
 778 install_registers(compiler_context *ctx, struct lcra_state *l)
 779 {
 780         mir_foreach_instr_global(ctx, ins)
 781                 install_registers_instr(ctx, l, ins);
 782 }
 783
 784
 785 /* If register allocation fails, find the best spill node */
 786
 787 static signed
 788 mir_choose_spill_node(
 789                 compiler_context *ctx,
 790                 struct lcra_state *l)
 791 {
 792         /* We can't spill a previously spilled value or an unspill */
 793
 794         mir_foreach_instr_global(ctx, ins) {
 795                 if (ins->no_spill & (1 << l->spill_class)) {
 796                         lcra_set_node_spill_cost(l, ins->dest, -1);
 797
 798                         if (l->spill_class != REG_CLASS_WORK) {
 799                                 mir_foreach_src(ins, s)
 800                                         lcra_set_node_spill_cost(l, ins->src[s], -1);
 801                         }
 802                 }
 803         }
 804
 805         return lcra_get_best_spill_node(l);
 806 }
 807
 808 /* Once we've chosen a spill node, spill it */
 809
 810 static void
 811 mir_spill_register(
 812                 compiler_context *ctx,
 813                 unsigned spill_node,
 814                 unsigned spill_class,
 815                 unsigned *spill_count)
 816 {
 817         unsigned spill_index = ctx->temp_count;
 818
 819         /* We have a spill node, so check the class. Work registers
 820          * legitimately spill to TLS, but special registers just spill to work
 821          * registers */
 822
 823         bool is_special = spill_class != REG_CLASS_WORK;
 824         bool is_special_w = spill_class == REG_CLASS_TEXW;
 825
 826         /* Allocate TLS slot (maybe) */
 827         unsigned spill_slot = !is_special ? (*spill_count)++ : 0;
 828
 829         /* For TLS, replace all stores to the spilled node. For
 830          * special reads, just keep as-is; the class will be demoted
 831          * implicitly. For special writes, spill to a work register */
 832
 833         if (!is_special || is_special_w) {
 834                 if (is_special_w)
 835                         spill_slot = spill_index++;
 836
 837                 mir_foreach_block(ctx, _block) {
 838                 midgard_block *block = (midgard_block *) _block;
 839                 mir_foreach_instr_in_block_safe(block, ins) {
 840                         if (ins->dest != spill_node) continue;
 841
 842                         midgard_instruction st;
 843
 844                         if (is_special_w) {
 845                                 st = v_mov(spill_node, spill_slot);
 846                                 st.no_spill |= (1 << spill_class);
 847                         } else {
 848                                 ins->dest = spill_index++;
 849                                 ins->no_spill |= (1 << spill_class);
 850                                 st = v_load_store_scratch(ins->dest, spill_slot, true, ins->mask);
 851                         }
 852
 853                         /* Hint: don't rewrite this node */
 854                         st.hint = true;
 855
 856                         mir_insert_instruction_after_scheduled(ctx, block, ins, st);
 857
 858                         if (!is_special)
 859                                 ctx->spills++;
 860                 }
 861                 }
 862         }
 863
 864         /* For special reads, figure out how many bytes we need */
 865         unsigned read_bytemask = 0;
 866
 867         mir_foreach_instr_global_safe(ctx, ins) {
 868                 read_bytemask |= mir_bytemask_of_read_components(ins, spill_node);
 869         }
 870
 871         /* Insert a load from TLS before the first consecutive
 872          * use of the node, rewriting to use spilled indices to
 873          * break up the live range. Or, for special, insert a
 874          * move. Ironically the latter *increases* register
 875          * pressure, but the two uses of the spilling mechanism
 876          * are somewhat orthogonal. (special spilling is to use
 877          * work registers to back special registers; TLS
 878          * spilling is to use memory to back work registers) */
 879
 880         mir_foreach_block(ctx, _block) {
 881                 midgard_block *block = (midgard_block *) _block;
 882                 mir_foreach_instr_in_block(block, ins) {
 883                         /* We can't rewrite the moves used to spill in the
 884                          * first place. These moves are hinted. */
 885                         if (ins->hint) continue;
 886
 887                         /* If we don't use the spilled value, nothing to do */
 888                         if (!mir_has_arg(ins, spill_node)) continue;
 889
 890                         unsigned index = 0;
 891
 892                         if (!is_special_w) {
 893                                 index = ++spill_index;
 894
 895                                 midgard_instruction *before = ins;
 896                                 midgard_instruction st;
 897
 898                                 if (is_special) {
 899                                         /* Move */
 900                                         st = v_mov(spill_node, index);
 901                                         st.no_spill |= (1 << spill_class);
 902                                 } else {
 903                                         /* TLS load */
 904                                         st = v_load_store_scratch(index, spill_slot, false, 0xF);
 905                                 }
 906
 907                                 /* Mask the load based on the component count
 908                                  * actually needed to prevent RA loops */
 909
 910                                 st.mask = mir_from_bytemask(read_bytemask, 32);
 911
 912                                 mir_insert_instruction_before_scheduled(ctx, block, before, st);
 913                         } else {
 914                                 /* Special writes already have their move spilled in */
 915                                 index = spill_slot;
 916                         }
 917
 918
 919                         /* Rewrite to use */
 920                         mir_rewrite_index_src_single(ins, spill_node, index);
 921
 922                         if (!is_special)
 923                                 ctx->fills++;
 924                 }
 925         }
 926
 927         /* Reset hints */
 928
 929         mir_foreach_instr_global(ctx, ins) {
 930                 ins->hint = false;
 931         }
 932 }
 933
 934 /* Run register allocation in a loop, spilling until we succeed */
 935
 936 void
 937 mir_ra(compiler_context *ctx)
 938 {
 939         struct lcra_state *l = NULL;
 940         bool spilled = false;
 941         int iter_count = 1000; /* max iterations */
 942
 943         /* Number of 128-bit slots in memory we've spilled into */
 944         unsigned spill_count = 0;
 945
 946
 947         mir_create_pipeline_registers(ctx);
 948
 949         do {
 950                 if (spilled) {
 951                         signed spill_node = mir_choose_spill_node(ctx, l);
 952
 953                         if (spill_node == -1) {
 954                                 fprintf(stderr, "ERROR: Failed to choose spill node\n");
 955                                 return;
 956                         }
 957
 958                         mir_spill_register(ctx, spill_node, l->spill_class, &spill_count);
 959                 }
 960
 961                 mir_squeeze_index(ctx);
 962                 mir_invalidate_liveness(ctx);
 963
 964                 if (l) {
 965                         lcra_free(l);
 966                         l = NULL;
 967                 }
 968
 969                 l = allocate_registers(ctx, &spilled);
 970         } while(spilled && ((iter_count--) > 0));
 971
 972         if (iter_count <= 0) {
 973                 fprintf(stderr, "panfrost: Gave up allocating registers, rendering will be incomplete\n");
 974                 assert(0);
 975         }
 976
 977         /* Report spilling information. spill_count is in 128-bit slots (vec4 x
 978          * fp32), but tls_size is in bytes, so multiply by 16 */
 979
 980         ctx->tls_size = spill_count * 16;
 981
 982         install_registers(ctx, l);
 983
 984         lcra_free(l);
 985 }