src/panfrost/midgard/midgard_ra.c

   1 /*
   2  * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  * Copyright (C) 2019 Collabora, Ltd.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  */
  24
  25 #include "compiler.h"
  26 #include "midgard_ops.h"
  27 #include "util/u_math.h"
  28 #include "util/u_memory.h"
  29 #include "lcra.h"
  30 #include "midgard_quirks.h"
  31
  32 struct phys_reg {
  33         /* Physical register: 0-31 */
  34         unsigned reg;
  35
  36         /* Byte offset into the physical register: 0-15 */
  37         unsigned offset;
  38
  39         /* Number of bytes in a component of this register */
  40         unsigned size;
  41 };
  42
  43 /* Shift up by reg_offset and horizontally by dst_offset. */
  44
  45 static void
  46 offset_swizzle(unsigned *swizzle, unsigned reg_offset, unsigned srcsize, unsigned dst_offset)
  47 {
  48         unsigned out[MIR_VEC_COMPONENTS];
  49
  50         signed reg_comp = reg_offset / srcsize;
  51         signed dst_comp = dst_offset / srcsize;
  52
  53         unsigned max_component = (16 / srcsize) - 1;
  54
  55         assert(reg_comp * srcsize == reg_offset);
  56         assert(dst_comp * srcsize == dst_offset);
  57
  58         for (signed c = 0; c < MIR_VEC_COMPONENTS; ++c) {
  59                 signed comp = MAX2(c - dst_comp, 0);
  60                 out[c] = MIN2(swizzle[comp] + reg_comp, max_component);
  61         }
  62
  63         memcpy(swizzle, out, sizeof(out));
  64 }
  65
  66 /* Helper to return the default phys_reg for a given register */
  67
  68 static struct phys_reg
  69 default_phys_reg(int reg, midgard_reg_mode size)
  70 {
  71         struct phys_reg r = {
  72                 .reg = reg,
  73                 .offset = 0,
  74                 .size = mir_bytes_for_mode(size)
  75         };
  76
  77         return r;
  78 }
  79
  80 /* Determine which physical register, swizzle, and mask a virtual
  81  * register corresponds to */
  82
  83 static struct phys_reg
  84 index_to_reg(compiler_context *ctx, struct lcra_state *l, unsigned reg, midgard_reg_mode size)
  85 {
  86         /* Check for special cases */
  87         if (reg == ~0)
  88                 return default_phys_reg(REGISTER_UNUSED, size);
  89         else if (reg >= SSA_FIXED_MINIMUM)
  90                 return default_phys_reg(SSA_REG_FROM_FIXED(reg), size);
  91         else if (!l)
  92                 return default_phys_reg(REGISTER_UNUSED, size);
  93
  94         struct phys_reg r = {
  95                 .reg = l->solutions[reg] / 16,
  96                 .offset = l->solutions[reg] & 0xF,
  97                 .size = mir_bytes_for_mode(size)
  98         };
  99
 100         /* Report that we actually use this register, and return it */
 101
 102         if (r.reg < 16)
 103                 ctx->work_registers = MAX2(ctx->work_registers, r.reg);
 104
 105         return r;
 106 }
 107
 108 static void
 109 set_class(unsigned *classes, unsigned node, unsigned class)
 110 {
 111         if (node < SSA_FIXED_MINIMUM && class != classes[node]) {
 112                 assert(classes[node] == REG_CLASS_WORK);
 113                 classes[node] = class;
 114         }
 115 }
 116
 117 /* Special register classes impose special constraints on who can read their
 118  * values, so check that */
 119
 120 static bool
 121 check_read_class(unsigned *classes, unsigned tag, unsigned node)
 122 {
 123         /* Non-nodes are implicitly ok */
 124         if (node >= SSA_FIXED_MINIMUM)
 125                 return true;
 126
 127         switch (classes[node]) {
 128         case REG_CLASS_LDST:
 129                 return (tag == TAG_LOAD_STORE_4);
 130         case REG_CLASS_TEXR:
 131                 return (tag == TAG_TEXTURE_4);
 132         case REG_CLASS_TEXW:
 133                 return (tag != TAG_LOAD_STORE_4);
 134         case REG_CLASS_WORK:
 135                 return IS_ALU(tag);
 136         default:
 137                 unreachable("Invalid class");
 138         }
 139 }
 140
 141 static bool
 142 check_write_class(unsigned *classes, unsigned tag, unsigned node)
 143 {
 144         /* Non-nodes are implicitly ok */
 145         if (node >= SSA_FIXED_MINIMUM)
 146                 return true;
 147
 148         switch (classes[node]) {
 149         case REG_CLASS_TEXR:
 150                 return true;
 151         case REG_CLASS_TEXW:
 152                 return (tag == TAG_TEXTURE_4);
 153         case REG_CLASS_LDST:
 154         case REG_CLASS_WORK:
 155                 return IS_ALU(tag) || (tag == TAG_LOAD_STORE_4);
 156         default:
 157                 unreachable("Invalid class");
 158         }
 159 }
 160
 161 /* Prepass before RA to ensure special class restrictions are met. The idea is
 162  * to create a bit field of types of instructions that read a particular index.
 163  * Later, we'll add moves as appropriate and rewrite to specialize by type. */
 164
 165 static void
 166 mark_node_class (unsigned *bitfield, unsigned node)
 167 {
 168         if (node < SSA_FIXED_MINIMUM)
 169                 BITSET_SET(bitfield, node);
 170 }
 171
 172 void
 173 mir_lower_special_reads(compiler_context *ctx)
 174 {
 175         size_t sz = BITSET_WORDS(ctx->temp_count) * sizeof(BITSET_WORD);
 176
 177         /* Bitfields for the various types of registers we could have. aluw can
 178          * be written by either ALU or load/store */
 179
 180         unsigned *alur = calloc(sz, 1);
 181         unsigned *aluw = calloc(sz, 1);
 182         unsigned *brar = calloc(sz, 1);
 183         unsigned *ldst = calloc(sz, 1);
 184         unsigned *texr = calloc(sz, 1);
 185         unsigned *texw = calloc(sz, 1);
 186
 187         /* Pass #1 is analysis, a linear scan to fill out the bitfields */
 188
 189         mir_foreach_instr_global(ctx, ins) {
 190                 switch (ins->type) {
 191                 case TAG_ALU_4:
 192                         mark_node_class(aluw, ins->dest);
 193                         mark_node_class(alur, ins->src[0]);
 194                         mark_node_class(alur, ins->src[1]);
 195                         mark_node_class(alur, ins->src[2]);
 196
 197                         if (ins->compact_branch && ins->writeout)
 198                                 mark_node_class(brar, ins->src[0]);
 199
 200                         break;
 201
 202                 case TAG_LOAD_STORE_4:
 203                         mark_node_class(aluw, ins->dest);
 204                         mark_node_class(ldst, ins->src[0]);
 205                         mark_node_class(ldst, ins->src[1]);
 206                         mark_node_class(ldst, ins->src[2]);
 207                         break;
 208
 209                 case TAG_TEXTURE_4:
 210                         mark_node_class(texr, ins->src[0]);
 211                         mark_node_class(texr, ins->src[1]);
 212                         mark_node_class(texr, ins->src[2]);
 213                         mark_node_class(texw, ins->dest);
 214                         break;
 215                 }
 216         }
 217
 218         /* Pass #2 is lowering now that we've analyzed all the classes.
 219          * Conceptually, if an index is only marked for a single type of use,
 220          * there is nothing to lower. If it is marked for different uses, we
 221          * split up based on the number of types of uses. To do so, we divide
 222          * into N distinct classes of use (where N>1 by definition), emit N-1
 223          * moves from the index to copies of the index, and finally rewrite N-1
 224          * of the types of uses to use the corresponding move */
 225
 226         unsigned spill_idx = ctx->temp_count;
 227
 228         for (unsigned i = 0; i < ctx->temp_count; ++i) {
 229                 bool is_alur = BITSET_TEST(alur, i);
 230                 bool is_aluw = BITSET_TEST(aluw, i);
 231                 bool is_brar = BITSET_TEST(brar, i);
 232                 bool is_ldst = BITSET_TEST(ldst, i);
 233                 bool is_texr = BITSET_TEST(texr, i);
 234                 bool is_texw = BITSET_TEST(texw, i);
 235
 236                 /* Analyse to check how many distinct uses there are. ALU ops
 237                  * (alur) can read the results of the texture pipeline (texw)
 238                  * but not ldst or texr. Load/store ops (ldst) cannot read
 239                  * anything but load/store inputs. Texture pipeline cannot read
 240                  * anything but texture inputs. TODO: Simplify.  */
 241
 242                 bool collision =
 243                         (is_alur && (is_ldst || is_texr)) ||
 244                         (is_ldst && (is_alur || is_texr || is_texw)) ||
 245                         (is_texr && (is_alur || is_ldst || is_texw)) ||
 246                         (is_texw && (is_aluw || is_ldst || is_texr)) ||
 247                         (is_brar && is_texw);
 248
 249                 if (!collision)
 250                         continue;
 251
 252                 /* Use the index as-is as the work copy. Emit copies for
 253                  * special uses */
 254
 255                 unsigned classes[] = { TAG_LOAD_STORE_4, TAG_TEXTURE_4, TAG_TEXTURE_4, TAG_ALU_4};
 256                 bool collisions[] = { is_ldst, is_texr, is_texw && is_aluw, is_brar };
 257
 258                 for (unsigned j = 0; j < ARRAY_SIZE(collisions); ++j) {
 259                         if (!collisions[j]) continue;
 260
 261                         /* When the hazard is from reading, we move and rewrite
 262                          * sources (typical case). When it's from writing, we
 263                          * flip the move and rewrite destinations (obscure,
 264                          * only from control flow -- impossible in SSA) */
 265
 266                         bool hazard_write = (j == 2);
 267
 268                         unsigned idx = spill_idx++;
 269
 270                         midgard_instruction m = hazard_write ?
 271                                 v_mov(idx, i) : v_mov(i, idx);
 272
 273                         /* Insert move before each read/write, depending on the
 274                          * hazard we're trying to account for */
 275
 276                         mir_foreach_instr_global_safe(ctx, pre_use) {
 277                                 if (pre_use->type != classes[j])
 278                                         continue;
 279
 280                                 if (hazard_write) {
 281                                         if (pre_use->dest != i)
 282                                                 continue;
 283                                 } else {
 284                                         if (!mir_has_arg(pre_use, i))
 285                                                 continue;
 286                                 }
 287
 288                                 if (hazard_write) {
 289                                         midgard_instruction *use = mir_next_op(pre_use);
 290                                         assert(use);
 291                                         mir_insert_instruction_before(ctx, use, m);
 292                                         mir_rewrite_index_dst_single(pre_use, i, idx);
 293                                 } else {
 294                                         idx = spill_idx++;
 295                                         m = v_mov(i, idx);
 296                                         m.mask = mir_from_bytemask(mir_bytemask_of_read_components(pre_use, i), midgard_reg_mode_32);
 297                                         mir_insert_instruction_before(ctx, pre_use, m);
 298                                         mir_rewrite_index_src_single(pre_use, i, idx);
 299                                 }
 300                         }
 301                 }
 302         }
 303
 304         free(alur);
 305         free(aluw);
 306         free(brar);
 307         free(ldst);
 308         free(texr);
 309         free(texw);
 310 }
 311
 312 /* We register allocate after scheduling, so we need to ensure instructions
 313  * executing in parallel within a segment of a bundle don't clobber each
 314  * other's registers. This is mostly a non-issue thanks to scheduling, but
 315  * there are edge cases. In particular, after a register is written in a
 316  * segment, it interferes with anything reading. */
 317
 318 static void
 319 mir_compute_segment_interference(
 320                 compiler_context *ctx,
 321                 struct lcra_state *l,
 322                 midgard_bundle *bun,
 323                 unsigned pivot,
 324                 unsigned i)
 325 {
 326         for (unsigned j = pivot; j < i; ++j) {
 327                 mir_foreach_src(bun->instructions[j], s) {
 328                         if (bun->instructions[j]->src[s] >= ctx->temp_count)
 329                                 continue;
 330
 331                         for (unsigned q = pivot; q < i; ++q) {
 332                                 if (bun->instructions[q]->dest >= ctx->temp_count)
 333                                         continue;
 334
 335                                 /* See dEQP-GLES2.functional.shaders.return.output_write_in_func_dynamic_fragment */
 336
 337                                 if (q >= j) {
 338                                         if (!(bun->instructions[j]->unit == UNIT_SMUL && bun->instructions[q]->unit == UNIT_VLUT))
 339                                                 continue;
 340                                 }
 341
 342                                 unsigned mask = mir_bytemask(bun->instructions[q]);
 343                                 unsigned rmask = mir_bytemask_of_read_components(bun->instructions[j], bun->instructions[j]->src[s]);
 344                                 lcra_add_node_interference(l, bun->instructions[q]->dest, mask, bun->instructions[j]->src[s], rmask);
 345                         }
 346                 }
 347         }
 348 }
 349
 350 static void
 351 mir_compute_bundle_interference(
 352                 compiler_context *ctx,
 353                 struct lcra_state *l,
 354                 midgard_bundle *bun)
 355 {
 356         if (!IS_ALU(bun->tag))
 357                 return;
 358
 359         bool old = bun->instructions[0]->unit >= UNIT_VADD;
 360         unsigned pivot = 0;
 361
 362         for (unsigned i = 1; i < bun->instruction_count; ++i) {
 363                 bool new = bun->instructions[i]->unit >= UNIT_VADD;
 364
 365                 if (old != new) {
 366                         mir_compute_segment_interference(ctx, l, bun, 0, i);
 367                         pivot = i;
 368                         break;
 369                 }
 370         }
 371
 372         mir_compute_segment_interference(ctx, l, bun, pivot, bun->instruction_count);
 373 }
 374
 375 static void
 376 mir_compute_interference(
 377                 compiler_context *ctx,
 378                 struct lcra_state *l)
 379 {
 380         /* First, we need liveness information to be computed per block */
 381         mir_compute_liveness(ctx);
 382
 383         /* Now that every block has live_in/live_out computed, we can determine
 384          * interference by walking each block linearly. Take live_out at the
 385          * end of each block and walk the block backwards. */
 386
 387         mir_foreach_block(ctx, blk) {
 388                 uint16_t *live = mem_dup(blk->live_out, ctx->temp_count * sizeof(uint16_t));
 389
 390                 mir_foreach_instr_in_block_rev(blk, ins) {
 391                         /* Mark all registers live after the instruction as
 392                          * interfering with the destination */
 393
 394                         unsigned dest = ins->dest;
 395
 396                         if (dest < ctx->temp_count) {
 397                                 for (unsigned i = 0; i < ctx->temp_count; ++i)
 398                                         if (live[i]) {
 399                                                 unsigned mask = mir_bytemask(ins);
 400                                                 lcra_add_node_interference(l, dest, mask, i, live[i]);
 401                                         }
 402                         }
 403
 404                         /* Update live_in */
 405                         mir_liveness_ins_update(live, ins, ctx->temp_count);
 406                 }
 407
 408                 mir_foreach_bundle_in_block(blk, bun)
 409                         mir_compute_bundle_interference(ctx, l, bun);
 410
 411                 free(live);
 412         }
 413 }
 414
 415 /* This routine performs the actual register allocation. It should be succeeded
 416  * by install_registers */
 417
 418 static struct lcra_state *
 419 allocate_registers(compiler_context *ctx, bool *spilled)
 420 {
 421         /* The number of vec4 work registers available depends on when the
 422          * uniforms start, so compute that first */
 423         int work_count = 16 - MAX2((ctx->uniform_cutoff - 8), 0);
 424
 425        /* No register allocation to do with no SSA */
 426
 427         if (!ctx->temp_count)
 428                 return NULL;
 429
 430         struct lcra_state *l = lcra_alloc_equations(ctx->temp_count, 1, 8, 16, 5);
 431
 432         /* Starts of classes, in bytes */
 433         l->class_start[REG_CLASS_WORK]  = 16 * 0;
 434         l->class_start[REG_CLASS_LDST]  = 16 * 26;
 435         l->class_start[REG_CLASS_TEXR]  = 16 * 28;
 436         l->class_start[REG_CLASS_TEXW]  = 16 * 28;
 437
 438         l->class_size[REG_CLASS_WORK] = 16 * work_count;
 439         l->class_size[REG_CLASS_LDST]  = 16 * 2;
 440         l->class_size[REG_CLASS_TEXR]  = 16 * 2;
 441         l->class_size[REG_CLASS_TEXW]  = 16 * 2;
 442
 443         lcra_set_disjoint_class(l, REG_CLASS_TEXR, REG_CLASS_TEXW);
 444
 445         /* To save space on T*20, we don't have real texture registers.
 446          * Instead, tex inputs reuse the load/store pipeline registers, and
 447          * tex outputs use work r0/r1. Note we still use TEXR/TEXW classes,
 448          * noting that this handles interferences and sizes correctly. */
 449
 450         if (ctx->quirks & MIDGARD_INTERPIPE_REG_ALIASING) {
 451                 l->class_start[REG_CLASS_TEXR] = l->class_start[REG_CLASS_LDST];
 452                 l->class_start[REG_CLASS_TEXW] = l->class_start[REG_CLASS_WORK];
 453         }
 454
 455         unsigned *found_class = calloc(sizeof(unsigned), ctx->temp_count);
 456         unsigned *min_alignment = calloc(sizeof(unsigned), ctx->temp_count);
 457
 458         mir_foreach_instr_global(ctx, ins) {
 459                 if (ins->dest >= SSA_FIXED_MINIMUM) continue;
 460
 461                 /* 0 for x, 1 for xy, 2 for xyz, 3 for xyzw */
 462                 int class = util_logbase2(ins->mask);
 463
 464                 /* Use the largest class if there's ambiguity, this
 465                  * handles partial writes */
 466
 467                 int dest = ins->dest;
 468                 found_class[dest] = MAX2(found_class[dest], class);
 469
 470                 /* XXX: Ensure swizzles align the right way with more LCRA constraints? */
 471                 if (ins->type == TAG_ALU_4 && ins->alu.reg_mode != midgard_reg_mode_32)
 472                         min_alignment[dest] = 3; /* (1 << 3) = 8 */
 473
 474                 if (ins->type == TAG_LOAD_STORE_4 && ins->load_64)
 475                         min_alignment[dest] = 3;
 476
 477                 /* We don't have a swizzle for the conditional and we don't
 478                  * want to muck with the conditional itself, so just force
 479                  * alignment for now */
 480
 481                 if (ins->type == TAG_ALU_4 && OP_IS_CSEL_V(ins->alu.op))
 482                         min_alignment[dest] = 4; /* 1 << 4= 16-byte = vec4 */
 483
 484         }
 485
 486         for (unsigned i = 0; i < ctx->temp_count; ++i) {
 487                 lcra_set_alignment(l, i, min_alignment[i] ? min_alignment[i] : 2);
 488                 lcra_restrict_range(l, i, (found_class[i] + 1) * 4);
 489         }
 490
 491         free(found_class);
 492         free(min_alignment);
 493
 494         /* Next, we'll determine semantic class. We default to zero (work).
 495          * But, if we're used with a special operation, that will force us to a
 496          * particular class. Each node must be assigned to exactly one class; a
 497          * prepass before RA should have lowered what-would-have-been
 498          * multiclass nodes into a series of moves to break it up into multiple
 499          * nodes (TODO) */
 500
 501         mir_foreach_instr_global(ctx, ins) {
 502                 /* Check if this operation imposes any classes */
 503
 504                 if (ins->type == TAG_LOAD_STORE_4) {
 505                         set_class(l->class, ins->src[0], REG_CLASS_LDST);
 506                         set_class(l->class, ins->src[1], REG_CLASS_LDST);
 507                         set_class(l->class, ins->src[2], REG_CLASS_LDST);
 508
 509                         if (OP_IS_VEC4_ONLY(ins->load_store.op))
 510                                 lcra_restrict_range(l, ins->dest, 16);
 511                 } else if (ins->type == TAG_TEXTURE_4) {
 512                         set_class(l->class, ins->dest, REG_CLASS_TEXW);
 513                         set_class(l->class, ins->src[0], REG_CLASS_TEXR);
 514                         set_class(l->class, ins->src[1], REG_CLASS_TEXR);
 515                         set_class(l->class, ins->src[2], REG_CLASS_TEXR);
 516                 }
 517         }
 518
 519         /* Check that the semantics of the class are respected */
 520         mir_foreach_instr_global(ctx, ins) {
 521                 assert(check_write_class(l->class, ins->type, ins->dest));
 522                 assert(check_read_class(l->class, ins->type, ins->src[0]));
 523                 assert(check_read_class(l->class, ins->type, ins->src[1]));
 524                 assert(check_read_class(l->class, ins->type, ins->src[2]));
 525         }
 526
 527         /* Mark writeout to r0, render target to r1.z, unknown to r1.w */
 528         mir_foreach_instr_global(ctx, ins) {
 529                 if (!(ins->compact_branch && ins->writeout)) continue;
 530
 531                 if (ins->src[0] < ctx->temp_count)
 532                         l->solutions[ins->src[0]] = 0;
 533
 534                 if (ins->src[1] < ctx->temp_count)
 535                         l->solutions[ins->src[1]] = (16 * 1) + COMPONENT_Z * 4;
 536
 537                 if (ins->src[2] < ctx->temp_count)
 538                         l->solutions[ins->src[2]] = (16 * 1) + COMPONENT_W * 4;
 539         }
 540
 541         mir_compute_interference(ctx, l);
 542
 543         *spilled = !lcra_solve(l);
 544         return l;
 545 }
 546
 547 /* Once registers have been decided via register allocation
 548  * (allocate_registers), we need to rewrite the MIR to use registers instead of
 549  * indices */
 550
 551 static void
 552 install_registers_instr(
 553         compiler_context *ctx,
 554         struct lcra_state *l,
 555         midgard_instruction *ins)
 556 {
 557         switch (ins->type) {
 558         case TAG_ALU_4:
 559         case TAG_ALU_8:
 560         case TAG_ALU_12:
 561         case TAG_ALU_16: {
 562                  if (ins->compact_branch)
 563                          return;
 564
 565                 struct phys_reg src1 = index_to_reg(ctx, l, ins->src[0], mir_srcsize(ins, 0));
 566                 struct phys_reg src2 = index_to_reg(ctx, l, ins->src[1], mir_srcsize(ins, 1));
 567                 struct phys_reg dest = index_to_reg(ctx, l, ins->dest, mir_typesize(ins));
 568
 569                 mir_set_bytemask(ins, mir_bytemask(ins) << dest.offset);
 570
 571                 unsigned dest_offset =
 572                         GET_CHANNEL_COUNT(alu_opcode_props[ins->alu.op].props) ? 0 :
 573                         dest.offset;
 574
 575                 offset_swizzle(ins->swizzle[0], src1.offset, src1.size, dest_offset);
 576
 577                 ins->registers.src1_reg = src1.reg;
 578
 579                 ins->registers.src2_imm = ins->has_inline_constant;
 580
 581                 if (ins->has_inline_constant) {
 582                         /* Encode inline 16-bit constant. See disassembler for
 583                          * where the algorithm is from */
 584
 585                         ins->registers.src2_reg = ins->inline_constant >> 11;
 586
 587                         int lower_11 = ins->inline_constant & ((1 << 12) - 1);
 588                         uint16_t imm = ((lower_11 >> 8) & 0x7) |
 589                                        ((lower_11 & 0xFF) << 3);
 590
 591                         ins->alu.src2 = imm << 2;
 592                 } else {
 593                         midgard_vector_alu_src mod2 =
 594                                 vector_alu_from_unsigned(ins->alu.src2);
 595                         offset_swizzle(ins->swizzle[1], src2.offset, src2.size, dest_offset);
 596                         ins->alu.src2 = vector_alu_srco_unsigned(mod2);
 597
 598                         ins->registers.src2_reg = src2.reg;
 599                 }
 600
 601                 ins->registers.out_reg = dest.reg;
 602                 break;
 603         }
 604
 605         case TAG_LOAD_STORE_4: {
 606                 /* Which physical register we read off depends on
 607                  * whether we are loading or storing -- think about the
 608                  * logical dataflow */
 609
 610                 bool encodes_src = OP_IS_STORE(ins->load_store.op);
 611
 612                 if (encodes_src) {
 613                         struct phys_reg src = index_to_reg(ctx, l, ins->src[0], mir_srcsize(ins, 0));
 614                         assert(src.reg == 26 || src.reg == 27);
 615
 616                         ins->load_store.reg = src.reg - 26;
 617                         offset_swizzle(ins->swizzle[0], src.offset, src.size, 0);
 618                } else {
 619                         struct phys_reg dst = index_to_reg(ctx, l, ins->dest, mir_typesize(ins));
 620
 621                         ins->load_store.reg = dst.reg;
 622                         offset_swizzle(ins->swizzle[0], 0, 4, dst.offset);
 623                         mir_set_bytemask(ins, mir_bytemask(ins) << dst.offset);
 624                 }
 625
 626                 /* We also follow up by actual arguments */
 627
 628                 unsigned src2 = ins->src[1];
 629                 unsigned src3 = ins->src[2];
 630
 631                 if (src2 != ~0) {
 632                         struct phys_reg src = index_to_reg(ctx, l, src2, mir_srcsize(ins, 1));
 633                         unsigned component = src.offset / src.size;
 634                         assert(component * src.size == src.offset);
 635                         ins->load_store.arg_1 |= midgard_ldst_reg(src.reg, component);
 636                 }
 637
 638                 if (src3 != ~0) {
 639                         struct phys_reg src = index_to_reg(ctx, l, src3, mir_srcsize(ins, 2));
 640                         unsigned component = src.offset / src.size;
 641                         assert(component * src.size == src.offset);
 642                         ins->load_store.arg_2 |= midgard_ldst_reg(src.reg, component);
 643                 }
 644
 645                 break;
 646         }
 647
 648         case TAG_TEXTURE_4: {
 649                 /* Grab RA results */
 650                 struct phys_reg dest = index_to_reg(ctx, l, ins->dest, mir_typesize(ins));
 651                 struct phys_reg coord = index_to_reg(ctx, l, ins->src[1], mir_srcsize(ins, 1));
 652                 struct phys_reg lod = index_to_reg(ctx, l, ins->src[2], mir_srcsize(ins, 2));
 653
 654                 /* First, install the texture coordinate */
 655                 ins->texture.in_reg_full = 1;
 656                 ins->texture.in_reg_upper = 0;
 657                 ins->texture.in_reg_select = coord.reg & 1;
 658                 offset_swizzle(ins->swizzle[1], coord.offset, coord.size, 0);
 659
 660                 /* Next, install the destination */
 661                 ins->texture.out_full = 1;
 662                 ins->texture.out_upper = 0;
 663                 ins->texture.out_reg_select = dest.reg & 1;
 664                 offset_swizzle(ins->swizzle[0], 0, 4, dest.offset);
 665                 mir_set_bytemask(ins, mir_bytemask(ins) << dest.offset);
 666
 667                 /* If there is a register LOD/bias, use it */
 668                 if (ins->src[2] != ~0) {
 669                         assert(!(lod.offset & 3));
 670                         midgard_tex_register_select sel = {
 671                                 .select = lod.reg,
 672                                 .full = 1,
 673                                 .component = lod.offset / 4
 674                         };
 675
 676                         uint8_t packed;
 677                         memcpy(&packed, &sel, sizeof(packed));
 678                         ins->texture.bias = packed;
 679                 }
 680
 681                 break;
 682         }
 683
 684         default:
 685                 break;
 686         }
 687 }
 688
 689 static void
 690 install_registers(compiler_context *ctx, struct lcra_state *l)
 691 {
 692         mir_foreach_instr_global(ctx, ins)
 693                 install_registers_instr(ctx, l, ins);
 694 }
 695
 696
 697 /* If register allocation fails, find the best spill node */
 698
 699 static signed
 700 mir_choose_spill_node(
 701                 compiler_context *ctx,
 702                 struct lcra_state *l)
 703 {
 704         /* We can't spill a previously spilled value or an unspill */
 705
 706         mir_foreach_instr_global(ctx, ins) {
 707                 if (ins->no_spill & (1 << l->spill_class)) {
 708                         lcra_set_node_spill_cost(l, ins->dest, -1);
 709
 710                         if (l->spill_class != REG_CLASS_WORK) {
 711                                 mir_foreach_src(ins, s)
 712                                         lcra_set_node_spill_cost(l, ins->src[s], -1);
 713                         }
 714                 }
 715         }
 716
 717         return lcra_get_best_spill_node(l);
 718 }
 719
 720 /* Once we've chosen a spill node, spill it */
 721
 722 static void
 723 mir_spill_register(
 724                 compiler_context *ctx,
 725                 unsigned spill_node,
 726                 unsigned spill_class,
 727                 unsigned *spill_count)
 728 {
 729         unsigned spill_index = ctx->temp_count;
 730
 731         /* We have a spill node, so check the class. Work registers
 732          * legitimately spill to TLS, but special registers just spill to work
 733          * registers */
 734
 735         bool is_special = spill_class != REG_CLASS_WORK;
 736         bool is_special_w = spill_class == REG_CLASS_TEXW;
 737
 738         /* Allocate TLS slot (maybe) */
 739         unsigned spill_slot = !is_special ? (*spill_count)++ : 0;
 740
 741         /* For TLS, replace all stores to the spilled node. For
 742          * special reads, just keep as-is; the class will be demoted
 743          * implicitly. For special writes, spill to a work register */
 744
 745         if (!is_special || is_special_w) {
 746                 if (is_special_w)
 747                         spill_slot = spill_index++;
 748
 749                 mir_foreach_block(ctx, block) {
 750                 mir_foreach_instr_in_block_safe(block, ins) {
 751                         if (ins->dest != spill_node) continue;
 752
 753                         midgard_instruction st;
 754
 755                         if (is_special_w) {
 756                                 st = v_mov(spill_node, spill_slot);
 757                                 st.no_spill |= (1 << spill_class);
 758                         } else {
 759                                 ins->dest = spill_index++;
 760                                 ins->no_spill |= (1 << spill_class);
 761                                 st = v_load_store_scratch(ins->dest, spill_slot, true, ins->mask);
 762                         }
 763
 764                         /* Hint: don't rewrite this node */
 765                         st.hint = true;
 766
 767                         mir_insert_instruction_after_scheduled(ctx, block, ins, st);
 768
 769                         if (!is_special)
 770                                 ctx->spills++;
 771                 }
 772                 }
 773         }
 774
 775         /* For special reads, figure out how many bytes we need */
 776         unsigned read_bytemask = 0;
 777
 778         mir_foreach_instr_global_safe(ctx, ins) {
 779                 read_bytemask |= mir_bytemask_of_read_components(ins, spill_node);
 780         }
 781
 782         /* Insert a load from TLS before the first consecutive
 783          * use of the node, rewriting to use spilled indices to
 784          * break up the live range. Or, for special, insert a
 785          * move. Ironically the latter *increases* register
 786          * pressure, but the two uses of the spilling mechanism
 787          * are somewhat orthogonal. (special spilling is to use
 788          * work registers to back special registers; TLS
 789          * spilling is to use memory to back work registers) */
 790
 791         mir_foreach_block(ctx, block) {
 792                 mir_foreach_instr_in_block(block, ins) {
 793                         /* We can't rewrite the moves used to spill in the
 794                          * first place. These moves are hinted. */
 795                         if (ins->hint) continue;
 796
 797                         /* If we don't use the spilled value, nothing to do */
 798                         if (!mir_has_arg(ins, spill_node)) continue;
 799
 800                         unsigned index = 0;
 801
 802                         if (!is_special_w) {
 803                                 index = ++spill_index;
 804
 805                                 midgard_instruction *before = ins;
 806                                 midgard_instruction st;
 807
 808                                 if (is_special) {
 809                                         /* Move */
 810                                         st = v_mov(spill_node, index);
 811                                         st.no_spill |= (1 << spill_class);
 812                                 } else {
 813                                         /* TLS load */
 814                                         st = v_load_store_scratch(index, spill_slot, false, 0xF);
 815                                 }
 816
 817                                 /* Mask the load based on the component count
 818                                  * actually needed to prevent RA loops */
 819
 820                                 st.mask = mir_from_bytemask(read_bytemask, midgard_reg_mode_32);
 821
 822                                 mir_insert_instruction_before_scheduled(ctx, block, before, st);
 823                         } else {
 824                                 /* Special writes already have their move spilled in */
 825                                 index = spill_slot;
 826                         }
 827
 828
 829                         /* Rewrite to use */
 830                         mir_rewrite_index_src_single(ins, spill_node, index);
 831
 832                         if (!is_special)
 833                                 ctx->fills++;
 834                 }
 835         }
 836
 837         /* Reset hints */
 838
 839         mir_foreach_instr_global(ctx, ins) {
 840                 ins->hint = false;
 841         }
 842 }
 843
 844 /* Run register allocation in a loop, spilling until we succeed */
 845
 846 void
 847 mir_ra(compiler_context *ctx)
 848 {
 849         struct lcra_state *l = NULL;
 850         bool spilled = false;
 851         int iter_count = 1000; /* max iterations */
 852
 853         /* Number of 128-bit slots in memory we've spilled into */
 854         unsigned spill_count = 0;
 855
 856
 857         mir_create_pipeline_registers(ctx);
 858
 859         do {
 860                 if (spilled) {
 861                         signed spill_node = mir_choose_spill_node(ctx, l);
 862
 863                         if (spill_node == -1) {
 864                                 fprintf(stderr, "ERROR: Failed to choose spill node\n");
 865                                 return;
 866                         }
 867
 868                         mir_spill_register(ctx, spill_node, l->spill_class, &spill_count);
 869                 }
 870
 871                 mir_squeeze_index(ctx);
 872                 mir_invalidate_liveness(ctx);
 873
 874                 if (l) {
 875                         lcra_free(l);
 876                         l = NULL;
 877                 }
 878
 879                 l = allocate_registers(ctx, &spilled);
 880         } while(spilled && ((iter_count--) > 0));
 881
 882         if (iter_count <= 0) {
 883                 fprintf(stderr, "panfrost: Gave up allocating registers, rendering will be incomplete\n");
 884                 assert(0);
 885         }
 886
 887         /* Report spilling information. spill_count is in 128-bit slots (vec4 x
 888          * fp32), but tls_size is in bytes, so multiply by 16 */
 889
 890         ctx->tls_size = spill_count * 16;
 891
 892         install_registers(ctx, l);
 893
 894         lcra_free(l);
 895 }