src/util/u_cpu_detect.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2008 Dennis Smit
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * on the rights to use, copy, modify, merge, publish, distribute, sub
  10  * license, and/or sell copies of the Software, and to permit persons to whom
  11  * the Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
  20  * AUTHORS, COPYRIGHT HOLDERS, AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  21  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  22  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  **************************************************************************/
  26
  27 /**
  28  * @file
  29  * CPU feature detection.
  30  *
  31  * @author Dennis Smit
  32  * @author Based on the work of Eric Anholt <anholt@FreeBSD.org>
  33  */
  34
  35 #include "pipe/p_config.h"
  36
  37 #include "util/u_debug.h"
  38 #include "u_cpu_detect.h"
  39 #include "c11/threads.h"
  40
  41 #if defined(PIPE_ARCH_PPC)
  42 #if defined(PIPE_OS_APPLE)
  43 #include <sys/sysctl.h>
  44 #else
  45 #include <signal.h>
  46 #include <setjmp.h>
  47 #endif
  48 #endif
  49
  50 #if defined(PIPE_OS_NETBSD) || defined(PIPE_OS_OPENBSD)
  51 #include <sys/param.h>
  52 #include <sys/sysctl.h>
  53 #include <machine/cpu.h>
  54 #endif
  55
  56 #if defined(PIPE_OS_FREEBSD) || defined(PIPE_OS_DRAGONFLY)
  57 #include <sys/types.h>
  58 #include <sys/sysctl.h>
  59 #endif
  60
  61 #if defined(PIPE_OS_LINUX)
  62 #include <signal.h>
  63 #include <fcntl.h>
  64 #include <elf.h>
  65 #endif
  66
  67 #ifdef PIPE_OS_UNIX
  68 #include <unistd.h>
  69 #endif
  70
  71 #if defined(HAS_ANDROID_CPUFEATURES)
  72 #include <cpu-features.h>
  73 #endif
  74
  75 #if defined(PIPE_OS_WINDOWS)
  76 #include <windows.h>
  77 #if defined(PIPE_CC_MSVC)
  78 #include <intrin.h>
  79 #endif
  80 #endif
  81
  82
  83 #ifdef DEBUG
  84 DEBUG_GET_ONCE_BOOL_OPTION(dump_cpu, "GALLIUM_DUMP_CPU", FALSE)
  85 #endif
  86
  87
  88 struct util_cpu_caps util_cpu_caps;
  89
  90 #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
  91 static int has_cpuid(void);
  92 #endif
  93
  94
  95 #if defined(PIPE_ARCH_PPC) && !defined(PIPE_OS_APPLE) && !defined(PIPE_OS_LINUX)
  96 static jmp_buf  __lv_powerpc_jmpbuf;
  97 static volatile sig_atomic_t __lv_powerpc_canjump = 0;
  98
  99 static void
 100 sigill_handler(int sig)
 101 {
 102    if (!__lv_powerpc_canjump) {
 103       signal (sig, SIG_DFL);
 104       raise (sig);
 105    }
 106
 107    __lv_powerpc_canjump = 0;
 108    longjmp(__lv_powerpc_jmpbuf, 1);
 109 }
 110 #endif
 111
 112 #if defined(PIPE_ARCH_PPC)
 113 static void
 114 check_os_altivec_support(void)
 115 {
 116 #if defined(PIPE_OS_APPLE)
 117    int sels[2] = {CTL_HW, HW_VECTORUNIT};
 118    int has_vu = 0;
 119    int len = sizeof (has_vu);
 120    int err;
 121
 122    err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 123
 124    if (err == 0) {
 125       if (has_vu != 0) {
 126          util_cpu_caps.has_altivec = 1;
 127       }
 128    }
 129 #elif defined(PIPE_OS_LINUX) /* !PIPE_OS_APPLE */
 130 #if defined(PIPE_ARCH_PPC_64)
 131     Elf64_auxv_t aux;
 132 #else
 133     Elf32_auxv_t aux;
 134 #endif
 135     int fd = open("/proc/self/auxv", O_RDONLY | O_CLOEXEC);
 136     if (fd >= 0) {
 137        while (read(fd, &aux, sizeof(aux)) == sizeof(aux)) {
 138           if (aux.a_type == AT_HWCAP) {
 139              char *env_vsx = getenv("GALLIVM_VSX");
 140              uint64_t hwcap = aux.a_un.a_val;
 141              util_cpu_caps.has_altivec = (hwcap >> 28) & 1;
 142              if (!env_vsx || env_vsx[0] != '0') {
 143                 util_cpu_caps.has_vsx  = (hwcap >>  7) & 1;
 144              }
 145              break;
 146           }
 147        }
 148        close(fd);
 149     }
 150 #else /* !PIPE_OS_APPLE && !PIPE_OS_LINUX */
 151    /* not on Apple/Darwin or Linux, do it the brute-force way */
 152    /* this is borrowed from the libmpeg2 library */
 153    signal(SIGILL, sigill_handler);
 154    if (setjmp(__lv_powerpc_jmpbuf)) {
 155       signal(SIGILL, SIG_DFL);
 156    } else {
 157       boolean enable_altivec = TRUE;    /* Default: enable  if available, and if not overridden */
 158       boolean enable_vsx = TRUE;
 159 #ifdef DEBUG
 160       /* Disabling Altivec code generation is not the same as disabling VSX code generation,
 161        * which can be done simply by passing -mattr=-vsx to the LLVM compiler; cf.
 162        * lp_build_create_jit_compiler_for_module().
 163        * If you want to disable Altivec code generation, the best place to do it is here.
 164        */
 165       char *env_control = getenv("GALLIVM_ALTIVEC");    /* 1=enable (default); 0=disable */
 166       if (env_control && env_control[0] == '0') {
 167          enable_altivec = FALSE;
 168       }
 169 #endif
 170       /* VSX instructions can be explicitly enabled/disabled via GALLIVM_VSX=1 or 0 */
 171       char *env_vsx = getenv("GALLIVM_VSX");
 172       if (env_vsx && env_vsx[0] == '0') {
 173          enable_vsx = FALSE;
 174       }
 175       if (enable_altivec) {
 176          __lv_powerpc_canjump = 1;
 177
 178          __asm __volatile
 179             ("mtspr 256, %0\n\t"
 180              "vand %%v0, %%v0, %%v0"
 181              :
 182              : "r" (-1));
 183
 184          util_cpu_caps.has_altivec = 1;
 185
 186          if (enable_vsx) {
 187             __asm __volatile("xxland %vs0, %vs0, %vs0");
 188             util_cpu_caps.has_vsx = 1;
 189          }
 190          signal(SIGILL, SIG_DFL);
 191       } else {
 192          util_cpu_caps.has_altivec = 0;
 193       }
 194    }
 195 #endif /* !PIPE_OS_APPLE && !PIPE_OS_LINUX */
 196 }
 197 #endif /* PIPE_ARCH_PPC */
 198
 199
 200 #if defined(PIPE_ARCH_X86) || defined (PIPE_ARCH_X86_64)
 201 static int has_cpuid(void)
 202 {
 203 #if defined(PIPE_ARCH_X86)
 204 #if defined(PIPE_OS_GCC)
 205    int a, c;
 206
 207    __asm __volatile
 208       ("pushf\n"
 209        "popl %0\n"
 210        "movl %0, %1\n"
 211        "xorl $0x200000, %0\n"
 212        "push %0\n"
 213        "popf\n"
 214        "pushf\n"
 215        "popl %0\n"
 216        : "=a" (a), "=c" (c)
 217        :
 218        : "cc");
 219
 220    return a != c;
 221 #else
 222    /* FIXME */
 223    return 1;
 224 #endif
 225 #elif defined(PIPE_ARCH_X86_64)
 226    return 1;
 227 #else
 228    return 0;
 229 #endif
 230 }
 231
 232
 233 /**
 234  * @sa cpuid.h included in gcc-4.3 onwards.
 235  * @sa http://msdn.microsoft.com/en-us/library/hskdteyh.aspx
 236  */
 237 static inline void
 238 cpuid(uint32_t ax, uint32_t *p)
 239 {
 240 #if defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86)
 241    __asm __volatile (
 242      "xchgl %%ebx, %1\n\t"
 243      "cpuid\n\t"
 244      "xchgl %%ebx, %1"
 245      : "=a" (p[0]),
 246        "=S" (p[1]),
 247        "=c" (p[2]),
 248        "=d" (p[3])
 249      : "0" (ax)
 250    );
 251 #elif defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86_64)
 252    __asm __volatile (
 253      "cpuid\n\t"
 254      : "=a" (p[0]),
 255        "=b" (p[1]),
 256        "=c" (p[2]),
 257        "=d" (p[3])
 258      : "0" (ax)
 259    );
 260 #elif defined(PIPE_CC_MSVC)
 261    __cpuid(p, ax);
 262 #else
 263    p[0] = 0;
 264    p[1] = 0;
 265    p[2] = 0;
 266    p[3] = 0;
 267 #endif
 268 }
 269
 270 /**
 271  * @sa cpuid.h included in gcc-4.4 onwards.
 272  * @sa http://msdn.microsoft.com/en-us/library/hskdteyh%28v=vs.90%29.aspx
 273  */
 274 static inline void
 275 cpuid_count(uint32_t ax, uint32_t cx, uint32_t *p)
 276 {
 277 #if defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86)
 278    __asm __volatile (
 279      "xchgl %%ebx, %1\n\t"
 280      "cpuid\n\t"
 281      "xchgl %%ebx, %1"
 282      : "=a" (p[0]),
 283        "=S" (p[1]),
 284        "=c" (p[2]),
 285        "=d" (p[3])
 286      : "0" (ax), "2" (cx)
 287    );
 288 #elif defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86_64)
 289    __asm __volatile (
 290      "cpuid\n\t"
 291      : "=a" (p[0]),
 292        "=b" (p[1]),
 293        "=c" (p[2]),
 294        "=d" (p[3])
 295      : "0" (ax), "2" (cx)
 296    );
 297 #elif defined(PIPE_CC_MSVC)
 298    __cpuidex(p, ax, cx);
 299 #else
 300    p[0] = 0;
 301    p[1] = 0;
 302    p[2] = 0;
 303    p[3] = 0;
 304 #endif
 305 }
 306
 307
 308 static inline uint64_t xgetbv(void)
 309 {
 310 #if defined(PIPE_CC_GCC)
 311    uint32_t eax, edx;
 312
 313    __asm __volatile (
 314      ".byte 0x0f, 0x01, 0xd0" // xgetbv isn't supported on gcc < 4.4
 315      : "=a"(eax),
 316        "=d"(edx)
 317      : "c"(0)
 318    );
 319
 320    return ((uint64_t)edx << 32) | eax;
 321 #elif defined(PIPE_CC_MSVC) && defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
 322    return _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
 323 #else
 324    return 0;
 325 #endif
 326 }
 327
 328
 329 #if defined(PIPE_ARCH_X86)
 330 PIPE_ALIGN_STACK static inline boolean sse2_has_daz(void)
 331 {
 332    struct {
 333       uint32_t pad1[7];
 334       uint32_t mxcsr_mask;
 335       uint32_t pad2[128-8];
 336    } PIPE_ALIGN_VAR(16) fxarea;
 337
 338    fxarea.mxcsr_mask = 0;
 339 #if defined(PIPE_CC_GCC)
 340    __asm __volatile ("fxsave %0" : "+m" (fxarea));
 341 #elif defined(PIPE_CC_MSVC) || defined(PIPE_CC_ICL)
 342    _fxsave(&fxarea);
 343 #else
 344    fxarea.mxcsr_mask = 0;
 345 #endif
 346    return !!(fxarea.mxcsr_mask & (1 << 6));
 347 }
 348 #endif
 349
 350 #endif /* X86 or X86_64 */
 351
 352 #if defined(PIPE_ARCH_ARM)
 353 static void
 354 check_os_arm_support(void)
 355 {
 356    /*
 357     * On Android, the cpufeatures library is preferred way of checking
 358     * CPU capabilities. However, it is not available for standalone Mesa
 359     * builds, i.e. when Android build system (Android.mk-based) is not
 360     * used. Because of this we cannot use PIPE_OS_ANDROID here, but rather
 361     * have a separate macro that only gets enabled from respective Android.mk.
 362     */
 363 #if defined(__ARM_NEON) || defined(__ARM_NEON__)
 364    util_cpu_caps.has_neon = 1;
 365 #elif defined(HAS_ANDROID_CPUFEATURES)
 366    AndroidCpuFamily cpu_family = android_getCpuFamily();
 367    uint64_t cpu_features = android_getCpuFeatures();
 368
 369    if (cpu_family == ANDROID_CPU_FAMILY_ARM) {
 370       if (cpu_features & ANDROID_CPU_ARM_FEATURE_NEON)
 371          util_cpu_caps.has_neon = 1;
 372    }
 373 #elif defined(PIPE_OS_LINUX)
 374     Elf32_auxv_t aux;
 375     int fd;
 376
 377     fd = open("/proc/self/auxv", O_RDONLY | O_CLOEXEC);
 378     if (fd >= 0) {
 379        while (read(fd, &aux, sizeof(Elf32_auxv_t)) == sizeof(Elf32_auxv_t)) {
 380           if (aux.a_type == AT_HWCAP) {
 381              uint32_t hwcap = aux.a_un.a_val;
 382
 383              util_cpu_caps.has_neon = (hwcap >> 12) & 1;
 384              break;
 385           }
 386        }
 387        close (fd);
 388     }
 389 #endif /* PIPE_OS_LINUX */
 390 }
 391
 392 #elif defined(PIPE_ARCH_AARCH64)
 393 static void
 394 check_os_arm_support(void)
 395 {
 396     util_cpu_caps.has_neon = true;
 397 }
 398 #endif /* PIPE_ARCH_ARM || PIPE_ARCH_AARCH64 */
 399
 400 static void
 401 get_cpu_topology(void)
 402 {
 403    /* Default. This is correct if L3 is not present or there is only one. */
 404    util_cpu_caps.cores_per_L3 = util_cpu_caps.nr_cpus;
 405
 406 #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
 407    /* AMD Zen */
 408    if (util_cpu_caps.x86_cpu_type == 0x17) {
 409       uint32_t regs[4];
 410
 411       /* Query the L3 cache topology information. */
 412       cpuid_count(0x8000001D, 3, regs);
 413       unsigned cache_level = (regs[0] >> 5) & 0x7;
 414       unsigned cores_per_cache = ((regs[0] >> 14) & 0xfff) + 1;
 415
 416       if (cache_level == 3)
 417          util_cpu_caps.cores_per_L3 = cores_per_cache;
 418    }
 419 #endif
 420 }
 421
 422 static void
 423 util_cpu_detect_once(void)
 424 {
 425    memset(&util_cpu_caps, 0, sizeof util_cpu_caps);
 426
 427    /* Count the number of CPUs in system */
 428 #if defined(PIPE_OS_WINDOWS)
 429    {
 430       SYSTEM_INFO system_info;
 431       GetSystemInfo(&system_info);
 432       util_cpu_caps.nr_cpus = system_info.dwNumberOfProcessors;
 433    }
 434 #elif defined(PIPE_OS_UNIX) && defined(_SC_NPROCESSORS_ONLN)
 435    util_cpu_caps.nr_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 436    if (util_cpu_caps.nr_cpus == ~0)
 437       util_cpu_caps.nr_cpus = 1;
 438 #elif defined(PIPE_OS_BSD)
 439    {
 440       int mib[2], ncpu;
 441       int len;
 442
 443       mib[0] = CTL_HW;
 444       mib[1] = HW_NCPU;
 445
 446       len = sizeof (ncpu);
 447       sysctl(mib, 2, &ncpu, &len, NULL, 0);
 448       util_cpu_caps.nr_cpus = ncpu;
 449    }
 450 #else
 451    util_cpu_caps.nr_cpus = 1;
 452 #endif
 453
 454    /* Make the fallback cacheline size nonzero so that it can be
 455     * safely passed to align().
 456     */
 457    util_cpu_caps.cacheline = sizeof(void *);
 458
 459 #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
 460    if (has_cpuid()) {
 461       uint32_t regs[4];
 462       uint32_t regs2[4];
 463
 464       util_cpu_caps.cacheline = 32;
 465
 466       /* Get max cpuid level */
 467       cpuid(0x00000000, regs);
 468
 469       if (regs[0] >= 0x00000001) {
 470          unsigned int cacheline;
 471
 472          cpuid (0x00000001, regs2);
 473
 474          util_cpu_caps.x86_cpu_type = (regs2[0] >> 8) & 0xf;
 475          /* Add "extended family". */
 476          if (util_cpu_caps.x86_cpu_type == 0xf)
 477              util_cpu_caps.x86_cpu_type += ((regs2[0] >> 20) & 0xff);
 478
 479          /* general feature flags */
 480          util_cpu_caps.has_tsc    = (regs2[3] >>  4) & 1; /* 0x0000010 */
 481          util_cpu_caps.has_mmx    = (regs2[3] >> 23) & 1; /* 0x0800000 */
 482          util_cpu_caps.has_sse    = (regs2[3] >> 25) & 1; /* 0x2000000 */
 483          util_cpu_caps.has_sse2   = (regs2[3] >> 26) & 1; /* 0x4000000 */
 484          util_cpu_caps.has_sse3   = (regs2[2] >>  0) & 1; /* 0x0000001 */
 485          util_cpu_caps.has_ssse3  = (regs2[2] >>  9) & 1; /* 0x0000020 */
 486          util_cpu_caps.has_sse4_1 = (regs2[2] >> 19) & 1;
 487          util_cpu_caps.has_sse4_2 = (regs2[2] >> 20) & 1;
 488          util_cpu_caps.has_popcnt = (regs2[2] >> 23) & 1;
 489          util_cpu_caps.has_avx    = ((regs2[2] >> 28) & 1) && // AVX
 490                                     ((regs2[2] >> 27) & 1) && // OSXSAVE
 491                                     ((xgetbv() & 6) == 6);    // XMM & YMM
 492          util_cpu_caps.has_f16c   = ((regs2[2] >> 29) & 1) && util_cpu_caps.has_avx;
 493          util_cpu_caps.has_fma    = ((regs2[2] >> 12) & 1) && util_cpu_caps.has_avx;
 494          util_cpu_caps.has_mmx2   = util_cpu_caps.has_sse; /* SSE cpus supports mmxext too */
 495 #if defined(PIPE_ARCH_X86_64)
 496          util_cpu_caps.has_daz = 1;
 497 #else
 498          util_cpu_caps.has_daz = util_cpu_caps.has_sse3 ||
 499             (util_cpu_caps.has_sse2 && sse2_has_daz());
 500 #endif
 501
 502          cacheline = ((regs2[1] >> 8) & 0xFF) * 8;
 503          if (cacheline > 0)
 504             util_cpu_caps.cacheline = cacheline;
 505       }
 506       if (util_cpu_caps.has_avx && regs[0] >= 0x00000007) {
 507          uint32_t regs7[4];
 508          cpuid_count(0x00000007, 0x00000000, regs7);
 509          util_cpu_caps.has_avx2 = (regs7[1] >> 5) & 1;
 510       }
 511
 512       // check for avx512
 513       if (((regs2[2] >> 27) & 1) && // OSXSAVE
 514           (xgetbv() & (0x7 << 5)) && // OPMASK: upper-256 enabled by OS
 515           ((xgetbv() & 6) == 6)) { // XMM/YMM enabled by OS
 516          uint32_t regs3[4];
 517          cpuid_count(0x00000007, 0x00000000, regs3);
 518          util_cpu_caps.has_avx512f    = (regs3[1] >> 16) & 1;
 519          util_cpu_caps.has_avx512dq   = (regs3[1] >> 17) & 1;
 520          util_cpu_caps.has_avx512ifma = (regs3[1] >> 21) & 1;
 521          util_cpu_caps.has_avx512pf   = (regs3[1] >> 26) & 1;
 522          util_cpu_caps.has_avx512er   = (regs3[1] >> 27) & 1;
 523          util_cpu_caps.has_avx512cd   = (regs3[1] >> 28) & 1;
 524          util_cpu_caps.has_avx512bw   = (regs3[1] >> 30) & 1;
 525          util_cpu_caps.has_avx512vl   = (regs3[1] >> 31) & 1;
 526          util_cpu_caps.has_avx512vbmi = (regs3[2] >>  1) & 1;
 527       }
 528
 529       if (regs[1] == 0x756e6547 && regs[2] == 0x6c65746e && regs[3] == 0x49656e69) {
 530          /* GenuineIntel */
 531          util_cpu_caps.has_intel = 1;
 532       }
 533
 534       cpuid(0x80000000, regs);
 535
 536       if (regs[0] >= 0x80000001) {
 537
 538          cpuid(0x80000001, regs2);
 539
 540          util_cpu_caps.has_mmx  |= (regs2[3] >> 23) & 1;
 541          util_cpu_caps.has_mmx2 |= (regs2[3] >> 22) & 1;
 542          util_cpu_caps.has_3dnow = (regs2[3] >> 31) & 1;
 543          util_cpu_caps.has_3dnow_ext = (regs2[3] >> 30) & 1;
 544
 545          util_cpu_caps.has_xop = util_cpu_caps.has_avx &&
 546                                  ((regs2[2] >> 11) & 1);
 547       }
 548
 549       if (regs[0] >= 0x80000006) {
 550          /* should we really do this if the clflush size above worked? */
 551          unsigned int cacheline;
 552          cpuid(0x80000006, regs2);
 553          cacheline = regs2[2] & 0xFF;
 554          if (cacheline > 0)
 555             util_cpu_caps.cacheline = cacheline;
 556       }
 557
 558       if (!util_cpu_caps.has_sse) {
 559          util_cpu_caps.has_sse2 = 0;
 560          util_cpu_caps.has_sse3 = 0;
 561          util_cpu_caps.has_ssse3 = 0;
 562          util_cpu_caps.has_sse4_1 = 0;
 563       }
 564    }
 565 #endif /* PIPE_ARCH_X86 || PIPE_ARCH_X86_64 */
 566
 567 #if defined(PIPE_ARCH_ARM) || defined(PIPE_ARCH_AARCH64)
 568    check_os_arm_support();
 569 #endif
 570
 571 #if defined(PIPE_ARCH_PPC)
 572    check_os_altivec_support();
 573 #endif /* PIPE_ARCH_PPC */
 574
 575    get_cpu_topology();
 576
 577 #ifdef DEBUG
 578    if (debug_get_option_dump_cpu()) {
 579       debug_printf("util_cpu_caps.nr_cpus = %u\n", util_cpu_caps.nr_cpus);
 580
 581       debug_printf("util_cpu_caps.x86_cpu_type = %u\n", util_cpu_caps.x86_cpu_type);
 582       debug_printf("util_cpu_caps.cacheline = %u\n", util_cpu_caps.cacheline);
 583
 584       debug_printf("util_cpu_caps.has_tsc = %u\n", util_cpu_caps.has_tsc);
 585       debug_printf("util_cpu_caps.has_mmx = %u\n", util_cpu_caps.has_mmx);
 586       debug_printf("util_cpu_caps.has_mmx2 = %u\n", util_cpu_caps.has_mmx2);
 587       debug_printf("util_cpu_caps.has_sse = %u\n", util_cpu_caps.has_sse);
 588       debug_printf("util_cpu_caps.has_sse2 = %u\n", util_cpu_caps.has_sse2);
 589       debug_printf("util_cpu_caps.has_sse3 = %u\n", util_cpu_caps.has_sse3);
 590       debug_printf("util_cpu_caps.has_ssse3 = %u\n", util_cpu_caps.has_ssse3);
 591       debug_printf("util_cpu_caps.has_sse4_1 = %u\n", util_cpu_caps.has_sse4_1);
 592       debug_printf("util_cpu_caps.has_sse4_2 = %u\n", util_cpu_caps.has_sse4_2);
 593       debug_printf("util_cpu_caps.has_avx = %u\n", util_cpu_caps.has_avx);
 594       debug_printf("util_cpu_caps.has_avx2 = %u\n", util_cpu_caps.has_avx2);
 595       debug_printf("util_cpu_caps.has_f16c = %u\n", util_cpu_caps.has_f16c);
 596       debug_printf("util_cpu_caps.has_popcnt = %u\n", util_cpu_caps.has_popcnt);
 597       debug_printf("util_cpu_caps.has_3dnow = %u\n", util_cpu_caps.has_3dnow);
 598       debug_printf("util_cpu_caps.has_3dnow_ext = %u\n", util_cpu_caps.has_3dnow_ext);
 599       debug_printf("util_cpu_caps.has_xop = %u\n", util_cpu_caps.has_xop);
 600       debug_printf("util_cpu_caps.has_altivec = %u\n", util_cpu_caps.has_altivec);
 601       debug_printf("util_cpu_caps.has_vsx = %u\n", util_cpu_caps.has_vsx);
 602       debug_printf("util_cpu_caps.has_neon = %u\n", util_cpu_caps.has_neon);
 603       debug_printf("util_cpu_caps.has_daz = %u\n", util_cpu_caps.has_daz);
 604       debug_printf("util_cpu_caps.has_avx512f = %u\n", util_cpu_caps.has_avx512f);
 605       debug_printf("util_cpu_caps.has_avx512dq = %u\n", util_cpu_caps.has_avx512dq);
 606       debug_printf("util_cpu_caps.has_avx512ifma = %u\n", util_cpu_caps.has_avx512ifma);
 607       debug_printf("util_cpu_caps.has_avx512pf = %u\n", util_cpu_caps.has_avx512pf);
 608       debug_printf("util_cpu_caps.has_avx512er = %u\n", util_cpu_caps.has_avx512er);
 609       debug_printf("util_cpu_caps.has_avx512cd = %u\n", util_cpu_caps.has_avx512cd);
 610       debug_printf("util_cpu_caps.has_avx512bw = %u\n", util_cpu_caps.has_avx512bw);
 611       debug_printf("util_cpu_caps.has_avx512vl = %u\n", util_cpu_caps.has_avx512vl);
 612       debug_printf("util_cpu_caps.has_avx512vbmi = %u\n", util_cpu_caps.has_avx512vbmi);
 613    }
 614 #endif
 615 }
 616
 617 static once_flag cpu_once_flag = ONCE_FLAG_INIT;
 618
 619 void
 620 util_cpu_detect(void)
 621 {
 622    call_once(&cpu_once_flag, util_cpu_detect_once);
 623 }