src/util/u_cpu_detect.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2008 Dennis Smit
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * on the rights to use, copy, modify, merge, publish, distribute, sub
  10  * license, and/or sell copies of the Software, and to permit persons to whom
  11  * the Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
  20  * AUTHORS, COPYRIGHT HOLDERS, AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  21  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  22  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  **************************************************************************/
  26
  27 /**
  28  * @file
  29  * CPU feature detection.
  30  *
  31  * @author Dennis Smit
  32  * @author Based on the work of Eric Anholt <anholt@FreeBSD.org>
  33  */
  34
  35 #include "pipe/p_config.h"
  36
  37 #include "util/u_debug.h"
  38 #include "u_cpu_detect.h"
  39 #include "c11/threads.h"
  40
  41 #if defined(PIPE_ARCH_PPC)
  42 #if defined(PIPE_OS_APPLE)
  43 #include <sys/sysctl.h>
  44 #else
  45 #include <signal.h>
  46 #include <setjmp.h>
  47 #endif
  48 #endif
  49
  50 #if defined(PIPE_OS_BSD)
  51 #include <sys/param.h>
  52 #include <sys/sysctl.h>
  53 #include <machine/cpu.h>
  54 #endif
  55
  56 #if defined(PIPE_OS_FREEBSD)
  57 #if __has_include(<sys/auxv.h>)
  58 #include <sys/auxv.h>
  59 #define HAVE_ELF_AUX_INFO
  60 #endif
  61 #endif
  62
  63 #if defined(PIPE_OS_LINUX)
  64 #include <signal.h>
  65 #include <fcntl.h>
  66 #include <elf.h>
  67 #endif
  68
  69 #ifdef PIPE_OS_UNIX
  70 #include <unistd.h>
  71 #endif
  72
  73 #if defined(HAS_ANDROID_CPUFEATURES)
  74 #include <cpu-features.h>
  75 #endif
  76
  77 #if defined(PIPE_OS_WINDOWS)
  78 #include <windows.h>
  79 #if defined(PIPE_CC_MSVC)
  80 #include <intrin.h>
  81 #endif
  82 #endif
  83
  84
  85 #ifdef DEBUG
  86 DEBUG_GET_ONCE_BOOL_OPTION(dump_cpu, "GALLIUM_DUMP_CPU", FALSE)
  87 #endif
  88
  89
  90 struct util_cpu_caps util_cpu_caps;
  91
  92 #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
  93 static int has_cpuid(void);
  94 #endif
  95
  96
  97 #if defined(PIPE_ARCH_PPC) && !defined(PIPE_OS_APPLE) && !defined(PIPE_OS_BSD) && !defined(PIPE_OS_LINUX)
  98 static jmp_buf  __lv_powerpc_jmpbuf;
  99 static volatile sig_atomic_t __lv_powerpc_canjump = 0;
 100
 101 static void
 102 sigill_handler(int sig)
 103 {
 104    if (!__lv_powerpc_canjump) {
 105       signal (sig, SIG_DFL);
 106       raise (sig);
 107    }
 108
 109    __lv_powerpc_canjump = 0;
 110    longjmp(__lv_powerpc_jmpbuf, 1);
 111 }
 112 #endif
 113
 114 #if defined(PIPE_ARCH_PPC)
 115 static void
 116 check_os_altivec_support(void)
 117 {
 118 #if defined(__ALTIVEC__)
 119    util_cpu_caps.has_altivec = 1;
 120 #endif
 121 #if defined(__VSX__)
 122    util_cpu_caps.has_vsx = 1;
 123 #endif
 124 #if defined(__ALTIVEC__) && defined(__VSX__)
 125 /* Do nothing */
 126 #elif defined(PIPE_OS_APPLE) || defined(PIPE_OS_NETBSD) || defined(PIPE_OS_OPENBSD)
 127 #ifdef HW_VECTORUNIT
 128    int sels[2] = {CTL_HW, HW_VECTORUNIT};
 129 #else
 130    int sels[2] = {CTL_MACHDEP, CPU_ALTIVEC};
 131 #endif
 132    int has_vu = 0;
 133    int len = sizeof (has_vu);
 134    int err;
 135
 136    err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 137
 138    if (err == 0) {
 139       if (has_vu != 0) {
 140          util_cpu_caps.has_altivec = 1;
 141       }
 142    }
 143 #elif defined(PIPE_OS_FREEBSD) /* !PIPE_OS_APPLE && !PIPE_OS_NETBSD && !PIPE_OS_OPENBSD */
 144    unsigned long hwcap = 0;
 145 #ifdef HAVE_ELF_AUX_INFO
 146    elf_aux_info(AT_HWCAP, &hwcap, sizeof(hwcap));
 147 #else
 148    size_t len = sizeof(hwcap);
 149    sysctlbyname("hw.cpu_features", &hwcap, &len, NULL, 0);
 150 #endif
 151    if (hwcap & PPC_FEATURE_HAS_ALTIVEC)
 152       util_cpu_caps.has_altivec = 1;
 153    if (hwcap & PPC_FEATURE_HAS_VSX)
 154       util_cpu_caps.has_vsx = 1;
 155 #elif defined(PIPE_OS_LINUX) /* !PIPE_OS_FREEBSD */
 156 #if defined(PIPE_ARCH_PPC_64)
 157     Elf64_auxv_t aux;
 158 #else
 159     Elf32_auxv_t aux;
 160 #endif
 161     int fd = open("/proc/self/auxv", O_RDONLY | O_CLOEXEC);
 162     if (fd >= 0) {
 163        while (read(fd, &aux, sizeof(aux)) == sizeof(aux)) {
 164           if (aux.a_type == AT_HWCAP) {
 165              char *env_vsx = getenv("GALLIVM_VSX");
 166              uint64_t hwcap = aux.a_un.a_val;
 167              util_cpu_caps.has_altivec = (hwcap >> 28) & 1;
 168              if (!env_vsx || env_vsx[0] != '0') {
 169                 util_cpu_caps.has_vsx  = (hwcap >>  7) & 1;
 170              }
 171              break;
 172           }
 173        }
 174        close(fd);
 175     }
 176 #else /* !PIPE_OS_APPLE && !PIPE_OS_BSD && !PIPE_OS_LINUX */
 177    /* not on Apple/Darwin or Linux, do it the brute-force way */
 178    /* this is borrowed from the libmpeg2 library */
 179    signal(SIGILL, sigill_handler);
 180    if (setjmp(__lv_powerpc_jmpbuf)) {
 181       signal(SIGILL, SIG_DFL);
 182    } else {
 183       boolean enable_altivec = TRUE;    /* Default: enable  if available, and if not overridden */
 184       boolean enable_vsx = TRUE;
 185 #ifdef DEBUG
 186       /* Disabling Altivec code generation is not the same as disabling VSX code generation,
 187        * which can be done simply by passing -mattr=-vsx to the LLVM compiler; cf.
 188        * lp_build_create_jit_compiler_for_module().
 189        * If you want to disable Altivec code generation, the best place to do it is here.
 190        */
 191       char *env_control = getenv("GALLIVM_ALTIVEC");    /* 1=enable (default); 0=disable */
 192       if (env_control && env_control[0] == '0') {
 193          enable_altivec = FALSE;
 194       }
 195 #endif
 196       /* VSX instructions can be explicitly enabled/disabled via GALLIVM_VSX=1 or 0 */
 197       char *env_vsx = getenv("GALLIVM_VSX");
 198       if (env_vsx && env_vsx[0] == '0') {
 199          enable_vsx = FALSE;
 200       }
 201       if (enable_altivec) {
 202          __lv_powerpc_canjump = 1;
 203
 204          __asm __volatile
 205             ("mtspr 256, %0\n\t"
 206              "vand %%v0, %%v0, %%v0"
 207              :
 208              : "r" (-1));
 209
 210          util_cpu_caps.has_altivec = 1;
 211
 212          if (enable_vsx) {
 213             __asm __volatile("xxland %vs0, %vs0, %vs0");
 214             util_cpu_caps.has_vsx = 1;
 215          }
 216          signal(SIGILL, SIG_DFL);
 217       } else {
 218          util_cpu_caps.has_altivec = 0;
 219       }
 220    }
 221 #endif /* !PIPE_OS_APPLE && !PIPE_OS_LINUX */
 222 }
 223 #endif /* PIPE_ARCH_PPC */
 224
 225
 226 #if defined(PIPE_ARCH_X86) || defined (PIPE_ARCH_X86_64)
 227 static int has_cpuid(void)
 228 {
 229 #if defined(PIPE_ARCH_X86)
 230 #if defined(PIPE_OS_GCC)
 231    int a, c;
 232
 233    __asm __volatile
 234       ("pushf\n"
 235        "popl %0\n"
 236        "movl %0, %1\n"
 237        "xorl $0x200000, %0\n"
 238        "push %0\n"
 239        "popf\n"
 240        "pushf\n"
 241        "popl %0\n"
 242        : "=a" (a), "=c" (c)
 243        :
 244        : "cc");
 245
 246    return a != c;
 247 #else
 248    /* FIXME */
 249    return 1;
 250 #endif
 251 #elif defined(PIPE_ARCH_X86_64)
 252    return 1;
 253 #else
 254    return 0;
 255 #endif
 256 }
 257
 258
 259 /**
 260  * @sa cpuid.h included in gcc-4.3 onwards.
 261  * @sa http://msdn.microsoft.com/en-us/library/hskdteyh.aspx
 262  */
 263 static inline void
 264 cpuid(uint32_t ax, uint32_t *p)
 265 {
 266 #if defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86)
 267    __asm __volatile (
 268      "xchgl %%ebx, %1\n\t"
 269      "cpuid\n\t"
 270      "xchgl %%ebx, %1"
 271      : "=a" (p[0]),
 272        "=S" (p[1]),
 273        "=c" (p[2]),
 274        "=d" (p[3])
 275      : "0" (ax)
 276    );
 277 #elif defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86_64)
 278    __asm __volatile (
 279      "cpuid\n\t"
 280      : "=a" (p[0]),
 281        "=b" (p[1]),
 282        "=c" (p[2]),
 283        "=d" (p[3])
 284      : "0" (ax)
 285    );
 286 #elif defined(PIPE_CC_MSVC)
 287    __cpuid(p, ax);
 288 #else
 289    p[0] = 0;
 290    p[1] = 0;
 291    p[2] = 0;
 292    p[3] = 0;
 293 #endif
 294 }
 295
 296 /**
 297  * @sa cpuid.h included in gcc-4.4 onwards.
 298  * @sa http://msdn.microsoft.com/en-us/library/hskdteyh%28v=vs.90%29.aspx
 299  */
 300 static inline void
 301 cpuid_count(uint32_t ax, uint32_t cx, uint32_t *p)
 302 {
 303 #if defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86)
 304    __asm __volatile (
 305      "xchgl %%ebx, %1\n\t"
 306      "cpuid\n\t"
 307      "xchgl %%ebx, %1"
 308      : "=a" (p[0]),
 309        "=S" (p[1]),
 310        "=c" (p[2]),
 311        "=d" (p[3])
 312      : "0" (ax), "2" (cx)
 313    );
 314 #elif defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86_64)
 315    __asm __volatile (
 316      "cpuid\n\t"
 317      : "=a" (p[0]),
 318        "=b" (p[1]),
 319        "=c" (p[2]),
 320        "=d" (p[3])
 321      : "0" (ax), "2" (cx)
 322    );
 323 #elif defined(PIPE_CC_MSVC)
 324    __cpuidex(p, ax, cx);
 325 #else
 326    p[0] = 0;
 327    p[1] = 0;
 328    p[2] = 0;
 329    p[3] = 0;
 330 #endif
 331 }
 332
 333
 334 static inline uint64_t xgetbv(void)
 335 {
 336 #if defined(PIPE_CC_GCC)
 337    uint32_t eax, edx;
 338
 339    __asm __volatile (
 340      ".byte 0x0f, 0x01, 0xd0" // xgetbv isn't supported on gcc < 4.4
 341      : "=a"(eax),
 342        "=d"(edx)
 343      : "c"(0)
 344    );
 345
 346    return ((uint64_t)edx << 32) | eax;
 347 #elif defined(PIPE_CC_MSVC) && defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
 348    return _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
 349 #else
 350    return 0;
 351 #endif
 352 }
 353
 354
 355 #if defined(PIPE_ARCH_X86)
 356 PIPE_ALIGN_STACK static inline boolean sse2_has_daz(void)
 357 {
 358    struct {
 359       uint32_t pad1[7];
 360       uint32_t mxcsr_mask;
 361       uint32_t pad2[128-8];
 362    } PIPE_ALIGN_VAR(16) fxarea;
 363
 364    fxarea.mxcsr_mask = 0;
 365 #if defined(PIPE_CC_GCC)
 366    __asm __volatile ("fxsave %0" : "+m" (fxarea));
 367 #elif defined(PIPE_CC_MSVC) || defined(PIPE_CC_ICL)
 368    _fxsave(&fxarea);
 369 #else
 370    fxarea.mxcsr_mask = 0;
 371 #endif
 372    return !!(fxarea.mxcsr_mask & (1 << 6));
 373 }
 374 #endif
 375
 376 #endif /* X86 or X86_64 */
 377
 378 #if defined(PIPE_ARCH_ARM)
 379 static void
 380 check_os_arm_support(void)
 381 {
 382    /*
 383     * On Android, the cpufeatures library is preferred way of checking
 384     * CPU capabilities. However, it is not available for standalone Mesa
 385     * builds, i.e. when Android build system (Android.mk-based) is not
 386     * used. Because of this we cannot use PIPE_OS_ANDROID here, but rather
 387     * have a separate macro that only gets enabled from respective Android.mk.
 388     */
 389 #if defined(__ARM_NEON) || defined(__ARM_NEON__)
 390    util_cpu_caps.has_neon = 1;
 391 #elif defined(PIPE_OS_FREEBSD) && defined(HAVE_ELF_AUX_INFO)
 392    unsigned long hwcap = 0;
 393    elf_aux_info(AT_HWCAP, &hwcap, sizeof(hwcap));
 394    if (hwcap & HWCAP_NEON)
 395       util_cpu_caps.has_neon = 1;
 396 #elif defined(HAS_ANDROID_CPUFEATURES)
 397    AndroidCpuFamily cpu_family = android_getCpuFamily();
 398    uint64_t cpu_features = android_getCpuFeatures();
 399
 400    if (cpu_family == ANDROID_CPU_FAMILY_ARM) {
 401       if (cpu_features & ANDROID_CPU_ARM_FEATURE_NEON)
 402          util_cpu_caps.has_neon = 1;
 403    }
 404 #elif defined(PIPE_OS_LINUX)
 405     Elf32_auxv_t aux;
 406     int fd;
 407
 408     fd = open("/proc/self/auxv", O_RDONLY | O_CLOEXEC);
 409     if (fd >= 0) {
 410        while (read(fd, &aux, sizeof(Elf32_auxv_t)) == sizeof(Elf32_auxv_t)) {
 411           if (aux.a_type == AT_HWCAP) {
 412              uint32_t hwcap = aux.a_un.a_val;
 413
 414              util_cpu_caps.has_neon = (hwcap >> 12) & 1;
 415              break;
 416           }
 417        }
 418        close (fd);
 419     }
 420 #endif /* PIPE_OS_LINUX */
 421 }
 422
 423 #elif defined(PIPE_ARCH_AARCH64)
 424 static void
 425 check_os_arm_support(void)
 426 {
 427     util_cpu_caps.has_neon = true;
 428 }
 429 #endif /* PIPE_ARCH_ARM || PIPE_ARCH_AARCH64 */
 430
 431 static void
 432 get_cpu_topology(void)
 433 {
 434    /* Default. This is correct if L3 is not present or there is only one. */
 435    util_cpu_caps.cores_per_L3 = util_cpu_caps.nr_cpus;
 436
 437 #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
 438    /* AMD Zen */
 439    if (util_cpu_caps.x86_cpu_type == 0x17) {
 440       uint32_t regs[4];
 441
 442       /* Query the L3 cache topology information. */
 443       cpuid_count(0x8000001D, 3, regs);
 444       unsigned cache_level = (regs[0] >> 5) & 0x7;
 445       unsigned cores_per_cache = ((regs[0] >> 14) & 0xfff) + 1;
 446
 447       if (cache_level == 3)
 448          util_cpu_caps.cores_per_L3 = cores_per_cache;
 449    }
 450 #endif
 451 }
 452
 453 static void
 454 util_cpu_detect_once(void)
 455 {
 456    memset(&util_cpu_caps, 0, sizeof util_cpu_caps);
 457
 458    /* Count the number of CPUs in system */
 459 #if defined(PIPE_OS_WINDOWS)
 460    {
 461       SYSTEM_INFO system_info;
 462       GetSystemInfo(&system_info);
 463       util_cpu_caps.nr_cpus = system_info.dwNumberOfProcessors;
 464    }
 465 #elif defined(PIPE_OS_UNIX) && defined(_SC_NPROCESSORS_ONLN)
 466    util_cpu_caps.nr_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 467    if (util_cpu_caps.nr_cpus == ~0)
 468       util_cpu_caps.nr_cpus = 1;
 469 #elif defined(PIPE_OS_BSD)
 470    {
 471       int mib[2], ncpu;
 472       int len;
 473
 474       mib[0] = CTL_HW;
 475       mib[1] = HW_NCPU;
 476
 477       len = sizeof (ncpu);
 478       sysctl(mib, 2, &ncpu, &len, NULL, 0);
 479       util_cpu_caps.nr_cpus = ncpu;
 480    }
 481 #else
 482    util_cpu_caps.nr_cpus = 1;
 483 #endif
 484
 485    /* Make the fallback cacheline size nonzero so that it can be
 486     * safely passed to align().
 487     */
 488    util_cpu_caps.cacheline = sizeof(void *);
 489
 490 #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
 491    if (has_cpuid()) {
 492       uint32_t regs[4];
 493       uint32_t regs2[4];
 494
 495       util_cpu_caps.cacheline = 32;
 496
 497       /* Get max cpuid level */
 498       cpuid(0x00000000, regs);
 499
 500       if (regs[0] >= 0x00000001) {
 501          unsigned int cacheline;
 502
 503          cpuid (0x00000001, regs2);
 504
 505          util_cpu_caps.x86_cpu_type = (regs2[0] >> 8) & 0xf;
 506          /* Add "extended family". */
 507          if (util_cpu_caps.x86_cpu_type == 0xf)
 508              util_cpu_caps.x86_cpu_type += ((regs2[0] >> 20) & 0xff);
 509
 510          /* general feature flags */
 511          util_cpu_caps.has_tsc    = (regs2[3] >>  4) & 1; /* 0x0000010 */
 512          util_cpu_caps.has_mmx    = (regs2[3] >> 23) & 1; /* 0x0800000 */
 513          util_cpu_caps.has_sse    = (regs2[3] >> 25) & 1; /* 0x2000000 */
 514          util_cpu_caps.has_sse2   = (regs2[3] >> 26) & 1; /* 0x4000000 */
 515          util_cpu_caps.has_sse3   = (regs2[2] >>  0) & 1; /* 0x0000001 */
 516          util_cpu_caps.has_ssse3  = (regs2[2] >>  9) & 1; /* 0x0000020 */
 517          util_cpu_caps.has_sse4_1 = (regs2[2] >> 19) & 1;
 518          util_cpu_caps.has_sse4_2 = (regs2[2] >> 20) & 1;
 519          util_cpu_caps.has_popcnt = (regs2[2] >> 23) & 1;
 520          util_cpu_caps.has_avx    = ((regs2[2] >> 28) & 1) && // AVX
 521                                     ((regs2[2] >> 27) & 1) && // OSXSAVE
 522                                     ((xgetbv() & 6) == 6);    // XMM & YMM
 523          util_cpu_caps.has_f16c   = ((regs2[2] >> 29) & 1) && util_cpu_caps.has_avx;
 524          util_cpu_caps.has_fma    = ((regs2[2] >> 12) & 1) && util_cpu_caps.has_avx;
 525          util_cpu_caps.has_mmx2   = util_cpu_caps.has_sse; /* SSE cpus supports mmxext too */
 526 #if defined(PIPE_ARCH_X86_64)
 527          util_cpu_caps.has_daz = 1;
 528 #else
 529          util_cpu_caps.has_daz = util_cpu_caps.has_sse3 ||
 530             (util_cpu_caps.has_sse2 && sse2_has_daz());
 531 #endif
 532
 533          cacheline = ((regs2[1] >> 8) & 0xFF) * 8;
 534          if (cacheline > 0)
 535             util_cpu_caps.cacheline = cacheline;
 536       }
 537       if (util_cpu_caps.has_avx && regs[0] >= 0x00000007) {
 538          uint32_t regs7[4];
 539          cpuid_count(0x00000007, 0x00000000, regs7);
 540          util_cpu_caps.has_avx2 = (regs7[1] >> 5) & 1;
 541       }
 542
 543       // check for avx512
 544       if (((regs2[2] >> 27) & 1) && // OSXSAVE
 545           (xgetbv() & (0x7 << 5)) && // OPMASK: upper-256 enabled by OS
 546           ((xgetbv() & 6) == 6)) { // XMM/YMM enabled by OS
 547          uint32_t regs3[4];
 548          cpuid_count(0x00000007, 0x00000000, regs3);
 549          util_cpu_caps.has_avx512f    = (regs3[1] >> 16) & 1;
 550          util_cpu_caps.has_avx512dq   = (regs3[1] >> 17) & 1;
 551          util_cpu_caps.has_avx512ifma = (regs3[1] >> 21) & 1;
 552          util_cpu_caps.has_avx512pf   = (regs3[1] >> 26) & 1;
 553          util_cpu_caps.has_avx512er   = (regs3[1] >> 27) & 1;
 554          util_cpu_caps.has_avx512cd   = (regs3[1] >> 28) & 1;
 555          util_cpu_caps.has_avx512bw   = (regs3[1] >> 30) & 1;
 556          util_cpu_caps.has_avx512vl   = (regs3[1] >> 31) & 1;
 557          util_cpu_caps.has_avx512vbmi = (regs3[2] >>  1) & 1;
 558       }
 559
 560       if (regs[1] == 0x756e6547 && regs[2] == 0x6c65746e && regs[3] == 0x49656e69) {
 561          /* GenuineIntel */
 562          util_cpu_caps.has_intel = 1;
 563       }
 564
 565       cpuid(0x80000000, regs);
 566
 567       if (regs[0] >= 0x80000001) {
 568
 569          cpuid(0x80000001, regs2);
 570
 571          util_cpu_caps.has_mmx  |= (regs2[3] >> 23) & 1;
 572          util_cpu_caps.has_mmx2 |= (regs2[3] >> 22) & 1;
 573          util_cpu_caps.has_3dnow = (regs2[3] >> 31) & 1;
 574          util_cpu_caps.has_3dnow_ext = (regs2[3] >> 30) & 1;
 575
 576          util_cpu_caps.has_xop = util_cpu_caps.has_avx &&
 577                                  ((regs2[2] >> 11) & 1);
 578       }
 579
 580       if (regs[0] >= 0x80000006) {
 581          /* should we really do this if the clflush size above worked? */
 582          unsigned int cacheline;
 583          cpuid(0x80000006, regs2);
 584          cacheline = regs2[2] & 0xFF;
 585          if (cacheline > 0)
 586             util_cpu_caps.cacheline = cacheline;
 587       }
 588
 589       if (!util_cpu_caps.has_sse) {
 590          util_cpu_caps.has_sse2 = 0;
 591          util_cpu_caps.has_sse3 = 0;
 592          util_cpu_caps.has_ssse3 = 0;
 593          util_cpu_caps.has_sse4_1 = 0;
 594       }
 595    }
 596 #endif /* PIPE_ARCH_X86 || PIPE_ARCH_X86_64 */
 597
 598 #if defined(PIPE_ARCH_ARM) || defined(PIPE_ARCH_AARCH64)
 599    check_os_arm_support();
 600 #endif
 601
 602 #if defined(PIPE_ARCH_PPC)
 603    check_os_altivec_support();
 604 #endif /* PIPE_ARCH_PPC */
 605
 606    get_cpu_topology();
 607
 608 #ifdef DEBUG
 609    if (debug_get_option_dump_cpu()) {
 610       debug_printf("util_cpu_caps.nr_cpus = %u\n", util_cpu_caps.nr_cpus);
 611
 612       debug_printf("util_cpu_caps.x86_cpu_type = %u\n", util_cpu_caps.x86_cpu_type);
 613       debug_printf("util_cpu_caps.cacheline = %u\n", util_cpu_caps.cacheline);
 614
 615       debug_printf("util_cpu_caps.has_tsc = %u\n", util_cpu_caps.has_tsc);
 616       debug_printf("util_cpu_caps.has_mmx = %u\n", util_cpu_caps.has_mmx);
 617       debug_printf("util_cpu_caps.has_mmx2 = %u\n", util_cpu_caps.has_mmx2);
 618       debug_printf("util_cpu_caps.has_sse = %u\n", util_cpu_caps.has_sse);
 619       debug_printf("util_cpu_caps.has_sse2 = %u\n", util_cpu_caps.has_sse2);
 620       debug_printf("util_cpu_caps.has_sse3 = %u\n", util_cpu_caps.has_sse3);
 621       debug_printf("util_cpu_caps.has_ssse3 = %u\n", util_cpu_caps.has_ssse3);
 622       debug_printf("util_cpu_caps.has_sse4_1 = %u\n", util_cpu_caps.has_sse4_1);
 623       debug_printf("util_cpu_caps.has_sse4_2 = %u\n", util_cpu_caps.has_sse4_2);
 624       debug_printf("util_cpu_caps.has_avx = %u\n", util_cpu_caps.has_avx);
 625       debug_printf("util_cpu_caps.has_avx2 = %u\n", util_cpu_caps.has_avx2);
 626       debug_printf("util_cpu_caps.has_f16c = %u\n", util_cpu_caps.has_f16c);
 627       debug_printf("util_cpu_caps.has_popcnt = %u\n", util_cpu_caps.has_popcnt);
 628       debug_printf("util_cpu_caps.has_3dnow = %u\n", util_cpu_caps.has_3dnow);
 629       debug_printf("util_cpu_caps.has_3dnow_ext = %u\n", util_cpu_caps.has_3dnow_ext);
 630       debug_printf("util_cpu_caps.has_xop = %u\n", util_cpu_caps.has_xop);
 631       debug_printf("util_cpu_caps.has_altivec = %u\n", util_cpu_caps.has_altivec);
 632       debug_printf("util_cpu_caps.has_vsx = %u\n", util_cpu_caps.has_vsx);
 633       debug_printf("util_cpu_caps.has_neon = %u\n", util_cpu_caps.has_neon);
 634       debug_printf("util_cpu_caps.has_daz = %u\n", util_cpu_caps.has_daz);
 635       debug_printf("util_cpu_caps.has_avx512f = %u\n", util_cpu_caps.has_avx512f);
 636       debug_printf("util_cpu_caps.has_avx512dq = %u\n", util_cpu_caps.has_avx512dq);
 637       debug_printf("util_cpu_caps.has_avx512ifma = %u\n", util_cpu_caps.has_avx512ifma);
 638       debug_printf("util_cpu_caps.has_avx512pf = %u\n", util_cpu_caps.has_avx512pf);
 639       debug_printf("util_cpu_caps.has_avx512er = %u\n", util_cpu_caps.has_avx512er);
 640       debug_printf("util_cpu_caps.has_avx512cd = %u\n", util_cpu_caps.has_avx512cd);
 641       debug_printf("util_cpu_caps.has_avx512bw = %u\n", util_cpu_caps.has_avx512bw);
 642       debug_printf("util_cpu_caps.has_avx512vl = %u\n", util_cpu_caps.has_avx512vl);
 643       debug_printf("util_cpu_caps.has_avx512vbmi = %u\n", util_cpu_caps.has_avx512vbmi);
 644    }
 645 #endif
 646 }
 647
 648 static once_flag cpu_once_flag = ONCE_FLAG_INIT;
 649
 650 void
 651 util_cpu_detect(void)
 652 {
 653    call_once(&cpu_once_flag, util_cpu_detect_once);
 654 }