Added few more stubs so that control reaches to DestroyDevice().
[mesa.git] / src / util / u_cpu_detect.c
1 /**************************************************************************
2 *
3 * Copyright 2008 Dennis Smit
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * AUTHORS, COPYRIGHT HOLDERS, AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 **************************************************************************/
26
27 /**
28 * @file
29 * CPU feature detection.
30 *
31 * @author Dennis Smit
32 * @author Based on the work of Eric Anholt <anholt@FreeBSD.org>
33 */
34
35 #include "pipe/p_config.h"
36 #include "pipe/p_compiler.h"
37
38 #include "util/u_debug.h"
39 #include "u_cpu_detect.h"
40 #include "c11/threads.h"
41
42 #if defined(PIPE_ARCH_PPC)
43 #if defined(PIPE_OS_APPLE)
44 #include <sys/sysctl.h>
45 #else
46 #include <signal.h>
47 #include <setjmp.h>
48 #endif
49 #endif
50
51 #if defined(PIPE_OS_BSD)
52 #include <sys/param.h>
53 #include <sys/sysctl.h>
54 #include <machine/cpu.h>
55 #endif
56
57 #if defined(PIPE_OS_FREEBSD)
58 #if __has_include(<sys/auxv.h>)
59 #include <sys/auxv.h>
60 #define HAVE_ELF_AUX_INFO
61 #endif
62 #endif
63
64 #if defined(PIPE_OS_LINUX)
65 #include <signal.h>
66 #include <fcntl.h>
67 #include <elf.h>
68 #endif
69
70 #ifdef PIPE_OS_UNIX
71 #include <unistd.h>
72 #endif
73
74 #if defined(HAS_ANDROID_CPUFEATURES)
75 #include <cpu-features.h>
76 #endif
77
78 #if defined(PIPE_OS_WINDOWS)
79 #include <windows.h>
80 #if defined(PIPE_CC_MSVC)
81 #include <intrin.h>
82 #endif
83 #endif
84
85
86 #ifdef DEBUG
87 DEBUG_GET_ONCE_BOOL_OPTION(dump_cpu, "GALLIUM_DUMP_CPU", false)
88 #endif
89
90
91 struct util_cpu_caps util_cpu_caps;
92
93 #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
94 static int has_cpuid(void);
95 #endif
96
97
98 #if defined(PIPE_ARCH_PPC) && !defined(PIPE_OS_APPLE) && !defined(PIPE_OS_BSD) && !defined(PIPE_OS_LINUX)
99 static jmp_buf __lv_powerpc_jmpbuf;
100 static volatile sig_atomic_t __lv_powerpc_canjump = 0;
101
102 static void
103 sigill_handler(int sig)
104 {
105 if (!__lv_powerpc_canjump) {
106 signal (sig, SIG_DFL);
107 raise (sig);
108 }
109
110 __lv_powerpc_canjump = 0;
111 longjmp(__lv_powerpc_jmpbuf, 1);
112 }
113 #endif
114
115 #if defined(PIPE_ARCH_PPC)
116 static void
117 check_os_altivec_support(void)
118 {
119 #if defined(__ALTIVEC__)
120 util_cpu_caps.has_altivec = 1;
121 #endif
122 #if defined(__VSX__)
123 util_cpu_caps.has_vsx = 1;
124 #endif
125 #if defined(__ALTIVEC__) && defined(__VSX__)
126 /* Do nothing */
127 #elif defined(PIPE_OS_APPLE) || defined(PIPE_OS_NETBSD) || defined(PIPE_OS_OPENBSD)
128 #ifdef HW_VECTORUNIT
129 int sels[2] = {CTL_HW, HW_VECTORUNIT};
130 #else
131 int sels[2] = {CTL_MACHDEP, CPU_ALTIVEC};
132 #endif
133 int has_vu = 0;
134 int len = sizeof (has_vu);
135 int err;
136
137 err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
138
139 if (err == 0) {
140 if (has_vu != 0) {
141 util_cpu_caps.has_altivec = 1;
142 }
143 }
144 #elif defined(PIPE_OS_FREEBSD) /* !PIPE_OS_APPLE && !PIPE_OS_NETBSD && !PIPE_OS_OPENBSD */
145 unsigned long hwcap = 0;
146 #ifdef HAVE_ELF_AUX_INFO
147 elf_aux_info(AT_HWCAP, &hwcap, sizeof(hwcap));
148 #else
149 size_t len = sizeof(hwcap);
150 sysctlbyname("hw.cpu_features", &hwcap, &len, NULL, 0);
151 #endif
152 if (hwcap & PPC_FEATURE_HAS_ALTIVEC)
153 util_cpu_caps.has_altivec = 1;
154 if (hwcap & PPC_FEATURE_HAS_VSX)
155 util_cpu_caps.has_vsx = 1;
156 #elif defined(PIPE_OS_LINUX) /* !PIPE_OS_FREEBSD */
157 #if defined(PIPE_ARCH_PPC_64)
158 Elf64_auxv_t aux;
159 #else
160 Elf32_auxv_t aux;
161 #endif
162 int fd = open("/proc/self/auxv", O_RDONLY | O_CLOEXEC);
163 if (fd >= 0) {
164 while (read(fd, &aux, sizeof(aux)) == sizeof(aux)) {
165 if (aux.a_type == AT_HWCAP) {
166 char *env_vsx = getenv("GALLIVM_VSX");
167 uint64_t hwcap = aux.a_un.a_val;
168 util_cpu_caps.has_altivec = (hwcap >> 28) & 1;
169 if (!env_vsx || env_vsx[0] != '0') {
170 util_cpu_caps.has_vsx = (hwcap >> 7) & 1;
171 }
172 break;
173 }
174 }
175 close(fd);
176 }
177 #else /* !PIPE_OS_APPLE && !PIPE_OS_BSD && !PIPE_OS_LINUX */
178 /* not on Apple/Darwin or Linux, do it the brute-force way */
179 /* this is borrowed from the libmpeg2 library */
180 signal(SIGILL, sigill_handler);
181 if (setjmp(__lv_powerpc_jmpbuf)) {
182 signal(SIGILL, SIG_DFL);
183 } else {
184 boolean enable_altivec = TRUE; /* Default: enable if available, and if not overridden */
185 boolean enable_vsx = TRUE;
186 #ifdef DEBUG
187 /* Disabling Altivec code generation is not the same as disabling VSX code generation,
188 * which can be done simply by passing -mattr=-vsx to the LLVM compiler; cf.
189 * lp_build_create_jit_compiler_for_module().
190 * If you want to disable Altivec code generation, the best place to do it is here.
191 */
192 char *env_control = getenv("GALLIVM_ALTIVEC"); /* 1=enable (default); 0=disable */
193 if (env_control && env_control[0] == '0') {
194 enable_altivec = FALSE;
195 }
196 #endif
197 /* VSX instructions can be explicitly enabled/disabled via GALLIVM_VSX=1 or 0 */
198 char *env_vsx = getenv("GALLIVM_VSX");
199 if (env_vsx && env_vsx[0] == '0') {
200 enable_vsx = FALSE;
201 }
202 if (enable_altivec) {
203 __lv_powerpc_canjump = 1;
204
205 __asm __volatile
206 ("mtspr 256, %0\n\t"
207 "vand %%v0, %%v0, %%v0"
208 :
209 : "r" (-1));
210
211 util_cpu_caps.has_altivec = 1;
212
213 if (enable_vsx) {
214 __asm __volatile("xxland %vs0, %vs0, %vs0");
215 util_cpu_caps.has_vsx = 1;
216 }
217 signal(SIGILL, SIG_DFL);
218 } else {
219 util_cpu_caps.has_altivec = 0;
220 }
221 }
222 #endif /* !PIPE_OS_APPLE && !PIPE_OS_LINUX */
223 }
224 #endif /* PIPE_ARCH_PPC */
225
226
227 #if defined(PIPE_ARCH_X86) || defined (PIPE_ARCH_X86_64)
228 static int has_cpuid(void)
229 {
230 #if defined(PIPE_ARCH_X86)
231 #if defined(PIPE_OS_GCC)
232 int a, c;
233
234 __asm __volatile
235 ("pushf\n"
236 "popl %0\n"
237 "movl %0, %1\n"
238 "xorl $0x200000, %0\n"
239 "push %0\n"
240 "popf\n"
241 "pushf\n"
242 "popl %0\n"
243 : "=a" (a), "=c" (c)
244 :
245 : "cc");
246
247 return a != c;
248 #else
249 /* FIXME */
250 return 1;
251 #endif
252 #elif defined(PIPE_ARCH_X86_64)
253 return 1;
254 #else
255 return 0;
256 #endif
257 }
258
259
260 /**
261 * @sa cpuid.h included in gcc-4.3 onwards.
262 * @sa http://msdn.microsoft.com/en-us/library/hskdteyh.aspx
263 */
264 static inline void
265 cpuid(uint32_t ax, uint32_t *p)
266 {
267 #if defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86)
268 __asm __volatile (
269 "xchgl %%ebx, %1\n\t"
270 "cpuid\n\t"
271 "xchgl %%ebx, %1"
272 : "=a" (p[0]),
273 "=S" (p[1]),
274 "=c" (p[2]),
275 "=d" (p[3])
276 : "0" (ax)
277 );
278 #elif defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86_64)
279 __asm __volatile (
280 "cpuid\n\t"
281 : "=a" (p[0]),
282 "=b" (p[1]),
283 "=c" (p[2]),
284 "=d" (p[3])
285 : "0" (ax)
286 );
287 #elif defined(PIPE_CC_MSVC)
288 __cpuid(p, ax);
289 #else
290 p[0] = 0;
291 p[1] = 0;
292 p[2] = 0;
293 p[3] = 0;
294 #endif
295 }
296
297 /**
298 * @sa cpuid.h included in gcc-4.4 onwards.
299 * @sa http://msdn.microsoft.com/en-us/library/hskdteyh%28v=vs.90%29.aspx
300 */
301 static inline void
302 cpuid_count(uint32_t ax, uint32_t cx, uint32_t *p)
303 {
304 #if defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86)
305 __asm __volatile (
306 "xchgl %%ebx, %1\n\t"
307 "cpuid\n\t"
308 "xchgl %%ebx, %1"
309 : "=a" (p[0]),
310 "=S" (p[1]),
311 "=c" (p[2]),
312 "=d" (p[3])
313 : "0" (ax), "2" (cx)
314 );
315 #elif defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86_64)
316 __asm __volatile (
317 "cpuid\n\t"
318 : "=a" (p[0]),
319 "=b" (p[1]),
320 "=c" (p[2]),
321 "=d" (p[3])
322 : "0" (ax), "2" (cx)
323 );
324 #elif defined(PIPE_CC_MSVC)
325 __cpuidex(p, ax, cx);
326 #else
327 p[0] = 0;
328 p[1] = 0;
329 p[2] = 0;
330 p[3] = 0;
331 #endif
332 }
333
334
335 static inline uint64_t xgetbv(void)
336 {
337 #if defined(PIPE_CC_GCC)
338 uint32_t eax, edx;
339
340 __asm __volatile (
341 ".byte 0x0f, 0x01, 0xd0" // xgetbv isn't supported on gcc < 4.4
342 : "=a"(eax),
343 "=d"(edx)
344 : "c"(0)
345 );
346
347 return ((uint64_t)edx << 32) | eax;
348 #elif defined(PIPE_CC_MSVC) && defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
349 return _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
350 #else
351 return 0;
352 #endif
353 }
354
355
356 #if defined(PIPE_ARCH_X86)
357 PIPE_ALIGN_STACK static inline boolean sse2_has_daz(void)
358 {
359 struct {
360 uint32_t pad1[7];
361 uint32_t mxcsr_mask;
362 uint32_t pad2[128-8];
363 } PIPE_ALIGN_VAR(16) fxarea;
364
365 fxarea.mxcsr_mask = 0;
366 #if defined(PIPE_CC_GCC)
367 __asm __volatile ("fxsave %0" : "+m" (fxarea));
368 #elif defined(PIPE_CC_MSVC) || defined(PIPE_CC_ICL)
369 _fxsave(&fxarea);
370 #else
371 fxarea.mxcsr_mask = 0;
372 #endif
373 return !!(fxarea.mxcsr_mask & (1 << 6));
374 }
375 #endif
376
377 #endif /* X86 or X86_64 */
378
379 #if defined(PIPE_ARCH_ARM)
380 static void
381 check_os_arm_support(void)
382 {
383 /*
384 * On Android, the cpufeatures library is preferred way of checking
385 * CPU capabilities. However, it is not available for standalone Mesa
386 * builds, i.e. when Android build system (Android.mk-based) is not
387 * used. Because of this we cannot use PIPE_OS_ANDROID here, but rather
388 * have a separate macro that only gets enabled from respective Android.mk.
389 */
390 #if defined(__ARM_NEON) || defined(__ARM_NEON__)
391 util_cpu_caps.has_neon = 1;
392 #elif defined(PIPE_OS_FREEBSD) && defined(HAVE_ELF_AUX_INFO)
393 unsigned long hwcap = 0;
394 elf_aux_info(AT_HWCAP, &hwcap, sizeof(hwcap));
395 if (hwcap & HWCAP_NEON)
396 util_cpu_caps.has_neon = 1;
397 #elif defined(HAS_ANDROID_CPUFEATURES)
398 AndroidCpuFamily cpu_family = android_getCpuFamily();
399 uint64_t cpu_features = android_getCpuFeatures();
400
401 if (cpu_family == ANDROID_CPU_FAMILY_ARM) {
402 if (cpu_features & ANDROID_CPU_ARM_FEATURE_NEON)
403 util_cpu_caps.has_neon = 1;
404 }
405 #elif defined(PIPE_OS_LINUX)
406 Elf32_auxv_t aux;
407 int fd;
408
409 fd = open("/proc/self/auxv", O_RDONLY | O_CLOEXEC);
410 if (fd >= 0) {
411 while (read(fd, &aux, sizeof(Elf32_auxv_t)) == sizeof(Elf32_auxv_t)) {
412 if (aux.a_type == AT_HWCAP) {
413 uint32_t hwcap = aux.a_un.a_val;
414
415 util_cpu_caps.has_neon = (hwcap >> 12) & 1;
416 break;
417 }
418 }
419 close (fd);
420 }
421 #endif /* PIPE_OS_LINUX */
422 }
423
424 #elif defined(PIPE_ARCH_AARCH64)
425 static void
426 check_os_arm_support(void)
427 {
428 util_cpu_caps.has_neon = true;
429 }
430 #endif /* PIPE_ARCH_ARM || PIPE_ARCH_AARCH64 */
431
432 static void
433 get_cpu_topology(void)
434 {
435 /* Default. This is correct if L3 is not present or there is only one. */
436 util_cpu_caps.cores_per_L3 = util_cpu_caps.nr_cpus;
437
438 #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
439 /* AMD Zen */
440 if (util_cpu_caps.x86_cpu_type == 0x17) {
441 uint32_t regs[4];
442
443 /* Query the L3 cache topology information. */
444 cpuid_count(0x8000001D, 3, regs);
445 unsigned cache_level = (regs[0] >> 5) & 0x7;
446 unsigned cores_per_cache = ((regs[0] >> 14) & 0xfff) + 1;
447
448 if (cache_level == 3)
449 util_cpu_caps.cores_per_L3 = cores_per_cache;
450 }
451 #endif
452 }
453
454 static void
455 util_cpu_detect_once(void)
456 {
457 memset(&util_cpu_caps, 0, sizeof util_cpu_caps);
458
459 /* Count the number of CPUs in system */
460 #if defined(PIPE_OS_WINDOWS)
461 {
462 SYSTEM_INFO system_info;
463 GetSystemInfo(&system_info);
464 util_cpu_caps.nr_cpus = system_info.dwNumberOfProcessors;
465 }
466 #elif defined(PIPE_OS_UNIX) && defined(_SC_NPROCESSORS_ONLN)
467 util_cpu_caps.nr_cpus = sysconf(_SC_NPROCESSORS_ONLN);
468 if (util_cpu_caps.nr_cpus == ~0)
469 util_cpu_caps.nr_cpus = 1;
470 #elif defined(PIPE_OS_BSD)
471 {
472 int mib[2], ncpu;
473 int len;
474
475 mib[0] = CTL_HW;
476 mib[1] = HW_NCPU;
477
478 len = sizeof (ncpu);
479 sysctl(mib, 2, &ncpu, &len, NULL, 0);
480 util_cpu_caps.nr_cpus = ncpu;
481 }
482 #else
483 util_cpu_caps.nr_cpus = 1;
484 #endif
485
486 /* Make the fallback cacheline size nonzero so that it can be
487 * safely passed to align().
488 */
489 util_cpu_caps.cacheline = sizeof(void *);
490
491 #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
492 if (has_cpuid()) {
493 uint32_t regs[4];
494 uint32_t regs2[4];
495
496 util_cpu_caps.cacheline = 32;
497
498 /* Get max cpuid level */
499 cpuid(0x00000000, regs);
500
501 if (regs[0] >= 0x00000001) {
502 unsigned int cacheline;
503
504 cpuid (0x00000001, regs2);
505
506 util_cpu_caps.x86_cpu_type = (regs2[0] >> 8) & 0xf;
507 /* Add "extended family". */
508 if (util_cpu_caps.x86_cpu_type == 0xf)
509 util_cpu_caps.x86_cpu_type += ((regs2[0] >> 20) & 0xff);
510
511 /* general feature flags */
512 util_cpu_caps.has_tsc = (regs2[3] >> 4) & 1; /* 0x0000010 */
513 util_cpu_caps.has_mmx = (regs2[3] >> 23) & 1; /* 0x0800000 */
514 util_cpu_caps.has_sse = (regs2[3] >> 25) & 1; /* 0x2000000 */
515 util_cpu_caps.has_sse2 = (regs2[3] >> 26) & 1; /* 0x4000000 */
516 util_cpu_caps.has_sse3 = (regs2[2] >> 0) & 1; /* 0x0000001 */
517 util_cpu_caps.has_ssse3 = (regs2[2] >> 9) & 1; /* 0x0000020 */
518 util_cpu_caps.has_sse4_1 = (regs2[2] >> 19) & 1;
519 util_cpu_caps.has_sse4_2 = (regs2[2] >> 20) & 1;
520 util_cpu_caps.has_popcnt = (regs2[2] >> 23) & 1;
521 util_cpu_caps.has_avx = ((regs2[2] >> 28) & 1) && // AVX
522 ((regs2[2] >> 27) & 1) && // OSXSAVE
523 ((xgetbv() & 6) == 6); // XMM & YMM
524 util_cpu_caps.has_f16c = ((regs2[2] >> 29) & 1) && util_cpu_caps.has_avx;
525 util_cpu_caps.has_fma = ((regs2[2] >> 12) & 1) && util_cpu_caps.has_avx;
526 util_cpu_caps.has_mmx2 = util_cpu_caps.has_sse; /* SSE cpus supports mmxext too */
527 #if defined(PIPE_ARCH_X86_64)
528 util_cpu_caps.has_daz = 1;
529 #else
530 util_cpu_caps.has_daz = util_cpu_caps.has_sse3 ||
531 (util_cpu_caps.has_sse2 && sse2_has_daz());
532 #endif
533
534 cacheline = ((regs2[1] >> 8) & 0xFF) * 8;
535 if (cacheline > 0)
536 util_cpu_caps.cacheline = cacheline;
537 }
538 if (util_cpu_caps.has_avx && regs[0] >= 0x00000007) {
539 uint32_t regs7[4];
540 cpuid_count(0x00000007, 0x00000000, regs7);
541 util_cpu_caps.has_avx2 = (regs7[1] >> 5) & 1;
542 }
543
544 // check for avx512
545 if (((regs2[2] >> 27) & 1) && // OSXSAVE
546 (xgetbv() & (0x7 << 5)) && // OPMASK: upper-256 enabled by OS
547 ((xgetbv() & 6) == 6)) { // XMM/YMM enabled by OS
548 uint32_t regs3[4];
549 cpuid_count(0x00000007, 0x00000000, regs3);
550 util_cpu_caps.has_avx512f = (regs3[1] >> 16) & 1;
551 util_cpu_caps.has_avx512dq = (regs3[1] >> 17) & 1;
552 util_cpu_caps.has_avx512ifma = (regs3[1] >> 21) & 1;
553 util_cpu_caps.has_avx512pf = (regs3[1] >> 26) & 1;
554 util_cpu_caps.has_avx512er = (regs3[1] >> 27) & 1;
555 util_cpu_caps.has_avx512cd = (regs3[1] >> 28) & 1;
556 util_cpu_caps.has_avx512bw = (regs3[1] >> 30) & 1;
557 util_cpu_caps.has_avx512vl = (regs3[1] >> 31) & 1;
558 util_cpu_caps.has_avx512vbmi = (regs3[2] >> 1) & 1;
559 }
560
561 if (regs[1] == 0x756e6547 && regs[2] == 0x6c65746e && regs[3] == 0x49656e69) {
562 /* GenuineIntel */
563 util_cpu_caps.has_intel = 1;
564 }
565
566 cpuid(0x80000000, regs);
567
568 if (regs[0] >= 0x80000001) {
569
570 cpuid(0x80000001, regs2);
571
572 util_cpu_caps.has_mmx |= (regs2[3] >> 23) & 1;
573 util_cpu_caps.has_mmx2 |= (regs2[3] >> 22) & 1;
574 util_cpu_caps.has_3dnow = (regs2[3] >> 31) & 1;
575 util_cpu_caps.has_3dnow_ext = (regs2[3] >> 30) & 1;
576
577 util_cpu_caps.has_xop = util_cpu_caps.has_avx &&
578 ((regs2[2] >> 11) & 1);
579 }
580
581 if (regs[0] >= 0x80000006) {
582 /* should we really do this if the clflush size above worked? */
583 unsigned int cacheline;
584 cpuid(0x80000006, regs2);
585 cacheline = regs2[2] & 0xFF;
586 if (cacheline > 0)
587 util_cpu_caps.cacheline = cacheline;
588 }
589
590 if (!util_cpu_caps.has_sse) {
591 util_cpu_caps.has_sse2 = 0;
592 util_cpu_caps.has_sse3 = 0;
593 util_cpu_caps.has_ssse3 = 0;
594 util_cpu_caps.has_sse4_1 = 0;
595 }
596 }
597 #endif /* PIPE_ARCH_X86 || PIPE_ARCH_X86_64 */
598
599 #if defined(PIPE_ARCH_ARM) || defined(PIPE_ARCH_AARCH64)
600 check_os_arm_support();
601 #endif
602
603 #if defined(PIPE_ARCH_PPC)
604 check_os_altivec_support();
605 #endif /* PIPE_ARCH_PPC */
606
607 get_cpu_topology();
608
609 #ifdef DEBUG
610 if (debug_get_option_dump_cpu()) {
611 debug_printf("util_cpu_caps.nr_cpus = %u\n", util_cpu_caps.nr_cpus);
612
613 debug_printf("util_cpu_caps.x86_cpu_type = %u\n", util_cpu_caps.x86_cpu_type);
614 debug_printf("util_cpu_caps.cacheline = %u\n", util_cpu_caps.cacheline);
615
616 debug_printf("util_cpu_caps.has_tsc = %u\n", util_cpu_caps.has_tsc);
617 debug_printf("util_cpu_caps.has_mmx = %u\n", util_cpu_caps.has_mmx);
618 debug_printf("util_cpu_caps.has_mmx2 = %u\n", util_cpu_caps.has_mmx2);
619 debug_printf("util_cpu_caps.has_sse = %u\n", util_cpu_caps.has_sse);
620 debug_printf("util_cpu_caps.has_sse2 = %u\n", util_cpu_caps.has_sse2);
621 debug_printf("util_cpu_caps.has_sse3 = %u\n", util_cpu_caps.has_sse3);
622 debug_printf("util_cpu_caps.has_ssse3 = %u\n", util_cpu_caps.has_ssse3);
623 debug_printf("util_cpu_caps.has_sse4_1 = %u\n", util_cpu_caps.has_sse4_1);
624 debug_printf("util_cpu_caps.has_sse4_2 = %u\n", util_cpu_caps.has_sse4_2);
625 debug_printf("util_cpu_caps.has_avx = %u\n", util_cpu_caps.has_avx);
626 debug_printf("util_cpu_caps.has_avx2 = %u\n", util_cpu_caps.has_avx2);
627 debug_printf("util_cpu_caps.has_f16c = %u\n", util_cpu_caps.has_f16c);
628 debug_printf("util_cpu_caps.has_popcnt = %u\n", util_cpu_caps.has_popcnt);
629 debug_printf("util_cpu_caps.has_3dnow = %u\n", util_cpu_caps.has_3dnow);
630 debug_printf("util_cpu_caps.has_3dnow_ext = %u\n", util_cpu_caps.has_3dnow_ext);
631 debug_printf("util_cpu_caps.has_xop = %u\n", util_cpu_caps.has_xop);
632 debug_printf("util_cpu_caps.has_altivec = %u\n", util_cpu_caps.has_altivec);
633 debug_printf("util_cpu_caps.has_vsx = %u\n", util_cpu_caps.has_vsx);
634 debug_printf("util_cpu_caps.has_neon = %u\n", util_cpu_caps.has_neon);
635 debug_printf("util_cpu_caps.has_daz = %u\n", util_cpu_caps.has_daz);
636 debug_printf("util_cpu_caps.has_avx512f = %u\n", util_cpu_caps.has_avx512f);
637 debug_printf("util_cpu_caps.has_avx512dq = %u\n", util_cpu_caps.has_avx512dq);
638 debug_printf("util_cpu_caps.has_avx512ifma = %u\n", util_cpu_caps.has_avx512ifma);
639 debug_printf("util_cpu_caps.has_avx512pf = %u\n", util_cpu_caps.has_avx512pf);
640 debug_printf("util_cpu_caps.has_avx512er = %u\n", util_cpu_caps.has_avx512er);
641 debug_printf("util_cpu_caps.has_avx512cd = %u\n", util_cpu_caps.has_avx512cd);
642 debug_printf("util_cpu_caps.has_avx512bw = %u\n", util_cpu_caps.has_avx512bw);
643 debug_printf("util_cpu_caps.has_avx512vl = %u\n", util_cpu_caps.has_avx512vl);
644 debug_printf("util_cpu_caps.has_avx512vbmi = %u\n", util_cpu_caps.has_avx512vbmi);
645 }
646 #endif
647 }
648
649 static once_flag cpu_once_flag = ONCE_FLAG_INIT;
650
651 void
652 util_cpu_detect(void)
653 {
654 call_once(&cpu_once_flag, util_cpu_detect_once);
655 }