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Added few more stubs so that control reaches to DestroyDevice().
[mesa.git] / src / virtio / virtio-gpu / virgl_hw.h
1 /*
2 * Copyright 2014, 2015 Red Hat.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #ifndef VIRGL_HW_H
24 #define VIRGL_HW_H
25
26 #include <stdint.h>
27
28 struct virgl_box {
29 uint32_t x, y, z;
30 uint32_t w, h, d;
31 };
32
33 /* formats known by the HW device - based on gallium subset */
34 enum virgl_formats {
35 VIRGL_FORMAT_NONE = 0,
36 VIRGL_FORMAT_B8G8R8A8_UNORM = 1,
37 VIRGL_FORMAT_B8G8R8X8_UNORM = 2,
38 VIRGL_FORMAT_A8R8G8B8_UNORM = 3,
39 VIRGL_FORMAT_X8R8G8B8_UNORM = 4,
40 VIRGL_FORMAT_B5G5R5A1_UNORM = 5,
41 VIRGL_FORMAT_B4G4R4A4_UNORM = 6,
42 VIRGL_FORMAT_B5G6R5_UNORM = 7,
43 VIRGL_FORMAT_R10G10B10A2_UNORM = 8,
44 VIRGL_FORMAT_L8_UNORM = 9, /**< ubyte luminance */
45 VIRGL_FORMAT_A8_UNORM = 10, /**< ubyte alpha */
46 VIRGL_FORMAT_I8_UNORM = 11,
47 VIRGL_FORMAT_L8A8_UNORM = 12, /**< ubyte alpha, luminance */
48 VIRGL_FORMAT_L16_UNORM = 13, /**< ushort luminance */
49 VIRGL_FORMAT_UYVY = 14,
50 VIRGL_FORMAT_YUYV = 15,
51 VIRGL_FORMAT_Z16_UNORM = 16,
52 VIRGL_FORMAT_Z32_UNORM = 17,
53 VIRGL_FORMAT_Z32_FLOAT = 18,
54 VIRGL_FORMAT_Z24_UNORM_S8_UINT = 19,
55 VIRGL_FORMAT_S8_UINT_Z24_UNORM = 20,
56 VIRGL_FORMAT_Z24X8_UNORM = 21,
57 VIRGL_FORMAT_X8Z24_UNORM = 22,
58 VIRGL_FORMAT_S8_UINT = 23, /**< ubyte stencil */
59 VIRGL_FORMAT_R64_FLOAT = 24,
60 VIRGL_FORMAT_R64G64_FLOAT = 25,
61 VIRGL_FORMAT_R64G64B64_FLOAT = 26,
62 VIRGL_FORMAT_R64G64B64A64_FLOAT = 27,
63 VIRGL_FORMAT_R32_FLOAT = 28,
64 VIRGL_FORMAT_R32G32_FLOAT = 29,
65 VIRGL_FORMAT_R32G32B32_FLOAT = 30,
66 VIRGL_FORMAT_R32G32B32A32_FLOAT = 31,
67
68 VIRGL_FORMAT_R32_UNORM = 32,
69 VIRGL_FORMAT_R32G32_UNORM = 33,
70 VIRGL_FORMAT_R32G32B32_UNORM = 34,
71 VIRGL_FORMAT_R32G32B32A32_UNORM = 35,
72 VIRGL_FORMAT_R32_USCALED = 36,
73 VIRGL_FORMAT_R32G32_USCALED = 37,
74 VIRGL_FORMAT_R32G32B32_USCALED = 38,
75 VIRGL_FORMAT_R32G32B32A32_USCALED = 39,
76 VIRGL_FORMAT_R32_SNORM = 40,
77 VIRGL_FORMAT_R32G32_SNORM = 41,
78 VIRGL_FORMAT_R32G32B32_SNORM = 42,
79 VIRGL_FORMAT_R32G32B32A32_SNORM = 43,
80 VIRGL_FORMAT_R32_SSCALED = 44,
81 VIRGL_FORMAT_R32G32_SSCALED = 45,
82 VIRGL_FORMAT_R32G32B32_SSCALED = 46,
83 VIRGL_FORMAT_R32G32B32A32_SSCALED = 47,
84
85 VIRGL_FORMAT_R16_UNORM = 48,
86 VIRGL_FORMAT_R16G16_UNORM = 49,
87 VIRGL_FORMAT_R16G16B16_UNORM = 50,
88 VIRGL_FORMAT_R16G16B16A16_UNORM = 51,
89
90 VIRGL_FORMAT_R16_USCALED = 52,
91 VIRGL_FORMAT_R16G16_USCALED = 53,
92 VIRGL_FORMAT_R16G16B16_USCALED = 54,
93 VIRGL_FORMAT_R16G16B16A16_USCALED = 55,
94
95 VIRGL_FORMAT_R16_SNORM = 56,
96 VIRGL_FORMAT_R16G16_SNORM = 57,
97 VIRGL_FORMAT_R16G16B16_SNORM = 58,
98 VIRGL_FORMAT_R16G16B16A16_SNORM = 59,
99
100 VIRGL_FORMAT_R16_SSCALED = 60,
101 VIRGL_FORMAT_R16G16_SSCALED = 61,
102 VIRGL_FORMAT_R16G16B16_SSCALED = 62,
103 VIRGL_FORMAT_R16G16B16A16_SSCALED = 63,
104
105 VIRGL_FORMAT_R8_UNORM = 64,
106 VIRGL_FORMAT_R8G8_UNORM = 65,
107 VIRGL_FORMAT_R8G8B8_UNORM = 66,
108 VIRGL_FORMAT_R8G8B8A8_UNORM = 67,
109 VIRGL_FORMAT_X8B8G8R8_UNORM = 68,
110
111 VIRGL_FORMAT_R8_USCALED = 69,
112 VIRGL_FORMAT_R8G8_USCALED = 70,
113 VIRGL_FORMAT_R8G8B8_USCALED = 71,
114 VIRGL_FORMAT_R8G8B8A8_USCALED = 72,
115
116 VIRGL_FORMAT_R8_SNORM = 74,
117 VIRGL_FORMAT_R8G8_SNORM = 75,
118 VIRGL_FORMAT_R8G8B8_SNORM = 76,
119 VIRGL_FORMAT_R8G8B8A8_SNORM = 77,
120
121 VIRGL_FORMAT_R8_SSCALED = 82,
122 VIRGL_FORMAT_R8G8_SSCALED = 83,
123 VIRGL_FORMAT_R8G8B8_SSCALED = 84,
124 VIRGL_FORMAT_R8G8B8A8_SSCALED = 85,
125
126 VIRGL_FORMAT_R32_FIXED = 87,
127 VIRGL_FORMAT_R32G32_FIXED = 88,
128 VIRGL_FORMAT_R32G32B32_FIXED = 89,
129 VIRGL_FORMAT_R32G32B32A32_FIXED = 90,
130
131 VIRGL_FORMAT_R16_FLOAT = 91,
132 VIRGL_FORMAT_R16G16_FLOAT = 92,
133 VIRGL_FORMAT_R16G16B16_FLOAT = 93,
134 VIRGL_FORMAT_R16G16B16A16_FLOAT = 94,
135
136 VIRGL_FORMAT_L8_SRGB = 95,
137 VIRGL_FORMAT_L8A8_SRGB = 96,
138 VIRGL_FORMAT_R8G8B8_SRGB = 97,
139 VIRGL_FORMAT_A8B8G8R8_SRGB = 98,
140 VIRGL_FORMAT_X8B8G8R8_SRGB = 99,
141 VIRGL_FORMAT_B8G8R8A8_SRGB = 100,
142 VIRGL_FORMAT_B8G8R8X8_SRGB = 101,
143 VIRGL_FORMAT_A8R8G8B8_SRGB = 102,
144 VIRGL_FORMAT_X8R8G8B8_SRGB = 103,
145 VIRGL_FORMAT_R8G8B8A8_SRGB = 104,
146
147 /* compressed formats */
148 VIRGL_FORMAT_DXT1_RGB = 105,
149 VIRGL_FORMAT_DXT1_RGBA = 106,
150 VIRGL_FORMAT_DXT3_RGBA = 107,
151 VIRGL_FORMAT_DXT5_RGBA = 108,
152
153 /* sRGB, compressed */
154 VIRGL_FORMAT_DXT1_SRGB = 109,
155 VIRGL_FORMAT_DXT1_SRGBA = 110,
156 VIRGL_FORMAT_DXT3_SRGBA = 111,
157 VIRGL_FORMAT_DXT5_SRGBA = 112,
158
159 /* rgtc compressed */
160 VIRGL_FORMAT_RGTC1_UNORM = 113,
161 VIRGL_FORMAT_RGTC1_SNORM = 114,
162 VIRGL_FORMAT_RGTC2_UNORM = 115,
163 VIRGL_FORMAT_RGTC2_SNORM = 116,
164
165 VIRGL_FORMAT_R8G8_B8G8_UNORM = 117,
166 VIRGL_FORMAT_G8R8_G8B8_UNORM = 118,
167
168 VIRGL_FORMAT_R8SG8SB8UX8U_NORM = 119,
169 VIRGL_FORMAT_R5SG5SB6U_NORM = 120,
170
171 VIRGL_FORMAT_A8B8G8R8_UNORM = 121,
172 VIRGL_FORMAT_B5G5R5X1_UNORM = 122,
173 VIRGL_FORMAT_R10G10B10A2_USCALED = 123,
174 VIRGL_FORMAT_R11G11B10_FLOAT = 124,
175 VIRGL_FORMAT_R9G9B9E5_FLOAT = 125,
176 VIRGL_FORMAT_Z32_FLOAT_S8X24_UINT = 126,
177 VIRGL_FORMAT_R1_UNORM = 127,
178 VIRGL_FORMAT_R10G10B10X2_USCALED = 128,
179 VIRGL_FORMAT_R10G10B10X2_SNORM = 129,
180
181 VIRGL_FORMAT_L4A4_UNORM = 130,
182 VIRGL_FORMAT_B10G10R10A2_UNORM = 131,
183 VIRGL_FORMAT_R10SG10SB10SA2U_NORM = 132,
184 VIRGL_FORMAT_R8G8Bx_SNORM = 133,
185 VIRGL_FORMAT_R8G8B8X8_UNORM = 134,
186 VIRGL_FORMAT_B4G4R4X4_UNORM = 135,
187 VIRGL_FORMAT_X24S8_UINT = 136,
188 VIRGL_FORMAT_S8X24_UINT = 137,
189 VIRGL_FORMAT_X32_S8X24_UINT = 138,
190 VIRGL_FORMAT_B2G3R3_UNORM = 139,
191
192 VIRGL_FORMAT_L16A16_UNORM = 140,
193 VIRGL_FORMAT_A16_UNORM = 141,
194 VIRGL_FORMAT_I16_UNORM = 142,
195
196 VIRGL_FORMAT_LATC1_UNORM = 143,
197 VIRGL_FORMAT_LATC1_SNORM = 144,
198 VIRGL_FORMAT_LATC2_UNORM = 145,
199 VIRGL_FORMAT_LATC2_SNORM = 146,
200
201 VIRGL_FORMAT_A8_SNORM = 147,
202 VIRGL_FORMAT_L8_SNORM = 148,
203 VIRGL_FORMAT_L8A8_SNORM = 149,
204 VIRGL_FORMAT_I8_SNORM = 150,
205 VIRGL_FORMAT_A16_SNORM = 151,
206 VIRGL_FORMAT_L16_SNORM = 152,
207 VIRGL_FORMAT_L16A16_SNORM = 153,
208 VIRGL_FORMAT_I16_SNORM = 154,
209
210 VIRGL_FORMAT_A16_FLOAT = 155,
211 VIRGL_FORMAT_L16_FLOAT = 156,
212 VIRGL_FORMAT_L16A16_FLOAT = 157,
213 VIRGL_FORMAT_I16_FLOAT = 158,
214 VIRGL_FORMAT_A32_FLOAT = 159,
215 VIRGL_FORMAT_L32_FLOAT = 160,
216 VIRGL_FORMAT_L32A32_FLOAT = 161,
217 VIRGL_FORMAT_I32_FLOAT = 162,
218
219 VIRGL_FORMAT_YV12 = 163,
220 VIRGL_FORMAT_YV16 = 164,
221 VIRGL_FORMAT_IYUV = 165, /**< aka I420 */
222 VIRGL_FORMAT_NV12 = 166,
223 VIRGL_FORMAT_NV21 = 167,
224
225 VIRGL_FORMAT_A4R4_UNORM = 168,
226 VIRGL_FORMAT_R4A4_UNORM = 169,
227 VIRGL_FORMAT_R8A8_UNORM = 170,
228 VIRGL_FORMAT_A8R8_UNORM = 171,
229
230 VIRGL_FORMAT_R10G10B10A2_SSCALED = 172,
231 VIRGL_FORMAT_R10G10B10A2_SNORM = 173,
232 VIRGL_FORMAT_B10G10R10A2_USCALED = 174,
233 VIRGL_FORMAT_B10G10R10A2_SSCALED = 175,
234 VIRGL_FORMAT_B10G10R10A2_SNORM = 176,
235
236 VIRGL_FORMAT_R8_UINT = 177,
237 VIRGL_FORMAT_R8G8_UINT = 178,
238 VIRGL_FORMAT_R8G8B8_UINT = 179,
239 VIRGL_FORMAT_R8G8B8A8_UINT = 180,
240
241 VIRGL_FORMAT_R8_SINT = 181,
242 VIRGL_FORMAT_R8G8_SINT = 182,
243 VIRGL_FORMAT_R8G8B8_SINT = 183,
244 VIRGL_FORMAT_R8G8B8A8_SINT = 184,
245
246 VIRGL_FORMAT_R16_UINT = 185,
247 VIRGL_FORMAT_R16G16_UINT = 186,
248 VIRGL_FORMAT_R16G16B16_UINT = 187,
249 VIRGL_FORMAT_R16G16B16A16_UINT = 188,
250
251 VIRGL_FORMAT_R16_SINT = 189,
252 VIRGL_FORMAT_R16G16_SINT = 190,
253 VIRGL_FORMAT_R16G16B16_SINT = 191,
254 VIRGL_FORMAT_R16G16B16A16_SINT = 192,
255 VIRGL_FORMAT_R32_UINT = 193,
256 VIRGL_FORMAT_R32G32_UINT = 194,
257 VIRGL_FORMAT_R32G32B32_UINT = 195,
258 VIRGL_FORMAT_R32G32B32A32_UINT = 196,
259
260 VIRGL_FORMAT_R32_SINT = 197,
261 VIRGL_FORMAT_R32G32_SINT = 198,
262 VIRGL_FORMAT_R32G32B32_SINT = 199,
263 VIRGL_FORMAT_R32G32B32A32_SINT = 200,
264
265 VIRGL_FORMAT_A8_UINT = 201,
266 VIRGL_FORMAT_I8_UINT = 202,
267 VIRGL_FORMAT_L8_UINT = 203,
268 VIRGL_FORMAT_L8A8_UINT = 204,
269
270 VIRGL_FORMAT_A8_SINT = 205,
271 VIRGL_FORMAT_I8_SINT = 206,
272 VIRGL_FORMAT_L8_SINT = 207,
273 VIRGL_FORMAT_L8A8_SINT = 208,
274
275 VIRGL_FORMAT_A16_UINT = 209,
276 VIRGL_FORMAT_I16_UINT = 210,
277 VIRGL_FORMAT_L16_UINT = 211,
278 VIRGL_FORMAT_L16A16_UINT = 212,
279
280 VIRGL_FORMAT_A16_SINT = 213,
281 VIRGL_FORMAT_I16_SINT = 214,
282 VIRGL_FORMAT_L16_SINT = 215,
283 VIRGL_FORMAT_L16A16_SINT = 216,
284
285 VIRGL_FORMAT_A32_UINT = 217,
286 VIRGL_FORMAT_I32_UINT = 218,
287 VIRGL_FORMAT_L32_UINT = 219,
288 VIRGL_FORMAT_L32A32_UINT = 220,
289
290 VIRGL_FORMAT_A32_SINT = 221,
291 VIRGL_FORMAT_I32_SINT = 222,
292 VIRGL_FORMAT_L32_SINT = 223,
293 VIRGL_FORMAT_L32A32_SINT = 224,
294
295 VIRGL_FORMAT_B10G10R10A2_UINT = 225,
296 VIRGL_FORMAT_ETC1_RGB8 = 226,
297 VIRGL_FORMAT_R8G8_R8B8_UNORM = 227,
298 VIRGL_FORMAT_G8R8_B8R8_UNORM = 228,
299 VIRGL_FORMAT_R8G8B8X8_SNORM = 229,
300
301 VIRGL_FORMAT_R8G8B8X8_SRGB = 230,
302
303 VIRGL_FORMAT_R8G8B8X8_UINT = 231,
304 VIRGL_FORMAT_R8G8B8X8_SINT = 232,
305 VIRGL_FORMAT_B10G10R10X2_UNORM = 233,
306 VIRGL_FORMAT_R16G16B16X16_UNORM = 234,
307 VIRGL_FORMAT_R16G16B16X16_SNORM = 235,
308 VIRGL_FORMAT_R16G16B16X16_FLOAT = 236,
309 VIRGL_FORMAT_R16G16B16X16_UINT = 237,
310 VIRGL_FORMAT_R16G16B16X16_SINT = 238,
311 VIRGL_FORMAT_R32G32B32X32_FLOAT = 239,
312 VIRGL_FORMAT_R32G32B32X32_UINT = 240,
313 VIRGL_FORMAT_R32G32B32X32_SINT = 241,
314 VIRGL_FORMAT_R8A8_SNORM = 242,
315 VIRGL_FORMAT_R16A16_UNORM = 243,
316 VIRGL_FORMAT_R16A16_SNORM = 244,
317 VIRGL_FORMAT_R16A16_FLOAT = 245,
318 VIRGL_FORMAT_R32A32_FLOAT = 246,
319 VIRGL_FORMAT_R8A8_UINT = 247,
320 VIRGL_FORMAT_R8A8_SINT = 248,
321 VIRGL_FORMAT_R16A16_UINT = 249,
322 VIRGL_FORMAT_R16A16_SINT = 250,
323 VIRGL_FORMAT_R32A32_UINT = 251,
324 VIRGL_FORMAT_R32A32_SINT = 252,
325
326 VIRGL_FORMAT_R10G10B10A2_UINT = 253,
327 VIRGL_FORMAT_B5G6R5_SRGB = 254,
328
329 VIRGL_FORMAT_BPTC_RGBA_UNORM = 255,
330 VIRGL_FORMAT_BPTC_SRGBA = 256,
331 VIRGL_FORMAT_BPTC_RGB_FLOAT = 257,
332 VIRGL_FORMAT_BPTC_RGB_UFLOAT = 258,
333
334 VIRGL_FORMAT_A16L16_UNORM = 262,
335
336 VIRGL_FORMAT_G8R8_UNORM = 263,
337 VIRGL_FORMAT_G8R8_SNORM = 264,
338 VIRGL_FORMAT_G16R16_UNORM = 265,
339 VIRGL_FORMAT_G16R16_SNORM = 266,
340 VIRGL_FORMAT_A8B8G8R8_SNORM = 267,
341
342 VIRGL_FORMAT_A8L8_UNORM = 259,
343 VIRGL_FORMAT_A8L8_SNORM = 260,
344 VIRGL_FORMAT_A8L8_SRGB = 261,
345
346 VIRGL_FORMAT_X8B8G8R8_SNORM = 268,
347
348
349 /* etc2 compressed */
350 VIRGL_FORMAT_ETC2_RGB8 = 269,
351 VIRGL_FORMAT_ETC2_SRGB8 = 270,
352 VIRGL_FORMAT_ETC2_RGB8A1 = 271,
353 VIRGL_FORMAT_ETC2_SRGB8A1 = 272,
354 VIRGL_FORMAT_ETC2_RGBA8 = 273,
355 VIRGL_FORMAT_ETC2_SRGBA8 = 274,
356 VIRGL_FORMAT_ETC2_R11_UNORM = 275,
357 VIRGL_FORMAT_ETC2_R11_SNORM = 276,
358 VIRGL_FORMAT_ETC2_RG11_UNORM = 277,
359 VIRGL_FORMAT_ETC2_RG11_SNORM = 278,
360
361 VIRGL_FORMAT_R10G10B10X2_UNORM = 308,
362 VIRGL_FORMAT_A4B4G4R4_UNORM = 311,
363
364 VIRGL_FORMAT_R8_SRGB = 312,
365 VIRGL_FORMAT_MAX /* = PIPE_FORMAT_COUNT */,
366
367 /* Below formats must not be used in the guest. */
368 VIRGL_FORMAT_B8G8R8X8_UNORM_EMULATED,
369 VIRGL_FORMAT_B8G8R8A8_UNORM_EMULATED,
370 VIRGL_FORMAT_MAX_EXTENDED
371 };
372
373 /* These are used by the capability_bits field in virgl_caps_v2. */
374 #define VIRGL_CAP_NONE 0
375 #define VIRGL_CAP_TGSI_INVARIANT (1 << 0)
376 #define VIRGL_CAP_TEXTURE_VIEW (1 << 1)
377 #define VIRGL_CAP_SET_MIN_SAMPLES (1 << 2)
378 #define VIRGL_CAP_COPY_IMAGE (1 << 3)
379 #define VIRGL_CAP_TGSI_PRECISE (1 << 4)
380 #define VIRGL_CAP_TXQS (1 << 5)
381 #define VIRGL_CAP_MEMORY_BARRIER (1 << 6)
382 #define VIRGL_CAP_COMPUTE_SHADER (1 << 7)
383 #define VIRGL_CAP_FB_NO_ATTACH (1 << 8)
384 #define VIRGL_CAP_ROBUST_BUFFER_ACCESS (1 << 9)
385 #define VIRGL_CAP_TGSI_FBFETCH (1 << 10)
386 #define VIRGL_CAP_SHADER_CLOCK (1 << 11)
387 #define VIRGL_CAP_TEXTURE_BARRIER (1 << 12)
388 #define VIRGL_CAP_TGSI_COMPONENTS (1 << 13)
389 #define VIRGL_CAP_GUEST_MAY_INIT_LOG (1 << 14)
390 #define VIRGL_CAP_SRGB_WRITE_CONTROL (1 << 15)
391 #define VIRGL_CAP_QBO (1 << 16)
392 #define VIRGL_CAP_TRANSFER (1 << 17)
393 #define VIRGL_CAP_FBO_MIXED_COLOR_FORMATS (1 << 18)
394 #define VIRGL_CAP_FAKE_FP64 (1 << 19)
395 #define VIRGL_CAP_BIND_COMMAND_ARGS (1 << 20)
396 #define VIRGL_CAP_MULTI_DRAW_INDIRECT (1 << 21)
397 #define VIRGL_CAP_INDIRECT_PARAMS (1 << 22)
398 #define VIRGL_CAP_TRANSFORM_FEEDBACK3 (1 << 23)
399 #define VIRGL_CAP_3D_ASTC (1 << 24)
400 #define VIRGL_CAP_INDIRECT_INPUT_ADDR (1 << 25)
401 #define VIRGL_CAP_COPY_TRANSFER (1 << 26)
402 #define VIRGL_CAP_CLIP_HALFZ (1 << 27)
403 #define VIRGL_CAP_APP_TWEAK_SUPPORT (1 << 28)
404 #define VIRGL_CAP_BGRA_SRGB_IS_EMULATED (1 << 29)
405 #define VIRGL_CAP_CLEAR_TEXTURE (1 << 30)
406 #define VIRGL_CAP_ARB_BUFFER_STORAGE (1 << 31)
407
408 /* These are used by the capability_bits_v2 field in virgl_caps_v2. */
409 #define VIRGL_CAP_V2_BLEND_EQUATION (1 << 0)
410
411 /* virgl bind flags - these are compatible with mesa 10.5 gallium.
412 * but are fixed, no other should be passed to virgl either.
413 */
414 #define VIRGL_BIND_DEPTH_STENCIL (1 << 0)
415 #define VIRGL_BIND_RENDER_TARGET (1 << 1)
416 #define VIRGL_BIND_SAMPLER_VIEW (1 << 3)
417 #define VIRGL_BIND_VERTEX_BUFFER (1 << 4)
418 #define VIRGL_BIND_INDEX_BUFFER (1 << 5)
419 #define VIRGL_BIND_CONSTANT_BUFFER (1 << 6)
420 #define VIRGL_BIND_DISPLAY_TARGET (1 << 7)
421 #define VIRGL_BIND_COMMAND_ARGS (1 << 8)
422 #define VIRGL_BIND_STREAM_OUTPUT (1 << 11)
423 #define VIRGL_BIND_SHADER_BUFFER (1 << 14)
424 #define VIRGL_BIND_QUERY_BUFFER (1 << 15)
425 #define VIRGL_BIND_CURSOR (1 << 16)
426 #define VIRGL_BIND_CUSTOM (1 << 17)
427 #define VIRGL_BIND_SCANOUT (1 << 18)
428 /* Used for buffers that are backed by guest storage and
429 * are only read by the host.
430 */
431 #define VIRGL_BIND_STAGING (1 << 19)
432 #define VIRGL_BIND_SHARED (1 << 20)
433
434 #define VIRGL_BIND_PREFER_EMULATED_BGRA (1 << 21)
435
436 #define VIRGL_BIND_LINEAR (1 << 22)
437
438 #define VIRGL_BIND_SHARED_SUBFLAGS (0xff << 24)
439
440 #define VIRGL_BIND_MINIGBM_CAMERA_WRITE (1 << 24)
441 #define VIRGL_BIND_MINIGBM_CAMERA_READ (1 << 25)
442 #define VIRGL_BIND_MINIGBM_HW_VIDEO_DECODER (1 << 26)
443 #define VIRGL_BIND_MINIGBM_HW_VIDEO_ENCODER (1 << 27)
444 #define VIRGL_BIND_MINIGBM_SW_READ_OFTEN (1 << 28)
445 #define VIRGL_BIND_MINIGBM_SW_READ_RARELY (1 << 29)
446 #define VIRGL_BIND_MINIGBM_SW_WRITE_OFTEN (1 << 30)
447 #define VIRGL_BIND_MINIGBM_SW_WRITE_RARELY (1 << 31)
448 #define VIRGL_BIND_MINIGBM_PROTECTED (0xf << 28) // Mutually exclusive with SW_ flags
449
450 struct virgl_caps_bool_set1 {
451 unsigned indep_blend_enable:1;
452 unsigned indep_blend_func:1;
453 unsigned cube_map_array:1;
454 unsigned shader_stencil_export:1;
455 unsigned conditional_render:1;
456 unsigned start_instance:1;
457 unsigned primitive_restart:1;
458 unsigned blend_eq_sep:1;
459 unsigned instanceid:1;
460 unsigned vertex_element_instance_divisor:1;
461 unsigned seamless_cube_map:1;
462 unsigned occlusion_query:1;
463 unsigned timer_query:1;
464 unsigned streamout_pause_resume:1;
465 unsigned texture_multisample:1;
466 unsigned fragment_coord_conventions:1;
467 unsigned depth_clip_disable:1;
468 unsigned seamless_cube_map_per_texture:1;
469 unsigned ubo:1;
470 unsigned color_clamping:1; /* not in GL 3.1 core profile */
471 unsigned poly_stipple:1; /* not in GL 3.1 core profile */
472 unsigned mirror_clamp:1;
473 unsigned texture_query_lod:1;
474 unsigned has_fp64:1;
475 unsigned has_tessellation_shaders:1;
476 unsigned has_indirect_draw:1;
477 unsigned has_sample_shading:1;
478 unsigned has_cull:1;
479 unsigned conditional_render_inverted:1;
480 unsigned derivative_control:1;
481 unsigned polygon_offset_clamp:1;
482 unsigned transform_feedback_overflow_query:1;
483 /* DO NOT ADD ANYMORE MEMBERS - need to add another 32-bit to v2 caps */
484 };
485
486 /* endless expansion capabilites - current gallium has 252 formats */
487 struct virgl_supported_format_mask {
488 uint32_t bitmask[16];
489 };
490 /* capabilities set 2 - version 1 - 32-bit and float values */
491 struct virgl_caps_v1 {
492 uint32_t max_version;
493 struct virgl_supported_format_mask sampler;
494 struct virgl_supported_format_mask render;
495 struct virgl_supported_format_mask depthstencil;
496 struct virgl_supported_format_mask vertexbuffer;
497 struct virgl_caps_bool_set1 bset;
498 uint32_t glsl_level;
499 uint32_t max_texture_array_layers;
500 uint32_t max_streamout_buffers;
501 uint32_t max_dual_source_render_targets;
502 uint32_t max_render_targets;
503 uint32_t max_samples;
504 uint32_t prim_mask;
505 uint32_t max_tbo_size;
506 uint32_t max_uniform_blocks;
507 uint32_t max_viewports;
508 uint32_t max_texture_gather_components;
509 };
510
511 /*
512 * This struct should be growable when used in capset 2,
513 * so we shouldn't have to add a v3 ever.
514 */
515 struct virgl_caps_v2 {
516 struct virgl_caps_v1 v1;
517 float min_aliased_point_size;
518 float max_aliased_point_size;
519 float min_smooth_point_size;
520 float max_smooth_point_size;
521 float min_aliased_line_width;
522 float max_aliased_line_width;
523 float min_smooth_line_width;
524 float max_smooth_line_width;
525 float max_texture_lod_bias;
526 uint32_t max_geom_output_vertices;
527 uint32_t max_geom_total_output_components;
528 uint32_t max_vertex_outputs;
529 uint32_t max_vertex_attribs;
530 uint32_t max_shader_patch_varyings;
531 int32_t min_texel_offset;
532 int32_t max_texel_offset;
533 int32_t min_texture_gather_offset;
534 int32_t max_texture_gather_offset;
535 uint32_t texture_buffer_offset_alignment;
536 uint32_t uniform_buffer_offset_alignment;
537 uint32_t shader_buffer_offset_alignment;
538 uint32_t capability_bits;
539 uint32_t sample_locations[8];
540 uint32_t max_vertex_attrib_stride;
541 uint32_t max_shader_buffer_frag_compute;
542 uint32_t max_shader_buffer_other_stages;
543 uint32_t max_shader_image_frag_compute;
544 uint32_t max_shader_image_other_stages;
545 uint32_t max_image_samples;
546 uint32_t max_compute_work_group_invocations;
547 uint32_t max_compute_shared_memory_size;
548 uint32_t max_compute_grid_size[3];
549 uint32_t max_compute_block_size[3];
550 uint32_t max_texture_2d_size;
551 uint32_t max_texture_3d_size;
552 uint32_t max_texture_cube_size;
553 uint32_t max_combined_shader_buffers;
554 uint32_t max_atomic_counters[6];
555 uint32_t max_atomic_counter_buffers[6];
556 uint32_t max_combined_atomic_counters;
557 uint32_t max_combined_atomic_counter_buffers;
558 uint32_t host_feature_check_version;
559 struct virgl_supported_format_mask supported_readback_formats;
560 struct virgl_supported_format_mask scanout;
561 uint32_t capability_bits_v2;
562 };
563
564 union virgl_caps {
565 uint32_t max_version;
566 struct virgl_caps_v1 v1;
567 struct virgl_caps_v2 v2;
568 };
569
570 enum virgl_errors {
571 VIRGL_ERROR_NONE,
572 VIRGL_ERROR_UNKNOWN,
573 VIRGL_ERROR_UNKNOWN_RESOURCE_FORMAT,
574 };
575
576 enum virgl_ctx_errors {
577 VIRGL_ERROR_CTX_NONE,
578 VIRGL_ERROR_CTX_UNKNOWN,
579 VIRGL_ERROR_CTX_ILLEGAL_SHADER,
580 VIRGL_ERROR_CTX_ILLEGAL_HANDLE,
581 VIRGL_ERROR_CTX_ILLEGAL_RESOURCE,
582 VIRGL_ERROR_CTX_ILLEGAL_SURFACE,
583 VIRGL_ERROR_CTX_ILLEGAL_VERTEX_FORMAT,
584 VIRGL_ERROR_CTX_ILLEGAL_CMD_BUFFER,
585 VIRGL_ERROR_CTX_GLES_HAVE_TES_BUT_MISS_TCS,
586 VIRGL_ERROR_GL_ANY_SAMPLES_PASSED,
587 VIRGL_ERROR_CTX_ILLEGAL_FORMAT,
588 VIRGL_ERROR_CTX_ILLEGAL_SAMPLER_VIEW_TARGET,
589 VIRGL_ERROR_CTX_TRANSFER_IOV_BOUNDS,
590 VIRGL_ERROR_CTX_ILLEGAL_DUAL_SRC_BLEND
591 };
592
593 /**
594 * Flags for the driver about resource behaviour:
595 */
596 #define VIRGL_RESOURCE_Y_0_TOP (1 << 0)
597 #define VIRGL_RESOURCE_FLAG_MAP_PERSISTENT (1 << 1)
598 #define VIRGL_RESOURCE_FLAG_MAP_COHERENT (1 << 2)
599
600 #endif